VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac@ 15962

Last change on this file since 15962 was 15962, checked in by vboxsync, 16 years ago

Added debugging code (inactive) for tracking the state of the 32/64 switcher in crash dumps
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 17.8 KB
Line 
1; VMM - World Switchers, 32Bit to AMD64.
2;
3
4;
5; Copyright (C) 2006-2007 Sun Microsystems, Inc.
6;
7; This file is part of VirtualBox Open Source Edition (OSE), as
8; available from http://www.virtualbox.org. This file is free software;
9; you can redistribute it and/or modify it under the terms of the GNU
10; General Public License (GPL) as published by the Free Software
11; Foundation, in version 2 as it comes in the "COPYING" file of the
12; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
13; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
14;
15; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
16; Clara, CA 95054 USA or visit http://www.sun.com if you need
17; additional information or have any questions.
18;
19
20;%define DEBUG_STUFF 1
21;%define STRICT_IF 1
22
23;*******************************************************************************
24;* Defined Constants And Macros *
25;*******************************************************************************
26
27
28;*******************************************************************************
29;* Header Files *
30;*******************************************************************************
31%include "VBox/asmdefs.mac"
32%include "VBox/x86.mac"
33%include "VBox/cpum.mac"
34%include "VBox/stam.mac"
35%include "VBox/vm.mac"
36%include "CPUMInternal.mac"
37%include "VMMSwitcher/VMMSwitcher.mac"
38
39
40;
41; Start the fixup records
42; We collect the fixups in the .data section as we go along
43; It is therefore VITAL that no-one is using the .data section
44; for anything else between 'Start' and 'End'.
45;
46BEGINDATA
47GLOBALNAME Fixups
48
49
50
51BEGINCODE
52GLOBALNAME Start
53
54BITS 32
55
56;;
57; The C interface.
58;
59BEGINPROC vmmR0HostToGuest
60 %ifdef DEBUG_STUFF
61 COM32_S_NEWLINE
62 COM32_S_CHAR '^'
63 %endif
64
65 %ifdef VBOX_WITH_STATISTICS
66 ;
67 ; Switcher stats.
68 ;
69 FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToGC
70 mov edx, 0ffffffffh
71 STAM_PROFILE_ADV_START edx
72 %endif
73
74 ; turn off interrupts
75 pushf
76 cli
77
78 ;
79 ; Call worker.
80 ;
81 FIXUP FIX_HC_CPUM_OFF, 1, 0
82 mov edx, 0ffffffffh
83 push cs ; allow for far return and restore cs correctly.
84 call NAME(vmmR0HostToGuestAsm)
85
86 ; restore original flags
87 popf
88
89%ifdef VBOX_WITH_STATISTICS
90 ;
91 ; Switcher stats.
92 ;
93 FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToHC
94 mov edx, 0ffffffffh
95 STAM_PROFILE_ADV_STOP edx
96%endif
97
98 ret
99
100ENDPROC vmmR0HostToGuest
101
102; *****************************************************************************
103; vmmR0HostToGuestAsm
104;
105; Phase one of the switch from host to guest context (host MMU context)
106;
107; INPUT:
108; - edx virtual address of CPUM structure (valid in host context)
109;
110; USES/DESTROYS:
111; - eax, ecx, edx, esi
112;
113; ASSUMPTION:
114; - current CS and DS selectors are wide open
115;
116; *****************************************************************************
117ALIGNCODE(16)
118BEGINPROC vmmR0HostToGuestAsm
119 ;;
120 ;; Save CPU host context
121 ;; Skip eax, edx and ecx as these are not preserved over calls.
122 ;;
123 CPUMCPU_FROM_CPUM(edx)
124%ifdef VBOX_WITH_CRASHDUMP_MAGIC
125 ; phys address of scratch page
126 mov eax, dword [edx + CPUMCPU.Guest.dr + 4*8]
127 mov cr2, eax
128
129 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 1
130%endif
131
132 ; general registers.
133 mov [edx + CPUMCPU.Host.ebx], ebx
134 mov [edx + CPUMCPU.Host.edi], edi
135 mov [edx + CPUMCPU.Host.esi], esi
136 mov [edx + CPUMCPU.Host.esp], esp
137 mov [edx + CPUMCPU.Host.ebp], ebp
138 ; selectors.
139 mov [edx + CPUMCPU.Host.ds], ds
140 mov [edx + CPUMCPU.Host.es], es
141 mov [edx + CPUMCPU.Host.fs], fs
142 mov [edx + CPUMCPU.Host.gs], gs
143 mov [edx + CPUMCPU.Host.ss], ss
144 ; special registers.
145 sldt [edx + CPUMCPU.Host.ldtr]
146 sidt [edx + CPUMCPU.Host.idtr]
147 sgdt [edx + CPUMCPU.Host.gdtr]
148 str [edx + CPUMCPU.Host.tr]
149
150%ifdef VBOX_WITH_CRASHDUMP_MAGIC
151 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 2
152%endif
153
154 ; control registers.
155 mov eax, cr0
156 mov [edx + CPUMCPU.Host.cr0], eax
157 ;Skip cr2; assume host os don't stuff things in cr2. (safe)
158 mov eax, cr3
159 mov [edx + CPUMCPU.Host.cr3], eax
160 mov eax, cr4
161 mov [edx + CPUMCPU.Host.cr4], eax
162
163 ; save the host EFER msr
164 mov ebx, edx
165 mov ecx, MSR_K6_EFER
166 rdmsr
167 mov [ebx + CPUMCPU.Host.efer], eax
168 mov [ebx + CPUMCPU.Host.efer + 4], edx
169 mov edx, ebx
170
171%ifdef VBOX_WITH_CRASHDUMP_MAGIC
172 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 3
173%endif
174
175 CPUM_FROM_CPUMCPU(edx)
176 ; Load new gdt so we can do a far jump after going into 64 bits mode
177 lgdt [edx + CPUM.Hyper.gdtr]
178
179%ifdef VBOX_WITH_CRASHDUMP_MAGIC
180 CPUMCPU_FROM_CPUM(edx)
181 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 4
182 CPUM_FROM_CPUMCPU(edx)
183%endif
184
185 ;;
186 ;; Load Intermediate memory context.
187 ;;
188 FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
189 mov eax, 0ffffffffh
190 mov cr3, eax
191 DEBUG_CHAR('?')
192
193 ;;
194 ;; Jump to identity mapped location
195 ;;
196 FIXUP FIX_HC_2_ID_NEAR_REL, 1, NAME(IDEnterTarget) - NAME(Start)
197 jmp near NAME(IDEnterTarget)
198
199
200 ; We're now on identity mapped pages!
201ALIGNCODE(16)
202GLOBALNAME IDEnterTarget
203 DEBUG_CHAR('2')
204
205 ; 1. Disable paging.
206 mov ebx, cr0
207 and ebx, ~X86_CR0_PG
208 mov cr0, ebx
209 DEBUG_CHAR('2')
210
211%ifdef VBOX_WITH_CRASHDUMP_MAGIC
212 mov eax, cr2
213 mov dword [eax], 3
214%endif
215
216 ; 2. Enable PAE.
217 mov ecx, cr4
218 or ecx, X86_CR4_PAE
219 mov cr4, ecx
220
221 ; 3. Load long mode intermediate CR3.
222 FIXUP FIX_INTER_AMD64_CR3, 1
223 mov ecx, 0ffffffffh
224 mov cr3, ecx
225 DEBUG_CHAR('3')
226
227%ifdef VBOX_WITH_CRASHDUMP_MAGIC
228 mov eax, cr2
229 mov dword [eax], 4
230%endif
231
232 ; 4. Enable long mode.
233 mov ebp, edx
234 mov ecx, MSR_K6_EFER
235 rdmsr
236 or eax, MSR_K6_EFER_LME | MSR_K6_EFER_SCE | MSR_K6_EFER_NXE
237 wrmsr
238 mov edx, ebp
239 DEBUG_CHAR('4')
240
241%ifdef VBOX_WITH_CRASHDUMP_MAGIC
242 mov eax, cr2
243 mov dword [eax], 5
244%endif
245
246 ; 5. Enable paging.
247 or ebx, X86_CR0_PG
248 ; Disable ring 0 write protection too
249 and ebx, ~X86_CR0_WRITE_PROTECT
250 mov cr0, ebx
251 DEBUG_CHAR('5')
252
253 ; Jump from compatibility mode to 64-bit mode.
254 FIXUP FIX_ID_FAR32_TO_64BIT_MODE, 1, NAME(IDEnter64Mode) - NAME(Start)
255 jmp 0ffffh:0fffffffeh
256
257 ;
258 ; We're in 64-bit mode (ds, ss, es, fs, gs are all bogus).
259BITS 64
260ALIGNCODE(16)
261NAME(IDEnter64Mode):
262 DEBUG_CHAR('6')
263 jmp [NAME(pICEnterTarget) wrt rip]
264
265; 64-bit jump target
266NAME(pICEnterTarget):
267FIXUP FIX_HC_64BIT_NOCHECK, 0, NAME(ICEnterTarget) - NAME(Start)
268dq 0ffffffffffffffffh
269
270; 64-bit pCpum address.
271NAME(pCpumIC):
272FIXUP FIX_GC_64_BIT_CPUM_OFF, 0, 0
273dq 0ffffffffffffffffh
274
275%ifdef VBOX_WITH_CRASHDUMP_MAGIC
276NAME(pMarker):
277db 'Switch_marker'
278%endif
279
280 ;
281 ; When we arrive here we're in 64 bits mode in the intermediate context
282 ;
283ALIGNCODE(16)
284GLOBALNAME ICEnterTarget
285 ; Load CPUM pointer into rdx
286 mov rdx, [NAME(pCpumIC) wrt rip]
287
288 mov rax, cs
289 mov ds, rax
290 mov es, rax
291
292 ; Invalidate fs & gs
293 mov rax, 0
294 mov fs, rax
295 mov gs, rax
296
297%ifdef VBOX_WITH_CRASHDUMP_MAGIC
298 CPUMCPU_FROM_CPUM(edx)
299 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 5
300 CPUM_FROM_CPUMCPU(edx)
301%endif
302
303 ; Setup stack; use the lss_esp, ss pair for lss
304 DEBUG_CHAR('7')
305 mov rsp, 0
306 mov eax, [rdx + CPUM.Hyper.esp]
307 mov [rdx + CPUM.Hyper.lss_esp], eax
308 lss esp, [rdx + CPUM.Hyper.lss_esp]
309
310%ifdef VBOX_WITH_CRASHDUMP_MAGIC
311 CPUMCPU_FROM_CPUM(edx)
312 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 6
313 CPUM_FROM_CPUMCPU(edx)
314%endif
315
316
317 ; load the hypervisor function address
318 mov r9, [rdx + CPUM.Hyper.eip]
319
320 CPUMCPU_FROM_CPUM(edx)
321
322 ; Check if we need to restore the guest FPU state
323 mov esi, [rdx + CPUMCPU.fUseFlags] ; esi == use flags.
324 test esi, CPUM_SYNC_FPU_STATE
325 jz near gth_fpu_no
326
327%ifdef VBOX_WITH_CRASHDUMP_MAGIC
328 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 7
329%endif
330
331 mov rax, cr0
332 mov rcx, rax ; save old CR0
333 and rax, ~(X86_CR0_TS | X86_CR0_EM)
334 mov cr0, rax
335 fxrstor [rdx + CPUMCPU.Guest.fpu]
336 mov cr0, rcx ; and restore old CR0 again
337
338 and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_FPU_STATE
339
340gth_fpu_no:
341 ; Check if we need to restore the guest debug state
342 test esi, CPUM_SYNC_DEBUG_STATE
343 jz near gth_debug_no
344
345%ifdef VBOX_WITH_CRASHDUMP_MAGIC
346 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 8
347%endif
348
349 mov rax, qword [rdx + CPUMCPU.Guest.dr + 0*8]
350 mov dr0, rax
351 mov rax, qword [rdx + CPUMCPU.Guest.dr + 1*8]
352 mov dr1, rax
353 mov rax, qword [rdx + CPUMCPU.Guest.dr + 2*8]
354 mov dr2, rax
355 mov rax, qword [rdx + CPUMCPU.Guest.dr + 3*8]
356 mov dr3, rax
357 mov rax, qword [rdx + CPUMCPU.Guest.dr + 6*8]
358 mov dr6, rax ; not required for AMD-V
359
360 and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_DEBUG_STATE
361
362gth_debug_no:
363
364%ifdef VBOX_WITH_CRASHDUMP_MAGIC
365 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 9
366%endif
367
368 ; parameter for all helper functions (pCtx)
369 lea rsi, [rdx + CPUMCPU.Guest.fpu]
370 call r9
371
372 ; Load CPUM pointer into rdx
373 mov rdx, [NAME(pCpumIC) wrt rip]
374 CPUMCPU_FROM_CPUM(edx)
375
376%ifdef VBOX_WITH_CRASHDUMP_MAGIC
377 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 10
378%endif
379
380 ; Save the return code
381 mov dword [rdx + CPUMCPU.u32RetCode], eax
382
383 ; now let's switch back
384 jmp NAME(VMMGCGuestToHostAsm) ; rax = returncode.
385
386ENDPROC vmmR0HostToGuestAsm
387
388
389;;
390; Trampoline for doing a call when starting the hyper visor execution.
391;
392; Push any arguments to the routine.
393; Push the argument frame size (cArg * 4).
394; Push the call target (_cdecl convention).
395; Push the address of this routine.
396;
397;
398BITS 64
399ALIGNCODE(16)
400BEGINPROC vmmGCCallTrampoline
401%ifdef DEBUG_STUFF
402 COM32_S_CHAR 'c'
403 COM32_S_CHAR 't'
404 COM32_S_CHAR '!'
405%endif
406 int3
407ENDPROC vmmGCCallTrampoline
408
409
410;;
411; The C interface.
412;
413BITS 64
414ALIGNCODE(16)
415BEGINPROC vmmGCGuestToHost
416%ifdef DEBUG_STUFF
417 push esi
418 COM_NEWLINE
419 DEBUG_CHAR('b')
420 DEBUG_CHAR('a')
421 DEBUG_CHAR('c')
422 DEBUG_CHAR('k')
423 DEBUG_CHAR('!')
424 COM_NEWLINE
425 pop esi
426%endif
427 int3
428ENDPROC vmmGCGuestToHost
429
430;;
431; VMMGCGuestToHostAsm
432;
433; This is an alternative entry point which we'll be using
434; when the we have saved the guest state already or we haven't
435; been messing with the guest at all.
436;
437; @param eax Return code.
438; @uses eax, edx, ecx (or it may use them in the future)
439;
440BITS 64
441ALIGNCODE(16)
442BEGINPROC VMMGCGuestToHostAsm
443 ;; We're still in the intermediate memory context!
444
445 ;;
446 ;; Switch to compatibility mode, placing ourselves in identity mapped code.
447 ;;
448 jmp far [NAME(fpIDEnterTarget) wrt rip]
449
450; 16:32 Pointer to IDEnterTarget.
451NAME(fpIDEnterTarget):
452 FIXUP FIX_ID_32BIT, 0, NAME(IDExitTarget) - NAME(Start)
453dd 0
454 FIXUP FIX_HYPER_CS, 0
455dd 0
456
457 ; We're now on identity mapped pages!
458ALIGNCODE(16)
459GLOBALNAME IDExitTarget
460BITS 32
461 DEBUG_CHAR('1')
462
463 ; 1. Deactivate long mode by turning off paging.
464 mov ebx, cr0
465 and ebx, ~X86_CR0_PG
466 mov cr0, ebx
467 DEBUG_CHAR('2')
468
469 ; 2. Load intermediate page table.
470 FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
471 mov edx, 0ffffffffh
472 mov cr3, edx
473 DEBUG_CHAR('3')
474
475 ; 3. Disable long mode.
476 mov ecx, MSR_K6_EFER
477 rdmsr
478 DEBUG_CHAR('5')
479 and eax, ~(MSR_K6_EFER_LME)
480 wrmsr
481 DEBUG_CHAR('6')
482
483%ifndef NEED_PAE_ON_HOST
484 ; 3b. Disable PAE.
485 mov eax, cr4
486 and eax, ~X86_CR4_PAE
487 mov cr4, eax
488 DEBUG_CHAR('7')
489%endif
490
491 ; 4. Enable paging.
492 or ebx, X86_CR0_PG
493 mov cr0, ebx
494 jmp short just_a_jump
495just_a_jump:
496 DEBUG_CHAR('8')
497
498 ;;
499 ;; 5. Jump to guest code mapping of the code and load the Hypervisor CS.
500 ;;
501 FIXUP FIX_ID_2_HC_NEAR_REL, 1, NAME(ICExitTarget) - NAME(Start)
502 jmp near NAME(ICExitTarget)
503
504 ;;
505 ;; When we arrive at this label we're at the
506 ;; intermediate mapping of the switching code.
507 ;;
508BITS 32
509ALIGNCODE(16)
510GLOBALNAME ICExitTarget
511 DEBUG_CHAR('8')
512
513 ; load the hypervisor data selector into ds & es
514 FIXUP FIX_HYPER_DS, 1
515 mov eax, 0ffffh
516 mov ds, eax
517 mov es, eax
518
519 FIXUP FIX_GC_CPUM_OFF, 1, 0
520 mov edx, 0ffffffffh
521 CPUMCPU_FROM_CPUM(edx)
522 mov esi, [edx + CPUMCPU.Host.cr3]
523 mov cr3, esi
524
525 ;; now we're in host memory context, let's restore regs
526 FIXUP FIX_HC_CPUM_OFF, 1, 0
527 mov edx, 0ffffffffh
528 CPUMCPU_FROM_CPUM(edx)
529
530 ; restore the host EFER
531 mov ebx, edx
532 mov ecx, MSR_K6_EFER
533 mov eax, [ebx + CPUMCPU.Host.efer]
534 mov edx, [ebx + CPUMCPU.Host.efer + 4]
535 wrmsr
536 mov edx, ebx
537
538 ; activate host gdt and idt
539 lgdt [edx + CPUMCPU.Host.gdtr]
540 DEBUG_CHAR('0')
541 lidt [edx + CPUMCPU.Host.idtr]
542 DEBUG_CHAR('1')
543
544 ; Restore TSS selector; must mark it as not busy before using ltr (!)
545 ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
546 movzx eax, word [edx + CPUMCPU.Host.tr] ; eax <- TR
547 and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
548 add eax, [edx + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
549 and dword [eax + 4], ~0200h ; clear busy flag (2nd type2 bit)
550 ltr word [edx + CPUMCPU.Host.tr]
551
552 ; activate ldt
553 DEBUG_CHAR('2')
554 lldt [edx + CPUMCPU.Host.ldtr]
555
556 ; Restore segment registers
557 mov eax, [edx + CPUMCPU.Host.ds]
558 mov ds, eax
559 mov eax, [edx + CPUMCPU.Host.es]
560 mov es, eax
561 mov eax, [edx + CPUMCPU.Host.fs]
562 mov fs, eax
563 mov eax, [edx + CPUMCPU.Host.gs]
564 mov gs, eax
565 ; restore stack
566 lss esp, [edx + CPUMCPU.Host.esp]
567
568 ; Control registers.
569 mov ecx, [edx + CPUMCPU.Host.cr4]
570 mov cr4, ecx
571 mov ecx, [edx + CPUMCPU.Host.cr0]
572 mov cr0, ecx
573 ;mov ecx, [edx + CPUMCPU.Host.cr2] ; assumes this is waste of time.
574 ;mov cr2, ecx
575
576 ; restore general registers.
577 mov edi, [edx + CPUMCPU.Host.edi]
578 mov esi, [edx + CPUMCPU.Host.esi]
579 mov ebx, [edx + CPUMCPU.Host.ebx]
580 mov ebp, [edx + CPUMCPU.Host.ebp]
581
582 ; store the return code in eax
583 mov eax, [edx + CPUMCPU.u32RetCode]
584 retf
585ENDPROC VMMGCGuestToHostAsm
586
587;;
588; VMMGCGuestToHostAsmHyperCtx
589;
590; This is an alternative entry point which we'll be using
591; when the we have the hypervisor context and need to save
592; that before going to the host.
593;
594; This is typically useful when abandoning the hypervisor
595; because of a trap and want the trap state to be saved.
596;
597; @param eax Return code.
598; @param ecx Points to CPUMCTXCORE.
599; @uses eax,edx,ecx
600ALIGNCODE(16)
601BEGINPROC VMMGCGuestToHostAsmHyperCtx
602 int3
603
604;;
605; VMMGCGuestToHostAsmGuestCtx
606;
607; Switches from Guest Context to Host Context.
608; Of course it's only called from within the GC.
609;
610; @param eax Return code.
611; @param esp + 4 Pointer to CPUMCTXCORE.
612;
613; @remark ASSUMES interrupts disabled.
614;
615ALIGNCODE(16)
616BEGINPROC VMMGCGuestToHostAsmGuestCtx
617 int3
618
619GLOBALNAME End
620;
621; The description string (in the text section).
622;
623NAME(Description):
624 db SWITCHER_DESCRIPTION
625 db 0
626
627extern NAME(Relocate)
628
629;
630; End the fixup records.
631;
632BEGINDATA
633 db FIX_THE_END ; final entry.
634GLOBALNAME FixupsEnd
635
636;;
637; The switcher definition structure.
638ALIGNDATA(16)
639GLOBALNAME Def
640 istruc VMMSWITCHERDEF
641 at VMMSWITCHERDEF.pvCode, RTCCPTR_DEF NAME(Start)
642 at VMMSWITCHERDEF.pvFixups, RTCCPTR_DEF NAME(Fixups)
643 at VMMSWITCHERDEF.pszDesc, RTCCPTR_DEF NAME(Description)
644 at VMMSWITCHERDEF.pfnRelocate, RTCCPTR_DEF NAME(Relocate)
645 at VMMSWITCHERDEF.enmType, dd SWITCHER_TYPE
646 at VMMSWITCHERDEF.cbCode, dd NAME(End) - NAME(Start)
647 at VMMSWITCHERDEF.offR0HostToGuest, dd NAME(vmmR0HostToGuest) - NAME(Start)
648 at VMMSWITCHERDEF.offGCGuestToHost, dd NAME(vmmGCGuestToHost) - NAME(Start)
649 at VMMSWITCHERDEF.offGCCallTrampoline, dd NAME(vmmGCCallTrampoline) - NAME(Start)
650 at VMMSWITCHERDEF.offGCGuestToHostAsm, dd NAME(VMMGCGuestToHostAsm) - NAME(Start)
651 at VMMSWITCHERDEF.offGCGuestToHostAsmHyperCtx, dd NAME(VMMGCGuestToHostAsmHyperCtx)- NAME(Start)
652 at VMMSWITCHERDEF.offGCGuestToHostAsmGuestCtx, dd NAME(VMMGCGuestToHostAsmGuestCtx)- NAME(Start)
653 ; disasm help
654 at VMMSWITCHERDEF.offHCCode0, dd 0
655 at VMMSWITCHERDEF.cbHCCode0, dd NAME(IDEnterTarget) - NAME(Start)
656 at VMMSWITCHERDEF.offHCCode1, dd NAME(ICExitTarget) - NAME(Start)
657 at VMMSWITCHERDEF.cbHCCode1, dd NAME(End) - NAME(ICExitTarget)
658 at VMMSWITCHERDEF.offIDCode0, dd NAME(IDEnterTarget) - NAME(Start)
659 at VMMSWITCHERDEF.cbIDCode0, dd NAME(ICEnterTarget) - NAME(IDEnterTarget)
660 at VMMSWITCHERDEF.offIDCode1, dd NAME(IDExitTarget) - NAME(Start)
661 at VMMSWITCHERDEF.cbIDCode1, dd NAME(ICExitTarget) - NAME(Start)
662 at VMMSWITCHERDEF.offGCCode, dd 0
663 at VMMSWITCHERDEF.cbGCCode, dd 0
664
665 iend
666
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