VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac@ 30060

Last change on this file since 30060 was 28800, checked in by vboxsync, 14 years ago

Automated rebranding to Oracle copyright/license strings via filemuncher
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 17.3 KB
Line 
1; VMM - World Switchers, 32Bit to AMD64.
2;
3
4;
5; Copyright (C) 2006-2007 Oracle Corporation
6;
7; This file is part of VirtualBox Open Source Edition (OSE), as
8; available from http://www.virtualbox.org. This file is free software;
9; you can redistribute it and/or modify it under the terms of the GNU
10; General Public License (GPL) as published by the Free Software
11; Foundation, in version 2 as it comes in the "COPYING" file of the
12; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
13; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
14;
15
16;%define DEBUG_STUFF 1
17;%define STRICT_IF 1
18
19;*******************************************************************************
20;* Defined Constants And Macros *
21;*******************************************************************************
22
23
24;*******************************************************************************
25;* Header Files *
26;*******************************************************************************
27%include "VBox/asmdefs.mac"
28%include "VBox/x86.mac"
29%include "VBox/cpum.mac"
30%include "VBox/stam.mac"
31%include "VBox/vm.mac"
32%include "CPUMInternal.mac"
33%include "VMMSwitcher/VMMSwitcher.mac"
34
35
36;
37; Start the fixup records
38; We collect the fixups in the .data section as we go along
39; It is therefore VITAL that no-one is using the .data section
40; for anything else between 'Start' and 'End'.
41;
42BEGINDATA
43GLOBALNAME Fixups
44
45
46
47BEGINCODE
48GLOBALNAME Start
49
50BITS 32
51
52;;
53; The C interface.
54;
55BEGINPROC vmmR0HostToGuest
56 %ifdef DEBUG_STUFF
57 COM32_S_NEWLINE
58 COM32_S_CHAR '^'
59 %endif
60
61 %ifdef VBOX_WITH_STATISTICS
62 ;
63 ; Switcher stats.
64 ;
65 FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToGC
66 mov edx, 0ffffffffh
67 STAM_PROFILE_ADV_START edx
68 %endif
69
70 ; turn off interrupts
71 pushf
72 cli
73
74 ;
75 ; Call worker.
76 ;
77 FIXUP FIX_HC_CPUM_OFF, 1, 0
78 mov edx, 0ffffffffh
79 push cs ; allow for far return and restore cs correctly.
80 call NAME(vmmR0HostToGuestAsm)
81
82 ; restore original flags
83 popf
84
85%ifdef VBOX_WITH_STATISTICS
86 ;
87 ; Switcher stats.
88 ;
89 FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToHC
90 mov edx, 0ffffffffh
91 STAM_PROFILE_ADV_STOP edx
92%endif
93
94 ret
95
96ENDPROC vmmR0HostToGuest
97
98; *****************************************************************************
99; vmmR0HostToGuestAsm
100;
101; Phase one of the switch from host to guest context (host MMU context)
102;
103; INPUT:
104; - edx virtual address of CPUM structure (valid in host context)
105;
106; USES/DESTROYS:
107; - eax, ecx, edx, esi
108;
109; ASSUMPTION:
110; - current CS and DS selectors are wide open
111;
112; *****************************************************************************
113ALIGNCODE(16)
114BEGINPROC vmmR0HostToGuestAsm
115 ;;
116 ;; Save CPU host context
117 ;; Skip eax, edx and ecx as these are not preserved over calls.
118 ;;
119 CPUMCPU_FROM_CPUM(edx)
120%ifdef VBOX_WITH_CRASHDUMP_MAGIC
121 ; phys address of scratch page
122 mov eax, dword [edx + CPUMCPU.Guest.dr + 4*8]
123 mov cr2, eax
124
125 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 1
126%endif
127
128 ; general registers.
129 mov [edx + CPUMCPU.Host.ebx], ebx
130 mov [edx + CPUMCPU.Host.edi], edi
131 mov [edx + CPUMCPU.Host.esi], esi
132 mov [edx + CPUMCPU.Host.esp], esp
133 mov [edx + CPUMCPU.Host.ebp], ebp
134 ; selectors.
135 mov [edx + CPUMCPU.Host.ds], ds
136 mov [edx + CPUMCPU.Host.es], es
137 mov [edx + CPUMCPU.Host.fs], fs
138 mov [edx + CPUMCPU.Host.gs], gs
139 mov [edx + CPUMCPU.Host.ss], ss
140 ; special registers.
141 sldt [edx + CPUMCPU.Host.ldtr]
142 sidt [edx + CPUMCPU.Host.idtr]
143 sgdt [edx + CPUMCPU.Host.gdtr]
144 str [edx + CPUMCPU.Host.tr]
145
146%ifdef VBOX_WITH_CRASHDUMP_MAGIC
147 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 2
148%endif
149
150 ; control registers.
151 mov eax, cr0
152 mov [edx + CPUMCPU.Host.cr0], eax
153 ;Skip cr2; assume host os don't stuff things in cr2. (safe)
154 mov eax, cr3
155 mov [edx + CPUMCPU.Host.cr3], eax
156 mov eax, cr4
157 mov [edx + CPUMCPU.Host.cr4], eax
158
159 ; save the host EFER msr
160 mov ebx, edx
161 mov ecx, MSR_K6_EFER
162 rdmsr
163 mov [ebx + CPUMCPU.Host.efer], eax
164 mov [ebx + CPUMCPU.Host.efer + 4], edx
165 mov edx, ebx
166
167%ifdef VBOX_WITH_CRASHDUMP_MAGIC
168 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 3
169%endif
170
171 ; Load new gdt so we can do a far jump after going into 64 bits mode
172 lgdt [edx + CPUMCPU.Hyper.gdtr]
173
174%ifdef VBOX_WITH_CRASHDUMP_MAGIC
175 mov dword [edx + CPUMCPU.Guest.dr + 4*8], 4
176%endif
177
178 ;;
179 ;; Load Intermediate memory context.
180 ;;
181 FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
182 mov eax, 0ffffffffh
183 mov cr3, eax
184 DEBUG_CHAR('?')
185
186 ;;
187 ;; Jump to identity mapped location
188 ;;
189 FIXUP FIX_HC_2_ID_NEAR_REL, 1, NAME(IDEnterTarget) - NAME(Start)
190 jmp near NAME(IDEnterTarget)
191
192
193 ; We're now on identity mapped pages!
194ALIGNCODE(16)
195GLOBALNAME IDEnterTarget
196 DEBUG_CHAR('2')
197
198 ; 1. Disable paging.
199 mov ebx, cr0
200 and ebx, ~X86_CR0_PG
201 mov cr0, ebx
202 DEBUG_CHAR('2')
203
204%ifdef VBOX_WITH_CRASHDUMP_MAGIC
205 mov eax, cr2
206 mov dword [eax], 3
207%endif
208
209 ; 2. Enable PAE.
210 mov ecx, cr4
211 or ecx, X86_CR4_PAE
212 mov cr4, ecx
213
214 ; 3. Load long mode intermediate CR3.
215 FIXUP FIX_INTER_AMD64_CR3, 1
216 mov ecx, 0ffffffffh
217 mov cr3, ecx
218 DEBUG_CHAR('3')
219
220%ifdef VBOX_WITH_CRASHDUMP_MAGIC
221 mov eax, cr2
222 mov dword [eax], 4
223%endif
224
225 ; 4. Enable long mode.
226 mov ebp, edx
227 mov ecx, MSR_K6_EFER
228 rdmsr
229 or eax, MSR_K6_EFER_LME | MSR_K6_EFER_SCE | MSR_K6_EFER_NXE
230 wrmsr
231 mov edx, ebp
232 DEBUG_CHAR('4')
233
234%ifdef VBOX_WITH_CRASHDUMP_MAGIC
235 mov eax, cr2
236 mov dword [eax], 5
237%endif
238
239 ; 5. Enable paging.
240 or ebx, X86_CR0_PG
241 ; Disable ring 0 write protection too
242 and ebx, ~X86_CR0_WRITE_PROTECT
243 mov cr0, ebx
244 DEBUG_CHAR('5')
245
246 ; Jump from compatibility mode to 64-bit mode.
247 FIXUP FIX_ID_FAR32_TO_64BIT_MODE, 1, NAME(IDEnter64Mode) - NAME(Start)
248 jmp 0ffffh:0fffffffeh
249
250 ;
251 ; We're in 64-bit mode (ds, ss, es, fs, gs are all bogus).
252BITS 64
253ALIGNCODE(16)
254NAME(IDEnter64Mode):
255 DEBUG_CHAR('6')
256 jmp [NAME(pICEnterTarget) wrt rip]
257
258; 64-bit jump target
259NAME(pICEnterTarget):
260FIXUP FIX_HC_64BIT_NOCHECK, 0, NAME(ICEnterTarget) - NAME(Start)
261dq 0ffffffffffffffffh
262
263; 64-bit pCpum address.
264NAME(pCpumIC):
265FIXUP FIX_GC_64_BIT_CPUM_OFF, 0, 0
266dq 0ffffffffffffffffh
267
268%ifdef VBOX_WITH_CRASHDUMP_MAGIC
269NAME(pMarker):
270db 'Switch_marker'
271%endif
272
273 ;
274 ; When we arrive here we're in 64 bits mode in the intermediate context
275 ;
276ALIGNCODE(16)
277GLOBALNAME ICEnterTarget
278 ; Load CPUM pointer into rdx
279 mov rdx, [NAME(pCpumIC) wrt rip]
280 CPUMCPU_FROM_CPUM(edx)
281
282 mov rax, cs
283 mov ds, rax
284 mov es, rax
285
286 ; Invalidate fs & gs
287 mov rax, 0
288 mov fs, rax
289 mov gs, rax
290
291%ifdef VBOX_WITH_CRASHDUMP_MAGIC
292 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 5
293%endif
294
295 ; Setup stack; use the lss_esp, ss pair for lss
296 DEBUG_CHAR('7')
297 mov rsp, 0
298 mov eax, [rdx + CPUMCPU.Hyper.esp]
299 mov [rdx + CPUMCPU.Hyper.lss_esp], eax
300 lss esp, [rdx + CPUMCPU.Hyper.lss_esp]
301
302%ifdef VBOX_WITH_CRASHDUMP_MAGIC
303 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 6
304%endif
305
306
307 ; load the hypervisor function address
308 mov r9, [rdx + CPUMCPU.Hyper.eip]
309
310 ; Check if we need to restore the guest FPU state
311 mov esi, [rdx + CPUMCPU.fUseFlags] ; esi == use flags.
312 test esi, CPUM_SYNC_FPU_STATE
313 jz near gth_fpu_no
314
315%ifdef VBOX_WITH_CRASHDUMP_MAGIC
316 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 7
317%endif
318
319 mov rax, cr0
320 mov rcx, rax ; save old CR0
321 and rax, ~(X86_CR0_TS | X86_CR0_EM)
322 mov cr0, rax
323 fxrstor [rdx + CPUMCPU.Guest.fpu]
324 mov cr0, rcx ; and restore old CR0 again
325
326 and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_FPU_STATE
327
328gth_fpu_no:
329 ; Check if we need to restore the guest debug state
330 test esi, CPUM_SYNC_DEBUG_STATE
331 jz near gth_debug_no
332
333%ifdef VBOX_WITH_CRASHDUMP_MAGIC
334 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 8
335%endif
336
337 mov rax, qword [rdx + CPUMCPU.Guest.dr + 0*8]
338 mov dr0, rax
339 mov rax, qword [rdx + CPUMCPU.Guest.dr + 1*8]
340 mov dr1, rax
341 mov rax, qword [rdx + CPUMCPU.Guest.dr + 2*8]
342 mov dr2, rax
343 mov rax, qword [rdx + CPUMCPU.Guest.dr + 3*8]
344 mov dr3, rax
345 mov rax, qword [rdx + CPUMCPU.Guest.dr + 6*8]
346 mov dr6, rax ; not required for AMD-V
347
348 and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_DEBUG_STATE
349
350gth_debug_no:
351
352%ifdef VBOX_WITH_CRASHDUMP_MAGIC
353 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 9
354%endif
355
356 ; parameter for all helper functions (pCtx)
357 lea rsi, [rdx + CPUMCPU.Guest.fpu]
358 call r9
359
360 ; Load CPUM pointer into rdx
361 mov rdx, [NAME(pCpumIC) wrt rip]
362 CPUMCPU_FROM_CPUM(edx)
363
364%ifdef VBOX_WITH_CRASHDUMP_MAGIC
365 mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 10
366%endif
367
368 ; Save the return code
369 mov dword [rdx + CPUMCPU.u32RetCode], eax
370
371 ; now let's switch back
372 jmp NAME(VMMGCGuestToHostAsm) ; rax = returncode.
373
374ENDPROC vmmR0HostToGuestAsm
375
376
377;;
378; Trampoline for doing a call when starting the hyper visor execution.
379;
380; Push any arguments to the routine.
381; Push the argument frame size (cArg * 4).
382; Push the call target (_cdecl convention).
383; Push the address of this routine.
384;
385;
386BITS 64
387ALIGNCODE(16)
388BEGINPROC vmmGCCallTrampoline
389%ifdef DEBUG_STUFF
390 COM64_S_CHAR 'c'
391 COM64_S_CHAR 't'
392 COM64_S_CHAR '!'
393%endif
394 int3
395ENDPROC vmmGCCallTrampoline
396
397
398;;
399; The C interface.
400;
401BITS 64
402ALIGNCODE(16)
403BEGINPROC vmmGCGuestToHost
404%ifdef DEBUG_STUFF
405 push rsi
406 COM_NEWLINE
407 DEBUG_CHAR('b')
408 DEBUG_CHAR('a')
409 DEBUG_CHAR('c')
410 DEBUG_CHAR('k')
411 DEBUG_CHAR('!')
412 COM_NEWLINE
413 pop rsi
414%endif
415 int3
416ENDPROC vmmGCGuestToHost
417
418;;
419; VMMGCGuestToHostAsm
420;
421; This is an alternative entry point which we'll be using
422; when the we have saved the guest state already or we haven't
423; been messing with the guest at all.
424;
425; @param eax Return code.
426; @uses eax, edx, ecx (or it may use them in the future)
427;
428BITS 64
429ALIGNCODE(16)
430BEGINPROC VMMGCGuestToHostAsm
431 ;; We're still in the intermediate memory context!
432
433 ;;
434 ;; Switch to compatibility mode, placing ourselves in identity mapped code.
435 ;;
436 jmp far [NAME(fpIDEnterTarget) wrt rip]
437
438; 16:32 Pointer to IDEnterTarget.
439NAME(fpIDEnterTarget):
440 FIXUP FIX_ID_32BIT, 0, NAME(IDExitTarget) - NAME(Start)
441dd 0
442 FIXUP FIX_HYPER_CS, 0
443dd 0
444
445 ; We're now on identity mapped pages!
446ALIGNCODE(16)
447GLOBALNAME IDExitTarget
448BITS 32
449 DEBUG_CHAR('1')
450
451 ; 1. Deactivate long mode by turning off paging.
452 mov ebx, cr0
453 and ebx, ~X86_CR0_PG
454 mov cr0, ebx
455 DEBUG_CHAR('2')
456
457 ; 2. Load intermediate page table.
458 FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
459 mov edx, 0ffffffffh
460 mov cr3, edx
461 DEBUG_CHAR('3')
462
463 ; 3. Disable long mode.
464 mov ecx, MSR_K6_EFER
465 rdmsr
466 DEBUG_CHAR('5')
467 and eax, ~(MSR_K6_EFER_LME)
468 wrmsr
469 DEBUG_CHAR('6')
470
471%ifndef NEED_PAE_ON_HOST
472 ; 3b. Disable PAE.
473 mov eax, cr4
474 and eax, ~X86_CR4_PAE
475 mov cr4, eax
476 DEBUG_CHAR('7')
477%endif
478
479 ; 4. Enable paging.
480 or ebx, X86_CR0_PG
481 mov cr0, ebx
482 jmp short just_a_jump
483just_a_jump:
484 DEBUG_CHAR('8')
485
486 ;;
487 ;; 5. Jump to guest code mapping of the code and load the Hypervisor CS.
488 ;;
489 FIXUP FIX_ID_2_HC_NEAR_REL, 1, NAME(ICExitTarget) - NAME(Start)
490 jmp near NAME(ICExitTarget)
491
492 ;;
493 ;; When we arrive at this label we're at the
494 ;; intermediate mapping of the switching code.
495 ;;
496BITS 32
497ALIGNCODE(16)
498GLOBALNAME ICExitTarget
499 DEBUG_CHAR('8')
500
501 ; load the hypervisor data selector into ds & es
502 FIXUP FIX_HYPER_DS, 1
503 mov eax, 0ffffh
504 mov ds, eax
505 mov es, eax
506
507 FIXUP FIX_GC_CPUMCPU_OFF, 1, 0
508 mov edx, 0ffffffffh
509 mov esi, [edx + CPUMCPU.Host.cr3]
510 mov cr3, esi
511
512 ;; now we're in host memory context, let's restore regs
513 FIXUP FIX_HC_CPUM_OFF, 1, 0
514 mov edx, 0ffffffffh
515 CPUMCPU_FROM_CPUM(edx)
516
517 ; restore the host EFER
518 mov ebx, edx
519 mov ecx, MSR_K6_EFER
520 mov eax, [ebx + CPUMCPU.Host.efer]
521 mov edx, [ebx + CPUMCPU.Host.efer + 4]
522 wrmsr
523 mov edx, ebx
524
525 ; activate host gdt and idt
526 lgdt [edx + CPUMCPU.Host.gdtr]
527 DEBUG_CHAR('0')
528 lidt [edx + CPUMCPU.Host.idtr]
529 DEBUG_CHAR('1')
530
531 ; Restore TSS selector; must mark it as not busy before using ltr (!)
532 ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
533 movzx eax, word [edx + CPUMCPU.Host.tr] ; eax <- TR
534 and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
535 add eax, [edx + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
536 and dword [eax + 4], ~0200h ; clear busy flag (2nd type2 bit)
537 ltr word [edx + CPUMCPU.Host.tr]
538
539 ; activate ldt
540 DEBUG_CHAR('2')
541 lldt [edx + CPUMCPU.Host.ldtr]
542
543 ; Restore segment registers
544 mov eax, [edx + CPUMCPU.Host.ds]
545 mov ds, eax
546 mov eax, [edx + CPUMCPU.Host.es]
547 mov es, eax
548 mov eax, [edx + CPUMCPU.Host.fs]
549 mov fs, eax
550 mov eax, [edx + CPUMCPU.Host.gs]
551 mov gs, eax
552 ; restore stack
553 lss esp, [edx + CPUMCPU.Host.esp]
554
555 ; Control registers.
556 mov ecx, [edx + CPUMCPU.Host.cr4]
557 mov cr4, ecx
558 mov ecx, [edx + CPUMCPU.Host.cr0]
559 mov cr0, ecx
560 ;mov ecx, [edx + CPUMCPU.Host.cr2] ; assumes this is waste of time.
561 ;mov cr2, ecx
562
563 ; restore general registers.
564 mov edi, [edx + CPUMCPU.Host.edi]
565 mov esi, [edx + CPUMCPU.Host.esi]
566 mov ebx, [edx + CPUMCPU.Host.ebx]
567 mov ebp, [edx + CPUMCPU.Host.ebp]
568
569 ; store the return code in eax
570 mov eax, [edx + CPUMCPU.u32RetCode]
571 retf
572ENDPROC VMMGCGuestToHostAsm
573
574;;
575; VMMGCGuestToHostAsmHyperCtx
576;
577; This is an alternative entry point which we'll be using
578; when the we have the hypervisor context and need to save
579; that before going to the host.
580;
581; This is typically useful when abandoning the hypervisor
582; because of a trap and want the trap state to be saved.
583;
584; @param eax Return code.
585; @param ecx Points to CPUMCTXCORE.
586; @uses eax,edx,ecx
587ALIGNCODE(16)
588BEGINPROC VMMGCGuestToHostAsmHyperCtx
589 int3
590
591;;
592; VMMGCGuestToHostAsmGuestCtx
593;
594; Switches from Guest Context to Host Context.
595; Of course it's only called from within the GC.
596;
597; @param eax Return code.
598; @param esp + 4 Pointer to CPUMCTXCORE.
599;
600; @remark ASSUMES interrupts disabled.
601;
602ALIGNCODE(16)
603BEGINPROC VMMGCGuestToHostAsmGuestCtx
604 int3
605
606GLOBALNAME End
607;
608; The description string (in the text section).
609;
610NAME(Description):
611 db SWITCHER_DESCRIPTION
612 db 0
613
614extern NAME(Relocate)
615
616;
617; End the fixup records.
618;
619BEGINDATA
620 db FIX_THE_END ; final entry.
621GLOBALNAME FixupsEnd
622
623;;
624; The switcher definition structure.
625ALIGNDATA(16)
626GLOBALNAME Def
627 istruc VMMSWITCHERDEF
628 at VMMSWITCHERDEF.pvCode, RTCCPTR_DEF NAME(Start)
629 at VMMSWITCHERDEF.pvFixups, RTCCPTR_DEF NAME(Fixups)
630 at VMMSWITCHERDEF.pszDesc, RTCCPTR_DEF NAME(Description)
631 at VMMSWITCHERDEF.pfnRelocate, RTCCPTR_DEF NAME(Relocate)
632 at VMMSWITCHERDEF.enmType, dd SWITCHER_TYPE
633 at VMMSWITCHERDEF.cbCode, dd NAME(End) - NAME(Start)
634 at VMMSWITCHERDEF.offR0HostToGuest, dd NAME(vmmR0HostToGuest) - NAME(Start)
635 at VMMSWITCHERDEF.offGCGuestToHost, dd NAME(vmmGCGuestToHost) - NAME(Start)
636 at VMMSWITCHERDEF.offGCCallTrampoline, dd NAME(vmmGCCallTrampoline) - NAME(Start)
637 at VMMSWITCHERDEF.offGCGuestToHostAsm, dd NAME(VMMGCGuestToHostAsm) - NAME(Start)
638 at VMMSWITCHERDEF.offGCGuestToHostAsmHyperCtx, dd NAME(VMMGCGuestToHostAsmHyperCtx)- NAME(Start)
639 at VMMSWITCHERDEF.offGCGuestToHostAsmGuestCtx, dd NAME(VMMGCGuestToHostAsmGuestCtx)- NAME(Start)
640 ; disasm help
641 at VMMSWITCHERDEF.offHCCode0, dd 0
642 at VMMSWITCHERDEF.cbHCCode0, dd NAME(IDEnterTarget) - NAME(Start)
643 at VMMSWITCHERDEF.offHCCode1, dd NAME(ICExitTarget) - NAME(Start)
644 at VMMSWITCHERDEF.cbHCCode1, dd NAME(End) - NAME(ICExitTarget)
645 at VMMSWITCHERDEF.offIDCode0, dd NAME(IDEnterTarget) - NAME(Start)
646 at VMMSWITCHERDEF.cbIDCode0, dd NAME(ICEnterTarget) - NAME(IDEnterTarget)
647 at VMMSWITCHERDEF.offIDCode1, dd NAME(IDExitTarget) - NAME(Start)
648 at VMMSWITCHERDEF.cbIDCode1, dd NAME(ICExitTarget) - NAME(Start)
649 at VMMSWITCHERDEF.offGCCode, dd 0
650 at VMMSWITCHERDEF.cbGCCode, dd 0
651
652 iend
653
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette