AMD64andLegacy.mac@ 26753

Last change on this file since 26753 was 21946, checked in by vboxsync, 15 years ago
AMD64andLegacy.mac: CPUM.ulOffCPUMCPU is 32-bit.
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1	; $Id: AMD64andLegacy.mac 21946 2009-08-03 15:32:17Z vboxsync $
2	;; @file
3	; VMM - World Switchers, template for AMD64 to PAE and 32-bit.
4	;
5
6	;
7	; Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17	; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	; Clara, CA 95054 USA or visit http://www.sun.com if you need
19	; additional information or have any questions.
20	;
21
22	;%define DEBUG_STUFF 1
23	;%define STRICT_IF 1
24
25	;*******************************************************************************
26	;* Header Files *
27	;*******************************************************************************
28	%include "VBox/asmdefs.mac"
29	%include "VBox/x86.mac"
30	%include "VBox/cpum.mac"
31	%include "VBox/stam.mac"
32	%include "VBox/vm.mac"
33	%include "CPUMInternal.mac"
34	%include "VMMSwitcher/VMMSwitcher.mac"
35
36
37	;
38	; Start the fixup records
39	; We collect the fixups in the .data section as we go along
40	; It is therefore VITAL that no-one is using the .data section
41	; for anything else between 'Start' and 'End'.
42	;
43	BEGINDATA
44	GLOBALNAME Fixups
45
46
47
48	BEGINCODE
49	GLOBALNAME Start
50
51	%ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
52	BITS 64
53
54	;;
55	; The C interface.
56	;
57	; @param pVM GCC: rdi MSC:rcx The VM handle.
58	;
59	BEGINPROC vmmR0HostToGuest
60	%ifdef DEBUG_STUFF
61	COM64_S_NEWLINE
62	COM64_S_CHAR '^'
63	%endif
64	;
65	; The ordinary version of the code.
66	;
67
68	%ifdef STRICT_IF
69	pushf
70	pop rax
71	test eax, X86_EFL_IF
72	jz .if_clear_in
73	mov eax, 0c0ffee00h
74	ret
75	.if_clear_in:
76	%endif
77
78	;
79	; make r9 = pVM and rdx = pCpum.
80	; rax, rcx and r8 are scratch here after.
81	%ifdef RT_OS_WINDOWS
82	mov r9, rcx
83	%else
84	mov r9, rdi
85	%endif
86	lea rdx, [r9 + VM.cpum]
87
88	%ifdef VBOX_WITH_STATISTICS
89	;
90	; Switcher stats.
91	;
92	lea r8, [r9 + VM.StatSwitcherToGC]
93	STAM64_PROFILE_ADV_START r8
94	%endif
95
96	;
97	; Call worker (far return).
98	;
99	mov eax, cs
100	push rax
101	call NAME(vmmR0HostToGuestAsm)
102
103	%ifdef VBOX_WITH_STATISTICS
104	;
105	; Switcher stats.
106	;
107	lea r8, [r9 + VM.StatSwitcherToGC]
108	STAM64_PROFILE_ADV_STOP r8
109	%endif
110
111	ret
112	ENDPROC vmmR0HostToGuest
113
114
115	%else ; VBOX_WITH_HYBRID_32BIT_KERNEL
116
117
118	BITS 32
119
120	;;
121	; The C interface.
122	;
123	BEGINPROC vmmR0HostToGuest
124	%ifdef DEBUG_STUFF
125	COM32_S_NEWLINE
126	COM32_S_CHAR '^'
127	%endif
128
129	%ifdef VBOX_WITH_STATISTICS
130	;
131	; Switcher stats.
132	;
133	FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToGC
134	mov edx, 0ffffffffh
135	STAM_PROFILE_ADV_START edx
136	%endif
137
138	; Thunk to/from 64 bit when invoking the worker routine.
139	;
140	FIXUP FIX_HC_VM_OFF, 1, VM.cpum
141	mov edx, 0ffffffffh
142
143	push 0
144	push cs
145	push 0
146	FIXUP FIX_HC_32BIT, 1, .vmmR0HostToGuestReturn - NAME(Start)
147	push 0ffffffffh
148
149	FIXUP FIX_HC_64BIT_CS, 1
150	push 0ffffh
151	FIXUP FIX_HC_32BIT, 1, NAME(vmmR0HostToGuestAsm) - NAME(Start)
152	push 0ffffffffh
153	retf
154	.vmmR0HostToGuestReturn:
155
156	;
157	; This selector reloading is probably not necessary, but we do it anyway to be quite sure
158	; the CPU has the right idea about the selectors.
159	;
160	mov edx, ds
161	mov ds, edx
162	mov ecx, es
163	mov es, ecx
164	mov edx, ss
165	mov ss, edx
166
167	%ifdef VBOX_WITH_STATISTICS
168	;
169	; Switcher stats.
170	;
171	FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToHC
172	mov edx, 0ffffffffh
173	STAM_PROFILE_ADV_STOP edx
174	%endif
175
176	ret
177	ENDPROC vmmR0HostToGuest
178
179	BITS 64
180	%endif ;!VBOX_WITH_HYBRID_32BIT_KERNEL
181
182
183
184	; *****************************************************************************
185	; vmmR0HostToGuestAsm
186	;
187	; Phase one of the switch from host to guest context (host MMU context)
188	;
189	; INPUT:
190	; - edx virtual address of CPUM structure (valid in host context)
191	;
192	; USES/DESTROYS:
193	; - eax, ecx, edx, r8
194	;
195	; ASSUMPTION:
196	; - current CS and DS selectors are wide open
197	;
198	; *****************************************************************************
199	ALIGNCODE(16)
200	BEGINPROC vmmR0HostToGuestAsm
201	;; Store the offset from CPUM to CPUMCPU in r8
202	mov r8d, [rdx + CPUM.ulOffCPUMCPU]
203
204	;;
205	;; Save CPU host context
206	;; Skip eax, edx and ecx as these are not preserved over calls.
207	;;
208	; general registers.
209	; mov [rdx + r8 + CPUMCPU.Host.rax], rax - scratch
210	mov [rdx + r8 + CPUMCPU.Host.rbx], rbx
211	; mov [rdx + r8 + CPUMCPU.Host.rcx], rcx - scratch
212	; mov [rdx + r8 + CPUMCPU.Host.rdx], rdx - scratch
213	mov [rdx + r8 + CPUMCPU.Host.rdi], rdi
214	mov [rdx + r8 + CPUMCPU.Host.rsi], rsi
215	mov [rdx + r8 + CPUMCPU.Host.rsp], rsp
216	mov [rdx + r8 + CPUMCPU.Host.rbp], rbp
217	; mov [rdx + r8 + CPUMCPU.Host.r8 ], r8 - scratch
218	; mov [rdx + r8 + CPUMCPU.Host.r9 ], r9 - scratch
219	mov [rdx + r8 + CPUMCPU.Host.r10], r10
220	mov [rdx + r8 + CPUMCPU.Host.r11], r11
221	mov [rdx + r8 + CPUMCPU.Host.r12], r12
222	mov [rdx + r8 + CPUMCPU.Host.r13], r13
223	mov [rdx + r8 + CPUMCPU.Host.r14], r14
224	mov [rdx + r8 + CPUMCPU.Host.r15], r15
225	; selectors.
226	mov [rdx + r8 + CPUMCPU.Host.ds], ds
227	mov [rdx + r8 + CPUMCPU.Host.es], es
228	mov [rdx + r8 + CPUMCPU.Host.fs], fs
229	mov [rdx + r8 + CPUMCPU.Host.gs], gs
230	mov [rdx + r8 + CPUMCPU.Host.ss], ss
231	; MSRs
232	mov rbx, rdx
233	mov ecx, MSR_K8_FS_BASE
234	rdmsr
235	mov [rbx + r8 + CPUMCPU.Host.FSbase], eax
236	mov [rbx + r8 + CPUMCPU.Host.FSbase + 4], edx
237	mov ecx, MSR_K8_GS_BASE
238	rdmsr
239	mov [rbx + r8 + CPUMCPU.Host.GSbase], eax
240	mov [rbx + r8 + CPUMCPU.Host.GSbase + 4], edx
241	mov ecx, MSR_K6_EFER
242	rdmsr
243	mov [rbx + r8 + CPUMCPU.Host.efer], eax
244	mov [rbx + r8 + CPUMCPU.Host.efer + 4], edx
245	mov ecx, MSR_K6_EFER
246	mov rdx, rbx
247	; special registers.
248	sldt [rdx + r8 + CPUMCPU.Host.ldtr]
249	sidt [rdx + r8 + CPUMCPU.Host.idtr]
250	sgdt [rdx + r8 + CPUMCPU.Host.gdtr]
251	str [rdx + r8 + CPUMCPU.Host.tr] ; yasm BUG, generates sldt. YASMCHECK!
252	; flags
253	pushf
254	pop qword [rdx + r8 + CPUMCPU.Host.rflags]
255
256	FIXUP FIX_NO_SYSENTER_JMP, 0, htg_no_sysenter - NAME(Start) ; this will insert a jmp htg_no_sysenter if host doesn't use sysenter.
257	; save MSR_IA32_SYSENTER_CS register.
258	mov rbx, rdx ; save edx
259	mov ecx, MSR_IA32_SYSENTER_CS
260	rdmsr ; edx:eax <- MSR[ecx]
261	mov [rbx + r8 + CPUMCPU.Host.SysEnter.cs], eax
262	mov [rbx + r8 + CPUMCPU.Host.SysEnter.cs + 4], edx
263	xor eax, eax ; load 0:0 to cause #GP upon sysenter
264	xor edx, edx
265	wrmsr
266	mov rdx, rbx ; restore edx
267	jmp short htg_no_sysenter
268
269	ALIGNCODE(16)
270	htg_no_sysenter:
271
272	;; handle use flags.
273	mov esi, [rdx + r8 + CPUMCPU.fUseFlags] ; esi == use flags.
274	and esi, ~CPUM_USED_FPU ; Clear CPUM_USED_* flags. ;;@todo FPU check can be optimized to use cr0 flags!
275	mov [rdx + r8 + CPUMCPU.fUseFlags], esi
276
277	; debug registers.
278	test esi, CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HOST
279	jz htg_debug_regs_no
280	jmp htg_debug_regs_save
281	htg_debug_regs_no:
282	DEBUG_CHAR('a') ; trashes esi
283
284	; control registers.
285	mov rax, cr0
286	mov [rdx + r8 + CPUMCPU.Host.cr0], rax
287	;mov rax, cr2 ; assume host os don't stuff things in cr2. (safe)
288	;mov [rdx + r8 + CPUMCPU.Host.cr2], rax
289	mov rax, cr3
290	mov [rdx + r8 + CPUMCPU.Host.cr3], rax
291	mov rax, cr4
292	mov [rdx + r8 + CPUMCPU.Host.cr4], rax
293
294	;;
295	;; Start switching to VMM context.
296	;;
297
298	;
299	; Change CR0 and CR4 so we can correctly emulate FPU/MMX/SSE[23] exceptions
300	; Also disable WP. (eax==cr4 now)
301	; Note! X86_CR4_PSE and X86_CR4_PAE are important if the host thinks so :-)
302	;
303	and rax, X86_CR4_MCE \| X86_CR4_PSE \| X86_CR4_PAE
304	mov ecx, [rdx + r8 + CPUMCPU.Guest.cr4]
305	DEBUG_CHAR('b') ; trashes esi
306	;; @todo Switcher cleanup: Determine base CR4 during CPUMR0Init / VMMR3SelectSwitcher putting it
307	; in CPUMCPU.Hyper.cr4 (which isn't currently being used). That should
308	; simplify this operation a bit (and improve locality of the data).
309
310	;
311	; CR4.AndMask and CR4.OrMask are set in CPUMR3Init based on the presence of
312	; FXSAVE support on the host CPU
313	;
314	and ecx, [rdx + CPUM.CR4.AndMask]
315	or eax, ecx
316	or eax, [rdx + CPUM.CR4.OrMask]
317	mov cr4, rax
318	DEBUG_CHAR('c') ; trashes esi
319
320	mov eax, [rdx + r8 + CPUMCPU.Guest.cr0]
321	and eax, X86_CR0_EM
322	or eax, X86_CR0_PE \| X86_CR0_PG \| X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP
323	mov cr0, rax
324	DEBUG_CHAR('0') ; trashes esi
325
326
327	; Load new gdt so we can do far jump to guest code after cr3 reload.
328	lgdt [rdx + r8 + CPUMCPU.Hyper.gdtr]
329	DEBUG_CHAR('1') ; trashes esi
330
331	; Store the hypervisor cr3 for later loading
332	mov ebp, [rdx + r8 + CPUMCPU.Hyper.cr3]
333
334	;;
335	;; Load Intermediate memory context.
336	;;
337	FIXUP FIX_INTER_AMD64_CR3, 1
338	mov eax, 0ffffffffh
339	mov cr3, rax
340	DEBUG_CHAR('2') ; trashes esi
341
342	;;
343	;; 1. Switch to compatibility mode, placing ourselves in identity mapped code.
344	;;
345	jmp far [NAME(fpIDEnterTarget) wrt rip]
346
347	; 16:32 Pointer to IDEnterTarget.
348	NAME(fpIDEnterTarget):
349	FIXUP FIX_ID_32BIT, 0, NAME(IDEnterTarget) - NAME(Start)
350	dd 0
351	FIXUP FIX_HYPER_CS, 0
352	dd 0
353
354
355	;;
356	; Detour for saving the host DR7 and DR6.
357	; esi and rdx must be preserved.
358	htg_debug_regs_save:
359	DEBUG_S_CHAR('s');
360	mov rax, dr7 ; not sure, but if I read the docs right this will trap if GD is set. FIXME!!!
361	mov [rdx + r8 + CPUMCPU.Host.dr7], rax
362	xor eax, eax ; clear everything. (bit 12? is read as 1...)
363	mov dr7, rax
364	mov rax, dr6 ; just in case we save the state register too.
365	mov [rdx + r8 + CPUMCPU.Host.dr6], rax
366	; save host DR0-3?
367	test esi, CPUM_USE_DEBUG_REGS
368	jz near htg_debug_regs_no
369	DEBUG_S_CHAR('S');
370	mov rax, dr0
371	mov [rdx + r8 + CPUMCPU.Host.dr0], rax
372	mov rbx, dr1
373	mov [rdx + r8 + CPUMCPU.Host.dr1], rbx
374	mov rcx, dr2
375	mov [rdx + r8 + CPUMCPU.Host.dr2], rcx
376	mov rax, dr3
377	mov [rdx + r8 + CPUMCPU.Host.dr3], rax
378	jmp htg_debug_regs_no
379
380
381	; We're now on an identity mapped pages! in 32-bit compatability mode.
382	BITS 32
383	ALIGNCODE(16)
384	GLOBALNAME IDEnterTarget
385	DEBUG_CHAR('3')
386
387	; 2. Deactivate long mode by turning off paging.
388	mov ebx, cr0
389	and ebx, ~X86_CR0_PG
390	mov cr0, ebx
391	DEBUG_CHAR('4')
392
393	; 3. Load intermediate page table.
394	FIXUP SWITCHER_FIX_INTER_CR3_GC, 1
395	mov edx, 0ffffffffh
396	mov cr3, edx
397
398	; 4. Disable long mode.
399	; We also use the chance to disable syscall/sysret and fast fxsave/fxrstor.
400	mov ecx, MSR_K6_EFER
401	rdmsr
402	DEBUG_CHAR('5')
403	and eax, ~(MSR_K6_EFER_LME \| MSR_K6_EFER_SCE \| MSR_K6_EFER_FFXSR)
404	wrmsr
405	DEBUG_CHAR('6')
406
407	%ifndef SWITCHER_TO_PAE
408	; 4b. Disable PAE.
409	mov eax, cr4
410	and eax, ~X86_CR4_PAE
411	mov cr4, eax
412	%else
413	%endif
414
415	; 5. Enable paging.
416	or ebx, X86_CR0_PG
417	mov cr0, ebx
418	jmp short just_a_jump
419	just_a_jump:
420	DEBUG_CHAR('7')
421
422	;;
423	;; 6. Jump to guest code mapping of the code and load the Hypervisor CS.
424	;;
425	FIXUP FIX_ID_2_GC_NEAR_REL, 1, NAME(JmpGCTarget) - NAME(Start)
426	jmp near NAME(JmpGCTarget)
427
428
429	;;
430	;; When we arrive at this label we're at the
431	;; guest code mapping of the switching code.
432	;;
433	ALIGNCODE(16)
434	GLOBALNAME JmpGCTarget
435	DEBUG_CHAR('-')
436	;mov eax, 0ffff0000h
437	;.delay_loop:
438	;nop
439	;dec eax
440	;nop
441	;jnz .delay_loop
442	; load final cr3 and do far jump to load cs.
443	mov cr3, ebp ; ebp set above
444	DEBUG_CHAR('0')
445
446	;;
447	;; We're in VMM MMU context and VMM CS is loaded.
448	;; Setup the rest of the VMM state.
449	;;
450	; Load selectors
451	DEBUG_CHAR('1')
452	FIXUP FIX_HYPER_DS, 1
453	mov eax, 0ffffh
454	mov ds, eax
455	mov es, eax
456	xor eax, eax
457	mov gs, eax
458	mov fs, eax
459	; Load pCpum into EDX
460	FIXUP FIX_GC_CPUMCPU_OFF, 1, 0
461	mov edx, 0ffffffffh
462	; Activate guest IDT
463	DEBUG_CHAR('2')
464	lidt [edx + CPUMCPU.Hyper.idtr]
465
466	; Setup stack; use the lss_esp, ss pair for lss
467	DEBUG_CHAR('3')
468	mov eax, [edx + CPUMCPU.Hyper.esp]
469	mov [edx + CPUMCPU.Hyper.lss_esp], eax
470	lss esp, [edx + CPUMCPU.Hyper.lss_esp]
471
472	; Restore TSS selector; must mark it as not busy before using ltr (!)
473	DEBUG_CHAR('4')
474	FIXUP FIX_GC_TSS_GDTE_DW2, 2
475	and dword [0ffffffffh], ~0200h ; clear busy flag (2nd type2 bit)
476	DEBUG_CHAR('5')
477	ltr word [edx + CPUMCPU.Hyper.tr]
478	DEBUG_CHAR('6')
479
480	; Activate the ldt (now we can safely crash).
481	lldt [edx + CPUMCPU.Hyper.ldtr]
482	DEBUG_CHAR('7')
483
484	;; use flags.
485	mov esi, [edx + CPUMCPU.fUseFlags]
486
487	; debug registers
488	test esi, CPUM_USE_DEBUG_REGS
489	jz htg_debug_regs_guest_no
490	jmp htg_debug_regs_guest
491	htg_debug_regs_guest_no:
492	DEBUG_CHAR('9')
493
494	; General registers.
495	mov ebx, [edx + CPUMCPU.Hyper.ebx]
496	mov ebp, [edx + CPUMCPU.Hyper.ebp]
497	mov esi, [edx + CPUMCPU.Hyper.esi]
498	mov edi, [edx + CPUMCPU.Hyper.edi]
499	push dword [edx + CPUMCPU.Hyper.eflags]
500	popfd
501	DEBUG_CHAR('!')
502
503	;;
504	;; Return to the VMM code which either called the switcher or
505	;; the code set up to run by HC.
506	;;
507	%ifdef DEBUG_STUFF
508	COM32_S_PRINT ';eip='
509	mov eax, [edx + CPUMCPU.Hyper.eip]
510	COM32_S_DWORD_REG eax
511	COM32_S_CHAR ';'
512	%endif
513	mov eax, [edx + CPUMCPU.Hyper.eip]
514	; callees expect CPUM ptr
515	CPUM_FROM_CPUMCPU(edx)
516
517	%ifdef VBOX_WITH_STATISTICS
518	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToGC
519	mov edx, 0ffffffffh
520	STAM32_PROFILE_ADV_STOP edx
521	FIXUP FIX_GC_CPUM_OFF, 1, 0
522	mov edx, 0ffffffffh
523	%endif
524	jmp eax
525
526	;;
527	; Detour for saving host DR0-3 and loading hypervisor debug registers.
528	; esi and edx must be preserved.
529	htg_debug_regs_guest:
530	DEBUG_S_CHAR('D')
531	DEBUG_S_CHAR('R')
532	DEBUG_S_CHAR('x')
533	; load hyper DR0-7
534	mov ebx, [edx + CPUMCPU.Hyper.dr]
535	mov dr0, ebx
536	mov ecx, [edx + CPUMCPU.Hyper.dr + 8*1]
537	mov dr1, ecx
538	mov eax, [edx + CPUMCPU.Hyper.dr + 8*2]
539	mov dr2, eax
540	mov ebx, [edx + CPUMCPU.Hyper.dr + 8*3]
541	mov dr3, ebx
542	;mov eax, [edx + CPUMCPU.Hyper.dr + 8*6]
543	mov ecx, 0ffff0ff0h
544	mov dr6, ecx
545	mov eax, [edx + CPUMCPU.Hyper.dr + 8*7]
546	mov dr7, eax
547	jmp htg_debug_regs_guest_no
548
549	ENDPROC vmmR0HostToGuestAsm
550
551
552	;;
553	; Trampoline for doing a call when starting the hyper visor execution.
554	;
555	; Push any arguments to the routine.
556	; Push the argument frame size (cArg * 4).
557	; Push the call target (_cdecl convention).
558	; Push the address of this routine.
559	;
560	;
561	ALIGNCODE(16)
562	BEGINPROC vmmGCCallTrampoline
563	%ifdef DEBUG_STUFF
564	COM32_S_CHAR 'c'
565	COM32_S_CHAR 't'
566	COM32_S_CHAR '!'
567	%endif
568
569	; call routine
570	pop eax ; call address
571	mov esi, edx ; save edx
572	pop edi ; argument count.
573	%ifdef DEBUG_STUFF
574	COM32_S_PRINT ';eax='
575	COM32_S_DWORD_REG eax
576	COM32_S_CHAR ';'
577	%endif
578	call eax ; do call
579	add esp, edi ; cleanup stack
580
581	; return to the host context.
582	push byte 0 ; eip
583	mov edx, esi ; CPUM pointer
584
585	%ifdef DEBUG_STUFF
586	COM32_S_CHAR '`'
587	%endif
588	jmp NAME(VMMGCGuestToHostAsm) ; eax = returncode.
589	ENDPROC vmmGCCallTrampoline
590
591
592
593	;;
594	; The C interface.
595	;
596	ALIGNCODE(16)
597	BEGINPROC vmmGCGuestToHost
598	%ifdef DEBUG_STUFF
599	push esi
600	COM_NEWLINE
601	DEBUG_CHAR('b')
602	DEBUG_CHAR('a')
603	DEBUG_CHAR('c')
604	DEBUG_CHAR('k')
605	DEBUG_CHAR('!')
606	COM_NEWLINE
607	pop esi
608	%endif
609	mov eax, [esp + 4]
610	jmp NAME(VMMGCGuestToHostAsm)
611	ENDPROC vmmGCGuestToHost
612
613
614	;;
615	; VMMGCGuestToHostAsmGuestCtx
616	;
617	; Switches from Guest Context to Host Context.
618	; Of course it's only called from within the GC.
619	;
620	; @param eax Return code.
621	; @param esp + 4 Pointer to CPUMCTXCORE.
622	;
623	; @remark ASSUMES interrupts disabled.
624	;
625	ALIGNCODE(16)
626	BEGINPROC VMMGCGuestToHostAsmGuestCtx
627	DEBUG_CHAR('~')
628
629	%ifdef VBOX_WITH_STATISTICS
630	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalInGC
631	mov edx, 0ffffffffh
632	STAM32_PROFILE_ADV_STOP edx
633
634	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalGCToQemu
635	mov edx, 0ffffffffh
636	STAM32_PROFILE_ADV_START edx
637
638	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToHC
639	mov edx, 0ffffffffh
640	STAM32_PROFILE_ADV_START edx
641	%endif
642
643	;
644	; Load the CPUMCPU pointer.
645	;
646	FIXUP FIX_GC_CPUMCPU_OFF, 1, 0
647	mov edx, 0ffffffffh
648
649	; Skip return address (assumes called!)
650	lea esp, [esp + 4]
651
652	;
653	; Guest Context (assumes esp now points to CPUMCTXCORE structure).
654	;
655	; general purpose registers
656	push eax ; save return code.
657	mov eax, [esp + 4 + CPUMCTXCORE.edi]
658	mov [edx + CPUMCPU.Guest.edi], eax
659	mov eax, [esp + 4 + CPUMCTXCORE.esi]
660	mov [edx + CPUMCPU.Guest.esi], eax
661	mov eax, [esp + 4 + CPUMCTXCORE.ebp]
662	mov [edx + CPUMCPU.Guest.ebp], eax
663	mov eax, [esp + 4 + CPUMCTXCORE.eax]
664	mov [edx + CPUMCPU.Guest.eax], eax
665	mov eax, [esp + 4 + CPUMCTXCORE.ebx]
666	mov [edx + CPUMCPU.Guest.ebx], eax
667	mov eax, [esp + 4 + CPUMCTXCORE.edx]
668	mov [edx + CPUMCPU.Guest.edx], eax
669	mov eax, [esp + 4 + CPUMCTXCORE.ecx]
670	mov [edx + CPUMCPU.Guest.ecx], eax
671	mov eax, [esp + 4 + CPUMCTXCORE.esp]
672	mov [edx + CPUMCPU.Guest.esp], eax
673	; selectors
674	mov eax, [esp + 4 + CPUMCTXCORE.ss]
675	mov [edx + CPUMCPU.Guest.ss], eax
676	mov eax, [esp + 4 + CPUMCTXCORE.gs]
677	mov [edx + CPUMCPU.Guest.gs], eax
678	mov eax, [esp + 4 + CPUMCTXCORE.fs]
679	mov [edx + CPUMCPU.Guest.fs], eax
680	mov eax, [esp + 4 + CPUMCTXCORE.es]
681	mov [edx + CPUMCPU.Guest.es], eax
682	mov eax, [esp + 4 + CPUMCTXCORE.ds]
683	mov [edx + CPUMCPU.Guest.ds], eax
684	mov eax, [esp + 4 + CPUMCTXCORE.cs]
685	mov [edx + CPUMCPU.Guest.cs], eax
686	; flags
687	mov eax, [esp + 4 + CPUMCTXCORE.eflags]
688	mov [edx + CPUMCPU.Guest.eflags], eax
689	; eip
690	mov eax, [esp + 4 + CPUMCTXCORE.eip]
691	mov [edx + CPUMCPU.Guest.eip], eax
692	; jump to common worker code.
693	pop eax ; restore return code.
694
695	add esp, CPUMCTXCORE_size ; skip CPUMCTXCORE structure
696
697	jmp vmmGCGuestToHostAsm_EIPDone
698	ENDPROC VMMGCGuestToHostAsmGuestCtx
699
700
701	;;
702	; VMMGCGuestToHostAsmHyperCtx
703	;
704	; This is an alternative entry point which we'll be using
705	; when the we have the hypervisor context and need to save
706	; that before going to the host.
707	;
708	; This is typically useful when abandoning the hypervisor
709	; because of a trap and want the trap state to be saved.
710	;
711	; @param eax Return code.
712	; @param ecx Points to CPUMCTXCORE.
713	; @uses eax,edx,ecx
714	ALIGNCODE(16)
715	BEGINPROC VMMGCGuestToHostAsmHyperCtx
716	DEBUG_CHAR('#')
717
718	%ifdef VBOX_WITH_STATISTICS
719	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalInGC
720	mov edx, 0ffffffffh
721	STAM32_PROFILE_ADV_STOP edx
722
723	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalGCToQemu
724	mov edx, 0ffffffffh
725	STAM32_PROFILE_ADV_START edx
726
727	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToHC
728	mov edx, 0ffffffffh
729	STAM32_PROFILE_ADV_START edx
730	%endif
731
732	;
733	; Load the CPUM pointer.
734	;
735	FIXUP FIX_GC_CPUMCPU_OFF, 1, 0
736	mov edx, 0ffffffffh
737
738	push eax ; save return code.
739	; general purpose registers
740	mov eax, [ecx + CPUMCTXCORE.edi]
741	mov [edx + CPUMCPU.Hyper.edi], eax
742	mov eax, [ecx + CPUMCTXCORE.esi]
743	mov [edx + CPUMCPU.Hyper.esi], eax
744	mov eax, [ecx + CPUMCTXCORE.ebp]
745	mov [edx + CPUMCPU.Hyper.ebp], eax
746	mov eax, [ecx + CPUMCTXCORE.eax]
747	mov [edx + CPUMCPU.Hyper.eax], eax
748	mov eax, [ecx + CPUMCTXCORE.ebx]
749	mov [edx + CPUMCPU.Hyper.ebx], eax
750	mov eax, [ecx + CPUMCTXCORE.edx]
751	mov [edx + CPUMCPU.Hyper.edx], eax
752	mov eax, [ecx + CPUMCTXCORE.ecx]
753	mov [edx + CPUMCPU.Hyper.ecx], eax
754	mov eax, [ecx + CPUMCTXCORE.esp]
755	mov [edx + CPUMCPU.Hyper.esp], eax
756	; selectors
757	mov eax, [ecx + CPUMCTXCORE.ss]
758	mov [edx + CPUMCPU.Hyper.ss], eax
759	mov eax, [ecx + CPUMCTXCORE.gs]
760	mov [edx + CPUMCPU.Hyper.gs], eax
761	mov eax, [ecx + CPUMCTXCORE.fs]
762	mov [edx + CPUMCPU.Hyper.fs], eax
763	mov eax, [ecx + CPUMCTXCORE.es]
764	mov [edx + CPUMCPU.Hyper.es], eax
765	mov eax, [ecx + CPUMCTXCORE.ds]
766	mov [edx + CPUMCPU.Hyper.ds], eax
767	mov eax, [ecx + CPUMCTXCORE.cs]
768	mov [edx + CPUMCPU.Hyper.cs], eax
769	; flags
770	mov eax, [ecx + CPUMCTXCORE.eflags]
771	mov [edx + CPUMCPU.Hyper.eflags], eax
772	; eip
773	mov eax, [ecx + CPUMCTXCORE.eip]
774	mov [edx + CPUMCPU.Hyper.eip], eax
775	; jump to common worker code.
776	pop eax ; restore return code.
777	jmp vmmGCGuestToHostAsm_SkipHyperRegs
778
779	ENDPROC VMMGCGuestToHostAsmHyperCtx
780
781
782	;;
783	; VMMGCGuestToHostAsm
784	;
785	; This is an alternative entry point which we'll be using
786	; when the we have saved the guest state already or we haven't
787	; been messing with the guest at all.
788	;
789	; @param eax Return code.
790	; @uses eax, edx, ecx (or it may use them in the future)
791	;
792	ALIGNCODE(16)
793	BEGINPROC VMMGCGuestToHostAsm
794	DEBUG_CHAR('%')
795
796	%ifdef VBOX_WITH_STATISTICS
797	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalInGC
798	mov edx, 0ffffffffh
799	STAM32_PROFILE_ADV_STOP edx
800
801	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalGCToQemu
802	mov edx, 0ffffffffh
803	STAM32_PROFILE_ADV_START edx
804
805	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToHC
806	mov edx, 0ffffffffh
807	STAM32_PROFILE_ADV_START edx
808	%endif
809
810	;
811	; Load the CPUM pointer.
812	;
813	FIXUP FIX_GC_CPUMCPU_OFF, 1, 0
814	mov edx, 0ffffffffh
815
816	pop dword [edx + CPUMCPU.Hyper.eip] ; call return from stack
817	jmp short vmmGCGuestToHostAsm_EIPDone
818
819	ALIGNCODE(16)
820	vmmGCGuestToHostAsm_EIPDone:
821	; general registers which we care about.
822	mov dword [edx + CPUMCPU.Hyper.ebx], ebx
823	mov dword [edx + CPUMCPU.Hyper.esi], esi
824	mov dword [edx + CPUMCPU.Hyper.edi], edi
825	mov dword [edx + CPUMCPU.Hyper.ebp], ebp
826	mov dword [edx + CPUMCPU.Hyper.esp], esp
827
828	; special registers which may change.
829	vmmGCGuestToHostAsm_SkipHyperRegs:
830	%ifdef STRICT_IF
831	pushf
832	pop ecx
833	test ecx, X86_EFL_IF
834	jz .if_clear_out
835	mov eax, 0c0ffee01h
836	cli
837	.if_clear_out:
838	%endif
839	; str [edx + CPUMCPU.Hyper.tr] - double fault only, and it won't be right then either.
840	sldt [edx + CPUMCPU.Hyper.ldtr]
841
842	; No need to save CRx here. They are set dynamically according to Guest/Host requirements.
843	; FPU context is saved before restore of host saving (another) branch.
844
845
846	;;
847	;; Load Intermediate memory context.
848	;;
849	mov edi, eax ; save return code in EDI (careful with COM_DWORD_REG from here on!)
850	FIXUP SWITCHER_FIX_INTER_CR3_GC, 1
851	mov eax, 0ffffffffh
852	mov cr3, eax
853	DEBUG_CHAR('?')
854
855	;; We're now in intermediate memory context!
856
857	;;
858	;; 0. Jump to identity mapped location
859	;;
860	FIXUP FIX_GC_2_ID_NEAR_REL, 1, NAME(IDExitTarget) - NAME(Start)
861	jmp near NAME(IDExitTarget)
862
863	; We're now on identity mapped pages!
864	ALIGNCODE(16)
865	GLOBALNAME IDExitTarget
866	DEBUG_CHAR('1')
867
868	; 1. Disable paging.
869	mov ebx, cr0
870	and ebx, ~X86_CR0_PG
871	mov cr0, ebx
872	DEBUG_CHAR('2')
873
874	; 2. Enable PAE.
875	%ifdef SWITCHER_TO_PAE
876	; - already enabled
877	%else
878	mov ecx, cr4
879	or ecx, X86_CR4_PAE
880	mov cr4, ecx
881	%endif
882
883	; 3. Load long mode intermediate CR3.
884	FIXUP FIX_INTER_AMD64_CR3, 1
885	mov ecx, 0ffffffffh
886	mov cr3, ecx
887	DEBUG_CHAR('3')
888
889	; 4. Enable long mode.
890	mov ebp, edx
891	mov ecx, MSR_K6_EFER
892	rdmsr
893	or eax, MSR_K6_EFER_LME
894	wrmsr
895	mov edx, ebp
896	DEBUG_CHAR('4')
897
898	; 5. Enable paging.
899	or ebx, X86_CR0_PG
900	mov cr0, ebx
901	DEBUG_CHAR('5')
902
903	; Jump from compatability mode to 64-bit mode.
904	FIXUP FIX_ID_FAR32_TO_64BIT_MODE, 1, NAME(IDExit64Mode) - NAME(Start)
905	jmp 0ffffh:0fffffffeh
906
907	;
908	; We're in 64-bit mode (ds, ss, es, fs, gs are all bogus).
909	; Move on to the HC mapping.
910	;
911	BITS 64
912	ALIGNCODE(16)
913	NAME(IDExit64Mode):
914	DEBUG_CHAR('6')
915	jmp [NAME(pHCExitTarget) wrt rip]
916
917	; 64-bit jump target
918	NAME(pHCExitTarget):
919	FIXUP FIX_HC_64BIT, 0, NAME(HCExitTarget) - NAME(Start)
920	dq 0ffffffffffffffffh
921
922	; 64-bit pCpum address.
923	NAME(pCpumHC):
924	FIXUP FIX_HC_64BIT_CPUM, 0
925	dq 0ffffffffffffffffh
926
927	;
928	; When we arrive here we're at the host context
929	; mapping of the switcher code.
930	;
931	ALIGNCODE(16)
932	GLOBALNAME HCExitTarget
933	DEBUG_CHAR('9')
934
935	; Clear high dword of the CPUMCPU pointer
936	and rdx, 0ffffffffh
937
938	; load final cr3
939	mov rsi, [rdx + CPUMCPU.Host.cr3]
940	mov cr3, rsi
941	DEBUG_CHAR('@')
942
943	;;
944	;; Restore Host context.
945	;;
946	; Load CPUM pointer into edx
947	mov rdx, [NAME(pCpumHC) wrt rip]
948	; Load the CPUMCPU offset.
949	mov r8d, [rdx + CPUM.ulOffCPUMCPU]
950
951	; activate host gdt and idt
952	lgdt [rdx + r8 + CPUMCPU.Host.gdtr]
953	DEBUG_CHAR('0')
954	lidt [rdx + r8 + CPUMCPU.Host.idtr]
955	DEBUG_CHAR('1')
956	; Restore TSS selector; must mark it as not busy before using ltr (!)
957	%if 1 ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
958	movzx eax, word [rdx + r8 + CPUMCPU.Host.tr] ; eax <- TR
959	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
960	add rax, [rdx + r8 + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
961	and dword [rax + 4], ~0200h ; clear busy flag (2nd type2 bit)
962	ltr word [rdx + r8 + CPUMCPU.Host.tr]
963	%else
964	movzx eax, word [rdx + r8 + CPUMCPU.Host.tr] ; eax <- TR
965	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
966	add rax, [rdx + r8 + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
967	mov ecx, [rax + 4] ; ecx <- 2nd descriptor dword
968	mov ebx, ecx ; save orginal value
969	and ecx, ~0200h ; clear busy flag (2nd type2 bit)
970	mov [rax + 4], ccx ; not using xchg here is paranoia..
971	ltr word [rdx + r8 + CPUMCPU.Host.tr]
972	xchg [rax + 4], ebx ; using xchg is paranoia too...
973	%endif
974	; activate ldt
975	DEBUG_CHAR('2')
976	lldt [rdx + r8 + CPUMCPU.Host.ldtr]
977	; Restore segment registers
978	mov eax, [rdx + r8 + CPUMCPU.Host.ds]
979	mov ds, eax
980	mov eax, [rdx + r8 + CPUMCPU.Host.es]
981	mov es, eax
982	mov eax, [rdx + r8 + CPUMCPU.Host.fs]
983	mov fs, eax
984	mov eax, [rdx + r8 + CPUMCPU.Host.gs]
985	mov gs, eax
986	; restore stack
987	mov eax, [rdx + r8 + CPUMCPU.Host.ss]
988	mov ss, eax
989	mov rsp, [rdx + r8 + CPUMCPU.Host.rsp]
990
991	FIXUP FIX_NO_SYSENTER_JMP, 0, gth_sysenter_no - NAME(Start) ; this will insert a jmp gth_sysenter_no if host doesn't use sysenter.
992	; restore MSR_IA32_SYSENTER_CS register.
993	mov rbx, rdx ; save edx
994	mov ecx, MSR_IA32_SYSENTER_CS
995	mov eax, [rbx + r8 + CPUMCPU.Host.SysEnter.cs]
996	mov edx, [rbx + r8 + CPUMCPU.Host.SysEnter.cs + 4]
997	wrmsr ; MSR[ecx] <- edx:eax
998	mov rdx, rbx ; restore edx
999	jmp short gth_sysenter_no
1000
1001	ALIGNCODE(16)
1002	gth_sysenter_no:
1003
1004	;; @todo AMD syscall
1005
1006	; Restore FPU if guest has used it.
1007	; Using fxrstor should ensure that we're not causing unwanted exception on the host.
1008	mov esi, [rdx + r8 + CPUMCPU.fUseFlags] ; esi == use flags.
1009	test esi, CPUM_USED_FPU
1010	jz short gth_fpu_no
1011	mov rcx, cr0
1012	and rcx, ~(X86_CR0_TS \| X86_CR0_EM)
1013	mov cr0, rcx
1014
1015	fxsave [rdx + r8 + CPUMCPU.Guest.fpu]
1016	fxrstor [rdx + r8 + CPUMCPU.Host.fpu]
1017	jmp short gth_fpu_no
1018
1019	ALIGNCODE(16)
1020	gth_fpu_no:
1021
1022	; Control registers.
1023	; Would've liked to have these highere up in case of crashes, but
1024	; the fpu stuff must be done before we restore cr0.
1025	mov rcx, [rdx + r8 + CPUMCPU.Host.cr4]
1026	mov cr4, rcx
1027	mov rcx, [rdx + r8 + CPUMCPU.Host.cr0]
1028	mov cr0, rcx
1029	;mov rcx, [rdx + r8 + CPUMCPU.Host.cr2] ; assumes this is waste of time.
1030	;mov cr2, rcx
1031
1032	; restore debug registers (if modified) (esi must still be fUseFlags!)
1033	; (must be done after cr4 reload because of the debug extension.)
1034	test esi, CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HOST
1035	jz short gth_debug_regs_no
1036	jmp gth_debug_regs_restore
1037	gth_debug_regs_no:
1038
1039	; Restore MSRs
1040	mov rbx, rdx
1041	mov ecx, MSR_K8_FS_BASE
1042	mov eax, [rbx + r8 + CPUMCPU.Host.FSbase]
1043	mov edx, [rbx + r8 + CPUMCPU.Host.FSbase + 4]
1044	wrmsr
1045	mov ecx, MSR_K8_GS_BASE
1046	mov eax, [rbx + r8 + CPUMCPU.Host.GSbase]
1047	mov edx, [rbx + r8 + CPUMCPU.Host.GSbase + 4]
1048	wrmsr
1049	mov ecx, MSR_K6_EFER
1050	mov eax, [rbx + r8 + CPUMCPU.Host.efer]
1051	mov edx, [rbx + r8 + CPUMCPU.Host.efer + 4]
1052	wrmsr
1053	mov rdx, rbx
1054
1055
1056	; restore general registers.
1057	mov eax, edi ; restore return code. eax = return code !!
1058	; mov rax, [rdx + r8 + CPUMCPU.Host.rax] - scratch + return code
1059	mov rbx, [rdx + r8 + CPUMCPU.Host.rbx]
1060	; mov rcx, [rdx + r8 + CPUMCPU.Host.rcx] - scratch
1061	; mov rdx, [rdx + r8 + CPUMCPU.Host.rdx] - scratch
1062	mov rdi, [rdx + r8 + CPUMCPU.Host.rdi]
1063	mov rsi, [rdx + r8 + CPUMCPU.Host.rsi]
1064	mov rsp, [rdx + r8 + CPUMCPU.Host.rsp]
1065	mov rbp, [rdx + r8 + CPUMCPU.Host.rbp]
1066	; mov r8, [rdx + r8 + CPUMCPU.Host.r8 ] - scratch
1067	; mov r9, [rdx + r8 + CPUMCPU.Host.r9 ] - scratch
1068	mov r10, [rdx + r8 + CPUMCPU.Host.r10]
1069	mov r11, [rdx + r8 + CPUMCPU.Host.r11]
1070	mov r12, [rdx + r8 + CPUMCPU.Host.r12]
1071	mov r13, [rdx + r8 + CPUMCPU.Host.r13]
1072	mov r14, [rdx + r8 + CPUMCPU.Host.r14]
1073	mov r15, [rdx + r8 + CPUMCPU.Host.r15]
1074
1075	; finally restore flags. (probably not required)
1076	push qword [rdx + r8 + CPUMCPU.Host.rflags]
1077	popf
1078
1079
1080	%ifdef DEBUG_STUFF
1081	COM64_S_CHAR '4'
1082	%endif
1083	db 048h
1084	retf
1085
1086	;;
1087	; Detour for restoring the host debug registers.
1088	; edx and edi must be preserved.
1089	gth_debug_regs_restore:
1090	DEBUG_S_CHAR('d')
1091	xor eax, eax
1092	mov dr7, rax ; paranoia or not?
1093	test esi, CPUM_USE_DEBUG_REGS
1094	jz short gth_debug_regs_dr7
1095	DEBUG_S_CHAR('r')
1096	mov rax, [rdx + r8 + CPUMCPU.Host.dr0]
1097	mov dr0, rax
1098	mov rbx, [rdx + r8 + CPUMCPU.Host.dr1]
1099	mov dr1, rbx
1100	mov rcx, [rdx + r8 + CPUMCPU.Host.dr2]
1101	mov dr2, rcx
1102	mov rax, [rdx + r8 + CPUMCPU.Host.dr3]
1103	mov dr3, rax
1104	gth_debug_regs_dr7:
1105	mov rbx, [rdx + r8 + CPUMCPU.Host.dr6]
1106	mov dr6, rbx
1107	mov rcx, [rdx + r8 + CPUMCPU.Host.dr7]
1108	mov dr7, rcx
1109	jmp gth_debug_regs_no
1110
1111	ENDPROC VMMGCGuestToHostAsm
1112
1113
1114	GLOBALNAME End
1115	;
1116	; The description string (in the text section).
1117	;
1118	NAME(Description):
1119	db SWITCHER_DESCRIPTION
1120	db 0
1121
1122	extern NAME(Relocate)
1123
1124	;
1125	; End the fixup records.
1126	;
1127	BEGINDATA
1128	db FIX_THE_END ; final entry.
1129	GLOBALNAME FixupsEnd
1130
1131	;;
1132	; The switcher definition structure.
1133	ALIGNDATA(16)
1134	GLOBALNAME Def
1135	istruc VMMSWITCHERDEF
1136	at VMMSWITCHERDEF.pvCode, RTCCPTR_DEF NAME(Start)
1137	at VMMSWITCHERDEF.pvFixups, RTCCPTR_DEF NAME(Fixups)
1138	at VMMSWITCHERDEF.pszDesc, RTCCPTR_DEF NAME(Description)
1139	at VMMSWITCHERDEF.pfnRelocate, RTCCPTR_DEF NAME(Relocate)
1140	at VMMSWITCHERDEF.enmType, dd SWITCHER_TYPE
1141	at VMMSWITCHERDEF.cbCode, dd NAME(End) - NAME(Start)
1142	at VMMSWITCHERDEF.offR0HostToGuest, dd NAME(vmmR0HostToGuest) - NAME(Start)
1143	at VMMSWITCHERDEF.offGCGuestToHost, dd NAME(vmmGCGuestToHost) - NAME(Start)
1144	at VMMSWITCHERDEF.offGCCallTrampoline, dd NAME(vmmGCCallTrampoline) - NAME(Start)
1145	at VMMSWITCHERDEF.offGCGuestToHostAsm, dd NAME(VMMGCGuestToHostAsm) - NAME(Start)
1146	at VMMSWITCHERDEF.offGCGuestToHostAsmHyperCtx, dd NAME(VMMGCGuestToHostAsmHyperCtx)- NAME(Start)
1147	at VMMSWITCHERDEF.offGCGuestToHostAsmGuestCtx, dd NAME(VMMGCGuestToHostAsmGuestCtx)- NAME(Start)
1148	; disasm help
1149	at VMMSWITCHERDEF.offHCCode0, dd 0
1150	at VMMSWITCHERDEF.cbHCCode0, dd NAME(IDEnterTarget) - NAME(Start)
1151	at VMMSWITCHERDEF.offHCCode1, dd NAME(HCExitTarget) - NAME(Start)
1152	at VMMSWITCHERDEF.cbHCCode1, dd NAME(End) - NAME(HCExitTarget)
1153	at VMMSWITCHERDEF.offIDCode0, dd NAME(IDEnterTarget) - NAME(Start)
1154	at VMMSWITCHERDEF.cbIDCode0, dd NAME(JmpGCTarget) - NAME(IDEnterTarget)
1155	at VMMSWITCHERDEF.offIDCode1, dd NAME(IDExitTarget) - NAME(Start)
1156	at VMMSWITCHERDEF.cbIDCode1, dd NAME(HCExitTarget) - NAME(IDExitTarget)
1157	at VMMSWITCHERDEF.offGCCode, dd NAME(JmpGCTarget) - NAME(Start)
1158	at VMMSWITCHERDEF.cbGCCode, dd NAME(IDExitTarget) - NAME(JmpGCTarget)
1159
1160	iend
1161

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