VMMSwitcher.cpp@ 25946

Last change on this file since 25946 was 25946, checked in by vboxsync, 15 years ago
*: VBOX_WITH_RAW_MODE - Initial build changes (builds on mac os x).
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1	/* $Id: VMMSwitcher.cpp 25946 2010-01-20 23:52:24Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_VMM
26	#include <VBox/vmm.h>
27	#include <VBox/pgm.h>
28	#include <VBox/selm.h>
29	#include <VBox/mm.h>
30	#include <VBox/sup.h>
31	#include "VMMInternal.h"
32	#include "VMMSwitcher/VMMSwitcher.h"
33	#include <VBox/vm.h>
34	#include <VBox/dis.h>
35
36	#include <VBox/err.h>
37	#include <VBox/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/alloc.h>
40	#include <iprt/asm.h>
41	#include <iprt/string.h>
42	#include <iprt/ctype.h>
43
44
45	/*******************************************************************************
46	* Global Variables *
47	*******************************************************************************/
48	/** Array of switcher defininitions.
49	* The type and index shall match!
50	*/
51	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
52	{
53	NULL, /* invalid entry */
54	#ifdef VBOX_WITH_RAW_MODE
55	# ifndef RT_ARCH_AMD64
56	&vmmR3Switcher32BitTo32Bit_Def,
57	&vmmR3Switcher32BitToPAE_Def,
58	&vmmR3Switcher32BitToAMD64_Def,
59	&vmmR3SwitcherPAETo32Bit_Def,
60	&vmmR3SwitcherPAEToPAE_Def,
61	&vmmR3SwitcherPAEToAMD64_Def,
62	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
63	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
64	&vmmR3SwitcherAMD64ToPAE_Def,
65	# else
66	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
67	# endif
68	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
69	# else /* RT_ARCH_AMD64 */
70	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
71	NULL, //&vmmR3Switcher32BitToPAE_Def,
72	NULL, //&vmmR3Switcher32BitToAMD64_Def,
73	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
74	NULL, //&vmmR3SwitcherPAEToPAE_Def,
75	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
76	&vmmR3SwitcherAMD64To32Bit_Def,
77	&vmmR3SwitcherAMD64ToPAE_Def,
78	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
79	# endif /* RT_ARCH_AMD64 */
80	#else /* !VBOX_WITH_RAW_MODE */
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL,
87	NULL,
88	NULL,
89	NULL
90	#endif /* !VBOX_WITH_RAW_MODE */
91	};
92
93
94	/**
95	* VMMR3Init worker that initiates the switcher code (aka core code).
96	*
97	* This is core per VM code which might need fixups and/or for ease of use are
98	* put on linear contiguous backing.
99	*
100	* @returns VBox status code.
101	* @param pVM Pointer to the shared VM structure.
102	*/
103	int vmmR3SwitcherInit(PVM pVM)
104	{
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate continguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	}
226
227	/**
228	* Relocate the switchers, called by VMMR#Relocate.
229	*
230	* @param pVM Pointer to the shared VM structure.
231	* @param offDelta The relocation delta.
232	*/
233	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
234	{
235	/*
236	* Relocate all the switchers.
237	*/
238	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
239	{
240	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
241	if (pSwitcher && pSwitcher->pfnRelocate)
242	{
243	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
244	pSwitcher->pfnRelocate(pVM,
245	pSwitcher,
246	pVM->vmm.s.pvCoreCodeR0 + off,
247	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
248	pVM->vmm.s.pvCoreCodeRC + off,
249	pVM->vmm.s.HCPhysCoreCode + off);
250	}
251	}
252
253	/*
254	* Recalc the RC address for the current switcher.
255	*/
256	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
257	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
258	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
259	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
260	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
261	pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
262	pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
263
264	// AssertFailed();
265	}
266
267
268	/**
269	* Generic switcher code relocator.
270	*
271	* @param pVM The VM handle.
272	* @param pSwitcher The switcher definition.
273	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
274	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
275	* @param GCPtrCode The guest context address corresponding to pu8Code.
276	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
277	* @param SelCS The hypervisor CS selector.
278	* @param SelDS The hypervisor DS selector.
279	* @param SelTSS The hypervisor TSS selector.
280	* @param GCPtrGDT The GC address of the hypervisor GDT.
281	* @param SelCS64 The 64-bit mode hypervisor CS selector.
282	*/
283	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
284	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
285	{
286	union
287	{
288	const uint8_t *pu8;
289	const uint16_t *pu16;
290	const uint32_t *pu32;
291	const uint64_t *pu64;
292	const void *pv;
293	uintptr_t u;
294	} u;
295	u.pv = pSwitcher->pvFixups;
296
297	/*
298	* Process fixups.
299	*/
300	uint8_t u8;
301	while ((u8 = *u.pu8++) != FIX_THE_END)
302	{
303	/*
304	* Get the source (where to write the fixup).
305	*/
306	uint32_t offSrc = *u.pu32++;
307	Assert(offSrc < pSwitcher->cbCode);
308	union
309	{
310	uint8_t *pu8;
311	uint16_t *pu16;
312	uint32_t *pu32;
313	uint64_t *pu64;
314	uintptr_t u;
315	} uSrc;
316	uSrc.pu8 = pu8CodeR3 + offSrc;
317
318	/* The fixup target and method depends on the type. */
319	switch (u8)
320	{
321	/*
322	* 32-bit relative, source in HC and target in GC.
323	*/
324	case FIX_HC_2_GC_NEAR_REL:
325	{
326	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
327	uint32_t offTrg = *u.pu32++;
328	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
329	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
330	break;
331	}
332
333	/*
334	* 32-bit relative, source in HC and target in ID.
335	*/
336	case FIX_HC_2_ID_NEAR_REL:
337	{
338	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
339	uint32_t offTrg = *u.pu32++;
340	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
341	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
342	break;
343	}
344
345	/*
346	* 32-bit relative, source in GC and target in HC.
347	*/
348	case FIX_GC_2_HC_NEAR_REL:
349	{
350	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
351	uint32_t offTrg = *u.pu32++;
352	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
353	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
354	break;
355	}
356
357	/*
358	* 32-bit relative, source in GC and target in ID.
359	*/
360	case FIX_GC_2_ID_NEAR_REL:
361	{
362	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
363	uint32_t offTrg = *u.pu32++;
364	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
365	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
366	break;
367	}
368
369	/*
370	* 32-bit relative, source in ID and target in HC.
371	*/
372	case FIX_ID_2_HC_NEAR_REL:
373	{
374	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
375	uint32_t offTrg = *u.pu32++;
376	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
377	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
378	break;
379	}
380
381	/*
382	* 32-bit relative, source in ID and target in HC.
383	*/
384	case FIX_ID_2_GC_NEAR_REL:
385	{
386	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
387	uint32_t offTrg = *u.pu32++;
388	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
389	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
390	break;
391	}
392
393	/*
394	* 16:32 far jump, target in GC.
395	*/
396	case FIX_GC_FAR32:
397	{
398	uint32_t offTrg = *u.pu32++;
399	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
400	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
401	*uSrc.pu16++ = SelCS;
402	break;
403	}
404
405	/*
406	* Make 32-bit GC pointer given CPUM offset.
407	*/
408	case FIX_GC_CPUM_OFF:
409	{
410	uint32_t offCPUM = *u.pu32++;
411	Assert(offCPUM < sizeof(pVM->cpum));
412	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
413	break;
414	}
415
416	/*
417	* Make 32-bit GC pointer given CPUMCPU offset.
418	*/
419	case FIX_GC_CPUMCPU_OFF:
420	{
421	uint32_t offCPUM = *u.pu32++;
422	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
423	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
424	break;
425	}
426
427	/*
428	* Make 32-bit GC pointer given VM offset.
429	*/
430	case FIX_GC_VM_OFF:
431	{
432	uint32_t offVM = *u.pu32++;
433	Assert(offVM < sizeof(VM));
434	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
435	break;
436	}
437
438	/*
439	* Make 32-bit HC pointer given CPUM offset.
440	*/
441	case FIX_HC_CPUM_OFF:
442	{
443	uint32_t offCPUM = *u.pu32++;
444	Assert(offCPUM < sizeof(pVM->cpum));
445	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
446	break;
447	}
448
449	/*
450	* Make 32-bit R0 pointer given VM offset.
451	*/
452	case FIX_HC_VM_OFF:
453	{
454	uint32_t offVM = *u.pu32++;
455	Assert(offVM < sizeof(VM));
456	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
457	break;
458	}
459
460	/*
461	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
462	*/
463	case FIX_INTER_32BIT_CR3:
464	{
465
466	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
467	break;
468	}
469
470	/*
471	* Store the PAE CR3 (32-bit) for the intermediate memory context.
472	*/
473	case FIX_INTER_PAE_CR3:
474	{
475
476	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
477	break;
478	}
479
480	/*
481	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
482	*/
483	case FIX_INTER_AMD64_CR3:
484	{
485
486	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
487	break;
488	}
489
490	/*
491	* Store Hypervisor CS (16-bit).
492	*/
493	case FIX_HYPER_CS:
494	{
495	*uSrc.pu16 = SelCS;
496	break;
497	}
498
499	/*
500	* Store Hypervisor DS (16-bit).
501	*/
502	case FIX_HYPER_DS:
503	{
504	*uSrc.pu16 = SelDS;
505	break;
506	}
507
508	/*
509	* Store Hypervisor TSS (16-bit).
510	*/
511	case FIX_HYPER_TSS:
512	{
513	*uSrc.pu16 = SelTSS;
514	break;
515	}
516
517	/*
518	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
519	*/
520	case FIX_GC_TSS_GDTE_DW2:
521	{
522	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
523	*uSrc.pu32 = (uint32_t)GCPtr;
524	break;
525	}
526
527
528	///@todo case FIX_CR4_MASK:
529	///@todo case FIX_CR4_OSFSXR:
530
531	/*
532	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
533	*/
534	case FIX_NO_FXSAVE_JMP:
535	{
536	uint32_t offTrg = *u.pu32++;
537	Assert(offTrg < pSwitcher->cbCode);
538	if (!CPUMSupportsFXSR(pVM))
539	{
540	uSrc.pu8++ = 0xe9; / jmp rel32 */
541	*uSrc.pu32++ = offTrg - (offSrc + 5);
542	}
543	else
544	{
545	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
546	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
547	}
548	break;
549	}
550
551	/*
552	* Insert relative jump to specified target it SYSENTER isn't used by the host.
553	*/
554	case FIX_NO_SYSENTER_JMP:
555	{
556	uint32_t offTrg = *u.pu32++;
557	Assert(offTrg < pSwitcher->cbCode);
558	if (!CPUMIsHostUsingSysEnter(pVM))
559	{
560	uSrc.pu8++ = 0xe9; / jmp rel32 */
561	*uSrc.pu32++ = offTrg - (offSrc + 5);
562	}
563	else
564	{
565	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
566	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
567	}
568	break;
569	}
570
571	/*
572	* Insert relative jump to specified target it SYSCALL isn't used by the host.
573	*/
574	case FIX_NO_SYSCALL_JMP:
575	{
576	uint32_t offTrg = *u.pu32++;
577	Assert(offTrg < pSwitcher->cbCode);
578	if (!CPUMIsHostUsingSysCall(pVM))
579	{
580	uSrc.pu8++ = 0xe9; / jmp rel32 */
581	*uSrc.pu32++ = offTrg - (offSrc + 5);
582	}
583	else
584	{
585	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
586	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
587	}
588	break;
589	}
590
591	/*
592	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
593	*/
594	case FIX_HC_32BIT:
595	{
596	uint32_t offTrg = *u.pu32++;
597	Assert(offSrc < pSwitcher->cbCode);
598	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
599	*uSrc.pu32 = R0PtrCode + offTrg;
600	break;
601	}
602
603	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
604	/*
605	* 64-bit HC Code Selector (no argument).
606	*/
607	case FIX_HC_64BIT_CS:
608	{
609	Assert(offSrc < pSwitcher->cbCode);
610	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
611	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
612	# else
613	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
614	# endif
615	break;
616	}
617
618	/*
619	* 64-bit HC pointer to the CPUM instance data (no argument).
620	*/
621	case FIX_HC_64BIT_CPUM:
622	{
623	Assert(offSrc < pSwitcher->cbCode);
624	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
625	break;
626	}
627	#endif
628	/*
629	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
630	*/
631	case FIX_HC_64BIT:
632	{
633	uint32_t offTrg = *u.pu32++;
634	Assert(offSrc < pSwitcher->cbCode);
635	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
636	*uSrc.pu64 = R0PtrCode + offTrg;
637	break;
638	}
639
640	#ifdef RT_ARCH_X86
641	case FIX_GC_64_BIT_CPUM_OFF:
642	{
643	uint32_t offCPUM = *u.pu32++;
644	Assert(offCPUM < sizeof(pVM->cpum));
645	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
646	break;
647	}
648	#endif
649
650	/*
651	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
652	*/
653	case FIX_ID_32BIT:
654	{
655	uint32_t offTrg = *u.pu32++;
656	Assert(offSrc < pSwitcher->cbCode);
657	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
658	*uSrc.pu32 = u32IDCode + offTrg;
659	break;
660	}
661
662	/*
663	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
664	*/
665	case FIX_ID_64BIT:
666	case FIX_HC_64BIT_NOCHECK:
667	{
668	uint32_t offTrg = *u.pu32++;
669	Assert(offSrc < pSwitcher->cbCode);
670	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
671	*uSrc.pu64 = u32IDCode + offTrg;
672	break;
673	}
674
675	/*
676	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
677	*/
678	case FIX_ID_FAR32_TO_64BIT_MODE:
679	{
680	uint32_t offTrg = *u.pu32++;
681	Assert(offSrc < pSwitcher->cbCode);
682	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
683	*uSrc.pu32++ = u32IDCode + offTrg;
684	*uSrc.pu16 = SelCS64;
685	AssertRelease(SelCS64);
686	break;
687	}
688
689	#ifdef VBOX_WITH_NMI
690	/*
691	* 32-bit address to the APIC base.
692	*/
693	case FIX_GC_APIC_BASE_32BIT:
694	{
695	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
696	break;
697	}
698	#endif
699
700	default:
701	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
702	break;
703	}
704	}
705
706	#ifdef LOG_ENABLED
707	/*
708	* If Log2 is enabled disassemble the switcher code.
709	*
710	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
711	*/
712	if (LogIs2Enabled())
713	{
714	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
715	" R0PtrCode = %p\n"
716	" pu8CodeR3 = %p\n"
717	" GCPtrCode = %RGv\n"
718	" u32IDCode = %08x\n"
719	" pVMRC = %RRv\n"
720	" pCPUMRC = %RRv\n"
721	" pVMR3 = %p\n"
722	" pCPUMR3 = %p\n"
723	" GCPtrGDT = %RGv\n"
724	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
725	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
726	" SelCS = %04x\n"
727	" SelDS = %04x\n"
728	" SelCS64 = %04x\n"
729	" SelTSS = %04x\n",
730	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
731	R0PtrCode,
732	pu8CodeR3,
733	GCPtrCode,
734	u32IDCode,
735	VM_RC_ADDR(pVM, pVM),
736	VM_RC_ADDR(pVM, &pVM->cpum),
737	pVM,
738	&pVM->cpum,
739	GCPtrGDT,
740	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
741	PGMGetHyperCR3(VMMGetCpu(pVM)),
742	SelCS, SelDS, SelCS64, SelTSS);
743
744	uint32_t offCode = 0;
745	while (offCode < pSwitcher->cbCode)
746	{
747	/*
748	* Figure out where this is.
749	*/
750	const char *pszDesc = NULL;
751	RTUINTPTR uBase;
752	uint32_t cbCode;
753	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
754	{
755	pszDesc = "HCCode0";
756	uBase = R0PtrCode;
757	offCode = pSwitcher->offHCCode0;
758	cbCode = pSwitcher->cbHCCode0;
759	}
760	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
761	{
762	pszDesc = "HCCode1";
763	uBase = R0PtrCode;
764	offCode = pSwitcher->offHCCode1;
765	cbCode = pSwitcher->cbHCCode1;
766	}
767	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
768	{
769	pszDesc = "GCCode";
770	uBase = GCPtrCode;
771	offCode = pSwitcher->offGCCode;
772	cbCode = pSwitcher->cbGCCode;
773	}
774	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
775	{
776	pszDesc = "IDCode0";
777	uBase = u32IDCode;
778	offCode = pSwitcher->offIDCode0;
779	cbCode = pSwitcher->cbIDCode0;
780	}
781	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
782	{
783	pszDesc = "IDCode1";
784	uBase = u32IDCode;
785	offCode = pSwitcher->offIDCode1;
786	cbCode = pSwitcher->cbIDCode1;
787	}
788	else
789	{
790	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
791	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
792	offCode++;
793	continue;
794	}
795
796	/*
797	* Disassemble it.
798	*/
799	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
800	DISCPUSTATE Cpu;
801
802	memset(&Cpu, 0, sizeof(Cpu));
803	Cpu.mode = CPUMODE_32BIT;
804	while (cbCode > 0)
805	{
806	/* try label it */
807	if (pSwitcher->offR0HostToGuest == offCode)
808	RTLogPrintf(" *R0HostToGuest:\n");
809	if (pSwitcher->offGCGuestToHost == offCode)
810	RTLogPrintf(" *GCGuestToHost:\n");
811	if (pSwitcher->offGCCallTrampoline == offCode)
812	RTLogPrintf(" *GCCallTrampoline:\n");
813	if (pSwitcher->offGCGuestToHostAsm == offCode)
814	RTLogPrintf(" *GCGuestToHostAsm:\n");
815	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
816	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
817	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
818	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
819
820	/* disas */
821	uint32_t cbInstr = 0;
822	char szDisas[256];
823	if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
824	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
825	else
826	{
827	RTLogPrintf(" %04x: %02x '%c'\n",
828	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
829	cbInstr = 1;
830	}
831	offCode += cbInstr;
832	cbCode -= RT_MIN(cbInstr, cbCode);
833	}
834	}
835	}
836	#endif
837	}
838
839
840	/**
841	* Relocator for the 32-Bit to 32-Bit world switcher.
842	*/
843	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
844	{
845	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
846	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
847	}
848
849
850	/**
851	* Relocator for the 32-Bit to PAE world switcher.
852	*/
853	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
854	{
855	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
856	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
857	}
858
859
860	/**
861	* Relocator for the 32-Bit to AMD64 world switcher.
862	*/
863	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
864	{
865	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
866	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
867	}
868
869
870	/**
871	* Relocator for the PAE to 32-Bit world switcher.
872	*/
873	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
874	{
875	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
876	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
877	}
878
879
880	/**
881	* Relocator for the PAE to PAE world switcher.
882	*/
883	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
884	{
885	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
886	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
887	}
888
889	/**
890	* Relocator for the PAE to AMD64 world switcher.
891	*/
892	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
893	{
894	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
895	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
896	}
897
898
899	/**
900	* Relocator for the AMD64 to 32-bit world switcher.
901	*/
902	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
903	{
904	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
905	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
906	}
907
908
909	/**
910	* Relocator for the AMD64 to PAE world switcher.
911	*/
912	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
913	{
914	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
915	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
916	}
917
918
919	/**
920	* Selects the switcher to be used for switching to GC.
921	*
922	* @returns VBox status code.
923	* @param pVM VM handle.
924	* @param enmSwitcher The new switcher.
925	* @remark This function may be called before the VMM is initialized.
926	*/
927	VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
928	{
929	/*
930	* Validate input.
931	*/
932	if ( enmSwitcher < VMMSWITCHER_INVALID
933	\|\| enmSwitcher >= VMMSWITCHER_MAX)
934	{
935	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
936	return VERR_INVALID_PARAMETER;
937	}
938
939	/* Do nothing if the switcher is disabled. */
940	if (pVM->vmm.s.fSwitcherDisabled)
941	return VINF_SUCCESS;
942
943	/*
944	* Select the new switcher.
945	*/
946	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
947	if (pSwitcher)
948	{
949	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
950	pVM->vmm.s.enmSwitcher = enmSwitcher;
951
952	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
953	pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
954
955	RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
956	pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
957	pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
958	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
959	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
960	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
961	return VINF_SUCCESS;
962	}
963
964	return VERR_NOT_IMPLEMENTED;
965	}
966
967
968	/**
969	* Disable the switcher logic permanently.
970	*
971	* @returns VBox status code.
972	* @param pVM VM handle.
973	*/
974	VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
975	{
976	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
977	* @code
978	* mov eax, VERR_INTERNAL_ERROR
979	* ret
980	* @endcode
981	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
982	*/
983	pVM->vmm.s.fSwitcherDisabled = true;
984	return VINF_SUCCESS;
985	}
986
987
988	/**
989	* Gets the switcher to be used for switching to GC.
990	*
991	* @returns host to guest ring 0 switcher entrypoint
992	* @param pVM VM handle.
993	* @param enmSwitcher The new switcher.
994	*/
995	VMMR3DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
996	{
997	/*
998	* Validate input.
999	*/
1000	if ( enmSwitcher < VMMSWITCHER_INVALID
1001	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1002	{
1003	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1004	return NIL_RTR0PTR;
1005	}
1006
1007	/*
1008	* Select the new switcher.
1009	*/
1010	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1011	if (pSwitcher)
1012	{
1013	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1014	return pbCodeR0 + pSwitcher->offR0HostToGuest;
1015	}
1016	return NIL_RTR0PTR;
1017	}

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source: vbox/trunk/src/VBox/VMM/VMMSwitcher.cpp@ 25946

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