VMMSwitcher.cpp@ 19141

Last change on this file since 19141 was 18927, checked in by vboxsync, 16 years ago
Big step to separate VMM data structures for guest SMP. (pgm, em)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 36.6 KB

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1	/* $Id: VMMSwitcher.cpp 18927 2009-04-16 11:41:38Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_VMM
26	#include <VBox/vmm.h>
27	#include <VBox/pgm.h>
28	#include <VBox/selm.h>
29	#include <VBox/mm.h>
30	#include <VBox/sup.h>
31	#include "VMMInternal.h"
32	#include "VMMSwitcher/VMMSwitcher.h"
33	#include <VBox/vm.h>
34	#include <VBox/dis.h>
35
36	#include <VBox/err.h>
37	#include <VBox/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/alloc.h>
40	#include <iprt/asm.h>
41	#include <iprt/string.h>
42	#include <iprt/ctype.h>
43
44
45	/*******************************************************************************
46	* Global Variables *
47	*******************************************************************************/
48	/** Array of switcher defininitions.
49	* The type and index shall match!
50	*/
51	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
52	{
53	NULL, /* invalid entry */
54	#ifndef RT_ARCH_AMD64
55	&vmmR3Switcher32BitTo32Bit_Def,
56	&vmmR3Switcher32BitToPAE_Def,
57	&vmmR3Switcher32BitToAMD64_Def,
58	&vmmR3SwitcherPAETo32Bit_Def,
59	&vmmR3SwitcherPAEToPAE_Def,
60	&vmmR3SwitcherPAEToAMD64_Def,
61	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
62	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63	&vmmR3SwitcherAMD64ToPAE_Def,
64	# else
65	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
66	# endif
67	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
68	#else /* RT_ARCH_AMD64 */
69	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
70	NULL, //&vmmR3Switcher32BitToPAE_Def,
71	NULL, //&vmmR3Switcher32BitToAMD64_Def,
72	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
73	NULL, //&vmmR3SwitcherPAEToPAE_Def,
74	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
75	&vmmR3SwitcherAMD64To32Bit_Def,
76	&vmmR3SwitcherAMD64ToPAE_Def,
77	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
78	#endif /* RT_ARCH_AMD64 */
79	};
80
81
82	/**
83	* VMMR3Init worker that initiates the switcher code (aka core code).
84	*
85	* This is core per VM code which might need fixups and/or for ease of use are
86	* put on linear contiguous backing.
87	*
88	* @returns VBox status code.
89	* @param pVM Pointer to the shared VM structure.
90	*/
91	int vmmR3SwitcherInit(PVM pVM)
92	{
93	/*
94	* Calc the size.
95	*/
96	unsigned cbCoreCode = 0;
97	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
98	{
99	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
100	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
101	if (pSwitcher)
102	{
103	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
104	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
105	}
106	}
107
108	/*
109	* Allocate continguous pages for switchers and deal with
110	* conflicts in the intermediate mapping of the code.
111	*/
112	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
113	pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
114	int rc = VERR_NO_MEMORY;
115	if (pVM->vmm.s.pvCoreCodeR3)
116	{
117	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
118	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
119	{
120	/* try more allocations - Solaris, Linux. */
121	const unsigned cTries = 8234;
122	struct VMMInitBadTry
123	{
124	RTR0PTR pvR0;
125	void *pvR3;
126	RTHCPHYS HCPhys;
127	RTUINT cb;
128	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
129	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
130	unsigned i = 0;
131	do
132	{
133	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
134	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
135	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
136	i++;
137	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
138	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
139	pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
140	if (!pVM->vmm.s.pvCoreCodeR3)
141	break;
142	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
143	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
144	&& i < cTries - 1);
145
146	/* cleanup */
147	if (RT_FAILURE(rc))
148	{
149	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
150	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
151	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
152	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
153	i++;
154	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
155	}
156	while (i-- > 0)
157	{
158	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
159	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
160	SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
161	}
162	RTMemTmpFree(paBadTries);
163	}
164	}
165	if (RT_SUCCESS(rc))
166	{
167	/*
168	* copy the code.
169	*/
170	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
171	{
172	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
173	if (pSwitcher)
174	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
175	pSwitcher->pvCode, pSwitcher->cbCode);
176	}
177
178	/*
179	* Map the code into the GC address space.
180	*/
181	RTGCPTR GCPtr;
182	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
183	cbCoreCode, "Core Code", &GCPtr);
184	if (RT_SUCCESS(rc))
185	{
186	pVM->vmm.s.pvCoreCodeRC = GCPtr;
187	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
188	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
189	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
190
191	/*
192	* Finally, PGM probably has selected a switcher already but we need
193	* to get the routine addresses, so we'll reselect it.
194	* This may legally fail so, we're ignoring the rc.
195	*/
196	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
197	return rc;
198	}
199
200	/* shit */
201	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
202	SUPContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
203	}
204	else
205	VMSetError(pVM, rc, RT_SRC_POS,
206	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
207	cbCoreCode);
208
209	pVM->vmm.s.pvCoreCodeR3 = NULL;
210	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
211	pVM->vmm.s.pvCoreCodeRC = 0;
212	return rc;
213	}
214
215	/**
216	* Relocate the switchers, called by VMMR#Relocate.
217	*
218	* @param pVM Pointer to the shared VM structure.
219	* @param offDelta The relocation delta.
220	*/
221	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
222	{
223	/*
224	* Relocate all the switchers.
225	*/
226	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
227	{
228	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
229	if (pSwitcher && pSwitcher->pfnRelocate)
230	{
231	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
232	pSwitcher->pfnRelocate(pVM,
233	pSwitcher,
234	pVM->vmm.s.pvCoreCodeR0 + off,
235	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
236	pVM->vmm.s.pvCoreCodeRC + off,
237	pVM->vmm.s.HCPhysCoreCode + off);
238	}
239	}
240
241	/*
242	* Recalc the RC address for the current switcher.
243	*/
244	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
245	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
246	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
247	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
248	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
249	pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
250	pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
251
252	// AssertFailed();
253	}
254
255
256	/**
257	* Generic switcher code relocator.
258	*
259	* @param pVM The VM handle.
260	* @param pSwitcher The switcher definition.
261	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
262	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
263	* @param GCPtrCode The guest context address corresponding to pu8Code.
264	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
265	* @param SelCS The hypervisor CS selector.
266	* @param SelDS The hypervisor DS selector.
267	* @param SelTSS The hypervisor TSS selector.
268	* @param GCPtrGDT The GC address of the hypervisor GDT.
269	* @param SelCS64 The 64-bit mode hypervisor CS selector.
270	*/
271	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
272	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
273	{
274	union
275	{
276	const uint8_t *pu8;
277	const uint16_t *pu16;
278	const uint32_t *pu32;
279	const uint64_t *pu64;
280	const void *pv;
281	uintptr_t u;
282	} u;
283	u.pv = pSwitcher->pvFixups;
284
285	/*
286	* Process fixups.
287	*/
288	uint8_t u8;
289	while ((u8 = *u.pu8++) != FIX_THE_END)
290	{
291	/*
292	* Get the source (where to write the fixup).
293	*/
294	uint32_t offSrc = *u.pu32++;
295	Assert(offSrc < pSwitcher->cbCode);
296	union
297	{
298	uint8_t *pu8;
299	uint16_t *pu16;
300	uint32_t *pu32;
301	uint64_t *pu64;
302	uintptr_t u;
303	} uSrc;
304	uSrc.pu8 = pu8CodeR3 + offSrc;
305
306	/* The fixup target and method depends on the type. */
307	switch (u8)
308	{
309	/*
310	* 32-bit relative, source in HC and target in GC.
311	*/
312	case FIX_HC_2_GC_NEAR_REL:
313	{
314	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
315	uint32_t offTrg = *u.pu32++;
316	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
317	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
318	break;
319	}
320
321	/*
322	* 32-bit relative, source in HC and target in ID.
323	*/
324	case FIX_HC_2_ID_NEAR_REL:
325	{
326	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
327	uint32_t offTrg = *u.pu32++;
328	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
329	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
330	break;
331	}
332
333	/*
334	* 32-bit relative, source in GC and target in HC.
335	*/
336	case FIX_GC_2_HC_NEAR_REL:
337	{
338	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
339	uint32_t offTrg = *u.pu32++;
340	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
341	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
342	break;
343	}
344
345	/*
346	* 32-bit relative, source in GC and target in ID.
347	*/
348	case FIX_GC_2_ID_NEAR_REL:
349	{
350	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
351	uint32_t offTrg = *u.pu32++;
352	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
353	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
354	break;
355	}
356
357	/*
358	* 32-bit relative, source in ID and target in HC.
359	*/
360	case FIX_ID_2_HC_NEAR_REL:
361	{
362	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
363	uint32_t offTrg = *u.pu32++;
364	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
365	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
366	break;
367	}
368
369	/*
370	* 32-bit relative, source in ID and target in HC.
371	*/
372	case FIX_ID_2_GC_NEAR_REL:
373	{
374	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
375	uint32_t offTrg = *u.pu32++;
376	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
377	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
378	break;
379	}
380
381	/*
382	* 16:32 far jump, target in GC.
383	*/
384	case FIX_GC_FAR32:
385	{
386	uint32_t offTrg = *u.pu32++;
387	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
388	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
389	*uSrc.pu16++ = SelCS;
390	break;
391	}
392
393	/*
394	* Make 32-bit GC pointer given CPUM offset.
395	*/
396	case FIX_GC_CPUM_OFF:
397	{
398	uint32_t offCPUM = *u.pu32++;
399	Assert(offCPUM < sizeof(pVM->cpum));
400	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
401	break;
402	}
403
404	/*
405	* Make 32-bit GC pointer given CPUMCPU offset.
406	*/
407	case FIX_GC_CPUMCPU_OFF:
408	{
409	uint32_t offCPUM = *u.pu32++;
410	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
411	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
412	break;
413	}
414
415	/*
416	* Make 32-bit GC pointer given VM offset.
417	*/
418	case FIX_GC_VM_OFF:
419	{
420	uint32_t offVM = *u.pu32++;
421	Assert(offVM < sizeof(VM));
422	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
423	break;
424	}
425
426	/*
427	* Make 32-bit HC pointer given CPUM offset.
428	*/
429	case FIX_HC_CPUM_OFF:
430	{
431	uint32_t offCPUM = *u.pu32++;
432	Assert(offCPUM < sizeof(pVM->cpum));
433	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
434	break;
435	}
436
437	/*
438	* Make 32-bit R0 pointer given VM offset.
439	*/
440	case FIX_HC_VM_OFF:
441	{
442	uint32_t offVM = *u.pu32++;
443	Assert(offVM < sizeof(VM));
444	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
445	break;
446	}
447
448	/*
449	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
450	*/
451	case FIX_INTER_32BIT_CR3:
452	{
453
454	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
455	break;
456	}
457
458	/*
459	* Store the PAE CR3 (32-bit) for the intermediate memory context.
460	*/
461	case FIX_INTER_PAE_CR3:
462	{
463
464	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
465	break;
466	}
467
468	/*
469	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
470	*/
471	case FIX_INTER_AMD64_CR3:
472	{
473
474	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
475	break;
476	}
477
478	/*
479	* Store Hypervisor CS (16-bit).
480	*/
481	case FIX_HYPER_CS:
482	{
483	*uSrc.pu16 = SelCS;
484	break;
485	}
486
487	/*
488	* Store Hypervisor DS (16-bit).
489	*/
490	case FIX_HYPER_DS:
491	{
492	*uSrc.pu16 = SelDS;
493	break;
494	}
495
496	/*
497	* Store Hypervisor TSS (16-bit).
498	*/
499	case FIX_HYPER_TSS:
500	{
501	*uSrc.pu16 = SelTSS;
502	break;
503	}
504
505	/*
506	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
507	*/
508	case FIX_GC_TSS_GDTE_DW2:
509	{
510	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
511	*uSrc.pu32 = (uint32_t)GCPtr;
512	break;
513	}
514
515
516	///@todo case FIX_CR4_MASK:
517	///@todo case FIX_CR4_OSFSXR:
518
519	/*
520	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
521	*/
522	case FIX_NO_FXSAVE_JMP:
523	{
524	uint32_t offTrg = *u.pu32++;
525	Assert(offTrg < pSwitcher->cbCode);
526	if (!CPUMSupportsFXSR(pVM))
527	{
528	uSrc.pu8++ = 0xe9; / jmp rel32 */
529	*uSrc.pu32++ = offTrg - (offSrc + 5);
530	}
531	else
532	{
533	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
534	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
535	}
536	break;
537	}
538
539	/*
540	* Insert relative jump to specified target it SYSENTER isn't used by the host.
541	*/
542	case FIX_NO_SYSENTER_JMP:
543	{
544	uint32_t offTrg = *u.pu32++;
545	Assert(offTrg < pSwitcher->cbCode);
546	if (!CPUMIsHostUsingSysEnter(pVM))
547	{
548	uSrc.pu8++ = 0xe9; / jmp rel32 */
549	*uSrc.pu32++ = offTrg - (offSrc + 5);
550	}
551	else
552	{
553	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
554	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
555	}
556	break;
557	}
558
559	/*
560	* Insert relative jump to specified target it SYSENTER isn't used by the host.
561	*/
562	case FIX_NO_SYSCALL_JMP:
563	{
564	uint32_t offTrg = *u.pu32++;
565	Assert(offTrg < pSwitcher->cbCode);
566	if (!CPUMIsHostUsingSysEnter(pVM))
567	{
568	uSrc.pu8++ = 0xe9; / jmp rel32 */
569	*uSrc.pu32++ = offTrg - (offSrc + 5);
570	}
571	else
572	{
573	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
574	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
575	}
576	break;
577	}
578
579	/*
580	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
581	*/
582	case FIX_HC_32BIT:
583	{
584	uint32_t offTrg = *u.pu32++;
585	Assert(offSrc < pSwitcher->cbCode);
586	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
587	*uSrc.pu32 = R0PtrCode + offTrg;
588	break;
589	}
590
591	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
592	/*
593	* 64-bit HC Code Selector (no argument).
594	*/
595	case FIX_HC_64BIT_CS:
596	{
597	Assert(offSrc < pSwitcher->cbCode);
598	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
599	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
600	# else
601	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
602	# endif
603	break;
604	}
605
606	/*
607	* 64-bit HC pointer to the CPUM instance data (no argument).
608	*/
609	case FIX_HC_64BIT_CPUM:
610	{
611	Assert(offSrc < pSwitcher->cbCode);
612	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
613	break;
614	}
615	#endif
616	/*
617	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
618	*/
619	case FIX_HC_64BIT:
620	{
621	uint32_t offTrg = *u.pu32++;
622	Assert(offSrc < pSwitcher->cbCode);
623	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
624	*uSrc.pu64 = R0PtrCode + offTrg;
625	break;
626	}
627
628	#ifdef RT_ARCH_X86
629	case FIX_GC_64_BIT_CPUM_OFF:
630	{
631	uint32_t offCPUM = *u.pu32++;
632	Assert(offCPUM < sizeof(pVM->cpum));
633	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
634	break;
635	}
636	#endif
637
638	/*
639	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
640	*/
641	case FIX_ID_32BIT:
642	{
643	uint32_t offTrg = *u.pu32++;
644	Assert(offSrc < pSwitcher->cbCode);
645	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
646	*uSrc.pu32 = u32IDCode + offTrg;
647	break;
648	}
649
650	/*
651	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
652	*/
653	case FIX_ID_64BIT:
654	case FIX_HC_64BIT_NOCHECK:
655	{
656	uint32_t offTrg = *u.pu32++;
657	Assert(offSrc < pSwitcher->cbCode);
658	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
659	*uSrc.pu64 = u32IDCode + offTrg;
660	break;
661	}
662
663	/*
664	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
665	*/
666	case FIX_ID_FAR32_TO_64BIT_MODE:
667	{
668	uint32_t offTrg = *u.pu32++;
669	Assert(offSrc < pSwitcher->cbCode);
670	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
671	*uSrc.pu32++ = u32IDCode + offTrg;
672	*uSrc.pu16 = SelCS64;
673	AssertRelease(SelCS64);
674	break;
675	}
676
677	#ifdef VBOX_WITH_NMI
678	/*
679	* 32-bit address to the APIC base.
680	*/
681	case FIX_GC_APIC_BASE_32BIT:
682	{
683	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
684	break;
685	}
686	#endif
687
688	default:
689	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
690	break;
691	}
692	}
693
694	#ifdef LOG_ENABLED
695	/*
696	* If Log2 is enabled disassemble the switcher code.
697	*
698	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
699	*/
700	if (LogIs2Enabled())
701	{
702	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
703	" R0PtrCode = %p\n"
704	" pu8CodeR3 = %p\n"
705	" GCPtrCode = %RGv\n"
706	" u32IDCode = %08x\n"
707	" pVMRC = %RRv\n"
708	" pCPUMRC = %RRv\n"
709	" pVMR3 = %p\n"
710	" pCPUMR3 = %p\n"
711	" GCPtrGDT = %RGv\n"
712	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
713	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
714	" SelCS = %04x\n"
715	" SelDS = %04x\n"
716	" SelCS64 = %04x\n"
717	" SelTSS = %04x\n",
718	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
719	R0PtrCode,
720	pu8CodeR3,
721	GCPtrCode,
722	u32IDCode,
723	VM_RC_ADDR(pVM, pVM),
724	VM_RC_ADDR(pVM, &pVM->cpum),
725	pVM,
726	&pVM->cpum,
727	GCPtrGDT,
728	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
729	PGMGetHyperCR3(VMMGetCpu(pVM)),
730	SelCS, SelDS, SelCS64, SelTSS);
731
732	uint32_t offCode = 0;
733	while (offCode < pSwitcher->cbCode)
734	{
735	/*
736	* Figure out where this is.
737	*/
738	const char *pszDesc = NULL;
739	RTUINTPTR uBase;
740	uint32_t cbCode;
741	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
742	{
743	pszDesc = "HCCode0";
744	uBase = R0PtrCode;
745	offCode = pSwitcher->offHCCode0;
746	cbCode = pSwitcher->cbHCCode0;
747	}
748	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
749	{
750	pszDesc = "HCCode1";
751	uBase = R0PtrCode;
752	offCode = pSwitcher->offHCCode1;
753	cbCode = pSwitcher->cbHCCode1;
754	}
755	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
756	{
757	pszDesc = "GCCode";
758	uBase = GCPtrCode;
759	offCode = pSwitcher->offGCCode;
760	cbCode = pSwitcher->cbGCCode;
761	}
762	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
763	{
764	pszDesc = "IDCode0";
765	uBase = u32IDCode;
766	offCode = pSwitcher->offIDCode0;
767	cbCode = pSwitcher->cbIDCode0;
768	}
769	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
770	{
771	pszDesc = "IDCode1";
772	uBase = u32IDCode;
773	offCode = pSwitcher->offIDCode1;
774	cbCode = pSwitcher->cbIDCode1;
775	}
776	else
777	{
778	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
779	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
780	offCode++;
781	continue;
782	}
783
784	/*
785	* Disassemble it.
786	*/
787	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
788	DISCPUSTATE Cpu;
789
790	memset(&Cpu, 0, sizeof(Cpu));
791	Cpu.mode = CPUMODE_32BIT;
792	while (cbCode > 0)
793	{
794	/* try label it */
795	if (pSwitcher->offR0HostToGuest == offCode)
796	RTLogPrintf(" *R0HostToGuest:\n");
797	if (pSwitcher->offGCGuestToHost == offCode)
798	RTLogPrintf(" *GCGuestToHost:\n");
799	if (pSwitcher->offGCCallTrampoline == offCode)
800	RTLogPrintf(" *GCCallTrampoline:\n");
801	if (pSwitcher->offGCGuestToHostAsm == offCode)
802	RTLogPrintf(" *GCGuestToHostAsm:\n");
803	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
804	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
805	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
806	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
807
808	/* disas */
809	uint32_t cbInstr = 0;
810	char szDisas[256];
811	if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
812	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
813	else
814	{
815	RTLogPrintf(" %04x: %02x '%c'\n",
816	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
817	cbInstr = 1;
818	}
819	offCode += cbInstr;
820	cbCode -= RT_MIN(cbInstr, cbCode);
821	}
822	}
823	}
824	#endif
825	}
826
827
828	/**
829	* Relocator for the 32-Bit to 32-Bit world switcher.
830	*/
831	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
832	{
833	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
834	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
835	}
836
837
838	/**
839	* Relocator for the 32-Bit to PAE world switcher.
840	*/
841	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
842	{
843	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
844	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
845	}
846
847
848	/**
849	* Relocator for the 32-Bit to AMD64 world switcher.
850	*/
851	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
852	{
853	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
854	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
855	}
856
857
858	/**
859	* Relocator for the PAE to 32-Bit world switcher.
860	*/
861	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
862	{
863	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
864	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
865	}
866
867
868	/**
869	* Relocator for the PAE to PAE world switcher.
870	*/
871	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
872	{
873	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
874	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
875	}
876
877	/**
878	* Relocator for the PAE to AMD64 world switcher.
879	*/
880	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
881	{
882	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
883	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
884	}
885
886
887	/**
888	* Relocator for the AMD64 to 32-bit world switcher.
889	*/
890	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
891	{
892	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
893	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
894	}
895
896
897	/**
898	* Relocator for the AMD64 to PAE world switcher.
899	*/
900	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
901	{
902	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
903	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
904	}
905
906
907	/**
908	* Selects the switcher to be used for switching to GC.
909	*
910	* @returns VBox status code.
911	* @param pVM VM handle.
912	* @param enmSwitcher The new switcher.
913	* @remark This function may be called before the VMM is initialized.
914	*/
915	VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
916	{
917	/*
918	* Validate input.
919	*/
920	if ( enmSwitcher < VMMSWITCHER_INVALID
921	\|\| enmSwitcher >= VMMSWITCHER_MAX)
922	{
923	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
924	return VERR_INVALID_PARAMETER;
925	}
926
927	/* Do nothing if the switcher is disabled. */
928	if (pVM->vmm.s.fSwitcherDisabled)
929	return VINF_SUCCESS;
930
931	/*
932	* Select the new switcher.
933	*/
934	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
935	if (pSwitcher)
936	{
937	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
938	pVM->vmm.s.enmSwitcher = enmSwitcher;
939
940	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
941	pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
942
943	RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
944	pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
945	pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
946	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
947	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
948	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
949	return VINF_SUCCESS;
950	}
951
952	return VERR_NOT_IMPLEMENTED;
953	}
954
955
956	/**
957	* Disable the switcher logic permanently.
958	*
959	* @returns VBox status code.
960	* @param pVM VM handle.
961	*/
962	VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
963	{
964	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
965	* @code
966	* mov eax, VERR_INTERNAL_ERROR
967	* ret
968	* @endcode
969	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
970	*/
971	pVM->vmm.s.fSwitcherDisabled = true;
972	return VINF_SUCCESS;
973	}
974
975	/**
976	* Gets the switcher to be used for switching to GC.
977	*
978	* @returns host to guest ring 0 switcher entrypoint
979	* @param pVM VM handle.
980	* @param enmSwitcher The new switcher.
981	*/
982	VMMR3DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
983	{
984	/*
985	* Validate input.
986	*/
987	if ( enmSwitcher < VMMSWITCHER_INVALID
988	\|\| enmSwitcher >= VMMSWITCHER_MAX)
989	{
990	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
991	return VERR_INVALID_PARAMETER;
992	}
993
994	/*
995	* Select the new switcher.
996	*/
997	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
998	if (pSwitcher)
999	{
1000	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1001	return pbCodeR0 + pSwitcher->offR0HostToGuest;
1002	}
1003	return (RTR0PTR)0;
1004	}

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source: vbox/trunk/src/VBox/VMM/VMMSwitcher.cpp@ 19141

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