VMMSwitcher.cpp@ 35273

Last change on this file since 35273 was 34322, checked in by vboxsync, 14 years ago
VMM: Changed a bunch of VMMR3DECLs to VMMR3_INT_DECL.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 37.3 KB

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1	/* $Id: VMMSwitcher.cpp 34322 2010-11-24 13:36:24Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_VMM
22	#include <VBox/vmm.h>
23	#include <VBox/pgm.h>
24	#include <VBox/selm.h>
25	#include <VBox/mm.h>
26	#include <VBox/sup.h>
27	#include "VMMInternal.h"
28	#include "VMMSwitcher/VMMSwitcher.h"
29	#include <VBox/vm.h>
30	#include <VBox/dis.h>
31
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/alloc.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Global Variables *
44	*******************************************************************************/
45	/** Array of switcher definitions.
46	* The type and index shall match!
47	*/
48	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
49	{
50	NULL, /* invalid entry */
51	#ifdef VBOX_WITH_RAW_MODE
52	# ifndef RT_ARCH_AMD64
53	&vmmR3Switcher32BitTo32Bit_Def,
54	&vmmR3Switcher32BitToPAE_Def,
55	&vmmR3Switcher32BitToAMD64_Def,
56	&vmmR3SwitcherPAETo32Bit_Def,
57	&vmmR3SwitcherPAEToPAE_Def,
58	&vmmR3SwitcherPAEToAMD64_Def,
59	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
60	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
61	&vmmR3SwitcherAMD64ToPAE_Def,
62	# else
63	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64	# endif
65	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
66	# else /* RT_ARCH_AMD64 */
67	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68	NULL, //&vmmR3Switcher32BitToPAE_Def,
69	NULL, //&vmmR3Switcher32BitToAMD64_Def,
70	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71	NULL, //&vmmR3SwitcherPAEToPAE_Def,
72	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
73	&vmmR3SwitcherAMD64To32Bit_Def,
74	&vmmR3SwitcherAMD64ToPAE_Def,
75	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
76	# endif /* RT_ARCH_AMD64 */
77	#else /* !VBOX_WITH_RAW_MODE */
78	NULL,
79	NULL,
80	NULL,
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL
87	#endif /* !VBOX_WITH_RAW_MODE */
88	};
89
90
91	/**
92	* VMMR3Init worker that initiates the switcher code (aka core code).
93	*
94	* This is core per VM code which might need fixups and/or for ease of use are
95	* put on linear contiguous backing.
96	*
97	* @returns VBox status code.
98	* @param pVM Pointer to the shared VM structure.
99	*/
100	int vmmR3SwitcherInit(PVM pVM)
101	{
102	#ifndef VBOX_WITH_RAW_MODE
103	return VINF_SUCCESS;
104	#else
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate contiguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	#endif
226	}
227
228	/**
229	* Relocate the switchers, called by VMMR#Relocate.
230	*
231	* @param pVM Pointer to the shared VM structure.
232	* @param offDelta The relocation delta.
233	*/
234	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
235	{
236	#ifdef VBOX_WITH_RAW_MODE
237	/*
238	* Relocate all the switchers.
239	*/
240	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
241	{
242	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
243	if (pSwitcher && pSwitcher->pfnRelocate)
244	{
245	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
246	pSwitcher->pfnRelocate(pVM,
247	pSwitcher,
248	pVM->vmm.s.pvCoreCodeR0 + off,
249	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
250	pVM->vmm.s.pvCoreCodeRC + off,
251	pVM->vmm.s.HCPhysCoreCode + off);
252	}
253	}
254
255	/*
256	* Recalc the RC address for the current switcher.
257	*/
258	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
259	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
260	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
261	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
262	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
263	pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
264	pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
265
266	// AssertFailed();
267	#endif
268	}
269
270
271	/**
272	* Generic switcher code relocator.
273	*
274	* @param pVM The VM handle.
275	* @param pSwitcher The switcher definition.
276	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
277	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
278	* @param GCPtrCode The guest context address corresponding to pu8Code.
279	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
280	* @param SelCS The hypervisor CS selector.
281	* @param SelDS The hypervisor DS selector.
282	* @param SelTSS The hypervisor TSS selector.
283	* @param GCPtrGDT The GC address of the hypervisor GDT.
284	* @param SelCS64 The 64-bit mode hypervisor CS selector.
285	*/
286	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
287	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
288	{
289	union
290	{
291	const uint8_t *pu8;
292	const uint16_t *pu16;
293	const uint32_t *pu32;
294	const uint64_t *pu64;
295	const void *pv;
296	uintptr_t u;
297	} u;
298	u.pv = pSwitcher->pvFixups;
299
300	/*
301	* Process fixups.
302	*/
303	uint8_t u8;
304	while ((u8 = *u.pu8++) != FIX_THE_END)
305	{
306	/*
307	* Get the source (where to write the fixup).
308	*/
309	uint32_t offSrc = *u.pu32++;
310	Assert(offSrc < pSwitcher->cbCode);
311	union
312	{
313	uint8_t *pu8;
314	uint16_t *pu16;
315	uint32_t *pu32;
316	uint64_t *pu64;
317	uintptr_t u;
318	} uSrc;
319	uSrc.pu8 = pu8CodeR3 + offSrc;
320
321	/* The fixup target and method depends on the type. */
322	switch (u8)
323	{
324	/*
325	* 32-bit relative, source in HC and target in GC.
326	*/
327	case FIX_HC_2_GC_NEAR_REL:
328	{
329	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
330	uint32_t offTrg = *u.pu32++;
331	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
332	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
333	break;
334	}
335
336	/*
337	* 32-bit relative, source in HC and target in ID.
338	*/
339	case FIX_HC_2_ID_NEAR_REL:
340	{
341	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
342	uint32_t offTrg = *u.pu32++;
343	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
344	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
345	break;
346	}
347
348	/*
349	* 32-bit relative, source in GC and target in HC.
350	*/
351	case FIX_GC_2_HC_NEAR_REL:
352	{
353	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
354	uint32_t offTrg = *u.pu32++;
355	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
356	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
357	break;
358	}
359
360	/*
361	* 32-bit relative, source in GC and target in ID.
362	*/
363	case FIX_GC_2_ID_NEAR_REL:
364	{
365	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
366	uint32_t offTrg = *u.pu32++;
367	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
368	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
369	break;
370	}
371
372	/*
373	* 32-bit relative, source in ID and target in HC.
374	*/
375	case FIX_ID_2_HC_NEAR_REL:
376	{
377	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
378	uint32_t offTrg = *u.pu32++;
379	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
380	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
381	break;
382	}
383
384	/*
385	* 32-bit relative, source in ID and target in HC.
386	*/
387	case FIX_ID_2_GC_NEAR_REL:
388	{
389	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
390	uint32_t offTrg = *u.pu32++;
391	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
392	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
393	break;
394	}
395
396	/*
397	* 16:32 far jump, target in GC.
398	*/
399	case FIX_GC_FAR32:
400	{
401	uint32_t offTrg = *u.pu32++;
402	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
403	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
404	*uSrc.pu16++ = SelCS;
405	break;
406	}
407
408	/*
409	* Make 32-bit GC pointer given CPUM offset.
410	*/
411	case FIX_GC_CPUM_OFF:
412	{
413	uint32_t offCPUM = *u.pu32++;
414	Assert(offCPUM < sizeof(pVM->cpum));
415	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
416	break;
417	}
418
419	/*
420	* Make 32-bit GC pointer given CPUMCPU offset.
421	*/
422	case FIX_GC_CPUMCPU_OFF:
423	{
424	uint32_t offCPUM = *u.pu32++;
425	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
426	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
427	break;
428	}
429
430	/*
431	* Make 32-bit GC pointer given VM offset.
432	*/
433	case FIX_GC_VM_OFF:
434	{
435	uint32_t offVM = *u.pu32++;
436	Assert(offVM < sizeof(VM));
437	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
438	break;
439	}
440
441	/*
442	* Make 32-bit HC pointer given CPUM offset.
443	*/
444	case FIX_HC_CPUM_OFF:
445	{
446	uint32_t offCPUM = *u.pu32++;
447	Assert(offCPUM < sizeof(pVM->cpum));
448	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
449	break;
450	}
451
452	/*
453	* Make 32-bit R0 pointer given VM offset.
454	*/
455	case FIX_HC_VM_OFF:
456	{
457	uint32_t offVM = *u.pu32++;
458	Assert(offVM < sizeof(VM));
459	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
460	break;
461	}
462
463	/*
464	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
465	*/
466	case FIX_INTER_32BIT_CR3:
467	{
468
469	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
470	break;
471	}
472
473	/*
474	* Store the PAE CR3 (32-bit) for the intermediate memory context.
475	*/
476	case FIX_INTER_PAE_CR3:
477	{
478
479	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
480	break;
481	}
482
483	/*
484	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
485	*/
486	case FIX_INTER_AMD64_CR3:
487	{
488
489	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
490	break;
491	}
492
493	/*
494	* Store Hypervisor CS (16-bit).
495	*/
496	case FIX_HYPER_CS:
497	{
498	*uSrc.pu16 = SelCS;
499	break;
500	}
501
502	/*
503	* Store Hypervisor DS (16-bit).
504	*/
505	case FIX_HYPER_DS:
506	{
507	*uSrc.pu16 = SelDS;
508	break;
509	}
510
511	/*
512	* Store Hypervisor TSS (16-bit).
513	*/
514	case FIX_HYPER_TSS:
515	{
516	*uSrc.pu16 = SelTSS;
517	break;
518	}
519
520	/*
521	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
522	*/
523	case FIX_GC_TSS_GDTE_DW2:
524	{
525	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
526	*uSrc.pu32 = (uint32_t)GCPtr;
527	break;
528	}
529
530	/*
531	* Store the EFER or mask for the 32->64 bit switcher.
532	*/
533	case FIX_EFER_OR_MASK:
534	{
535	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
536	/** note: we don't care if cpuid 0x8000001 isn't supported as that implies long mode isn't either, so this switcher would never be used. */
537	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
538	u32OrMask \|= MSR_K6_EFER_NXE;
539
540	*uSrc.pu32 = u32OrMask;
541	break;
542	}
543
544	/*
545	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
546	*/
547	case FIX_NO_FXSAVE_JMP:
548	{
549	uint32_t offTrg = *u.pu32++;
550	Assert(offTrg < pSwitcher->cbCode);
551	if (!CPUMSupportsFXSR(pVM))
552	{
553	uSrc.pu8++ = 0xe9; / jmp rel32 */
554	*uSrc.pu32++ = offTrg - (offSrc + 5);
555	}
556	else
557	{
558	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
559	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
560	}
561	break;
562	}
563
564	/*
565	* Insert relative jump to specified target it SYSENTER isn't used by the host.
566	*/
567	case FIX_NO_SYSENTER_JMP:
568	{
569	uint32_t offTrg = *u.pu32++;
570	Assert(offTrg < pSwitcher->cbCode);
571	if (!CPUMIsHostUsingSysEnter(pVM))
572	{
573	uSrc.pu8++ = 0xe9; / jmp rel32 */
574	*uSrc.pu32++ = offTrg - (offSrc + 5);
575	}
576	else
577	{
578	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
579	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
580	}
581	break;
582	}
583
584	/*
585	* Insert relative jump to specified target it SYSCALL isn't used by the host.
586	*/
587	case FIX_NO_SYSCALL_JMP:
588	{
589	uint32_t offTrg = *u.pu32++;
590	Assert(offTrg < pSwitcher->cbCode);
591	if (!CPUMIsHostUsingSysCall(pVM))
592	{
593	uSrc.pu8++ = 0xe9; / jmp rel32 */
594	*uSrc.pu32++ = offTrg - (offSrc + 5);
595	}
596	else
597	{
598	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
599	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
600	}
601	break;
602	}
603
604	/*
605	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
606	*/
607	case FIX_HC_32BIT:
608	{
609	uint32_t offTrg = *u.pu32++;
610	Assert(offSrc < pSwitcher->cbCode);
611	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
612	*uSrc.pu32 = R0PtrCode + offTrg;
613	break;
614	}
615
616	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
617	/*
618	* 64-bit HC Code Selector (no argument).
619	*/
620	case FIX_HC_64BIT_CS:
621	{
622	Assert(offSrc < pSwitcher->cbCode);
623	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
624	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
625	# else
626	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
627	# endif
628	break;
629	}
630
631	/*
632	* 64-bit HC pointer to the CPUM instance data (no argument).
633	*/
634	case FIX_HC_64BIT_CPUM:
635	{
636	Assert(offSrc < pSwitcher->cbCode);
637	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
638	break;
639	}
640	#endif
641	/*
642	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
643	*/
644	case FIX_HC_64BIT:
645	{
646	uint32_t offTrg = *u.pu32++;
647	Assert(offSrc < pSwitcher->cbCode);
648	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
649	*uSrc.pu64 = R0PtrCode + offTrg;
650	break;
651	}
652
653	#ifdef RT_ARCH_X86
654	case FIX_GC_64_BIT_CPUM_OFF:
655	{
656	uint32_t offCPUM = *u.pu32++;
657	Assert(offCPUM < sizeof(pVM->cpum));
658	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
659	break;
660	}
661	#endif
662
663	/*
664	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
665	*/
666	case FIX_ID_32BIT:
667	{
668	uint32_t offTrg = *u.pu32++;
669	Assert(offSrc < pSwitcher->cbCode);
670	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
671	*uSrc.pu32 = u32IDCode + offTrg;
672	break;
673	}
674
675	/*
676	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
677	*/
678	case FIX_ID_64BIT:
679	case FIX_HC_64BIT_NOCHECK:
680	{
681	uint32_t offTrg = *u.pu32++;
682	Assert(offSrc < pSwitcher->cbCode);
683	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
684	*uSrc.pu64 = u32IDCode + offTrg;
685	break;
686	}
687
688	/*
689	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
690	*/
691	case FIX_ID_FAR32_TO_64BIT_MODE:
692	{
693	uint32_t offTrg = *u.pu32++;
694	Assert(offSrc < pSwitcher->cbCode);
695	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
696	*uSrc.pu32++ = u32IDCode + offTrg;
697	*uSrc.pu16 = SelCS64;
698	AssertRelease(SelCS64);
699	break;
700	}
701
702	#ifdef VBOX_WITH_NMI
703	/*
704	* 32-bit address to the APIC base.
705	*/
706	case FIX_GC_APIC_BASE_32BIT:
707	{
708	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
709	break;
710	}
711	#endif
712
713	default:
714	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
715	break;
716	}
717	}
718
719	#ifdef LOG_ENABLED
720	/*
721	* If Log2 is enabled disassemble the switcher code.
722	*
723	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
724	*/
725	if (LogIs2Enabled())
726	{
727	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
728	" R0PtrCode = %p\n"
729	" pu8CodeR3 = %p\n"
730	" GCPtrCode = %RGv\n"
731	" u32IDCode = %08x\n"
732	" pVMRC = %RRv\n"
733	" pCPUMRC = %RRv\n"
734	" pVMR3 = %p\n"
735	" pCPUMR3 = %p\n"
736	" GCPtrGDT = %RGv\n"
737	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
738	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
739	" SelCS = %04x\n"
740	" SelDS = %04x\n"
741	" SelCS64 = %04x\n"
742	" SelTSS = %04x\n",
743	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
744	R0PtrCode,
745	pu8CodeR3,
746	GCPtrCode,
747	u32IDCode,
748	VM_RC_ADDR(pVM, pVM),
749	VM_RC_ADDR(pVM, &pVM->cpum),
750	pVM,
751	&pVM->cpum,
752	GCPtrGDT,
753	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
754	PGMGetHyperCR3(VMMGetCpu(pVM)),
755	SelCS, SelDS, SelCS64, SelTSS);
756
757	uint32_t offCode = 0;
758	while (offCode < pSwitcher->cbCode)
759	{
760	/*
761	* Figure out where this is.
762	*/
763	const char *pszDesc = NULL;
764	RTUINTPTR uBase;
765	uint32_t cbCode;
766	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
767	{
768	pszDesc = "HCCode0";
769	uBase = R0PtrCode;
770	offCode = pSwitcher->offHCCode0;
771	cbCode = pSwitcher->cbHCCode0;
772	}
773	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
774	{
775	pszDesc = "HCCode1";
776	uBase = R0PtrCode;
777	offCode = pSwitcher->offHCCode1;
778	cbCode = pSwitcher->cbHCCode1;
779	}
780	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
781	{
782	pszDesc = "GCCode";
783	uBase = GCPtrCode;
784	offCode = pSwitcher->offGCCode;
785	cbCode = pSwitcher->cbGCCode;
786	}
787	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
788	{
789	pszDesc = "IDCode0";
790	uBase = u32IDCode;
791	offCode = pSwitcher->offIDCode0;
792	cbCode = pSwitcher->cbIDCode0;
793	}
794	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
795	{
796	pszDesc = "IDCode1";
797	uBase = u32IDCode;
798	offCode = pSwitcher->offIDCode1;
799	cbCode = pSwitcher->cbIDCode1;
800	}
801	else
802	{
803	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
804	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
805	offCode++;
806	continue;
807	}
808
809	/*
810	* Disassemble it.
811	*/
812	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
813	DISCPUSTATE Cpu;
814
815	memset(&Cpu, 0, sizeof(Cpu));
816	Cpu.mode = CPUMODE_32BIT;
817	while (cbCode > 0)
818	{
819	/* try label it */
820	if (pSwitcher->offR0HostToGuest == offCode)
821	RTLogPrintf(" *R0HostToGuest:\n");
822	if (pSwitcher->offGCGuestToHost == offCode)
823	RTLogPrintf(" *GCGuestToHost:\n");
824	if (pSwitcher->offGCCallTrampoline == offCode)
825	RTLogPrintf(" *GCCallTrampoline:\n");
826	if (pSwitcher->offGCGuestToHostAsm == offCode)
827	RTLogPrintf(" *GCGuestToHostAsm:\n");
828	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
829	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
830	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
831	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
832
833	/* disas */
834	uint32_t cbInstr = 0;
835	char szDisas[256];
836	if (RT_SUCCESS(DISInstr(&Cpu, (uintptr_t)pu8CodeR3 + offCode, uBase - (uintptr_t)pu8CodeR3, &cbInstr, szDisas)))
837	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
838	else
839	{
840	RTLogPrintf(" %04x: %02x '%c'\n",
841	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
842	cbInstr = 1;
843	}
844	offCode += cbInstr;
845	cbCode -= RT_MIN(cbInstr, cbCode);
846	}
847	}
848	}
849	#endif
850	}
851
852
853	/**
854	* Relocator for the 32-Bit to 32-Bit world switcher.
855	*/
856	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
857	{
858	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
859	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
860	}
861
862
863	/**
864	* Relocator for the 32-Bit to PAE world switcher.
865	*/
866	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
867	{
868	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
869	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
870	}
871
872
873	/**
874	* Relocator for the 32-Bit to AMD64 world switcher.
875	*/
876	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
877	{
878	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
879	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
880	}
881
882
883	/**
884	* Relocator for the PAE to 32-Bit world switcher.
885	*/
886	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
887	{
888	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
889	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
890	}
891
892
893	/**
894	* Relocator for the PAE to PAE world switcher.
895	*/
896	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
897	{
898	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
899	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
900	}
901
902	/**
903	* Relocator for the PAE to AMD64 world switcher.
904	*/
905	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
906	{
907	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
908	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
909	}
910
911
912	/**
913	* Relocator for the AMD64 to 32-bit world switcher.
914	*/
915	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
916	{
917	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
918	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
919	}
920
921
922	/**
923	* Relocator for the AMD64 to PAE world switcher.
924	*/
925	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
926	{
927	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
928	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
929	}
930
931
932	/**
933	* Selects the switcher to be used for switching to GC.
934	*
935	* @returns VBox status code.
936	* @param pVM VM handle.
937	* @param enmSwitcher The new switcher.
938	* @remark This function may be called before the VMM is initialized.
939	*/
940	VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
941	{
942	/*
943	* Validate input.
944	*/
945	if ( enmSwitcher < VMMSWITCHER_INVALID
946	\|\| enmSwitcher >= VMMSWITCHER_MAX)
947	{
948	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
949	return VERR_INVALID_PARAMETER;
950	}
951
952	/* Do nothing if the switcher is disabled. */
953	if (pVM->vmm.s.fSwitcherDisabled)
954	return VINF_SUCCESS;
955
956	/*
957	* Select the new switcher.
958	*/
959	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
960	if (pSwitcher)
961	{
962	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
963	pVM->vmm.s.enmSwitcher = enmSwitcher;
964
965	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
966	pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
967
968	RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
969	pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
970	pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
971	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
972	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
973	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
974	return VINF_SUCCESS;
975	}
976
977	return VERR_NOT_IMPLEMENTED;
978	}
979
980
981	/**
982	* Disable the switcher logic permanently.
983	*
984	* @returns VBox status code.
985	* @param pVM VM handle.
986	*/
987	VMMR3_INT_DECL(int) VMMR3DisableSwitcher(PVM pVM)
988	{
989	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
990	* @code
991	* mov eax, VERR_INTERNAL_ERROR
992	* ret
993	* @endcode
994	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
995	*/
996	pVM->vmm.s.fSwitcherDisabled = true;
997	return VINF_SUCCESS;
998	}
999
1000
1001	/**
1002	* Gets the switcher to be used for switching to GC.
1003	*
1004	* @returns host to guest ring 0 switcher entrypoint
1005	* @param pVM VM handle.
1006	* @param enmSwitcher The new switcher.
1007	*/
1008	VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1009	{
1010	/*
1011	* Validate input.
1012	*/
1013	if ( enmSwitcher < VMMSWITCHER_INVALID
1014	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1015	{
1016	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1017	return NIL_RTR0PTR;
1018	}
1019
1020	/*
1021	* Select the new switcher.
1022	*/
1023	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1024	if (pSwitcher)
1025	{
1026	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1027	return pbCodeR0 + pSwitcher->offR0HostToGuest;
1028	}
1029	return NIL_RTR0PTR;
1030	}

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source: vbox/trunk/src/VBox/VMM/VMMSwitcher.cpp@ 35273

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