1 | /* $Id: DBGFRZ.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
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2 | /** @file
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3 | * DBGF - Debugger Facility, RZ part.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2017 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*********************************************************************************************************************************
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20 | * Header Files *
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21 | *********************************************************************************************************************************/
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22 | #define LOG_GROUP LOG_GROUP_DBGF
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23 | #include <VBox/vmm/dbgf.h>
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24 | #include <VBox/vmm/selm.h>
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25 | #include <VBox/log.h>
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26 | #include "DBGFInternal.h"
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27 | #include <VBox/vmm/vm.h>
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28 | #include <VBox/err.h>
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29 | #include <iprt/assert.h>
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30 |
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31 |
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32 |
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33 | /**
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34 | * \#DB (Debug event) handler.
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35 | *
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36 | * @returns VBox status code.
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37 | * VINF_SUCCESS means we completely handled this trap,
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38 | * other codes are passed execution to host context.
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39 | *
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40 | * @param pVM The cross context VM structure.
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41 | * @param pVCpu The cross context virtual CPU structure.
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42 | * @param pRegFrame Pointer to the register frame for the trap.
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43 | * @param uDr6 The DR6 hypervisor register value.
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44 | * @param fAltStepping Alternative stepping indicator.
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45 | */
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46 | VMMRZ_INT_DECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping)
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47 | {
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48 | #ifdef IN_RC
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49 | const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
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50 | #else
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51 | NOREF(pRegFrame);
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52 | const bool fInHyper = false;
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53 | #endif
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54 |
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55 | /** @todo Intel docs say that X86_DR6_BS has the highest priority... */
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56 | /*
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57 | * A breakpoint?
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58 | */
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59 | AssertCompile(X86_DR6_B0 == 1 && X86_DR6_B1 == 2 && X86_DR6_B2 == 4 && X86_DR6_B3 == 8);
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60 | if ( (uDr6 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3))
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61 | && pVM->dbgf.s.cEnabledHwBreakpoints > 0)
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62 | {
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63 | for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
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64 | {
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65 | if ( ((uint32_t)uDr6 & RT_BIT_32(iBp))
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66 | && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG)
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67 | {
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68 | pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
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69 | pVCpu->dbgf.s.fSingleSteppingRaw = false;
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70 | LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %d at %04x:%RGv\n",
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71 | pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs.Sel, pRegFrame->rip));
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72 |
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73 | return fInHyper ? VINF_EM_DBG_HYPER_BREAKPOINT : VINF_EM_DBG_BREAKPOINT;
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74 | }
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75 | }
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76 | }
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77 |
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78 | /*
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79 | * Single step?
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80 | * Are we single stepping or is it the guest?
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81 | */
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82 | if ( (uDr6 & X86_DR6_BS)
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83 | && (fInHyper || pVCpu->dbgf.s.fSingleSteppingRaw || fAltStepping))
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84 | {
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85 | pVCpu->dbgf.s.fSingleSteppingRaw = false;
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86 | LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
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87 | return fInHyper ? VINF_EM_DBG_HYPER_STEPPED : VINF_EM_DBG_STEPPED;
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88 | }
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89 |
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90 | /*
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91 | * Either an ICEBP in hypervisor code or a guest related debug exception
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92 | * of sorts.
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93 | */
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94 | if (RT_UNLIKELY(fInHyper))
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95 | {
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96 | LogFlow(("DBGFRZTrap01Handler: unabled bp at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
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97 | return VERR_DBGF_HYPER_DB_XCPT;
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98 | }
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99 |
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100 | LogFlow(("DBGFRZTrap01Handler: guest debug event %#x at %04x:%RGv!\n", (uint32_t)uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
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101 | return VINF_EM_RAW_GUEST_TRAP;
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102 | }
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103 |
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104 |
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105 | /**
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106 | * \#BP (Breakpoint) handler.
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107 | *
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108 | * @returns VBox status code.
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109 | * VINF_SUCCESS means we completely handled this trap,
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110 | * other codes are passed execution to host context.
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111 | *
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112 | * @param pVM The cross context VM structure.
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113 | * @param pVCpu The cross context virtual CPU structure.
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114 | * @param pRegFrame Pointer to the register frame for the trap.
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115 | */
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116 | VMMRZ_INT_DECL(int) DBGFRZTrap03Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
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117 | {
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118 | #ifdef IN_RC
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119 | const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
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120 | #else
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121 | const bool fInHyper = false;
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122 | #endif
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123 |
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124 | /*
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125 | * Get the trap address and look it up in the breakpoint table.
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126 | * Don't bother if we don't have any breakpoints.
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127 | */
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128 | unsigned cToSearch = pVM->dbgf.s.Int3.cToSearch;
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129 | if (cToSearch > 0)
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130 | {
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131 | RTGCPTR pPc;
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132 | int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
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133 | #ifdef IN_RC
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134 | pRegFrame->eip - 1,
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135 | #else
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136 | pRegFrame->rip /* no -1 in R0 */,
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137 | #endif
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138 | &pPc);
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139 | AssertRCReturn(rc, rc);
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140 |
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141 | unsigned iBp = pVM->dbgf.s.Int3.iStartSearch;
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142 | while (cToSearch-- > 0)
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143 | {
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144 | if ( pVM->dbgf.s.aBreakpoints[iBp].u.GCPtr == (RTGCUINTPTR)pPc
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145 | && pVM->dbgf.s.aBreakpoints[iBp].enmType == DBGFBPTYPE_INT3)
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146 | {
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147 | pVM->dbgf.s.aBreakpoints[iBp].cHits++;
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148 | pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aBreakpoints[iBp].iBp;
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149 |
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150 | LogFlow(("DBGFRZTrap03Handler: hit breakpoint %d at %RGv (%04x:%RGv) cHits=0x%RX64\n",
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151 | pVM->dbgf.s.aBreakpoints[iBp].iBp, pPc, pRegFrame->cs.Sel, pRegFrame->rip,
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152 | pVM->dbgf.s.aBreakpoints[iBp].cHits));
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153 | return fInHyper
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154 | ? VINF_EM_DBG_HYPER_BREAKPOINT
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155 | : VINF_EM_DBG_BREAKPOINT;
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156 | }
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157 | iBp++;
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158 | }
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159 | }
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160 |
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161 | return fInHyper
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162 | ? VINF_EM_DBG_HYPER_ASSERTION
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163 | : VINF_EM_RAW_GUEST_TRAP;
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164 | }
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165 |
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