TRPMRCHandlers.cpp@ 73471

Last change on this file since 73471 was 72655, checked in by vboxsync, 7 years ago
EM,HM,NEM,TRPM: Renamed some EMEXIT_XXXX stuff to shorten things down a bit. Added missing HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST) after EMHistoryExec in the VT-x code. Prepped the SVM code for CPUID, IO and MMIO exit optimizations. bugref:9198
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 61.9 KB

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1	/* $Id: TRPMRCHandlers.cpp 72655 2018-06-22 10:05:53Z vboxsync $ */
2	/** @file
3	* TRPM - Raw-mode Context Trap Handlers, CPP part
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_TRPM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/iom.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/em.h>
29	#include <VBox/vmm/gim.h>
30	#include <VBox/vmm/apic.h>
31	#include <VBox/vmm/csam.h>
32	#include <VBox/vmm/patm.h>
33	#include <VBox/vmm/mm.h>
34	#include <VBox/vmm/cpum.h>
35	#include "TRPMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/vmm.h>
38	#include <VBox/param.h>
39
40	#include <VBox/err.h>
41	#include <VBox/dis.h>
42	#include <VBox/disopcode.h>
43	#include <VBox/log.h>
44	#include <VBox/vmm/tm.h>
45	#include <iprt/asm.h>
46	#include <iprt/asm-amd64-x86.h>
47	#include <iprt/assert.h>
48	#include <iprt/x86.h>
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	/* still here. MODR/M byte parsing */
55	#define X86_OPCODE_MODRM_MOD_MASK 0xc0
56	#define X86_OPCODE_MODRM_REG_MASK 0x38
57	#define X86_OPCODE_MODRM_RM_MASK 0x07
58
59	/** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
60	#define DTRACE_EXPERIMENT
61
62	#if 1
63	# define TRPM_ENTER_DBG_HOOK(a_iVector) do {} while (0)
64	# define TRPM_EXIT_DBG_HOOK(a_iVector) do {} while (0)
65	# define TRPM_ENTER_DBG_HOOK_HYPER(a_iVector) do {} while (0)
66	# define TRPM_EXIT_DBG_HOOK_HYPER(a_iVector) do {} while (0)
67	#else
68	# define TRPM_ENTER_DBG_HOOK(a_iVector) \
69	uint32_t const fDbgEFlags1 = CPUMRawGetEFlags(pVCpu); \
70	if (!(fDbgEFlags1 & X86_EFL_IF)) Log(("%s: IF=0 ##\n", __FUNCTION__)); \
71	else do {} while (0)
72	# define TRPM_EXIT_DBG_HOOK(a_iVector) \
73	do { \
74	uint32_t const fDbgEFlags2 = CPUMRawGetEFlags(pVCpu); \
75	if ((fDbgEFlags1 ^ fDbgEFlags2) & (X86_EFL_IF \| X86_EFL_IOPL)) \
76	Log(("%s: IF=%d->%d IOPL=%d->%d !#\n", __FUNCTION__, \
77	!!(fDbgEFlags1 & X86_EFL_IF), !!(fDbgEFlags2 & X86_EFL_IF), \
78	X86_EFL_GET_IOPL(fDbgEFlags1), X86_EFL_GET_IOPL(fDbgEFlags2) )); \
79	else if (!(fDbgEFlags2 & X86_EFL_IF)) Log(("%s: IF=0 [ret] ##\n", __FUNCTION__)); \
80	} while (0)
81	# define TRPM_ENTER_DBG_HOOK_HYPER(a_iVector) do {} while (0)
82	# define TRPM_EXIT_DBG_HOOK_HYPER(a_iVector) do {} while (0)
83	#endif
84
85
86	/*********************************************************************************************************************************
87	* Structures and Typedefs *
88	*********************************************************************************************************************************/
89	/** Pointer to a readonly hypervisor trap record. */
90	typedef const struct TRPMGCHYPER *PCTRPMGCHYPER;
91
92	/**
93	* A hypervisor trap record.
94	* This contains information about a handler for a instruction range.
95	*
96	* @remark This must match what TRPM_HANDLER outputs.
97	*/
98	typedef struct TRPMGCHYPER
99	{
100	/** The start address. */
101	uintptr_t uStartEIP;
102	/** The end address. (exclusive)
103	* If NULL the it's only for the instruction at pvStartEIP. */
104	uintptr_t uEndEIP;
105	/**
106	* The handler.
107	*
108	* @returns VBox status code
109	* VINF_SUCCESS means we've handled the trap.
110	* Any other error code means returning to the host context.
111	* @param pVM The cross context VM structure.
112	* @param pRegFrame The register frame.
113	* @param uUser The user argument.
114	*/
115	DECLRCCALLBACKMEMBER(int, pfnHandler, (PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser));
116	/** Whatever the handler desires to put here. */
117	uintptr_t uUser;
118	} TRPMGCHYPER;
119
120
121	/*********************************************************************************************************************************
122	* Global Variables *
123	*********************************************************************************************************************************/
124	RT_C_DECLS_BEGIN
125	/** Defined in VMMRC0.asm or VMMRC99.asm.
126	* @{ */
127	extern const TRPMGCHYPER g_aTrap0bHandlers[1];
128	extern const TRPMGCHYPER g_aTrap0bHandlersEnd[1];
129	extern const TRPMGCHYPER g_aTrap0dHandlers[1];
130	extern const TRPMGCHYPER g_aTrap0dHandlersEnd[1];
131	extern const TRPMGCHYPER g_aTrap0eHandlers[1];
132	extern const TRPMGCHYPER g_aTrap0eHandlersEnd[1];
133	/** @} */
134	RT_C_DECLS_END
135
136
137	/*********************************************************************************************************************************
138	* Internal Functions *
139	*********************************************************************************************************************************/
140	RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
141	DECLCALLBACK(int) trpmRCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
142	RT_C_DECLS_END
143
144
145
146	/**
147	* Exits the trap, called when exiting a trap handler.
148	*
149	* Will reset the trap if it's not a guest trap or the trap
150	* is already handled. Will process resume guest FFs.
151	*
152	* @returns rc, can be adjusted if its VINF_SUCCESS or something really bad
153	* happened.
154	* @param pVM The cross context VM structure.
155	* @param pVCpu The cross context virtual CPU structure.
156	* @param rc The VBox status code to return.
157	* @param pRegFrame Pointer to the register frame for the trap.
158	*
159	* @remarks This must not be used for hypervisor traps, only guest traps.
160	*/
161	static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
162	{
163	uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
164	NOREF(uOldActiveVector);
165
166	/* Reset trap? */
167	if ( rc != VINF_EM_RAW_GUEST_TRAP
168	&& rc != VINF_EM_RAW_RING_SWITCH_INT)
169	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
170
171	#ifdef VBOX_HIGH_RES_TIMERS_HACK
172	/*
173	* We should poll the timers occasionally.
174	* We must NOT do this too frequently as it adds a significant overhead
175	* and it'll kill us if the trap load is high. (See @bugref{1354}.)
176	* (The heuristic is not very intelligent, we should really check trap
177	* frequency etc. here, but alas, we lack any such information atm.)
178	*/
179	static unsigned s_iTimerPoll = 0;
180	if (rc == VINF_SUCCESS)
181	{
182	if (!(++s_iTimerPoll & 0xf))
183	{
184	TMTimerPollVoid(pVM, pVCpu);
185	Log2(("TMTimerPoll at %08RX32 - VM_FF_TM_VIRTUAL_SYNC=%d VM_FF_TM_VIRTUAL_SYNC=%d\n", pRegFrame->eip,
186	VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER)));
187	}
188	}
189	else
190	s_iTimerPoll = 0;
191	#endif
192
193	/* Clear pending inhibit interrupt state if required. (necessary for dispatching interrupts later on) */
194	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
195	{
196	Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
197	if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
198	{
199	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
200	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
201	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
202	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
203	*/
204	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
205	}
206	}
207
208	/*
209	* Pending resume-guest-FF?
210	* Or pending (A)PIC interrupt? Windows XP will crash if we delay APIC interrupts.
211	*/
212	if ( rc == VINF_SUCCESS
213	&& ( VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC \| VM_FF_REQUEST \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_DMA)
214	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_TO_R3
215	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
216	\| VMCPU_FF_REQUEST \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
217	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_IEM \| VMCPU_FF_SELM_SYNC_GDT
218	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
219	\| VMCPU_FF_IOM \| VMCPU_FF_CPUM
220	)
221	)
222	)
223	{
224	/* The out of memory condition naturally outranks the others. */
225	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
226	rc = VINF_EM_NO_MEMORY;
227	else
228	{
229	/* APIC needs updating. */
230	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
231	APICUpdatePendingInterrupts(pVCpu);
232
233	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_CPUM))
234	CPUMRCProcessForceFlag(pVCpu);
235
236	/* Pending Ring-3 action. */
237	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TO_R3 \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_IEM \| VMCPU_FF_IOM))
238	{
239	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
240	rc = VINF_EM_RAW_TO_R3;
241	}
242	/* Pending timer action. */
243	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER))
244	rc = VINF_EM_RAW_TIMER_PENDING;
245	/* The Virtual Sync clock has stopped. */
246	else if (VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
247	rc = VINF_EM_RAW_TO_R3;
248	/* DMA work pending? */
249	else if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
250	rc = VINF_EM_RAW_TO_R3;
251	/* Pending request packets might contain actions that need immediate
252	attention, such as pending hardware interrupts. */
253	else if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
254	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
255	rc = VINF_EM_PENDING_REQUEST;
256	/* Pending GDT/LDT/TSS sync. */
257	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS))
258	rc = VINF_SELM_SYNC_GDT;
259	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
260	rc = VINF_EM_RAW_TO_R3;
261	/* Possibly pending interrupt: dispatch it. */
262	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
263	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
264	&& PATMAreInterruptsEnabledByCtx(pVM, CPUMCTX_FROM_CORE(pRegFrame))
265	)
266	{
267	uint8_t u8Interrupt;
268	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
269	Log(("trpmGCExitTrap: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
270	if (RT_SUCCESS(rc))
271	{
272	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
273	/* can't return if successful */
274	Assert(rc != VINF_SUCCESS);
275
276	/* Stop the profile counter that was started in TRPMRCHandlersA.asm */
277	Assert(uOldActiveVector <= 16);
278	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
279
280	/* Assert the trap and go to the recompiler to dispatch it. */
281	TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
282
283	STAM_PROFILE_ADV_START(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
284	rc = VINF_EM_RAW_INTERRUPT_PENDING;
285	}
286	else if ( rc == VERR_APIC_INTR_MASKED_BY_TPR /* Can happen if TPR is too high for the newly arrived interrupt. */
287	\|\| rc == VERR_NO_DATA) /* Can happen if the APIC is disabled. */
288	{
289	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
290	rc = VINF_SUCCESS;
291	}
292	else
293	AssertFatalMsgRC(rc, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
294	}
295	/*
296	* Try sync CR3?
297	*/
298	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
299	{
300	#if 1
301	PGMRZDynMapReleaseAutoSet(pVCpu);
302	PGMRZDynMapStartAutoSet(pVCpu);
303	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
304	#else
305	rc = VINF_PGM_SYNC_CR3;
306	#endif
307	}
308	}
309	}
310
311	/* Note! TRPMRCHandlersA.asm performs sanity checks in debug builds.*/
312	PGMRZDynMapReleaseAutoSet(pVCpu);
313	return rc;
314	}
315
316
317	/**
318	* \#DB (Debug event) handler.
319	*
320	* @returns VBox status code.
321	* VINF_SUCCESS means we completely handled this trap,
322	* other codes are passed execution to host context.
323	*
324	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
325	* @param pRegFrame Pointer to the register frame for the trap.
326	* @internal
327	*/
328	DECLASM(int) TRPMGCTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
329	{
330	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
331	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
332	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
333	LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
334	TRPM_ENTER_DBG_HOOK(1);
335	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_DB),
336	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
337
338	/*
339	* We currently don't make use of the X86_DR7_GD bit, but
340	* there might come a time when we do.
341	*/
342	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
343	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
344	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
345	VERR_NOT_IMPLEMENTED);
346	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
347
348	/*
349	* Now leave the rest to the DBGF.
350	*/
351	PGMRZDynMapStartAutoSet(pVCpu);
352	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6, false /fAltStepping/);
353	if (rc == VINF_EM_RAW_GUEST_TRAP)
354	{
355	CPUMSetGuestDR6(pVCpu, (CPUMGetGuestDR6(pVCpu) & ~X86_DR6_B_MASK) \| uDr6);
356	if (CPUMGetGuestDR7(pVCpu) & X86_DR7_GD)
357	CPUMSetGuestDR7(pVCpu, CPUMGetGuestDR7(pVCpu) & ~X86_DR7_GD);
358	}
359	else if (rc == VINF_EM_DBG_STEPPED)
360	pRegFrame->eflags.Bits.u1TF = 0;
361
362	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
363	Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg EFlag=%#x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
364	TRPM_EXIT_DBG_HOOK(1);
365	return rc;
366	}
367
368
369	/**
370	* \#DB (Debug event) handler for the hypervisor code.
371	*
372	* This is mostly the same as TRPMGCTrap01Handler, but we skip the PGM auto
373	* mapping set as well as the default trap exit path since they are both really
374	* bad ideas in this context.
375	*
376	* @returns VBox status code.
377	* VINF_SUCCESS means we completely handled this trap,
378	* other codes are passed execution to host context.
379	*
380	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
381	* @param pRegFrame Pointer to the register frame for the trap.
382	* @internal
383	*/
384	DECLASM(int) TRPMGCHyperTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
385	{
386	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
387	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
388	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
389	TRPM_ENTER_DBG_HOOK_HYPER(1);
390	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_DB),
391	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
392	LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
393
394	/*
395	* We currently don't make use of the X86_DR7_GD bit, but
396	* there might come a time when we do.
397	*/
398	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
399	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
400	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
401	VERR_NOT_IMPLEMENTED);
402	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
403
404	/*
405	* Now leave the rest to the DBGF.
406	*/
407	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6, false /fAltStepping/);
408	if (rc == VINF_EM_DBG_STEPPED)
409	pRegFrame->eflags.Bits.u1TF = 0;
410
411	Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
412	TRPM_EXIT_DBG_HOOK_HYPER(1);
413	return rc;
414	}
415
416
417	/**
418	* NMI handler, for when we are using NMIs to debug things.
419	*
420	* @returns VBox status code.
421	* VINF_SUCCESS means we completely handled this trap,
422	* other codes are passed execution to host context.
423	*
424	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
425	* @param pRegFrame Pointer to the register frame for the trap.
426	* @internal
427	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
428	*/
429	DECLASM(int) TRPMGCTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
430	{
431	LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
432	EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NMI),
433	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
434	#if 0 /* Enable this iff you have a COM port and really want this debug info. */
435	RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
436	#endif
437	NOREF(pTrpmCpu); RT_NOREF_PV(pRegFrame);
438	return VERR_TRPM_DONT_PANIC;
439	}
440
441
442	/**
443	* NMI handler, for when we are using NMIs to debug things.
444	*
445	* This is the handler we're most likely to hit when the NMI fires (it is
446	* unlikely that we'll be stuck in guest code).
447	*
448	* @returns VBox status code.
449	* VINF_SUCCESS means we completely handled this trap,
450	* other codes are passed execution to host context.
451	*
452	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
453	* @param pRegFrame Pointer to the register frame for the trap.
454	* @internal
455	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
456	*/
457	DECLASM(int) TRPMGCHyperTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
458	{
459	LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
460	EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NMI),
461	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
462	#if 0 /* Enable this iff you have a COM port and really want this debug info. */
463	RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
464	#endif
465	NOREF(pTrpmCpu); RT_NOREF_PV(pRegFrame);
466	return VERR_TRPM_DONT_PANIC;
467	}
468
469
470	/**
471	* \#BP (Breakpoint) handler.
472	*
473	* @returns VBox status code.
474	* VINF_SUCCESS means we completely handled this trap,
475	* other codes are passed execution to host context.
476	*
477	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
478	* @param pRegFrame Pointer to the register frame for the trap.
479	* @internal
480	*/
481	DECLASM(int) TRPMGCTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
482	{
483	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
484	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
485	int rc;
486	LogFlow(("TRPMGC03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
487	TRPM_ENTER_DBG_HOOK(3);
488	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_BP),
489	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
490	PGMRZDynMapStartAutoSet(pVCpu);
491
492	/*
493	* PATM is using INT3s, let them have a go first.
494	*/
495	if ( ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1
496	\|\| (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2) )
497	&& !pRegFrame->eflags.Bits.u1VM)
498	{
499	rc = PATMRCHandleInt3PatchTrap(pVM, pRegFrame);
500	if ( rc == VINF_SUCCESS
501	\|\| rc == VINF_EM_RESCHEDULE
502	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
503	\|\| rc == VINF_PATM_PATCH_INT3
504	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION )
505	{
506	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
507	Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
508	TRPM_EXIT_DBG_HOOK(3);
509	return rc;
510	}
511	}
512	rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
513
514	/* anything we should do with this? Schedule it in GC? */
515	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
516	Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
517	TRPM_EXIT_DBG_HOOK(3);
518	return rc;
519	}
520
521
522	/**
523	* \#BP (Breakpoint) handler.
524	*
525	* This is similar to TRPMGCTrap03Handler but we bits which are potentially
526	* harmful to us (common trap exit and the auto mapping set).
527	*
528	* @returns VBox status code.
529	* VINF_SUCCESS means we completely handled this trap,
530	* other codes are passed execution to host context.
531	*
532	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
533	* @param pRegFrame Pointer to the register frame for the trap.
534	* @internal
535	*/
536	DECLASM(int) TRPMGCHyperTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
537	{
538	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
539	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
540	LogFlow(("TRPMGCHyper03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
541	TRPM_ENTER_DBG_HOOK_HYPER(3);
542	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_BP),
543	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
544
545	/*
546	* Hand it over to DBGF.
547	*/
548	int rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
549	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_2);
550
551	Log6(("TRPMGCHyper03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
552	TRPM_EXIT_DBG_HOOK_HYPER(3);
553	return rc;
554	}
555
556
557	/**
558	* Trap handler for illegal opcode fault (\#UD).
559	*
560	* @returns VBox status code.
561	* VINF_SUCCESS means we completely handled this trap,
562	* other codes are passed execution to host context.
563	*
564	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
565	* @param pRegFrame Pointer to the register frame for the trap.
566	* @internal
567	*/
568	DECLASM(int) TRPMGCTrap06Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
569	{
570	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
571	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
572	int rc;
573	LogFlow(("TRPMGC06: %04x:%08x EFL=%#x/%#x\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->eflags.u32, CPUMRawGetEFlags(pVCpu)));
574	TRPM_ENTER_DBG_HOOK(6);
575	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_UD),
576	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
577	PGMRZDynMapStartAutoSet(pVCpu);
578
579	if (CPUMGetGuestCPL(pVCpu) <= (EMIsRawRing1Enabled(pVM) ? 1U : 0U))
580	{
581	/*
582	* Decode the instruction.
583	*/
584	RTGCPTR PC;
585	rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
586	pRegFrame->rip, &PC);
587	if (RT_FAILURE(rc))
588	{
589	Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
590	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
591	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (SELM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
592	TRPM_EXIT_DBG_HOOK(6);
593	return rc;
594	}
595
596	DISCPUSTATE Cpu;
597	uint32_t cbOp;
598	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
599	if (RT_FAILURE(rc))
600	{
601	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
602	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (EM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
603	TRPM_EXIT_DBG_HOOK(6);
604	return rc;
605	}
606
607	/*
608	* UD2 in a patch?
609	* Note! PATMGCHandleIllegalInstrTrap doesn't always return.
610	*/
611	if ( Cpu.pCurInstr->uOpcode == OP_ILLUD2
612	&& PATMIsPatchGCAddr(pVM, pRegFrame->eip))
613	{
614	LogFlow(("TRPMGCTrap06Handler: -> PATMRCHandleIllegalInstrTrap\n"));
615	rc = PATMRCHandleIllegalInstrTrap(pVM, pRegFrame);
616	/** @todo These tests are completely unnecessary, should just follow the
617	* flow and return at the end of the function. */
618	if ( rc == VINF_SUCCESS
619	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
620	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION
621	\|\| rc == VINF_PATM_PENDING_IRQ_AFTER_IRET
622	\|\| rc == VINF_EM_RESCHEDULE)
623	{
624	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
625	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
626	TRPM_EXIT_DBG_HOOK(6);
627	return rc;
628	}
629	}
630	/*
631	* Speed up dtrace and don't entrust invalid lock sequences to the recompiler.
632	*/
633	else if (Cpu.fPrefix & DISPREFIX_LOCK)
634	{
635	Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->uOpcode));
636	#ifdef DTRACE_EXPERIMENT /** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
637	Assert(!PATMIsPatchGCAddr(pVM, pRegFrame->eip));
638	rc = TRPMForwardTrap(pVCpu, pRegFrame, X86_XCPT_UD, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, X86_XCPT_UD);
639	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
640	#else
641	rc = VINF_EM_RAW_EMULATE_INSTR;
642	#endif
643	}
644	/*
645	* Handle MONITOR - it causes an #UD exception instead of #GP when not executed in ring 0.
646	*/
647	else if (Cpu.pCurInstr->uOpcode == OP_MONITOR)
648	{
649	LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
650	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR));
651	}
652	else if (GIMShouldTrapXcptUD(pVCpu))
653	{
654	LogFlow(("TRPMGCTrap06Handler: -> GIMXcptUD\n"));
655	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, CPUMCTX_FROM_CORE(pRegFrame), &Cpu, NULL /* pcbInstr */);
656	if (rcStrict == VINF_SUCCESS)
657	{
658	/* The interrupt inhibition wrt to EIP will be handled by trpmGCExitTrap() below. */
659	pRegFrame->eip += Cpu.cbInstr;
660	Assert(Cpu.cbInstr);
661	}
662	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
663	rc = VINF_SUCCESS;
664	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
665	rc = VINF_GIM_R3_HYPERCALL;
666	else
667	{
668	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
669	LogFlow(("TRPMGCTrap06Handler: GIMXcptUD returns %Rrc -> VINF_EM_RAW_EMULATE_INSTR\n", rc));
670	rc = VINF_EM_RAW_EMULATE_INSTR;
671	}
672	}
673	/* Never generate a raw trap here; it might be an instruction, that requires emulation. */
674	else
675	{
676	LogFlow(("TRPMGCTrap06Handler: -> VINF_EM_RAW_EMULATE_INSTR\n"));
677	rc = VINF_EM_RAW_EMULATE_INSTR;
678	}
679	}
680	else
681	{
682	LogFlow(("TRPMGCTrap06Handler: -> TRPMForwardTrap\n"));
683	rc = TRPMForwardTrap(pVCpu, pRegFrame, X86_XCPT_UD, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, X86_XCPT_UD);
684	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
685	}
686
687	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
688	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
689	TRPM_EXIT_DBG_HOOK(6);
690	return rc;
691	}
692
693
694	/**
695	* Trap handler for device not present fault (\#NM).
696	*
697	* Device not available, FP or (F)WAIT instruction.
698	*
699	* @returns VBox status code.
700	* VINF_SUCCESS means we completely handled this trap,
701	* other codes are passed execution to host context.
702	*
703	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
704	* @param pRegFrame Pointer to the register frame for the trap.
705	* @internal
706	*/
707	DECLASM(int) TRPMGCTrap07Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
708	{
709	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
710	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
711	LogFlow(("TRPMGC07: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
712	TRPM_ENTER_DBG_HOOK(7);
713	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NM),
714	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
715	PGMRZDynMapStartAutoSet(pVCpu);
716
717	int rc = CPUMHandleLazyFPU(pVCpu);
718	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
719	Log6(("TRPMGC07: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
720	TRPM_EXIT_DBG_HOOK(7);
721	return rc;
722	}
723
724
725	/**
726	* \#NP ((segment) Not Present) handler.
727	*
728	* @returns VBox status code.
729	* VINF_SUCCESS means we completely handled this trap,
730	* other codes are passed execution to host context.
731	*
732	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
733	* @param pRegFrame Pointer to the register frame for the trap.
734	* @internal
735	*/
736	DECLASM(int) TRPMGCTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
737	{
738	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
739	LogFlow(("TRPMGC0b: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
740	TRPM_ENTER_DBG_HOOK(0xb);
741	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NP),
742	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
743	PGMRZDynMapStartAutoSet(pVCpu);
744
745	/*
746	* Try to detect instruction by opcode which caused trap.
747	* XXX note: this code may cause \#PF (trap e) or \#GP (trap d) while
748	* accessing user code. need to handle it somehow in future!
749	*/
750	RTGCPTR GCPtr;
751	if ( SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
752	(RTGCPTR)pRegFrame->eip, &GCPtr)
753	== VINF_SUCCESS)
754	{
755	uint8_t pu8Code = (uint8_t )(uintptr_t)GCPtr;
756
757	/*
758	* First skip possible instruction prefixes, such as:
759	* OS, AS
760	* CS:, DS:, ES:, SS:, FS:, GS:
761	* REPE, REPNE
762	*
763	* note: Currently we supports only up to 4 prefixes per opcode, more
764	* prefixes (normally not used anyway) will cause trap d in guest.
765	* note: Instruction length in IA-32 may be up to 15 bytes, we dont
766	* check this issue, its too hard.
767	*/
768	for (unsigned i = 0; i < 4; i++)
769	{
770	if ( pu8Code[0] != 0xf2 /* REPNE/REPNZ */
771	&& pu8Code[0] != 0xf3 /* REP/REPE/REPZ */
772	&& pu8Code[0] != 0x2e /* CS: */
773	&& pu8Code[0] != 0x36 /* SS: */
774	&& pu8Code[0] != 0x3e /* DS: */
775	&& pu8Code[0] != 0x26 /* ES: */
776	&& pu8Code[0] != 0x64 /* FS: */
777	&& pu8Code[0] != 0x65 /* GS: */
778	&& pu8Code[0] != 0x66 /* OS */
779	&& pu8Code[0] != 0x67 /* AS */
780	)
781	break;
782	pu8Code++;
783	}
784
785	/*
786	* Detect right switch using a callgate.
787	*
788	* We recognize the following causes for the trap 0b:
789	* CALL FAR, CALL FAR []
790	* JMP FAR, JMP FAR []
791	* IRET (may cause a task switch)
792	*
793	* Note: we can't detect whether the trap was caused by a call to a
794	* callgate descriptor or it is a real trap 0b due to a bad selector.
795	* In both situations we'll pass execution to our recompiler so we don't
796	* have to worry.
797	* If we wanted to do better detection, we have set GDT entries to callgate
798	* descriptors pointing to our own handlers.
799	*/
800	/** @todo not sure about IRET, may generate Trap 0d (\#GP), NEED TO CHECK! */
801	if ( pu8Code[0] == 0x9a /* CALL FAR */
802	\|\| ( pu8Code[0] == 0xff /* CALL FAR [] */
803	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x18)
804	\|\| pu8Code[0] == 0xea /* JMP FAR */
805	\|\| ( pu8Code[0] == 0xff /* JMP FAR [] */
806	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x28)
807	\|\| pu8Code[0] == 0xcf /* IRET */
808	)
809	{
810	/*
811	* Got potential call to callgate.
812	* We simply return execution to the recompiler to do emulation
813	* starting from the instruction which caused the trap.
814	*/
815	pTrpmCpu->uActiveVector = UINT32_MAX;
816	Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
817	TRPM_EXIT_DBG_HOOK(0xb);
818	PGMRZDynMapReleaseAutoSet(pVCpu);
819	return VINF_EM_RAW_RING_SWITCH;
820	}
821	}
822
823	/*
824	* Pass trap 0b as is to the recompiler in all other cases.
825	*/
826	Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
827	PGMRZDynMapReleaseAutoSet(pVCpu);
828	TRPM_EXIT_DBG_HOOK(0xb);
829	return VINF_EM_RAW_GUEST_TRAP;
830	}
831
832
833	/**
834	* \#GP (General Protection Fault) handler for Ring-0 privileged instructions.
835	*
836	* @returns VBox status code.
837	* VINF_SUCCESS means we completely handled this trap,
838	* other codes are passed execution to host context.
839	*
840	* @param pVM The cross context VM structure.
841	* @param pVCpu The cross context virtual CPU structure.
842	* @param pRegFrame Pointer to the register frame for the trap.
843	* @param pCpu The opcode info.
844	* @param PC The program counter corresponding to cs:eip in pRegFrame.
845	*/
846	static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
847	{
848	int rc;
849	TRPM_ENTER_DBG_HOOK(0xd);
850
851	/*
852	* Try handle it here, if not return to HC and emulate/interpret it there.
853	*/
854	uint16_t const uOpcode = pCpu->pCurInstr->uOpcode;
855	switch (uOpcode)
856	{
857	case OP_INT3:
858	/*
859	* Little hack to make the code below not fail
860	*/
861	pCpu->Param1.fUse = DISUSE_IMMEDIATE8;
862	pCpu->Param1.uValue = 3;
863	RT_FALL_THRU();
864	case OP_INT:
865	{
866	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_INT));
867	Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
868	Assert(!(PATMIsPatchGCAddr(pVM, PC)));
869	if (pCpu->Param1.uValue == 3)
870	{
871	/* Int 3 replacement patch? */
872	if (PATMRCHandleInt3PatchTrap(pVM, pRegFrame) == VINF_SUCCESS)
873	{
874	AssertFailed();
875	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
876	}
877	}
878	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
879	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
880	{
881	TRPM_EXIT_DBG_HOOK(0xd);
882	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
883	}
884
885	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
886	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
887	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
888	}
889
890	#ifdef PATM_EMULATE_SYSENTER
891	case OP_SYSEXIT:
892	case OP_SYSRET:
893	rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu);
894	TRPM_EXIT_DBG_HOOK(0xd);
895	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
896	#endif
897
898	case OP_HLT:
899	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_HLT));
900
901	/* If it's in patch code, defer to ring-3. */
902	if (PATMIsPatchGCAddr(pVM, PC))
903	break;
904
905	pRegFrame->eip += pCpu->cbInstr;
906	TRPM_EXIT_DBG_HOOK(0xd);
907	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame);
908
909
910	/*
911	* These instructions are used by PATM and CASM for finding
912	* dangerous non-trapping instructions. Thus, since all
913	* scanning and patching is done in ring-3 we'll have to
914	* return to ring-3 on the first encounter of these instructions.
915	*/
916	case OP_MOV_CR:
917	case OP_MOV_DR:
918	/* We can safely emulate control/debug register move instructions in patched code. */
919	if ( !PATMIsPatchGCAddr(pVM, PC)
920	&& !CSAMIsKnownDangerousInstr(pVM, PC))
921	{
922	if (uOpcode == OP_MOV_CR)
923	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_CRX));
924	else
925	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_DRX));
926	break;
927	}
928	RT_FALL_THRU();
929	case OP_INVLPG:
930	case OP_LLDT:
931	case OP_STI:
932	case OP_RDTSC: /* just in case */
933	case OP_RDPMC:
934	case OP_CLTS:
935	case OP_WBINVD: /* nop */
936	case OP_RDMSR:
937	case OP_WRMSR:
938	{
939	/* Update history. */
940	switch (uOpcode)
941	{
942	case OP_MOV_CR:
943	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_CRX));
944	break;
945	case OP_MOV_DR:
946	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_DRX));
947	break;
948	case OP_INVLPG:
949	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_INVLPG));
950	break;
951	case OP_LLDT:
952	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_LLDT));
953	break;
954	case OP_STI:
955	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_STI));
956	break;
957	case OP_RDPMC:
958	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_RDPMC));
959	break;
960	case OP_CLTS:
961	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CLTS));
962	break;
963	case OP_WBINVD:
964	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CLTS));
965	break;
966	case OP_RDMSR:
967	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ));
968	break;
969	case OP_WRMSR:
970	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE));
971	break;
972	}
973
974	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR));
975	if (rc == VERR_EM_INTERPRETER)
976	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
977	TRPM_EXIT_DBG_HOOK(0xd);
978	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
979	}
980	}
981
982	TRPM_EXIT_DBG_HOOK(0xd);
983	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EXCEPTION_PRIVILEGED, pRegFrame);
984	}
985
986
987	/**
988	* \#GP (General Protection Fault) handler for Ring-3.
989	*
990	* @returns VBox status code.
991	* VINF_SUCCESS means we completely handled this trap,
992	* other codes are passed execution to host context.
993	*
994	* @param pVM The cross context VM structure.
995	* @param pVCpu The cross context virtual CPU structure.
996	* @param pRegFrame Pointer to the register frame for the trap.
997	* @param pCpu The opcode info.
998	* @param PC The program counter corresponding to cs:eip in pRegFrame.
999	*/
1000	static int trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
1001	{
1002	int rc;
1003	Assert(!pRegFrame->eflags.Bits.u1VM);
1004	TRPM_ENTER_DBG_HOOK(0xd);
1005
1006	uint16_t const uOpcode = pCpu->pCurInstr->uOpcode;
1007	switch (uOpcode)
1008	{
1009	/*
1010	* INT3 and INT xx are ring-switching.
1011	* (The shadow IDT will have set the entries to DPL=0, that's why we're here.)
1012	*/
1013	case OP_INT3:
1014	/*
1015	* Little hack to make the code below not fail
1016	*/
1017	pCpu->Param1.fUse = DISUSE_IMMEDIATE8;
1018	pCpu->Param1.uValue = 3;
1019	RT_FALL_THRU();
1020	case OP_INT:
1021	{
1022	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_INT));
1023	Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
1024	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
1025	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
1026	{
1027	TRPM_EXIT_DBG_HOOK(0xd);
1028	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
1029	}
1030
1031	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
1032	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
1033	TRPM_EXIT_DBG_HOOK(0xd);
1034	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
1035	}
1036
1037	/*
1038	* SYSCALL, SYSENTER, INTO and BOUND are also ring-switchers.
1039	*/
1040	case OP_SYSCALL:
1041	case OP_SYSENTER:
1042	if (uOpcode == OP_SYSCALL)
1043	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_SYSCALL));
1044	else
1045	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_SYSENTER));
1046	#ifdef PATM_EMULATE_SYSENTER
1047	rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu);
1048	if (rc == VINF_SUCCESS)
1049	{
1050	TRPM_EXIT_DBG_HOOK(0xd);
1051	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
1052	}
1053	/* else no break; */
1054	#endif
1055	RT_FALL_THRU();
1056	case OP_BOUND:
1057	case OP_INTO:
1058	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
1059	TRPM_EXIT_DBG_HOOK(0xd);
1060	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH, pRegFrame);
1061
1062	/*
1063	* Handle virtualized TSC & PMC reads, just in case.
1064	*/
1065	case OP_RDTSC:
1066	case OP_RDPMC:
1067	{
1068	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR));
1069	if (rc == VERR_EM_INTERPRETER)
1070	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1071	TRPM_EXIT_DBG_HOOK(0xd);
1072	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1073	}
1074
1075	/*
1076	* STI and CLI are I/O privileged, i.e. if IOPL
1077	*/
1078	case OP_STI:
1079	case OP_CLI:
1080	{
1081	uint32_t efl = CPUMRawGetEFlags(pVCpu);
1082	uint32_t cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1083	if (X86_EFL_GET_IOPL(efl) >= cpl)
1084	{
1085	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> REM\n"));
1086	TRPM_EXIT_DBG_HOOK(0xd);
1087	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RESCHEDULE_REM, pRegFrame);
1088	}
1089	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> #GP(0) iopl=%x, cpl=%x\n", X86_EFL_GET_IOPL(efl), cpl));
1090	break;
1091	}
1092	}
1093
1094	/*
1095	* A genuine guest fault.
1096	*/
1097	TRPM_EXIT_DBG_HOOK(0xd);
1098	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
1099	}
1100
1101
1102	/**
1103	* Emulates RDTSC for the \#GP handler.
1104	*
1105	* @returns VINF_SUCCESS or VINF_EM_RAW_EMULATE_INSTR.
1106	*
1107	* @param pVM The cross context VM structure.
1108	* @param pVCpu The cross context virtual CPU structure.
1109	* @param pRegFrame Pointer to the register frame for the trap.
1110	* This will be updated on successful return.
1111	*/
1112	DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1113	{
1114	STAM_COUNTER_INC(&pVM->trpm.s.StatTrap0dRdTsc);
1115	TRPM_ENTER_DBG_HOOK(0xd);
1116
1117	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
1118	{
1119	TRPM_EXIT_DBG_HOOK(0xd);
1120	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
1121	}
1122
1123	uint64_t uTicks = TMCpuTickGet(pVCpu);
1124	pRegFrame->eax = RT_LO_U32(uTicks);
1125	pRegFrame->edx = RT_HI_U32(uTicks);
1126	pRegFrame->eip += 2;
1127	TRPM_EXIT_DBG_HOOK(0xd);
1128	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
1129	}
1130
1131
1132	/**
1133	* \#GP (General Protection Fault) handler.
1134	*
1135	* @returns VBox status code.
1136	* VINF_SUCCESS means we completely handled this trap,
1137	* other codes are passed execution to host context.
1138	*
1139	* @param pVM The cross context VM structure.
1140	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1141	* @param pRegFrame Pointer to the register frame for the trap.
1142	*/
1143	static int trpmGCTrap0dHandler(PVM pVM, PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1144	{
1145	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1146	LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, pTrpmCpu->uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1147	TRPM_ENTER_DBG_HOOK(0xd);
1148
1149	/*
1150	* Convert and validate CS.
1151	*/
1152	STAM_PROFILE_START(&pVM->trpm.s.StatTrap0dDisasm, a);
1153	RTGCPTR PC;
1154	int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
1155	pRegFrame->rip, &PC);
1156	if (RT_FAILURE(rc))
1157	{
1158	Log(("trpmGCTrap0dHandler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n",
1159	pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
1160	TRPM_EXIT_DBG_HOOK(0xd);
1161	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1162	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1163	}
1164
1165	/*
1166	* Disassemble the instruction.
1167	*/
1168	DISCPUSTATE Cpu;
1169	uint32_t cbOp;
1170	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
1171	if (RT_FAILURE(rc))
1172	{
1173	AssertMsgFailed(("DISCoreOneEx failed to PC=%RGv rc=%Rrc\n", PC, rc));
1174	TRPM_EXIT_DBG_HOOK(0xd);
1175	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1176	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1177	}
1178	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1179
1180	/*
1181	* Optimize RDTSC traps.
1182	* Some guests (like Solaris) are using RDTSC all over the place and
1183	* will end up trapping a lot because of that.
1184	*
1185	* Note: it's no longer safe to access the instruction opcode directly due to possible stale code TLB entries
1186	*/
1187	if (Cpu.pCurInstr->uOpcode == OP_RDTSC)
1188	{
1189	EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_RDTSC));
1190	return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);
1191	}
1192
1193	/*
1194	* Deal with I/O port access.
1195	*/
1196	if ( pVCpu->trpm.s.uActiveErrorCode == 0
1197	&& (Cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
1198	{
1199	/* IOMRCIOPortHandler updates exit history. */
1200	VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, pVCpu, pRegFrame, &Cpu);
1201	TRPM_EXIT_DBG_HOOK(0xd);
1202	return trpmGCExitTrap(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict), pRegFrame);
1203	}
1204
1205	/*
1206	* Deal with Ring-0 (privileged instructions)
1207	*/
1208	if ( (pRegFrame->ss.Sel & X86_SEL_RPL) <= 1
1209	&& !pRegFrame->eflags.Bits.u1VM)
1210	return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
1211
1212	/*
1213	* Deal with Ring-3 GPs.
1214	*/
1215	if (!pRegFrame->eflags.Bits.u1VM)
1216	return trpmGCTrap0dHandlerRing3(pVM, pVCpu, pRegFrame, &Cpu, PC);
1217
1218	/*
1219	* Deal with v86 code.
1220	*
1221	* We always set IOPL to zero which makes e.g. pushf fault in V86
1222	* mode. The guest might use IOPL=3 and therefore not expect a #GP.
1223	* Simply fall back to the recompiler to emulate this instruction if
1224	* that's the case. To get the correct we must use CPUMRawGetEFlags.
1225	*/
1226	X86EFLAGS eflags;
1227	eflags.u32 = CPUMRawGetEFlags(pVCpu); /* Get the correct value. */
1228	Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs.Sel, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
1229	if (eflags.Bits.u2IOPL != 3)
1230	{
1231	Assert(EMIsRawRing1Enabled(pVM) \|\| eflags.Bits.u2IOPL == 0);
1232
1233	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xD, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xd);
1234	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1235	TRPM_EXIT_DBG_HOOK(0xd);
1236	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1237	}
1238	TRPM_EXIT_DBG_HOOK(0xd);
1239	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1240	}
1241
1242
1243	/**
1244	* \#GP (General Protection Fault) handler.
1245	*
1246	* @returns VBox status code.
1247	* VINF_SUCCESS means we completely handled this trap,
1248	* other codes are passed execution to host context.
1249	*
1250	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1251	* @param pRegFrame Pointer to the register frame for the trap.
1252	* @internal
1253	*/
1254	DECLASM(int) TRPMGCTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1255	{
1256	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1257	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1258	LogFlow(("TRPMGC0d: %04x:%08x err=%x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1259	TRPM_ENTER_DBG_HOOK(0xd);
1260	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_GP),
1261	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
1262
1263	PGMRZDynMapStartAutoSet(pVCpu);
1264	int rc = trpmGCTrap0dHandler(pVM, pTrpmCpu, pRegFrame);
1265	switch (rc)
1266	{
1267	case VINF_EM_RAW_GUEST_TRAP:
1268	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1269	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1270	rc = VINF_PATM_PATCH_TRAP_GP;
1271	break;
1272
1273	case VINF_EM_RAW_INTERRUPT_PENDING:
1274	Assert(TRPMHasTrap(pVCpu));
1275	/* no break; */
1276	case VINF_PGM_SYNC_CR3:
1277	case VINF_EM_RAW_EMULATE_INSTR:
1278	case VINF_IOM_R3_IOPORT_READ:
1279	case VINF_IOM_R3_IOPORT_WRITE:
1280	case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
1281	case VINF_IOM_R3_MMIO_WRITE:
1282	case VINF_IOM_R3_MMIO_COMMIT_WRITE:
1283	case VINF_IOM_R3_MMIO_READ:
1284	case VINF_IOM_R3_MMIO_READ_WRITE:
1285	case VINF_CPUM_R3_MSR_READ:
1286	case VINF_CPUM_R3_MSR_WRITE:
1287	case VINF_PATM_PATCH_INT3:
1288	case VINF_EM_NO_MEMORY:
1289	case VINF_EM_RAW_TO_R3:
1290	case VINF_EM_RAW_TIMER_PENDING:
1291	case VINF_EM_PENDING_REQUEST:
1292	case VINF_EM_HALT:
1293	case VINF_SELM_SYNC_GDT:
1294	case VINF_SUCCESS:
1295	break;
1296
1297	default:
1298	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("return code %d\n", rc));
1299	break;
1300	}
1301	Log6(("TRPMGC0d: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
1302	TRPM_EXIT_DBG_HOOK(0xd);
1303	return rc;
1304	}
1305
1306
1307	/**
1308	* \#PF (Page Fault) handler.
1309	*
1310	* Calls PGM which does the actual handling.
1311	*
1312	*
1313	* @returns VBox status code.
1314	* VINF_SUCCESS means we completely handled this trap,
1315	* other codes are passed execution to host context.
1316	*
1317	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1318	* @param pRegFrame Pointer to the register frame for the trap.
1319	* @internal
1320	*/
1321	DECLASM(int) TRPMGCTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1322	{
1323	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1324	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1325	LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2, CPUMRawGetEFlags(pVCpu)));
1326	TRPM_ENTER_DBG_HOOK(0xe);
1327	EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_PF),
1328	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
1329
1330	/*
1331	* This is all PGM stuff.
1332	*/
1333	PGMRZDynMapStartAutoSet(pVCpu);
1334	int rc = PGMTrap0eHandler(pVCpu, pVCpu->trpm.s.uActiveErrorCode, pRegFrame, (RTGCPTR)pVCpu->trpm.s.uActiveCR2);
1335	switch (rc)
1336	{
1337	case VINF_EM_RAW_EMULATE_INSTR:
1338	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
1339	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
1340	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
1341	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
1342	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1343	rc = VINF_PATCH_EMULATE_INSTR;
1344	break;
1345
1346	case VINF_EM_RAW_GUEST_TRAP:
1347	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1348	{
1349	PGMRZDynMapReleaseAutoSet(pVCpu);
1350	TRPM_EXIT_DBG_HOOK(0xe);
1351	return VINF_PATM_PATCH_TRAP_PF;
1352	}
1353
1354	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xE, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xe);
1355	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1356	break;
1357
1358	case VINF_EM_RAW_INTERRUPT_PENDING:
1359	Assert(TRPMHasTrap(pVCpu));
1360	/* no break; */
1361	case VINF_IOM_R3_MMIO_READ:
1362	case VINF_IOM_R3_MMIO_WRITE:
1363	case VINF_IOM_R3_MMIO_COMMIT_WRITE:
1364	case VINF_IOM_R3_MMIO_READ_WRITE:
1365	case VINF_PATM_HC_MMIO_PATCH_READ:
1366	case VINF_PATM_HC_MMIO_PATCH_WRITE:
1367	case VINF_SUCCESS:
1368	case VINF_EM_RAW_TO_R3:
1369	case VINF_EM_PENDING_REQUEST:
1370	case VINF_EM_RAW_TIMER_PENDING:
1371	case VINF_EM_NO_MEMORY:
1372	case VINF_CSAM_PENDING_ACTION:
1373	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1374	break;
1375
1376	default:
1377	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("Patch address for return code %d. eip=%08x\n", rc, pRegFrame->eip));
1378	break;
1379	}
1380	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1381	Log6(("TRPMGC0e: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
1382	TRPM_EXIT_DBG_HOOK(0xe);
1383	return rc;
1384	}
1385
1386
1387	/**
1388	* Scans for the EIP in the specified array of trap handlers.
1389	*
1390	* If we don't fine the EIP, we'll panic.
1391	*
1392	* @returns VBox status code.
1393	*
1394	* @param pVM The cross context VM structure.
1395	* @param pRegFrame Pointer to the register frame for the trap.
1396	* @param paHandlers The array of trap handler records.
1397	* @param pEndRecord The end record (exclusive).
1398	*/
1399	static int trpmGCHyperGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, PCTRPMGCHYPER paHandlers, PCTRPMGCHYPER pEndRecord)
1400	{
1401	uintptr_t uEip = (uintptr_t)pRegFrame->eip;
1402	Assert(paHandlers <= pEndRecord);
1403
1404	Log(("trpmGCHyperGeneric: uEip=%x %p-%p\n", uEip, paHandlers, pEndRecord));
1405
1406	#if 0 /// @todo later
1407	/*
1408	* Start by doing a kind of binary search.
1409	*/
1410	unsigned iStart = 0;
1411	unsigned iEnd = pEndRecord - paHandlers;
1412	unsigned i = iEnd / 2;
1413	#endif
1414
1415	/*
1416	* Do a linear search now (in case the array wasn't properly sorted).
1417	*/
1418	for (PCTRPMGCHYPER pCur = paHandlers; pCur < pEndRecord; pCur++)
1419	{
1420	if ( pCur->uStartEIP <= uEip
1421	&& (pCur->uEndEIP ? pCur->uEndEIP > uEip : pCur->uStartEIP == uEip))
1422	return pCur->pfnHandler(pVM, pRegFrame, pCur->uUser);
1423	}
1424
1425	return VERR_TRPM_DONT_PANIC;
1426	}
1427
1428
1429	/**
1430	* Hypervisor \#NP ((segment) Not Present) handler.
1431	*
1432	* Scans for the EIP in the registered trap handlers.
1433	*
1434	* @returns VBox status code.
1435	* VINF_SUCCESS means we completely handled this trap,
1436	* other codes are passed back to host context.
1437	*
1438	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1439	* @param pRegFrame Pointer to the register frame for the trap.
1440	* @internal
1441	*/
1442	DECLASM(int) TRPMGCHyperTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1443	{
1444	EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NP),
1445	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
1446	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0bHandlers, g_aTrap0bHandlersEnd);
1447	}
1448
1449
1450	/**
1451	* Hypervisor \#GP (General Protection Fault) handler.
1452	*
1453	* Scans for the EIP in the registered trap handlers.
1454	*
1455	* @returns VBox status code.
1456	* VINF_SUCCESS means we completely handled this trap,
1457	* other codes are passed back to host context.
1458	*
1459	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1460	* @param pRegFrame Pointer to the register frame for the trap.
1461	* @internal
1462	*/
1463	DECLASM(int) TRPMGCHyperTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1464	{
1465	EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_GP),
1466	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
1467	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1468	}
1469
1470
1471	/**
1472	* Hypervisor \#PF (Page Fault) handler.
1473	*
1474	* Scans for the EIP in the registered trap handlers.
1475	*
1476	* @returns VBox status code.
1477	* VINF_SUCCESS means we completely handled this trap,
1478	* other codes are passed back to host context.
1479	*
1480	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1481	* @param pRegFrame Pointer to the register frame for the trap.
1482	* @internal
1483	*/
1484	DECLASM(int) TRPMGCHyperTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1485	{
1486	EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_PF),
1487	pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC());
1488	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1489	}
1490
1491
1492	/**
1493	* Deal with hypervisor traps occurring when resuming execution on a trap.
1494	*
1495	* There is a little problem with recursive RC (hypervisor) traps. We deal with
1496	* this by not allowing recursion without it being the subject of a guru
1497	* meditation. (We used to / tried to handle this but there isn't any reason
1498	* for it.)
1499	*
1500	* So, do NOT use this for handling RC traps!
1501	*
1502	* @returns VBox status code. (Anything but VINF_SUCCESS will cause guru.)
1503	* @param pVM The cross context VM structure.
1504	* @param pRegFrame Register frame.
1505	* @param uUser User arg.
1506	*/
1507	DECLCALLBACK(int) trpmRCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1508	{
1509	RT_NOREF_PV(pRegFrame);
1510	Log(("********************************************************\n"));
1511	Log(("trpmRCTrapInGeneric: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
1512	Log(("********************************************************\n"));
1513
1514	/*
1515	* This used to be kind of complicated, but since we stopped storing
1516	* the register frame on the stack and instead storing it directly
1517	* in the CPUMCPU::Guest structure, we just have to figure out which
1518	* status to hand on to the host and let the recompiler/IEM do its
1519	* job.
1520	*/
1521	switch (uUser)
1522	{
1523	case TRPM_TRAP_IN_MOV_GS:
1524	case TRPM_TRAP_IN_MOV_FS:
1525	case TRPM_TRAP_IN_MOV_ES:
1526	case TRPM_TRAP_IN_MOV_DS:
1527	TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_STALE_SELECTOR);
1528	break;
1529
1530	case TRPM_TRAP_IN_IRET:
1531	case TRPM_TRAP_IN_IRET \| TRPM_TRAP_IN_V86:
1532	TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_IRET_TRAP);
1533	break;
1534
1535	default:
1536	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1537	return VERR_TRPM_BAD_TRAP_IN_OP;
1538	}
1539
1540	AssertMsgFailed(("Impossible!\n"));
1541	return VERR_TRPM_IPE_3;
1542	}
1543
1544
1545	/**
1546	* Generic hyper trap handler that sets the EIP to @a uUser.
1547	*
1548	* @returns VBox status code. (Anything but VINF_SUCCESS will cause guru.)
1549	* @param pVM The cross context VM structure.
1550	* @param pRegFrame Pointer to the register frame (within VM)
1551	* @param uUser The user arg, which should be the new EIP address.
1552	*/
1553	extern "C" DECLCALLBACK(int) TRPMRCTrapHyperHandlerSetEIP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1554	{
1555	AssertReturn(MMHyperIsInsideArea(pVM, uUser), VERR_TRPM_IPE_3);
1556	pRegFrame->eip = uUser;
1557	return VINF_SUCCESS;
1558	}
1559

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source: vbox/trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp@ 73471

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