TRPMRCHandlers.cpp@ 65381

Last change on this file since 65381 was 64626, checked in by vboxsync, 8 years ago
Recompiler, VMM, Devices: Purge the old APIC and the VBOX_WITH_NEW_APIC define.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 56.8 KB

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1	/* $Id: TRPMRCHandlers.cpp 64626 2016-11-10 10:31:39Z vboxsync $ */
2	/** @file
3	* TRPM - Raw-mode Context Trap Handlers, CPP part
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_TRPM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/iom.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/em.h>
29	#include <VBox/vmm/gim.h>
30	#include <VBox/vmm/apic.h>
31	#include <VBox/vmm/csam.h>
32	#include <VBox/vmm/patm.h>
33	#include <VBox/vmm/mm.h>
34	#include <VBox/vmm/cpum.h>
35	#include "TRPMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/vmm.h>
38	#include <VBox/param.h>
39
40	#include <VBox/err.h>
41	#include <VBox/dis.h>
42	#include <VBox/disopcode.h>
43	#include <VBox/log.h>
44	#include <VBox/vmm/tm.h>
45	#include <iprt/asm.h>
46	#include <iprt/asm-amd64-x86.h>
47	#include <iprt/assert.h>
48	#include <iprt/x86.h>
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	/* still here. MODR/M byte parsing */
55	#define X86_OPCODE_MODRM_MOD_MASK 0xc0
56	#define X86_OPCODE_MODRM_REG_MASK 0x38
57	#define X86_OPCODE_MODRM_RM_MASK 0x07
58
59	/** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
60	#define DTRACE_EXPERIMENT
61
62	#if 1
63	# define TRPM_ENTER_DBG_HOOK(a_iVector) do {} while (0)
64	# define TRPM_EXIT_DBG_HOOK(a_iVector) do {} while (0)
65	# define TRPM_ENTER_DBG_HOOK_HYPER(a_iVector) do {} while (0)
66	# define TRPM_EXIT_DBG_HOOK_HYPER(a_iVector) do {} while (0)
67	#else
68	# define TRPM_ENTER_DBG_HOOK(a_iVector) \
69	uint32_t const fDbgEFlags1 = CPUMRawGetEFlags(pVCpu); \
70	if (!(fDbgEFlags1 & X86_EFL_IF)) Log(("%s: IF=0 ##\n", __FUNCTION__)); \
71	else do {} while (0)
72	# define TRPM_EXIT_DBG_HOOK(a_iVector) \
73	do { \
74	uint32_t const fDbgEFlags2 = CPUMRawGetEFlags(pVCpu); \
75	if ((fDbgEFlags1 ^ fDbgEFlags2) & (X86_EFL_IF \| X86_EFL_IOPL)) \
76	Log(("%s: IF=%d->%d IOPL=%d->%d !#\n", __FUNCTION__, \
77	!!(fDbgEFlags1 & X86_EFL_IF), !!(fDbgEFlags2 & X86_EFL_IF), \
78	X86_EFL_GET_IOPL(fDbgEFlags1), X86_EFL_GET_IOPL(fDbgEFlags2) )); \
79	else if (!(fDbgEFlags2 & X86_EFL_IF)) Log(("%s: IF=0 [ret] ##\n", __FUNCTION__)); \
80	} while (0)
81	# define TRPM_ENTER_DBG_HOOK_HYPER(a_iVector) do {} while (0)
82	# define TRPM_EXIT_DBG_HOOK_HYPER(a_iVector) do {} while (0)
83	#endif
84
85
86	/*********************************************************************************************************************************
87	* Structures and Typedefs *
88	*********************************************************************************************************************************/
89	/** Pointer to a readonly hypervisor trap record. */
90	typedef const struct TRPMGCHYPER *PCTRPMGCHYPER;
91
92	/**
93	* A hypervisor trap record.
94	* This contains information about a handler for a instruction range.
95	*
96	* @remark This must match what TRPM_HANDLER outputs.
97	*/
98	typedef struct TRPMGCHYPER
99	{
100	/** The start address. */
101	uintptr_t uStartEIP;
102	/** The end address. (exclusive)
103	* If NULL the it's only for the instruction at pvStartEIP. */
104	uintptr_t uEndEIP;
105	/**
106	* The handler.
107	*
108	* @returns VBox status code
109	* VINF_SUCCESS means we've handled the trap.
110	* Any other error code means returning to the host context.
111	* @param pVM The cross context VM structure.
112	* @param pRegFrame The register frame.
113	* @param uUser The user argument.
114	*/
115	DECLRCCALLBACKMEMBER(int, pfnHandler, (PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser));
116	/** Whatever the handler desires to put here. */
117	uintptr_t uUser;
118	} TRPMGCHYPER;
119
120
121	/*********************************************************************************************************************************
122	* Global Variables *
123	*********************************************************************************************************************************/
124	RT_C_DECLS_BEGIN
125	/** Defined in VMMRC0.asm or VMMRC99.asm.
126	* @{ */
127	extern const TRPMGCHYPER g_aTrap0bHandlers[1];
128	extern const TRPMGCHYPER g_aTrap0bHandlersEnd[1];
129	extern const TRPMGCHYPER g_aTrap0dHandlers[1];
130	extern const TRPMGCHYPER g_aTrap0dHandlersEnd[1];
131	extern const TRPMGCHYPER g_aTrap0eHandlers[1];
132	extern const TRPMGCHYPER g_aTrap0eHandlersEnd[1];
133	/** @} */
134	RT_C_DECLS_END
135
136
137	/*********************************************************************************************************************************
138	* Internal Functions *
139	*********************************************************************************************************************************/
140	RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
141	DECLCALLBACK(int) trpmRCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
142	RT_C_DECLS_END
143
144
145
146	/**
147	* Exits the trap, called when exiting a trap handler.
148	*
149	* Will reset the trap if it's not a guest trap or the trap
150	* is already handled. Will process resume guest FFs.
151	*
152	* @returns rc, can be adjusted if its VINF_SUCCESS or something really bad
153	* happened.
154	* @param pVM The cross context VM structure.
155	* @param pVCpu The cross context virtual CPU structure.
156	* @param rc The VBox status code to return.
157	* @param pRegFrame Pointer to the register frame for the trap.
158	*
159	* @remarks This must not be used for hypervisor traps, only guest traps.
160	*/
161	static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
162	{
163	uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
164	NOREF(uOldActiveVector);
165
166	/* Reset trap? */
167	if ( rc != VINF_EM_RAW_GUEST_TRAP
168	&& rc != VINF_EM_RAW_RING_SWITCH_INT)
169	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
170
171	#ifdef VBOX_HIGH_RES_TIMERS_HACK
172	/*
173	* We should poll the timers occasionally.
174	* We must NOT do this too frequently as it adds a significant overhead
175	* and it'll kill us if the trap load is high. (See @bugref{1354}.)
176	* (The heuristic is not very intelligent, we should really check trap
177	* frequency etc. here, but alas, we lack any such information atm.)
178	*/
179	static unsigned s_iTimerPoll = 0;
180	if (rc == VINF_SUCCESS)
181	{
182	if (!(++s_iTimerPoll & 0xf))
183	{
184	TMTimerPollVoid(pVM, pVCpu);
185	Log2(("TMTimerPoll at %08RX32 - VM_FF_TM_VIRTUAL_SYNC=%d VM_FF_TM_VIRTUAL_SYNC=%d\n", pRegFrame->eip,
186	VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER)));
187	}
188	}
189	else
190	s_iTimerPoll = 0;
191	#endif
192
193	/* Clear pending inhibit interrupt state if required. (necessary for dispatching interrupts later on) */
194	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
195	{
196	Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
197	if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
198	{
199	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
200	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
201	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
202	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
203	*/
204	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
205	}
206	}
207
208	/*
209	* Pending resume-guest-FF?
210	* Or pending (A)PIC interrupt? Windows XP will crash if we delay APIC interrupts.
211	*/
212	if ( rc == VINF_SUCCESS
213	&& ( VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC \| VM_FF_REQUEST \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_DMA)
214	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_TO_R3
215	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
216	\| VMCPU_FF_REQUEST \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
217	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_IEM \| VMCPU_FF_SELM_SYNC_GDT
218	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
219	\| VMCPU_FF_IOM \| VMCPU_FF_CPUM
220	)
221	)
222	)
223	{
224	/* The out of memory condition naturally outranks the others. */
225	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
226	rc = VINF_EM_NO_MEMORY;
227	else
228	{
229	/* APIC needs updating. */
230	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
231	APICUpdatePendingInterrupts(pVCpu);
232
233	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_CPUM))
234	CPUMRCProcessForceFlag(pVCpu);
235
236	/* Pending Ring-3 action. */
237	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TO_R3 \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_IEM \| VMCPU_FF_IOM))
238	{
239	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
240	rc = VINF_EM_RAW_TO_R3;
241	}
242	/* Pending timer action. */
243	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER))
244	rc = VINF_EM_RAW_TIMER_PENDING;
245	/* The Virtual Sync clock has stopped. */
246	else if (VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
247	rc = VINF_EM_RAW_TO_R3;
248	/* DMA work pending? */
249	else if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
250	rc = VINF_EM_RAW_TO_R3;
251	/* Pending request packets might contain actions that need immediate
252	attention, such as pending hardware interrupts. */
253	else if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
254	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
255	rc = VINF_EM_PENDING_REQUEST;
256	/* Pending GDT/LDT/TSS sync. */
257	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS))
258	rc = VINF_SELM_SYNC_GDT;
259	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
260	rc = VINF_EM_RAW_TO_R3;
261	/* Possibly pending interrupt: dispatch it. */
262	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
263	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
264	&& PATMAreInterruptsEnabledByCtx(pVM, CPUMCTX_FROM_CORE(pRegFrame))
265	)
266	{
267	uint8_t u8Interrupt;
268	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
269	Log(("trpmGCExitTrap: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
270	if (RT_SUCCESS(rc))
271	{
272	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
273	/* can't return if successful */
274	Assert(rc != VINF_SUCCESS);
275
276	/* Stop the profile counter that was started in TRPMRCHandlersA.asm */
277	Assert(uOldActiveVector <= 16);
278	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
279
280	/* Assert the trap and go to the recompiler to dispatch it. */
281	TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
282
283	STAM_PROFILE_ADV_START(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
284	rc = VINF_EM_RAW_INTERRUPT_PENDING;
285	}
286	else if ( rc == VERR_APIC_INTR_MASKED_BY_TPR /* Can happen if TPR is too high for the newly arrived interrupt. */
287	\|\| rc == VERR_NO_DATA) /* Can happen if the APIC is disabled. */
288	{
289	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
290	rc = VINF_SUCCESS;
291	}
292	else
293	AssertFatalMsgRC(rc, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
294	}
295	/*
296	* Try sync CR3?
297	*/
298	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
299	{
300	#if 1
301	PGMRZDynMapReleaseAutoSet(pVCpu);
302	PGMRZDynMapStartAutoSet(pVCpu);
303	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
304	#else
305	rc = VINF_PGM_SYNC_CR3;
306	#endif
307	}
308	}
309	}
310
311	/* Note! TRPMRCHandlersA.asm performs sanity checks in debug builds.*/
312	PGMRZDynMapReleaseAutoSet(pVCpu);
313	return rc;
314	}
315
316
317	/**
318	* \#DB (Debug event) handler.
319	*
320	* @returns VBox status code.
321	* VINF_SUCCESS means we completely handled this trap,
322	* other codes are passed execution to host context.
323	*
324	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
325	* @param pRegFrame Pointer to the register frame for the trap.
326	* @internal
327	*/
328	DECLASM(int) TRPMGCTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
329	{
330	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
331	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
332	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
333	LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
334	TRPM_ENTER_DBG_HOOK(1);
335
336	/*
337	* We currently don't make use of the X86_DR7_GD bit, but
338	* there might come a time when we do.
339	*/
340	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
341	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
342	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
343	VERR_NOT_IMPLEMENTED);
344	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
345
346	/*
347	* Now leave the rest to the DBGF.
348	*/
349	PGMRZDynMapStartAutoSet(pVCpu);
350	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6, false /fAltStepping/);
351	if (rc == VINF_EM_RAW_GUEST_TRAP)
352	{
353	CPUMSetGuestDR6(pVCpu, (CPUMGetGuestDR6(pVCpu) & ~X86_DR6_B_MASK) \| uDr6);
354	if (CPUMGetGuestDR7(pVCpu) & X86_DR7_GD)
355	CPUMSetGuestDR7(pVCpu, CPUMGetGuestDR7(pVCpu) & ~X86_DR7_GD);
356	}
357	else if (rc == VINF_EM_DBG_STEPPED)
358	pRegFrame->eflags.Bits.u1TF = 0;
359
360	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
361	Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg EFlag=%#x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
362	TRPM_EXIT_DBG_HOOK(1);
363	return rc;
364	}
365
366
367	/**
368	* \#DB (Debug event) handler for the hypervisor code.
369	*
370	* This is mostly the same as TRPMGCTrap01Handler, but we skip the PGM auto
371	* mapping set as well as the default trap exit path since they are both really
372	* bad ideas in this context.
373	*
374	* @returns VBox status code.
375	* VINF_SUCCESS means we completely handled this trap,
376	* other codes are passed execution to host context.
377	*
378	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
379	* @param pRegFrame Pointer to the register frame for the trap.
380	* @internal
381	*/
382	DECLASM(int) TRPMGCHyperTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
383	{
384	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
385	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
386	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
387	TRPM_ENTER_DBG_HOOK_HYPER(1);
388	LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
389
390	/*
391	* We currently don't make use of the X86_DR7_GD bit, but
392	* there might come a time when we do.
393	*/
394	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
395	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
396	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
397	VERR_NOT_IMPLEMENTED);
398	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
399
400	/*
401	* Now leave the rest to the DBGF.
402	*/
403	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6, false /fAltStepping/);
404	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_1);
405	if (rc == VINF_EM_DBG_STEPPED)
406	pRegFrame->eflags.Bits.u1TF = 0;
407
408	Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
409	TRPM_EXIT_DBG_HOOK_HYPER(1);
410	return rc;
411	}
412
413
414	/**
415	* NMI handler, for when we are using NMIs to debug things.
416	*
417	* @returns VBox status code.
418	* VINF_SUCCESS means we completely handled this trap,
419	* other codes are passed execution to host context.
420	*
421	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
422	* @param pRegFrame Pointer to the register frame for the trap.
423	* @internal
424	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
425	*/
426	DECLASM(int) TRPMGCTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
427	{
428	LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
429	#if 0 /* Enable this iff you have a COM port and really want this debug info. */
430	RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
431	#endif
432	NOREF(pTrpmCpu); RT_NOREF_PV(pRegFrame);
433	return VERR_TRPM_DONT_PANIC;
434	}
435
436
437	/**
438	* NMI handler, for when we are using NMIs to debug things.
439	*
440	* This is the handler we're most likely to hit when the NMI fires (it is
441	* unlikely that we'll be stuck in guest code).
442	*
443	* @returns VBox status code.
444	* VINF_SUCCESS means we completely handled this trap,
445	* other codes are passed execution to host context.
446	*
447	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
448	* @param pRegFrame Pointer to the register frame for the trap.
449	* @internal
450	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
451	*/
452	DECLASM(int) TRPMGCHyperTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
453	{
454	LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
455	#if 0 /* Enable this iff you have a COM port and really want this debug info. */
456	RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
457	#endif
458	NOREF(pTrpmCpu); RT_NOREF_PV(pRegFrame);
459	return VERR_TRPM_DONT_PANIC;
460	}
461
462
463	/**
464	* \#BP (Breakpoint) handler.
465	*
466	* @returns VBox status code.
467	* VINF_SUCCESS means we completely handled this trap,
468	* other codes are passed execution to host context.
469	*
470	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
471	* @param pRegFrame Pointer to the register frame for the trap.
472	* @internal
473	*/
474	DECLASM(int) TRPMGCTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
475	{
476	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
477	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
478	int rc;
479	LogFlow(("TRPMGC03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
480	TRPM_ENTER_DBG_HOOK(3);
481	PGMRZDynMapStartAutoSet(pVCpu);
482
483	/*
484	* PATM is using INT3s, let them have a go first.
485	*/
486	if ( ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1
487	\|\| (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2) )
488	&& !pRegFrame->eflags.Bits.u1VM)
489	{
490	rc = PATMRCHandleInt3PatchTrap(pVM, pRegFrame);
491	if ( rc == VINF_SUCCESS
492	\|\| rc == VINF_EM_RESCHEDULE
493	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
494	\|\| rc == VINF_PATM_PATCH_INT3
495	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION )
496	{
497	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
498	Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
499	TRPM_EXIT_DBG_HOOK(3);
500	return rc;
501	}
502	}
503	rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
504
505	/* anything we should do with this? Schedule it in GC? */
506	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
507	Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
508	TRPM_EXIT_DBG_HOOK(3);
509	return rc;
510	}
511
512
513	/**
514	* \#BP (Breakpoint) handler.
515	*
516	* This is similar to TRPMGCTrap03Handler but we bits which are potentially
517	* harmful to us (common trap exit and the auto mapping set).
518	*
519	* @returns VBox status code.
520	* VINF_SUCCESS means we completely handled this trap,
521	* other codes are passed execution to host context.
522	*
523	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
524	* @param pRegFrame Pointer to the register frame for the trap.
525	* @internal
526	*/
527	DECLASM(int) TRPMGCHyperTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
528	{
529	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
530	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
531	LogFlow(("TRPMGCHyper03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
532	TRPM_ENTER_DBG_HOOK_HYPER(3);
533
534	/*
535	* Hand it over to DBGF.
536	*/
537	int rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
538	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_2);
539
540	Log6(("TRPMGCHyper03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
541	TRPM_EXIT_DBG_HOOK_HYPER(3);
542	return rc;
543	}
544
545
546	/**
547	* Trap handler for illegal opcode fault (\#UD).
548	*
549	* @returns VBox status code.
550	* VINF_SUCCESS means we completely handled this trap,
551	* other codes are passed execution to host context.
552	*
553	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
554	* @param pRegFrame Pointer to the register frame for the trap.
555	* @internal
556	*/
557	DECLASM(int) TRPMGCTrap06Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
558	{
559	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
560	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
561	int rc;
562	LogFlow(("TRPMGC06: %04x:%08x EFL=%#x/%#x\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->eflags.u32, CPUMRawGetEFlags(pVCpu)));
563	TRPM_ENTER_DBG_HOOK(6);
564	PGMRZDynMapStartAutoSet(pVCpu);
565
566	if (CPUMGetGuestCPL(pVCpu) <= (EMIsRawRing1Enabled(pVM) ? 1U : 0U))
567	{
568	/*
569	* Decode the instruction.
570	*/
571	RTGCPTR PC;
572	rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
573	pRegFrame->rip, &PC);
574	if (RT_FAILURE(rc))
575	{
576	Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
577	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
578	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (SELM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
579	TRPM_EXIT_DBG_HOOK(6);
580	return rc;
581	}
582
583	DISCPUSTATE Cpu;
584	uint32_t cbOp;
585	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
586	if (RT_FAILURE(rc))
587	{
588	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
589	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (EM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
590	TRPM_EXIT_DBG_HOOK(6);
591	return rc;
592	}
593
594	/*
595	* UD2 in a patch?
596	* Note! PATMGCHandleIllegalInstrTrap doesn't always return.
597	*/
598	if ( Cpu.pCurInstr->uOpcode == OP_ILLUD2
599	&& PATMIsPatchGCAddr(pVM, pRegFrame->eip))
600	{
601	LogFlow(("TRPMGCTrap06Handler: -> PATMRCHandleIllegalInstrTrap\n"));
602	rc = PATMRCHandleIllegalInstrTrap(pVM, pRegFrame);
603	/** @todo These tests are completely unnecessary, should just follow the
604	* flow and return at the end of the function. */
605	if ( rc == VINF_SUCCESS
606	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
607	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION
608	\|\| rc == VINF_PATM_PENDING_IRQ_AFTER_IRET
609	\|\| rc == VINF_EM_RESCHEDULE)
610	{
611	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
612	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
613	TRPM_EXIT_DBG_HOOK(6);
614	return rc;
615	}
616	}
617	/*
618	* Speed up dtrace and don't entrust invalid lock sequences to the recompiler.
619	*/
620	else if (Cpu.fPrefix & DISPREFIX_LOCK)
621	{
622	Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->uOpcode));
623	#ifdef DTRACE_EXPERIMENT /** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
624	Assert(!PATMIsPatchGCAddr(pVM, pRegFrame->eip));
625	rc = TRPMForwardTrap(pVCpu, pRegFrame, X86_XCPT_UD, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, X86_XCPT_UD);
626	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
627	#else
628	rc = VINF_EM_RAW_EMULATE_INSTR;
629	#endif
630	}
631	/*
632	* Handle MONITOR - it causes an #UD exception instead of #GP when not executed in ring 0.
633	*/
634	else if (Cpu.pCurInstr->uOpcode == OP_MONITOR)
635	{
636	LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
637	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR));
638	}
639	else if (GIMShouldTrapXcptUD(pVCpu))
640	{
641	LogFlow(("TRPMGCTrap06Handler: -> GIMXcptUD\n"));
642	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, CPUMCTX_FROM_CORE(pRegFrame), &Cpu, NULL /* pcbInstr */);
643	if (rcStrict == VINF_SUCCESS)
644	{
645	/* The interrupt inhibition wrt to EIP will be handled by trpmGCExitTrap() below. */
646	pRegFrame->eip += Cpu.cbInstr;
647	Assert(Cpu.cbInstr);
648	}
649	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
650	rc = VINF_SUCCESS;
651	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
652	rc = VINF_GIM_R3_HYPERCALL;
653	else
654	{
655	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
656	LogFlow(("TRPMGCTrap06Handler: GIMXcptUD returns %Rrc -> VINF_EM_RAW_EMULATE_INSTR\n", rc));
657	rc = VINF_EM_RAW_EMULATE_INSTR;
658	}
659	}
660	/* Never generate a raw trap here; it might be an instruction, that requires emulation. */
661	else
662	{
663	LogFlow(("TRPMGCTrap06Handler: -> VINF_EM_RAW_EMULATE_INSTR\n"));
664	rc = VINF_EM_RAW_EMULATE_INSTR;
665	}
666	}
667	else
668	{
669	LogFlow(("TRPMGCTrap06Handler: -> TRPMForwardTrap\n"));
670	rc = TRPMForwardTrap(pVCpu, pRegFrame, X86_XCPT_UD, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, X86_XCPT_UD);
671	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
672	}
673
674	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
675	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
676	TRPM_EXIT_DBG_HOOK(6);
677	return rc;
678	}
679
680
681	/**
682	* Trap handler for device not present fault (\#NM).
683	*
684	* Device not available, FP or (F)WAIT instruction.
685	*
686	* @returns VBox status code.
687	* VINF_SUCCESS means we completely handled this trap,
688	* other codes are passed execution to host context.
689	*
690	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
691	* @param pRegFrame Pointer to the register frame for the trap.
692	* @internal
693	*/
694	DECLASM(int) TRPMGCTrap07Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
695	{
696	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
697	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
698	LogFlow(("TRPMGC07: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
699	TRPM_ENTER_DBG_HOOK(7);
700	PGMRZDynMapStartAutoSet(pVCpu);
701
702	int rc = CPUMHandleLazyFPU(pVCpu);
703	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
704	Log6(("TRPMGC07: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
705	TRPM_EXIT_DBG_HOOK(7);
706	return rc;
707	}
708
709
710	/**
711	* \#NP ((segment) Not Present) handler.
712	*
713	* @returns VBox status code.
714	* VINF_SUCCESS means we completely handled this trap,
715	* other codes are passed execution to host context.
716	*
717	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
718	* @param pRegFrame Pointer to the register frame for the trap.
719	* @internal
720	*/
721	DECLASM(int) TRPMGCTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
722	{
723	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
724	LogFlow(("TRPMGC0b: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
725	TRPM_ENTER_DBG_HOOK(0xb);
726	PGMRZDynMapStartAutoSet(pVCpu);
727
728	/*
729	* Try to detect instruction by opcode which caused trap.
730	* XXX note: this code may cause \#PF (trap e) or \#GP (trap d) while
731	* accessing user code. need to handle it somehow in future!
732	*/
733	RTGCPTR GCPtr;
734	if ( SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
735	(RTGCPTR)pRegFrame->eip, &GCPtr)
736	== VINF_SUCCESS)
737	{
738	uint8_t pu8Code = (uint8_t )(uintptr_t)GCPtr;
739
740	/*
741	* First skip possible instruction prefixes, such as:
742	* OS, AS
743	* CS:, DS:, ES:, SS:, FS:, GS:
744	* REPE, REPNE
745	*
746	* note: Currently we supports only up to 4 prefixes per opcode, more
747	* prefixes (normally not used anyway) will cause trap d in guest.
748	* note: Instruction length in IA-32 may be up to 15 bytes, we dont
749	* check this issue, its too hard.
750	*/
751	for (unsigned i = 0; i < 4; i++)
752	{
753	if ( pu8Code[0] != 0xf2 /* REPNE/REPNZ */
754	&& pu8Code[0] != 0xf3 /* REP/REPE/REPZ */
755	&& pu8Code[0] != 0x2e /* CS: */
756	&& pu8Code[0] != 0x36 /* SS: */
757	&& pu8Code[0] != 0x3e /* DS: */
758	&& pu8Code[0] != 0x26 /* ES: */
759	&& pu8Code[0] != 0x64 /* FS: */
760	&& pu8Code[0] != 0x65 /* GS: */
761	&& pu8Code[0] != 0x66 /* OS */
762	&& pu8Code[0] != 0x67 /* AS */
763	)
764	break;
765	pu8Code++;
766	}
767
768	/*
769	* Detect right switch using a callgate.
770	*
771	* We recognize the following causes for the trap 0b:
772	* CALL FAR, CALL FAR []
773	* JMP FAR, JMP FAR []
774	* IRET (may cause a task switch)
775	*
776	* Note: we can't detect whether the trap was caused by a call to a
777	* callgate descriptor or it is a real trap 0b due to a bad selector.
778	* In both situations we'll pass execution to our recompiler so we don't
779	* have to worry.
780	* If we wanted to do better detection, we have set GDT entries to callgate
781	* descriptors pointing to our own handlers.
782	*/
783	/** @todo not sure about IRET, may generate Trap 0d (\#GP), NEED TO CHECK! */
784	if ( pu8Code[0] == 0x9a /* CALL FAR */
785	\|\| ( pu8Code[0] == 0xff /* CALL FAR [] */
786	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x18)
787	\|\| pu8Code[0] == 0xea /* JMP FAR */
788	\|\| ( pu8Code[0] == 0xff /* JMP FAR [] */
789	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x28)
790	\|\| pu8Code[0] == 0xcf /* IRET */
791	)
792	{
793	/*
794	* Got potential call to callgate.
795	* We simply return execution to the recompiler to do emulation
796	* starting from the instruction which caused the trap.
797	*/
798	pTrpmCpu->uActiveVector = UINT32_MAX;
799	Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
800	TRPM_EXIT_DBG_HOOK(0xb);
801	PGMRZDynMapReleaseAutoSet(pVCpu);
802	return VINF_EM_RAW_RING_SWITCH;
803	}
804	}
805
806	/*
807	* Pass trap 0b as is to the recompiler in all other cases.
808	*/
809	Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
810	PGMRZDynMapReleaseAutoSet(pVCpu);
811	TRPM_EXIT_DBG_HOOK(0xb);
812	return VINF_EM_RAW_GUEST_TRAP;
813	}
814
815
816	/**
817	* \#GP (General Protection Fault) handler for Ring-0 privileged instructions.
818	*
819	* @returns VBox status code.
820	* VINF_SUCCESS means we completely handled this trap,
821	* other codes are passed execution to host context.
822	*
823	* @param pVM The cross context VM structure.
824	* @param pVCpu The cross context virtual CPU structure.
825	* @param pRegFrame Pointer to the register frame for the trap.
826	* @param pCpu The opcode info.
827	* @param PC The program counter corresponding to cs:eip in pRegFrame.
828	*/
829	static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
830	{
831	int rc;
832	TRPM_ENTER_DBG_HOOK(0xd);
833
834	/*
835	* Try handle it here, if not return to HC and emulate/interpret it there.
836	*/
837	switch (pCpu->pCurInstr->uOpcode)
838	{
839	case OP_INT3:
840	/*
841	* Little hack to make the code below not fail
842	*/
843	pCpu->Param1.fUse = DISUSE_IMMEDIATE8;
844	pCpu->Param1.uValue = 3;
845	/* fallthru */
846	case OP_INT:
847	{
848	Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
849	Assert(!(PATMIsPatchGCAddr(pVM, PC)));
850	if (pCpu->Param1.uValue == 3)
851	{
852	/* Int 3 replacement patch? */
853	if (PATMRCHandleInt3PatchTrap(pVM, pRegFrame) == VINF_SUCCESS)
854	{
855	AssertFailed();
856	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
857	}
858	}
859	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
860	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
861	{
862	TRPM_EXIT_DBG_HOOK(0xd);
863	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
864	}
865
866	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
867	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
868	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
869	}
870
871	#ifdef PATM_EMULATE_SYSENTER
872	case OP_SYSEXIT:
873	case OP_SYSRET:
874	rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu);
875	TRPM_EXIT_DBG_HOOK(0xd);
876	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
877	#endif
878
879	case OP_HLT:
880	/* If it's in patch code, defer to ring-3. */
881	if (PATMIsPatchGCAddr(pVM, PC))
882	break;
883
884	pRegFrame->eip += pCpu->cbInstr;
885	TRPM_EXIT_DBG_HOOK(0xd);
886	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame);
887
888
889	/*
890	* These instructions are used by PATM and CASM for finding
891	* dangerous non-trapping instructions. Thus, since all
892	* scanning and patching is done in ring-3 we'll have to
893	* return to ring-3 on the first encounter of these instructions.
894	*/
895	case OP_MOV_CR:
896	case OP_MOV_DR:
897	/* We can safely emulate control/debug register move instructions in patched code. */
898	if ( !PATMIsPatchGCAddr(pVM, PC)
899	&& !CSAMIsKnownDangerousInstr(pVM, PC))
900	break;
901	case OP_INVLPG:
902	case OP_LLDT:
903	case OP_STI:
904	case OP_RDTSC: /* just in case */
905	case OP_RDPMC:
906	case OP_CLTS:
907	case OP_WBINVD: /* nop */
908	case OP_RDMSR:
909	case OP_WRMSR:
910	{
911	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR));
912	if (rc == VERR_EM_INTERPRETER)
913	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
914	TRPM_EXIT_DBG_HOOK(0xd);
915	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
916	}
917	}
918
919	TRPM_EXIT_DBG_HOOK(0xd);
920	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EXCEPTION_PRIVILEGED, pRegFrame);
921	}
922
923
924	/**
925	* \#GP (General Protection Fault) handler for Ring-3.
926	*
927	* @returns VBox status code.
928	* VINF_SUCCESS means we completely handled this trap,
929	* other codes are passed execution to host context.
930	*
931	* @param pVM The cross context VM structure.
932	* @param pVCpu The cross context virtual CPU structure.
933	* @param pRegFrame Pointer to the register frame for the trap.
934	* @param pCpu The opcode info.
935	* @param PC The program counter corresponding to cs:eip in pRegFrame.
936	*/
937	static int trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
938	{
939	int rc;
940	Assert(!pRegFrame->eflags.Bits.u1VM);
941	TRPM_ENTER_DBG_HOOK(0xd);
942
943	switch (pCpu->pCurInstr->uOpcode)
944	{
945	/*
946	* INT3 and INT xx are ring-switching.
947	* (The shadow IDT will have set the entries to DPL=0, that's why we're here.)
948	*/
949	case OP_INT3:
950	/*
951	* Little hack to make the code below not fail
952	*/
953	pCpu->Param1.fUse = DISUSE_IMMEDIATE8;
954	pCpu->Param1.uValue = 3;
955	/* fall thru */
956	case OP_INT:
957	{
958	Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
959	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
960	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
961	{
962	TRPM_EXIT_DBG_HOOK(0xd);
963	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
964	}
965
966	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
967	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
968	TRPM_EXIT_DBG_HOOK(0xd);
969	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
970	}
971
972	/*
973	* SYSCALL, SYSENTER, INTO and BOUND are also ring-switchers.
974	*/
975	case OP_SYSCALL:
976	case OP_SYSENTER:
977	#ifdef PATM_EMULATE_SYSENTER
978	rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu);
979	if (rc == VINF_SUCCESS)
980	{
981	TRPM_EXIT_DBG_HOOK(0xd);
982	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
983	}
984	/* else no break; */
985	#endif
986	case OP_BOUND:
987	case OP_INTO:
988	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
989	TRPM_EXIT_DBG_HOOK(0xd);
990	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH, pRegFrame);
991
992	/*
993	* Handle virtualized TSC & PMC reads, just in case.
994	*/
995	case OP_RDTSC:
996	case OP_RDPMC:
997	{
998	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR));
999	if (rc == VERR_EM_INTERPRETER)
1000	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1001	TRPM_EXIT_DBG_HOOK(0xd);
1002	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1003	}
1004
1005	/*
1006	* STI and CLI are I/O privileged, i.e. if IOPL
1007	*/
1008	case OP_STI:
1009	case OP_CLI:
1010	{
1011	uint32_t efl = CPUMRawGetEFlags(pVCpu);
1012	uint32_t cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1013	if (X86_EFL_GET_IOPL(efl) >= cpl)
1014	{
1015	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> REM\n"));
1016	TRPM_EXIT_DBG_HOOK(0xd);
1017	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RESCHEDULE_REM, pRegFrame);
1018	}
1019	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> #GP(0) iopl=%x, cpl=%x\n", X86_EFL_GET_IOPL(efl), cpl));
1020	break;
1021	}
1022	}
1023
1024	/*
1025	* A genuine guest fault.
1026	*/
1027	TRPM_EXIT_DBG_HOOK(0xd);
1028	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
1029	}
1030
1031
1032	/**
1033	* Emulates RDTSC for the \#GP handler.
1034	*
1035	* @returns VINF_SUCCESS or VINF_EM_RAW_EMULATE_INSTR.
1036	*
1037	* @param pVM The cross context VM structure.
1038	* @param pVCpu The cross context virtual CPU structure.
1039	* @param pRegFrame Pointer to the register frame for the trap.
1040	* This will be updated on successful return.
1041	*/
1042	DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1043	{
1044	STAM_COUNTER_INC(&pVM->trpm.s.StatTrap0dRdTsc);
1045	TRPM_ENTER_DBG_HOOK(0xd);
1046
1047	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
1048	{
1049	TRPM_EXIT_DBG_HOOK(0xd);
1050	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
1051	}
1052
1053	uint64_t uTicks = TMCpuTickGet(pVCpu);
1054	pRegFrame->eax = uTicks;
1055	pRegFrame->edx = uTicks >> 32;
1056	pRegFrame->eip += 2;
1057	TRPM_EXIT_DBG_HOOK(0xd);
1058	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
1059	}
1060
1061
1062	/**
1063	* \#GP (General Protection Fault) handler.
1064	*
1065	* @returns VBox status code.
1066	* VINF_SUCCESS means we completely handled this trap,
1067	* other codes are passed execution to host context.
1068	*
1069	* @param pVM The cross context VM structure.
1070	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1071	* @param pRegFrame Pointer to the register frame for the trap.
1072	*/
1073	static int trpmGCTrap0dHandler(PVM pVM, PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1074	{
1075	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1076	LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, pTrpmCpu->uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1077	TRPM_ENTER_DBG_HOOK(0xd);
1078
1079	/*
1080	* Convert and validate CS.
1081	*/
1082	STAM_PROFILE_START(&pVM->trpm.s.StatTrap0dDisasm, a);
1083	RTGCPTR PC;
1084	int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
1085	pRegFrame->rip, &PC);
1086	if (RT_FAILURE(rc))
1087	{
1088	Log(("trpmGCTrap0dHandler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n",
1089	pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
1090	TRPM_EXIT_DBG_HOOK(0xd);
1091	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1092	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1093	}
1094
1095	/*
1096	* Disassemble the instruction.
1097	*/
1098	DISCPUSTATE Cpu;
1099	uint32_t cbOp;
1100	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
1101	if (RT_FAILURE(rc))
1102	{
1103	AssertMsgFailed(("DISCoreOneEx failed to PC=%RGv rc=%Rrc\n", PC, rc));
1104	TRPM_EXIT_DBG_HOOK(0xd);
1105	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1106	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1107	}
1108	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1109
1110	/*
1111	* Optimize RDTSC traps.
1112	* Some guests (like Solaris) are using RDTSC all over the place and
1113	* will end up trapping a lot because of that.
1114	*
1115	* Note: it's no longer safe to access the instruction opcode directly due to possible stale code TLB entries
1116	*/
1117	if (Cpu.pCurInstr->uOpcode == OP_RDTSC)
1118	return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);
1119
1120	/*
1121	* Deal with I/O port access.
1122	*/
1123	if ( pVCpu->trpm.s.uActiveErrorCode == 0
1124	&& (Cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
1125	{
1126	VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, pVCpu, pRegFrame, &Cpu);
1127	TRPM_EXIT_DBG_HOOK(0xd);
1128	return trpmGCExitTrap(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict), pRegFrame);
1129	}
1130
1131	/*
1132	* Deal with Ring-0 (privileged instructions)
1133	*/
1134	if ( (pRegFrame->ss.Sel & X86_SEL_RPL) <= 1
1135	&& !pRegFrame->eflags.Bits.u1VM)
1136	return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
1137
1138	/*
1139	* Deal with Ring-3 GPs.
1140	*/
1141	if (!pRegFrame->eflags.Bits.u1VM)
1142	return trpmGCTrap0dHandlerRing3(pVM, pVCpu, pRegFrame, &Cpu, PC);
1143
1144	/*
1145	* Deal with v86 code.
1146	*
1147	* We always set IOPL to zero which makes e.g. pushf fault in V86
1148	* mode. The guest might use IOPL=3 and therefore not expect a #GP.
1149	* Simply fall back to the recompiler to emulate this instruction if
1150	* that's the case. To get the correct we must use CPUMRawGetEFlags.
1151	*/
1152	X86EFLAGS eflags;
1153	eflags.u32 = CPUMRawGetEFlags(pVCpu); /* Get the correct value. */
1154	Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs.Sel, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
1155	if (eflags.Bits.u2IOPL != 3)
1156	{
1157	Assert(EMIsRawRing1Enabled(pVM) \|\| eflags.Bits.u2IOPL == 0);
1158
1159	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xD, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xd);
1160	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1161	TRPM_EXIT_DBG_HOOK(0xd);
1162	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1163	}
1164	TRPM_EXIT_DBG_HOOK(0xd);
1165	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1166	}
1167
1168
1169	/**
1170	* \#GP (General Protection Fault) handler.
1171	*
1172	* @returns VBox status code.
1173	* VINF_SUCCESS means we completely handled this trap,
1174	* other codes are passed execution to host context.
1175	*
1176	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1177	* @param pRegFrame Pointer to the register frame for the trap.
1178	* @internal
1179	*/
1180	DECLASM(int) TRPMGCTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1181	{
1182	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1183	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1184	LogFlow(("TRPMGC0d: %04x:%08x err=%x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1185	TRPM_ENTER_DBG_HOOK(0xd);
1186
1187	PGMRZDynMapStartAutoSet(pVCpu);
1188	int rc = trpmGCTrap0dHandler(pVM, pTrpmCpu, pRegFrame);
1189	switch (rc)
1190	{
1191	case VINF_EM_RAW_GUEST_TRAP:
1192	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1193	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1194	rc = VINF_PATM_PATCH_TRAP_GP;
1195	break;
1196
1197	case VINF_EM_RAW_INTERRUPT_PENDING:
1198	Assert(TRPMHasTrap(pVCpu));
1199	/* no break; */
1200	case VINF_PGM_SYNC_CR3:
1201	case VINF_EM_RAW_EMULATE_INSTR:
1202	case VINF_IOM_R3_IOPORT_READ:
1203	case VINF_IOM_R3_IOPORT_WRITE:
1204	case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
1205	case VINF_IOM_R3_MMIO_WRITE:
1206	case VINF_IOM_R3_MMIO_COMMIT_WRITE:
1207	case VINF_IOM_R3_MMIO_READ:
1208	case VINF_IOM_R3_MMIO_READ_WRITE:
1209	case VINF_CPUM_R3_MSR_READ:
1210	case VINF_CPUM_R3_MSR_WRITE:
1211	case VINF_PATM_PATCH_INT3:
1212	case VINF_EM_NO_MEMORY:
1213	case VINF_EM_RAW_TO_R3:
1214	case VINF_EM_RAW_TIMER_PENDING:
1215	case VINF_EM_PENDING_REQUEST:
1216	case VINF_EM_HALT:
1217	case VINF_SELM_SYNC_GDT:
1218	case VINF_SUCCESS:
1219	break;
1220
1221	default:
1222	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("return code %d\n", rc));
1223	break;
1224	}
1225	Log6(("TRPMGC0d: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
1226	TRPM_EXIT_DBG_HOOK(0xd);
1227	return rc;
1228	}
1229
1230
1231	/**
1232	* \#PF (Page Fault) handler.
1233	*
1234	* Calls PGM which does the actual handling.
1235	*
1236	*
1237	* @returns VBox status code.
1238	* VINF_SUCCESS means we completely handled this trap,
1239	* other codes are passed execution to host context.
1240	*
1241	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1242	* @param pRegFrame Pointer to the register frame for the trap.
1243	* @internal
1244	*/
1245	DECLASM(int) TRPMGCTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1246	{
1247	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1248	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1249	LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2, CPUMRawGetEFlags(pVCpu)));
1250	TRPM_ENTER_DBG_HOOK(0xe);
1251
1252	/*
1253	* This is all PGM stuff.
1254	*/
1255	PGMRZDynMapStartAutoSet(pVCpu);
1256	int rc = PGMTrap0eHandler(pVCpu, pVCpu->trpm.s.uActiveErrorCode, pRegFrame, (RTGCPTR)pVCpu->trpm.s.uActiveCR2);
1257	switch (rc)
1258	{
1259	case VINF_EM_RAW_EMULATE_INSTR:
1260	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
1261	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
1262	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
1263	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
1264	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1265	rc = VINF_PATCH_EMULATE_INSTR;
1266	break;
1267
1268	case VINF_EM_RAW_GUEST_TRAP:
1269	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1270	{
1271	PGMRZDynMapReleaseAutoSet(pVCpu);
1272	TRPM_EXIT_DBG_HOOK(0xe);
1273	return VINF_PATM_PATCH_TRAP_PF;
1274	}
1275
1276	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xE, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xe);
1277	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1278	break;
1279
1280	case VINF_EM_RAW_INTERRUPT_PENDING:
1281	Assert(TRPMHasTrap(pVCpu));
1282	/* no break; */
1283	case VINF_IOM_R3_MMIO_READ:
1284	case VINF_IOM_R3_MMIO_WRITE:
1285	case VINF_IOM_R3_MMIO_COMMIT_WRITE:
1286	case VINF_IOM_R3_MMIO_READ_WRITE:
1287	case VINF_PATM_HC_MMIO_PATCH_READ:
1288	case VINF_PATM_HC_MMIO_PATCH_WRITE:
1289	case VINF_SUCCESS:
1290	case VINF_EM_RAW_TO_R3:
1291	case VINF_EM_PENDING_REQUEST:
1292	case VINF_EM_RAW_TIMER_PENDING:
1293	case VINF_EM_NO_MEMORY:
1294	case VINF_CSAM_PENDING_ACTION:
1295	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1296	break;
1297
1298	default:
1299	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("Patch address for return code %d. eip=%08x\n", rc, pRegFrame->eip));
1300	break;
1301	}
1302	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1303	Log6(("TRPMGC0e: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
1304	TRPM_EXIT_DBG_HOOK(0xe);
1305	return rc;
1306	}
1307
1308
1309	/**
1310	* Scans for the EIP in the specified array of trap handlers.
1311	*
1312	* If we don't fine the EIP, we'll panic.
1313	*
1314	* @returns VBox status code.
1315	*
1316	* @param pVM The cross context VM structure.
1317	* @param pRegFrame Pointer to the register frame for the trap.
1318	* @param paHandlers The array of trap handler records.
1319	* @param pEndRecord The end record (exclusive).
1320	*/
1321	static int trpmGCHyperGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, PCTRPMGCHYPER paHandlers, PCTRPMGCHYPER pEndRecord)
1322	{
1323	uintptr_t uEip = (uintptr_t)pRegFrame->eip;
1324	Assert(paHandlers <= pEndRecord);
1325
1326	Log(("trpmGCHyperGeneric: uEip=%x %p-%p\n", uEip, paHandlers, pEndRecord));
1327
1328	#if 0 /// @todo later
1329	/*
1330	* Start by doing a kind of binary search.
1331	*/
1332	unsigned iStart = 0;
1333	unsigned iEnd = pEndRecord - paHandlers;
1334	unsigned i = iEnd / 2;
1335	#endif
1336
1337	/*
1338	* Do a linear search now (in case the array wasn't properly sorted).
1339	*/
1340	for (PCTRPMGCHYPER pCur = paHandlers; pCur < pEndRecord; pCur++)
1341	{
1342	if ( pCur->uStartEIP <= uEip
1343	&& (pCur->uEndEIP ? pCur->uEndEIP > uEip : pCur->uStartEIP == uEip))
1344	return pCur->pfnHandler(pVM, pRegFrame, pCur->uUser);
1345	}
1346
1347	return VERR_TRPM_DONT_PANIC;
1348	}
1349
1350
1351	/**
1352	* Hypervisor \#NP ((segment) Not Present) handler.
1353	*
1354	* Scans for the EIP in the registered trap handlers.
1355	*
1356	* @returns VBox status code.
1357	* VINF_SUCCESS means we completely handled this trap,
1358	* other codes are passed back to host context.
1359	*
1360	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1361	* @param pRegFrame Pointer to the register frame for the trap.
1362	* @internal
1363	*/
1364	DECLASM(int) TRPMGCHyperTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1365	{
1366	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0bHandlers, g_aTrap0bHandlersEnd);
1367	}
1368
1369
1370	/**
1371	* Hypervisor \#GP (General Protection Fault) handler.
1372	*
1373	* Scans for the EIP in the registered trap handlers.
1374	*
1375	* @returns VBox status code.
1376	* VINF_SUCCESS means we completely handled this trap,
1377	* other codes are passed back to host context.
1378	*
1379	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1380	* @param pRegFrame Pointer to the register frame for the trap.
1381	* @internal
1382	*/
1383	DECLASM(int) TRPMGCHyperTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1384	{
1385	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1386	}
1387
1388
1389	/**
1390	* Hypervisor \#PF (Page Fault) handler.
1391	*
1392	* Scans for the EIP in the registered trap handlers.
1393	*
1394	* @returns VBox status code.
1395	* VINF_SUCCESS means we completely handled this trap,
1396	* other codes are passed back to host context.
1397	*
1398	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1399	* @param pRegFrame Pointer to the register frame for the trap.
1400	* @internal
1401	*/
1402	DECLASM(int) TRPMGCHyperTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1403	{
1404	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1405	}
1406
1407
1408	/**
1409	* Deal with hypervisor traps occurring when resuming execution on a trap.
1410	*
1411	* There is a little problem with recursive RC (hypervisor) traps. We deal with
1412	* this by not allowing recursion without it being the subject of a guru
1413	* meditation. (We used to / tried to handle this but there isn't any reason
1414	* for it.)
1415	*
1416	* So, do NOT use this for handling RC traps!
1417	*
1418	* @returns VBox status code. (Anything but VINF_SUCCESS will cause guru.)
1419	* @param pVM The cross context VM structure.
1420	* @param pRegFrame Register frame.
1421	* @param uUser User arg.
1422	*/
1423	DECLCALLBACK(int) trpmRCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1424	{
1425	RT_NOREF_PV(pRegFrame);
1426	Log(("********************************************************\n"));
1427	Log(("trpmRCTrapInGeneric: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
1428	Log(("********************************************************\n"));
1429
1430	/*
1431	* This used to be kind of complicated, but since we stopped storing
1432	* the register frame on the stack and instead storing it directly
1433	* in the CPUMCPU::Guest structure, we just have to figure out which
1434	* status to hand on to the host and let the recompiler/IEM do its
1435	* job.
1436	*/
1437	switch (uUser)
1438	{
1439	case TRPM_TRAP_IN_MOV_GS:
1440	case TRPM_TRAP_IN_MOV_FS:
1441	case TRPM_TRAP_IN_MOV_ES:
1442	case TRPM_TRAP_IN_MOV_DS:
1443	TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_STALE_SELECTOR);
1444	break;
1445
1446	case TRPM_TRAP_IN_IRET:
1447	case TRPM_TRAP_IN_IRET \| TRPM_TRAP_IN_V86:
1448	TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_IRET_TRAP);
1449	break;
1450
1451	default:
1452	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1453	return VERR_TRPM_BAD_TRAP_IN_OP;
1454	}
1455
1456	AssertMsgFailed(("Impossible!\n"));
1457	return VERR_TRPM_IPE_3;
1458	}
1459
1460
1461	/**
1462	* Generic hyper trap handler that sets the EIP to @a uUser.
1463	*
1464	* @returns VBox status code. (Anything but VINF_SUCCESS will cause guru.)
1465	* @param pVM The cross context VM structure.
1466	* @param pRegFrame Pointer to the register frame (within VM)
1467	* @param uUser The user arg, which should be the new EIP address.
1468	*/
1469	extern "C" DECLCALLBACK(int) TRPMRCTrapHyperHandlerSetEIP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1470	{
1471	AssertReturn(MMHyperIsInsideArea(pVM, uUser), VERR_TRPM_IPE_3);
1472	pRegFrame->eip = uUser;
1473	return VINF_SUCCESS;
1474	}
1475

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source: vbox/trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp@ 65381

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