TRPMRCHandlers.cpp@ 45305

Last change on this file since 45305 was 45305, checked in by vboxsync, 12 years ago
IOM: Adding pVCpu to a lot of calls and moving the lookup caches from VM to VMCPU.
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1	/* $Id: TRPMRCHandlers.cpp 45305 2013-04-03 11:15:02Z vboxsync $ */
2	/** @file
3	* TRPM - Raw-mode Context Trap Handlers, CPP part
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_TRPM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/iom.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/em.h>
29	#include <VBox/vmm/csam.h>
30	#include <VBox/vmm/patm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/cpum.h>
33	#include "TRPMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/param.h>
37
38	#include <VBox/err.h>
39	#include <VBox/dis.h>
40	#include <VBox/disopcode.h>
41	#include <VBox/log.h>
42	#include <VBox/vmm/tm.h>
43	#include <iprt/asm.h>
44	#include <iprt/asm-amd64-x86.h>
45	#include <iprt/assert.h>
46	#include <iprt/x86.h>
47
48
49	/*******************************************************************************
50	* Defined Constants And Macros *
51	*******************************************************************************/
52	/* still here. MODR/M byte parsing */
53	#define X86_OPCODE_MODRM_MOD_MASK 0xc0
54	#define X86_OPCODE_MODRM_REG_MASK 0x38
55	#define X86_OPCODE_MODRM_RM_MASK 0x07
56
57	/** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
58	#define DTRACE_EXPERIMENT
59
60	#if 1
61	# define TRPM_ENTER_DBG_HOOK(a_iVector) do {} while (0)
62	# define TRPM_EXIT_DBG_HOOK(a_iVector) do {} while (0)
63	# define TRPM_ENTER_DBG_HOOK_HYPER(a_iVector) do {} while (0)
64	# define TRPM_EXIT_DBG_HOOK_HYPER(a_iVector) do {} while (0)
65	#else
66	# define TRPM_ENTER_DBG_HOOK(a_iVector) \
67	uint32_t const fDbgEFlags1 = CPUMRawGetEFlags(pVCpu); \
68	if (!(fDbgEFlags1 & X86_EFL_IF)) Log(("%s: IF=0 ##\n", __FUNCTION__)); \
69	else do {} while(0)
70	# define TRPM_EXIT_DBG_HOOK(a_iVector) \
71	do { \
72	uint32_t const fDbgEFlags2 = CPUMRawGetEFlags(pVCpu); \
73	if ((fDbgEFlags1 ^ fDbgEFlags2) & (X86_EFL_IF \| X86_EFL_IOPL)) \
74	Log(("%s: IF=%d->%d IOPL=%d->%d !#\n", __FUNCTION__, \
75	!!(fDbgEFlags1 & X86_EFL_IF), !!(fDbgEFlags2 & X86_EFL_IF), \
76	X86_EFL_GET_IOPL(fDbgEFlags1), X86_EFL_GET_IOPL(fDbgEFlags2) )); \
77	else if (!(fDbgEFlags2 & X86_EFL_IF)) Log(("%s: IF=0 [ret] ##\n", __FUNCTION__)); \
78	} while (0)
79	# define TRPM_ENTER_DBG_HOOK_HYPER(a_iVector) do {} while (0)
80	# define TRPM_EXIT_DBG_HOOK_HYPER(a_iVector) do {} while (0)
81	#endif
82
83	/*******************************************************************************
84	* Structures and Typedefs *
85	*******************************************************************************/
86	/** Pointer to a readonly hypervisor trap record. */
87	typedef const struct TRPMGCHYPER *PCTRPMGCHYPER;
88
89	/**
90	* A hypervisor trap record.
91	* This contains information about a handler for a instruction range.
92	*
93	* @remark This must match what TRPM_HANDLER outputs.
94	*/
95	typedef struct TRPMGCHYPER
96	{
97	/** The start address. */
98	uintptr_t uStartEIP;
99	/** The end address. (exclusive)
100	* If NULL the it's only for the instruction at pvStartEIP. */
101	uintptr_t uEndEIP;
102	/**
103	* The handler.
104	*
105	* @returns VBox status code
106	* VINF_SUCCESS means we've handled the trap.
107	* Any other error code means returning to the host context.
108	* @param pVM Pointer to the VM.
109	* @param pRegFrame The register frame.
110	* @param uUser The user argument.
111	*/
112	DECLRCCALLBACKMEMBER(int, pfnHandler, (PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser));
113	/** Whatever the handler desires to put here. */
114	uintptr_t uUser;
115	} TRPMGCHYPER;
116
117
118	/*******************************************************************************
119	* Global Variables *
120	*******************************************************************************/
121	RT_C_DECLS_BEGIN
122	/** Defined in VMMGC0.asm or VMMGC99.asm.
123	* @{ */
124	extern const TRPMGCHYPER g_aTrap0bHandlers[1];
125	extern const TRPMGCHYPER g_aTrap0bHandlersEnd[1];
126	extern const TRPMGCHYPER g_aTrap0dHandlers[1];
127	extern const TRPMGCHYPER g_aTrap0dHandlersEnd[1];
128	extern const TRPMGCHYPER g_aTrap0eHandlers[1];
129	extern const TRPMGCHYPER g_aTrap0eHandlersEnd[1];
130	/** @} */
131	RT_C_DECLS_END
132
133
134	/*******************************************************************************
135	* Internal Functions *
136	*******************************************************************************/
137	RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
138	DECLCALLBACK(int) trpmRCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
139	RT_C_DECLS_END
140
141
142
143	/**
144	* Exits the trap, called when exiting a trap handler.
145	*
146	* Will reset the trap if it's not a guest trap or the trap
147	* is already handled. Will process resume guest FFs.
148	*
149	* @returns rc, can be adjusted if its VINF_SUCCESS or something really bad
150	* happened.
151	* @param pVM Pointer to the VM.
152	* @param pVCpu Pointer to the VMCPU.
153	* @param rc The VBox status code to return.
154	* @param pRegFrame Pointer to the register frame for the trap.
155	*
156	* @remarks This must not be used for hypervisor traps, only guest traps.
157	*/
158	static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
159	{
160	uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
161	NOREF(uOldActiveVector);
162
163	/* Reset trap? */
164	if ( rc != VINF_EM_RAW_GUEST_TRAP
165	&& rc != VINF_EM_RAW_RING_SWITCH_INT)
166	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
167
168	#ifdef VBOX_HIGH_RES_TIMERS_HACK
169	/*
170	* We should poll the timers occasionally.
171	* We must NOT do this too frequently as it adds a significant overhead
172	* and it'll kill us if the trap load is high. (See @bugref{1354}.)
173	* (The heuristic is not very intelligent, we should really check trap
174	* frequency etc. here, but alas, we lack any such information atm.)
175	*/
176	static unsigned s_iTimerPoll = 0;
177	if (rc == VINF_SUCCESS)
178	{
179	if (!(++s_iTimerPoll & 0xf))
180	{
181	TMTimerPollVoid(pVM, pVCpu);
182	Log2(("TMTimerPoll at %08RX32 - VM_FF_TM_VIRTUAL_SYNC=%d VM_FF_TM_VIRTUAL_SYNC=%d\n", pRegFrame->eip,
183	VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)));
184	}
185	}
186	else
187	s_iTimerPoll = 0;
188	#endif
189
190	/* Clear pending inhibit interrupt state if required. (necessary for dispatching interrupts later on) */
191	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
192	{
193	Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
194	if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
195	{
196	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
197	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
198	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
199	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
200	*/
201	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
202	}
203	}
204
205	/*
206	* Pending resume-guest-FF?
207	* Or pending (A)PIC interrupt? Windows XP will crash if we delay APIC interrupts.
208	*/
209	if ( rc == VINF_SUCCESS
210	&& ( VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC \| VM_FF_REQUEST \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_DMA)
211	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_TO_R3 \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
212	\| VMCPU_FF_REQUEST \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
213	\| VMCPU_FF_PDM_CRITSECT
214	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS
215	)
216	)
217	)
218	{
219	/* The out of memory condition naturally outranks the others. */
220	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
221	rc = VINF_EM_NO_MEMORY;
222	/* Pending Ring-3 action. */
223	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TO_R3 \| VMCPU_FF_PDM_CRITSECT))
224	{
225	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
226	rc = VINF_EM_RAW_TO_R3;
227	}
228	/* Pending timer action. */
229	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER))
230	rc = VINF_EM_RAW_TIMER_PENDING;
231	/* The Virtual Sync clock has stopped. */
232	else if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
233	rc = VINF_EM_RAW_TO_R3;
234	/* DMA work pending? */
235	else if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA))
236	rc = VINF_EM_RAW_TO_R3;
237	/* Pending request packets might contain actions that need immediate
238	attention, such as pending hardware interrupts. */
239	else if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
240	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
241	rc = VINF_EM_PENDING_REQUEST;
242	/* Pending GDT/LDT/TSS sync. */
243	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS))
244	rc = VINF_SELM_SYNC_GDT;
245	/* Pending interrupt: dispatch it. */
246	else if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
247	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
248	&& PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame)
249	)
250	{
251	uint8_t u8Interrupt;
252	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
253	Log(("trpmGCExitTrap: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
254	AssertFatalMsgRC(rc, ("PDMGetInterrupt failed with %Rrc\n", rc));
255	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
256	/* can't return if successful */
257	Assert(rc != VINF_SUCCESS);
258
259	/* Stop the profile counter that was started in TRPMGCHandlersA.asm */
260	Assert(uOldActiveVector <= 16);
261	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
262
263	/* Assert the trap and go to the recompiler to dispatch it. */
264	TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
265
266	STAM_PROFILE_ADV_START(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
267	rc = VINF_EM_RAW_INTERRUPT_PENDING;
268	}
269	/*
270	* Try sync CR3?
271	*/
272	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
273	{
274	#if 1
275	PGMRZDynMapReleaseAutoSet(pVCpu);
276	PGMRZDynMapStartAutoSet(pVCpu);
277	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
278	#else
279	rc = VINF_PGM_SYNC_CR3;
280	#endif
281	}
282	}
283
284	/* Note! TRPMRCHandlersA.asm performs sanity checks in debug builds.*/
285	PGMRZDynMapReleaseAutoSet(pVCpu);
286	return rc;
287	}
288
289
290	/**
291	* \#DB (Debug event) handler.
292	*
293	* @returns VBox status code.
294	* VINF_SUCCESS means we completely handled this trap,
295	* other codes are passed execution to host context.
296	*
297	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
298	* @param pRegFrame Pointer to the register frame for the trap.
299	* @internal
300	*/
301	DECLASM(int) TRPMGCTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
302	{
303	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
304	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
305	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
306	//LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
307	TRPM_ENTER_DBG_HOOK(1);
308
309	/*
310	* We currently don't make use of the X86_DR7_GD bit, but
311	* there might come a time when we do.
312	*/
313	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
314	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
315	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
316	VERR_NOT_IMPLEMENTED);
317	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
318
319	/*
320	* Now leave the rest to the DBGF.
321	*/
322	PGMRZDynMapStartAutoSet(pVCpu);
323	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
324	if (rc == VINF_EM_RAW_GUEST_TRAP)
325	CPUMSetGuestDR6(pVCpu, uDr6);
326
327	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
328	Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg %EFlag=%#x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
329	TRPM_EXIT_DBG_HOOK(1);
330	return rc;
331	}
332
333
334	/**
335	* \#DB (Debug event) handler for the hypervisor code.
336	*
337	* This is mostly the same as TRPMGCTrap01Handler, but we skip the PGM auto
338	* mapping set as well as the default trap exit path since they are both really
339	* bad ideas in this context.
340	*
341	* @returns VBox status code.
342	* VINF_SUCCESS means we completely handled this trap,
343	* other codes are passed execution to host context.
344	*
345	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
346	* @param pRegFrame Pointer to the register frame for the trap.
347	* @internal
348	*/
349	DECLASM(int) TRPMGCHyperTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
350	{
351	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
352	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
353	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
354	TRPM_ENTER_DBG_HOOK_HYPER(1);
355	LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
356
357	/*
358	* We currently don't make use of the X86_DR7_GD bit, but
359	* there might come a time when we do.
360	*/
361	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
362	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
363	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
364	VERR_NOT_IMPLEMENTED);
365	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
366
367	/*
368	* Now leave the rest to the DBGF.
369	*/
370	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
371	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_1);
372
373	Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
374	TRPM_EXIT_DBG_HOOK_HYPER(1);
375	return rc;
376	}
377
378
379	/**
380	* NMI handler, for when we are using NMIs to debug things.
381	*
382	* @returns VBox status code.
383	* VINF_SUCCESS means we completely handled this trap,
384	* other codes are passed execution to host context.
385	*
386	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
387	* @param pRegFrame Pointer to the register frame for the trap.
388	* @internal
389	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
390	*/
391	DECLASM(int) TRPMGCTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
392	{
393	LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
394	RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
395	NOREF(pTrpmCpu);
396	return VERR_TRPM_DONT_PANIC;
397	}
398
399
400	/**
401	* NMI handler, for when we are using NMIs to debug things.
402	*
403	* This is the handler we're most likely to hit when the NMI fires (it is
404	* unlikely that we'll be stuck in guest code).
405	*
406	* @returns VBox status code.
407	* VINF_SUCCESS means we completely handled this trap,
408	* other codes are passed execution to host context.
409	*
410	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
411	* @param pRegFrame Pointer to the register frame for the trap.
412	* @internal
413	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
414	*/
415	DECLASM(int) TRPMGCHyperTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
416	{
417	LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
418	RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
419	NOREF(pTrpmCpu);
420	return VERR_TRPM_DONT_PANIC;
421	}
422
423
424	/**
425	* \#BP (Breakpoint) handler.
426	*
427	* @returns VBox status code.
428	* VINF_SUCCESS means we completely handled this trap,
429	* other codes are passed execution to host context.
430	*
431	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
432	* @param pRegFrame Pointer to the register frame for the trap.
433	* @internal
434	*/
435	DECLASM(int) TRPMGCTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
436	{
437	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
438	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
439	int rc;
440	LogFlow(("TRPMGC03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
441	TRPM_ENTER_DBG_HOOK(3);
442	PGMRZDynMapStartAutoSet(pVCpu);
443
444	/*
445	* PATM is using INT3s, let them have a go first.
446	*/
447	#ifdef VBOX_WITH_RAW_RING1
448	if ( ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1
449	\|\| (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2))
450	#else
451	if ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1
452	#endif
453	&& !pRegFrame->eflags.Bits.u1VM)
454	{
455	rc = PATMRCHandleInt3PatchTrap(pVM, pRegFrame);
456	if ( rc == VINF_SUCCESS
457	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
458	\|\| rc == VINF_PATM_PATCH_INT3
459	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION)
460	{
461	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
462	Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
463	TRPM_EXIT_DBG_HOOK(3);
464	return rc;
465	}
466	}
467	rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
468
469	/* anything we should do with this? Schedule it in GC? */
470	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
471	Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
472	TRPM_EXIT_DBG_HOOK(3);
473	return rc;
474	}
475
476
477	/**
478	* \#BP (Breakpoint) handler.
479	*
480	* This is similar to TRPMGCTrap03Handler but we bits which are potentially
481	* harmful to us (common trap exit and the auto mapping set).
482	*
483	* @returns VBox status code.
484	* VINF_SUCCESS means we completely handled this trap,
485	* other codes are passed execution to host context.
486	*
487	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
488	* @param pRegFrame Pointer to the register frame for the trap.
489	* @internal
490	*/
491	DECLASM(int) TRPMGCHyperTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
492	{
493	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
494	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
495	LogFlow(("TRPMGCHyper03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
496	TRPM_ENTER_DBG_HOOK_HYPER(3);
497
498	/*
499	* Hand it over to DBGF.
500	*/
501	int rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
502	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_2);
503
504	Log6(("TRPMGCHyper03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
505	TRPM_EXIT_DBG_HOOK_HYPER(3);
506	return rc;
507	}
508
509
510	/**
511	* Trap handler for illegal opcode fault (\#UD).
512	*
513	* @returns VBox status code.
514	* VINF_SUCCESS means we completely handled this trap,
515	* other codes are passed execution to host context.
516	*
517	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
518	* @param pRegFrame Pointer to the register frame for the trap.
519	* @internal
520	*/
521	DECLASM(int) TRPMGCTrap06Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
522	{
523	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
524	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
525	int rc;
526	LogFlow(("TRPMGC06: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->eflags.u32, CPUMRawGetEFlags(pVCpu)));
527	TRPM_ENTER_DBG_HOOK(6);
528	PGMRZDynMapStartAutoSet(pVCpu);
529
530	#ifdef VBOX_WITH_RAW_RING1
531	if (CPUMGetGuestCPL(pVCpu) <= (unsigned)(EMIsRawRing1Enabled(pVM) ? 1 : 0))
532	#else
533	if (CPUMGetGuestCPL(pVCpu) == 0)
534	#endif
535	{
536	/*
537	* Decode the instruction.
538	*/
539	RTGCPTR PC;
540	rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
541	pRegFrame->rip, &PC);
542	if (RT_FAILURE(rc))
543	{
544	Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
545	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
546	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (SELM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
547	TRPM_EXIT_DBG_HOOK(6);
548	return rc;
549	}
550
551	DISCPUSTATE Cpu;
552	uint32_t cbOp;
553	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
554	if (RT_FAILURE(rc))
555	{
556	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
557	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (EM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
558	TRPM_EXIT_DBG_HOOK(6);
559	return rc;
560	}
561
562	/*
563	* UD2 in a patch?
564	* Note! PATMGCHandleIllegalInstrTrap doesn't always return.
565	*/
566	if ( Cpu.pCurInstr->uOpcode == OP_ILLUD2
567	&& PATMIsPatchGCAddr(pVM, pRegFrame->eip))
568	{
569	LogFlow(("TRPMGCTrap06Handler: -> PATMRCHandleIllegalInstrTrap\n"));
570	rc = PATMRCHandleIllegalInstrTrap(pVM, pRegFrame);
571	/** @todo These tests are completely unnecessary, should just follow the
572	* flow and return at the end of the function. */
573	if ( rc == VINF_SUCCESS
574	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
575	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION
576	\|\| rc == VINF_PATM_PENDING_IRQ_AFTER_IRET
577	\|\| rc == VINF_EM_RESCHEDULE)
578	{
579	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
580	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
581	TRPM_EXIT_DBG_HOOK(6);
582	return rc;
583	}
584	}
585	/*
586	* Speed up dtrace and don't entrust invalid lock sequences to the recompiler.
587	*/
588	else if (Cpu.fPrefix & DISPREFIX_LOCK)
589	{
590	Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->uOpcode));
591	#ifdef DTRACE_EXPERIMENT /** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
592	Assert(!PATMIsPatchGCAddr(pVM, pRegFrame->eip));
593	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
594	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
595	#else
596	rc = VINF_EM_RAW_EMULATE_INSTR;
597	#endif
598	}
599	/*
600	* Handle MONITOR - it causes an #UD exception instead of #GP when not executed in ring 0.
601	*/
602	else if (Cpu.pCurInstr->uOpcode == OP_MONITOR)
603	{
604	LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
605	rc = EMInterpretInstructionDisasState(pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
606	}
607	/* Never generate a raw trap here; it might be an instruction, that requires emulation. */
608	else
609	{
610	LogFlow(("TRPMGCTrap06Handler: -> VINF_EM_RAW_EMULATE_INSTR\n"));
611	rc = VINF_EM_RAW_EMULATE_INSTR;
612	}
613	}
614	else
615	{
616	LogFlow(("TRPMGCTrap06Handler: -> TRPMForwardTrap\n"));
617	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
618	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
619	}
620
621	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
622	Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
623	TRPM_EXIT_DBG_HOOK(6);
624	return rc;
625	}
626
627
628	/**
629	* Trap handler for device not present fault (\#NM).
630	*
631	* Device not available, FP or (F)WAIT instruction.
632	*
633	* @returns VBox status code.
634	* VINF_SUCCESS means we completely handled this trap,
635	* other codes are passed execution to host context.
636	*
637	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
638	* @param pRegFrame Pointer to the register frame for the trap.
639	* @internal
640	*/
641	DECLASM(int) TRPMGCTrap07Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
642	{
643	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
644	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
645	LogFlow(("TRPMGC07: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
646	TRPM_ENTER_DBG_HOOK(7);
647	PGMRZDynMapStartAutoSet(pVCpu);
648
649	int rc = CPUMHandleLazyFPU(pVCpu);
650	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
651	Log6(("TRPMGC07: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
652	TRPM_EXIT_DBG_HOOK(7);
653	return rc;
654	}
655
656
657	/**
658	* \#NP ((segment) Not Present) handler.
659	*
660	* @returns VBox status code.
661	* VINF_SUCCESS means we completely handled this trap,
662	* other codes are passed execution to host context.
663	*
664	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
665	* @param pRegFrame Pointer to the register frame for the trap.
666	* @internal
667	*/
668	DECLASM(int) TRPMGCTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
669	{
670	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
671	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
672	LogFlow(("TRPMGC0b: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
673	TRPM_ENTER_DBG_HOOK(0xb);
674	PGMRZDynMapStartAutoSet(pVCpu);
675
676	/*
677	* Try to detect instruction by opcode which caused trap.
678	* XXX note: this code may cause \#PF (trap e) or \#GP (trap d) while
679	* accessing user code. need to handle it somehow in future!
680	*/
681	RTGCPTR GCPtr;
682	if ( SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
683	(RTGCPTR)pRegFrame->eip, &GCPtr)
684	== VINF_SUCCESS)
685	{
686	uint8_t pu8Code = (uint8_t )(uintptr_t)GCPtr;
687
688	/*
689	* First skip possible instruction prefixes, such as:
690	* OS, AS
691	* CS:, DS:, ES:, SS:, FS:, GS:
692	* REPE, REPNE
693	*
694	* note: Currently we supports only up to 4 prefixes per opcode, more
695	* prefixes (normally not used anyway) will cause trap d in guest.
696	* note: Instruction length in IA-32 may be up to 15 bytes, we dont
697	* check this issue, its too hard.
698	*/
699	for (unsigned i = 0; i < 4; i++)
700	{
701	if ( pu8Code[0] != 0xf2 /* REPNE/REPNZ */
702	&& pu8Code[0] != 0xf3 /* REP/REPE/REPZ */
703	&& pu8Code[0] != 0x2e /* CS: */
704	&& pu8Code[0] != 0x36 /* SS: */
705	&& pu8Code[0] != 0x3e /* DS: */
706	&& pu8Code[0] != 0x26 /* ES: */
707	&& pu8Code[0] != 0x64 /* FS: */
708	&& pu8Code[0] != 0x65 /* GS: */
709	&& pu8Code[0] != 0x66 /* OS */
710	&& pu8Code[0] != 0x67 /* AS */
711	)
712	break;
713	pu8Code++;
714	}
715
716	/*
717	* Detect right switch using a callgate.
718	*
719	* We recognize the following causes for the trap 0b:
720	* CALL FAR, CALL FAR []
721	* JMP FAR, JMP FAR []
722	* IRET (may cause a task switch)
723	*
724	* Note: we can't detect whether the trap was caused by a call to a
725	* callgate descriptor or it is a real trap 0b due to a bad selector.
726	* In both situations we'll pass execution to our recompiler so we don't
727	* have to worry.
728	* If we wanted to do better detection, we have set GDT entries to callgate
729	* descriptors pointing to our own handlers.
730	*/
731	/** @todo not sure about IRET, may generate Trap 0d (\#GP), NEED TO CHECK! */
732	if ( pu8Code[0] == 0x9a /* CALL FAR */
733	\|\| ( pu8Code[0] == 0xff /* CALL FAR [] */
734	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x18)
735	\|\| pu8Code[0] == 0xea /* JMP FAR */
736	\|\| ( pu8Code[0] == 0xff /* JMP FAR [] */
737	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x28)
738	\|\| pu8Code[0] == 0xcf /* IRET */
739	)
740	{
741	/*
742	* Got potential call to callgate.
743	* We simply return execution to the recompiler to do emulation
744	* starting from the instruction which caused the trap.
745	*/
746	pTrpmCpu->uActiveVector = UINT32_MAX;
747	Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
748	TRPM_EXIT_DBG_HOOK(0xb);
749	PGMRZDynMapReleaseAutoSet(pVCpu);
750	return VINF_EM_RAW_RING_SWITCH;
751	}
752	}
753
754	/*
755	* Pass trap 0b as is to the recompiler in all other cases.
756	*/
757	Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
758	PGMRZDynMapReleaseAutoSet(pVCpu);
759	TRPM_EXIT_DBG_HOOK(0xb);
760	return VINF_EM_RAW_GUEST_TRAP;
761	}
762
763
764	/**
765	* \#GP (General Protection Fault) handler for Ring-0 privileged instructions.
766	*
767	* @returns VBox status code.
768	* VINF_SUCCESS means we completely handled this trap,
769	* other codes are passed execution to host context.
770	*
771	* @param pVM Pointer to the VM.
772	* @param pVCpu Pointer to the VMCPU.
773	* @param pRegFrame Pointer to the register frame for the trap.
774	* @param pCpu The opcode info.
775	* @param PC The program counter corresponding to cs:eip in pRegFrame.
776	*/
777	static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
778	{
779	int rc;
780	TRPM_ENTER_DBG_HOOK(0xd);
781
782	/*
783	* Try handle it here, if not return to HC and emulate/interpret it there.
784	*/
785	switch (pCpu->pCurInstr->uOpcode)
786	{
787	case OP_INT3:
788	/*
789	* Little hack to make the code below not fail
790	*/
791	pCpu->Param1.fUse = DISUSE_IMMEDIATE8;
792	pCpu->Param1.uValue = 3;
793	/* fallthru */
794	case OP_INT:
795	{
796	Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
797	Assert(!(PATMIsPatchGCAddr(pVM, PC)));
798	if (pCpu->Param1.uValue == 3)
799	{
800	/* Int 3 replacement patch? */
801	if (PATMRCHandleInt3PatchTrap(pVM, pRegFrame) == VINF_SUCCESS)
802	{
803	AssertFailed();
804	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
805	}
806	}
807	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
808	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
809	{
810	TRPM_EXIT_DBG_HOOK(0xd);
811	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
812	}
813
814	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
815	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
816	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
817	}
818
819	#ifdef PATM_EMULATE_SYSENTER
820	case OP_SYSEXIT:
821	case OP_SYSRET:
822	rc = PATMSysCall(pVM, pRegFrame, pCpu);
823	TRPM_EXIT_DBG_HOOK(0xd);
824	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
825	#endif
826
827	case OP_HLT:
828	/* If it's in patch code, defer to ring-3. */
829	if (PATMIsPatchGCAddr(pVM, PC))
830	break;
831
832	pRegFrame->eip += pCpu->cbInstr;
833	TRPM_EXIT_DBG_HOOK(0xd);
834	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame);
835
836
837	/*
838	* These instructions are used by PATM and CASM for finding
839	* dangerous non-trapping instructions. Thus, since all
840	* scanning and patching is done in ring-3 we'll have to
841	* return to ring-3 on the first encounter of these instructions.
842	*/
843	case OP_MOV_CR:
844	case OP_MOV_DR:
845	/* We can safely emulate control/debug register move instructions in patched code. */
846	if ( !PATMIsPatchGCAddr(pVM, PC)
847	&& !CSAMIsKnownDangerousInstr(pVM, PC))
848	break;
849	case OP_INVLPG:
850	case OP_LLDT:
851	case OP_STI:
852	case OP_RDTSC: /* just in case */
853	case OP_RDPMC:
854	case OP_CLTS:
855	case OP_WBINVD: /* nop */
856	case OP_RDMSR:
857	case OP_WRMSR:
858	{
859	rc = EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
860	if (rc == VERR_EM_INTERPRETER)
861	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
862	TRPM_EXIT_DBG_HOOK(0xd);
863	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
864	}
865	}
866
867	TRPM_EXIT_DBG_HOOK(0xd);
868	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EXCEPTION_PRIVILEGED, pRegFrame);
869	}
870
871
872	/**
873	* \#GP (General Protection Fault) handler for Ring-3.
874	*
875	* @returns VBox status code.
876	* VINF_SUCCESS means we completely handled this trap,
877	* other codes are passed execution to host context.
878	*
879	* @param pVM Pointer to the VM.
880	* @param pVCpu Pointer to the VMCPU.
881	* @param pRegFrame Pointer to the register frame for the trap.
882	* @param pCpu The opcode info.
883	* @param PC The program counter corresponding to cs:eip in pRegFrame.
884	*/
885	static int trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
886	{
887	int rc;
888	Assert(!pRegFrame->eflags.Bits.u1VM);
889	TRPM_ENTER_DBG_HOOK(0xd);
890
891	switch (pCpu->pCurInstr->uOpcode)
892	{
893	/*
894	* INT3 and INT xx are ring-switching.
895	* (The shadow IDT will have set the entries to DPL=0, that's why we're here.)
896	*/
897	case OP_INT3:
898	/*
899	* Little hack to make the code below not fail
900	*/
901	pCpu->Param1.fUse = DISUSE_IMMEDIATE8;
902	pCpu->Param1.uValue = 3;
903	/* fall thru */
904	case OP_INT:
905	{
906	Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
907	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
908	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
909	{
910	TRPM_EXIT_DBG_HOOK(0xd);
911	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
912	}
913
914	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
915	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
916	TRPM_EXIT_DBG_HOOK(0xd);
917	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
918	}
919
920	/*
921	* SYSCALL, SYSENTER, INTO and BOUND are also ring-switchers.
922	*/
923	case OP_SYSCALL:
924	case OP_SYSENTER:
925	#ifdef PATM_EMULATE_SYSENTER
926	rc = PATMSysCall(pVM, pRegFrame, pCpu);
927	if (rc == VINF_SUCCESS)
928	{
929	TRPM_EXIT_DBG_HOOK(0xd);
930	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
931	}
932	/* else no break; */
933	#endif
934	case OP_BOUND:
935	case OP_INTO:
936	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
937	TRPM_EXIT_DBG_HOOK(0xd);
938	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH, pRegFrame);
939
940	/*
941	* Handle virtualized TSC & PMC reads, just in case.
942	*/
943	case OP_RDTSC:
944	case OP_RDPMC:
945	{
946	rc = EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
947	if (rc == VERR_EM_INTERPRETER)
948	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
949	TRPM_EXIT_DBG_HOOK(0xd);
950	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
951	}
952
953	/*
954	* STI and CLI are I/O privileged, i.e. if IOPL
955	*/
956	case OP_STI:
957	case OP_CLI:
958	{
959	uint32_t efl = CPUMRawGetEFlags(pVCpu);
960	uint32_t cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
961	if (X86_EFL_GET_IOPL(efl) >= cpl)
962	{
963	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> REM\n"));
964	TRPM_EXIT_DBG_HOOK(0xd);
965	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RESCHEDULE_REM, pRegFrame);
966	}
967	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> #GP(0) iopl=%x, cpl=%x\n", X86_EFL_GET_IOPL(efl), cpl));
968	break;
969	}
970	}
971
972	/*
973	* A genuine guest fault.
974	*/
975	TRPM_EXIT_DBG_HOOK(0xd);
976	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
977	}
978
979
980	/**
981	* Emulates RDTSC for the \#GP handler.
982	*
983	* @returns VINF_SUCCESS or VINF_EM_RAW_EMULATE_INSTR.
984	*
985	* @param pVM Pointer to the VM.
986	* @param pVCpu Pointer to the VMCPU.
987	* @param pRegFrame Pointer to the register frame for the trap.
988	* This will be updated on successful return.
989	*/
990	DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
991	{
992	STAM_COUNTER_INC(&pVM->trpm.s.StatTrap0dRdTsc);
993	TRPM_ENTER_DBG_HOOK(0xd);
994
995	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
996	{
997	TRPM_EXIT_DBG_HOOK(0xd);
998	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
999	}
1000
1001	uint64_t uTicks = TMCpuTickGet(pVCpu);
1002	pRegFrame->eax = uTicks;
1003	pRegFrame->edx = uTicks >> 32;
1004	pRegFrame->eip += 2;
1005	TRPM_EXIT_DBG_HOOK(0xd);
1006	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
1007	}
1008
1009
1010	/**
1011	* \#GP (General Protection Fault) handler.
1012	*
1013	* @returns VBox status code.
1014	* VINF_SUCCESS means we completely handled this trap,
1015	* other codes are passed execution to host context.
1016	*
1017	* @param pVM Pointer to the VM.
1018	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1019	* @param pRegFrame Pointer to the register frame for the trap.
1020	*/
1021	static int trpmGCTrap0dHandler(PVM pVM, PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1022	{
1023	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1024	LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, pTrpmCpu->uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1025	TRPM_ENTER_DBG_HOOK(0xd);
1026
1027	/*
1028	* Convert and validate CS.
1029	*/
1030	STAM_PROFILE_START(&pVM->trpm.s.StatTrap0dDisasm, a);
1031	RTGCPTR PC;
1032	int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
1033	pRegFrame->rip, &PC);
1034	if (RT_FAILURE(rc))
1035	{
1036	Log(("trpmGCTrap0dHandler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n",
1037	pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
1038	TRPM_EXIT_DBG_HOOK(0xd);
1039	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1040	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1041	}
1042
1043	/*
1044	* Disassemble the instruction.
1045	*/
1046	DISCPUSTATE Cpu;
1047	uint32_t cbOp;
1048	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
1049	if (RT_FAILURE(rc))
1050	{
1051	AssertMsgFailed(("DISCoreOneEx failed to PC=%RGv rc=%Rrc\n", PC, rc));
1052	TRPM_EXIT_DBG_HOOK(0xd);
1053	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1054	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1055	}
1056	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
1057
1058	/*
1059	* Optimize RDTSC traps.
1060	* Some guests (like Solaris) are using RDTSC all over the place and
1061	* will end up trapping a lot because of that.
1062	*
1063	* Note: it's no longer safe to access the instruction opcode directly due to possible stale code TLB entries
1064	*/
1065	if (Cpu.pCurInstr->uOpcode == OP_RDTSC)
1066	return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);
1067
1068	/*
1069	* Deal with I/O port access.
1070	*/
1071	if ( pVCpu->trpm.s.uActiveErrorCode == 0
1072	&& (Cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
1073	{
1074	VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, pVCpu, pRegFrame, &Cpu);
1075	if (IOM_SUCCESS(rcStrict))
1076	pRegFrame->rip += cbOp;
1077	rc = VBOXSTRICTRC_TODO(rcStrict);
1078	TRPM_EXIT_DBG_HOOK(0xd);
1079	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1080	}
1081
1082	/*
1083	* Deal with Ring-0 (privileged instructions)
1084	*/
1085	if ( (pRegFrame->ss.Sel & X86_SEL_RPL) <= 1
1086	&& !pRegFrame->eflags.Bits.u1VM)
1087	return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
1088
1089	/*
1090	* Deal with Ring-3 GPs.
1091	*/
1092	if (!pRegFrame->eflags.Bits.u1VM)
1093	return trpmGCTrap0dHandlerRing3(pVM, pVCpu, pRegFrame, &Cpu, PC);
1094
1095	/*
1096	* Deal with v86 code.
1097	*
1098	* We always set IOPL to zero which makes e.g. pushf fault in V86
1099	* mode. The guest might use IOPL=3 and therefore not expect a #GP.
1100	* Simply fall back to the recompiler to emulate this instruction if
1101	* that's the case. To get the correct we must use CPUMRawGetEFlags.
1102	*/
1103	X86EFLAGS eflags;
1104	eflags.u32 = CPUMRawGetEFlags(pVCpu); /* Get the correct value. */
1105	Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs.Sel, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
1106	if (eflags.Bits.u2IOPL != 3)
1107	{
1108	Assert(EMIsRawRing1Enabled(pVM) \|\| eflags.Bits.u2IOPL == 0);
1109
1110	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xD, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xd);
1111	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1112	TRPM_EXIT_DBG_HOOK(0xd);
1113	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1114	}
1115	TRPM_EXIT_DBG_HOOK(0xd);
1116	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1117	}
1118
1119
1120	/**
1121	* \#GP (General Protection Fault) handler.
1122	*
1123	* @returns VBox status code.
1124	* VINF_SUCCESS means we completely handled this trap,
1125	* other codes are passed execution to host context.
1126	*
1127	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1128	* @param pRegFrame Pointer to the register frame for the trap.
1129	* @internal
1130	*/
1131	DECLASM(int) TRPMGCTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1132	{
1133	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1134	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1135	LogFlow(("TRPMGC0d: %04x:%08x err=%x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1136	TRPM_ENTER_DBG_HOOK(0xd);
1137
1138	PGMRZDynMapStartAutoSet(pVCpu);
1139	int rc = trpmGCTrap0dHandler(pVM, pTrpmCpu, pRegFrame);
1140	switch (rc)
1141	{
1142	case VINF_EM_RAW_GUEST_TRAP:
1143	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1144	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1145	rc = VINF_PATM_PATCH_TRAP_GP;
1146	break;
1147
1148	case VINF_EM_RAW_INTERRUPT_PENDING:
1149	Assert(TRPMHasTrap(pVCpu));
1150	/* no break; */
1151	case VINF_PGM_SYNC_CR3:
1152	case VINF_EM_RAW_EMULATE_INSTR:
1153	case VINF_IOM_R3_IOPORT_READ:
1154	case VINF_IOM_R3_IOPORT_WRITE:
1155	case VINF_IOM_R3_MMIO_WRITE:
1156	case VINF_IOM_R3_MMIO_READ:
1157	case VINF_IOM_R3_MMIO_READ_WRITE:
1158	case VINF_PATM_PATCH_INT3:
1159	case VINF_EM_NO_MEMORY:
1160	case VINF_EM_RAW_TO_R3:
1161	case VINF_EM_RAW_TIMER_PENDING:
1162	case VINF_EM_PENDING_REQUEST:
1163	case VINF_EM_HALT:
1164	case VINF_SELM_SYNC_GDT:
1165	case VINF_SUCCESS:
1166	break;
1167
1168	default:
1169	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("return code %d\n", rc));
1170	break;
1171	}
1172	Log6(("TRPMGC0d: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
1173	TRPM_EXIT_DBG_HOOK(0xd);
1174	return rc;
1175	}
1176
1177
1178	/**
1179	* \#PF (Page Fault) handler.
1180	*
1181	* Calls PGM which does the actual handling.
1182	*
1183	*
1184	* @returns VBox status code.
1185	* VINF_SUCCESS means we completely handled this trap,
1186	* other codes are passed execution to host context.
1187	*
1188	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1189	* @param pRegFrame Pointer to the register frame for the trap.
1190	* @internal
1191	*/
1192	DECLASM(int) TRPMGCTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1193	{
1194	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1195	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1196	LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2, CPUMRawGetEFlags(pVCpu)));
1197	TRPM_ENTER_DBG_HOOK(0xe);
1198
1199	/*
1200	* This is all PGM stuff.
1201	*/
1202	PGMRZDynMapStartAutoSet(pVCpu);
1203	int rc = PGMTrap0eHandler(pVCpu, pVCpu->trpm.s.uActiveErrorCode, pRegFrame, (RTGCPTR)pVCpu->trpm.s.uActiveCR2);
1204	switch (rc)
1205	{
1206	case VINF_EM_RAW_EMULATE_INSTR:
1207	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
1208	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
1209	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
1210	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
1211	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
1212	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1213	rc = VINF_PATCH_EMULATE_INSTR;
1214	break;
1215
1216	case VINF_EM_RAW_GUEST_TRAP:
1217	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1218	{
1219	PGMRZDynMapReleaseAutoSet(pVCpu);
1220	TRPM_EXIT_DBG_HOOK(0xe);
1221	return VINF_PATM_PATCH_TRAP_PF;
1222	}
1223
1224	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xE, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xe);
1225	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1226	break;
1227
1228	case VINF_EM_RAW_INTERRUPT_PENDING:
1229	Assert(TRPMHasTrap(pVCpu));
1230	/* no break; */
1231	case VINF_IOM_R3_MMIO_READ:
1232	case VINF_IOM_R3_MMIO_WRITE:
1233	case VINF_IOM_R3_MMIO_READ_WRITE:
1234	case VINF_PATM_HC_MMIO_PATCH_READ:
1235	case VINF_PATM_HC_MMIO_PATCH_WRITE:
1236	case VINF_SUCCESS:
1237	case VINF_EM_RAW_TO_R3:
1238	case VINF_EM_PENDING_REQUEST:
1239	case VINF_EM_RAW_TIMER_PENDING:
1240	case VINF_EM_NO_MEMORY:
1241	case VINF_CSAM_PENDING_ACTION:
1242	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1243	break;
1244
1245	default:
1246	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("Patch address for return code %d. eip=%08x\n", rc, pRegFrame->eip));
1247	break;
1248	}
1249	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1250	Log6(("TRPMGC0e: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
1251	TRPM_EXIT_DBG_HOOK(0xe);
1252	return rc;
1253	}
1254
1255
1256	/**
1257	* Scans for the EIP in the specified array of trap handlers.
1258	*
1259	* If we don't fine the EIP, we'll panic.
1260	*
1261	* @returns VBox status code.
1262	*
1263	* @param pVM Pointer to the VM.
1264	* @param pRegFrame Pointer to the register frame for the trap.
1265	* @param paHandlers The array of trap handler records.
1266	* @param pEndRecord The end record (exclusive).
1267	*/
1268	static int trpmGCHyperGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, PCTRPMGCHYPER paHandlers, PCTRPMGCHYPER pEndRecord)
1269	{
1270	uintptr_t uEip = (uintptr_t)pRegFrame->eip;
1271	Assert(paHandlers <= pEndRecord);
1272
1273	Log(("trpmGCHyperGeneric: uEip=%x %p-%p\n", uEip, paHandlers, pEndRecord));
1274
1275	#if 0 /// @todo later
1276	/*
1277	* Start by doing a kind of binary search.
1278	*/
1279	unsigned iStart = 0;
1280	unsigned iEnd = pEndRecord - paHandlers;
1281	unsigned i = iEnd / 2;
1282	#endif
1283
1284	/*
1285	* Do a linear search now (in case the array wasn't properly sorted).
1286	*/
1287	for (PCTRPMGCHYPER pCur = paHandlers; pCur < pEndRecord; pCur++)
1288	{
1289	if ( pCur->uStartEIP <= uEip
1290	&& (pCur->uEndEIP ? pCur->uEndEIP > uEip : pCur->uStartEIP == uEip))
1291	return pCur->pfnHandler(pVM, pRegFrame, pCur->uUser);
1292	}
1293
1294	return VERR_TRPM_DONT_PANIC;
1295	}
1296
1297
1298	/**
1299	* Hypervisor \#NP ((segment) Not Present) handler.
1300	*
1301	* Scans for the EIP in the registered trap handlers.
1302	*
1303	* @returns VBox status code.
1304	* VINF_SUCCESS means we completely handled this trap,
1305	* other codes are passed back to host context.
1306	*
1307	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1308	* @param pRegFrame Pointer to the register frame for the trap.
1309	* @internal
1310	*/
1311	DECLASM(int) TRPMGCHyperTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1312	{
1313	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0bHandlers, g_aTrap0bHandlersEnd);
1314	}
1315
1316
1317	/**
1318	* Hypervisor \#GP (General Protection Fault) handler.
1319	*
1320	* Scans for the EIP in the registered trap handlers.
1321	*
1322	* @returns VBox status code.
1323	* VINF_SUCCESS means we completely handled this trap,
1324	* other codes are passed back to host context.
1325	*
1326	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1327	* @param pRegFrame Pointer to the register frame for the trap.
1328	* @internal
1329	*/
1330	DECLASM(int) TRPMGCHyperTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1331	{
1332	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1333	}
1334
1335
1336	/**
1337	* Hypervisor \#PF (Page Fault) handler.
1338	*
1339	* Scans for the EIP in the registered trap handlers.
1340	*
1341	* @returns VBox status code.
1342	* VINF_SUCCESS means we completely handled this trap,
1343	* other codes are passed back to host context.
1344	*
1345	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1346	* @param pRegFrame Pointer to the register frame for the trap.
1347	* @internal
1348	*/
1349	DECLASM(int) TRPMGCHyperTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1350	{
1351	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1352	}
1353
1354
1355	/**
1356	* Deal with hypervisor traps occurring when resuming execution on a trap.
1357	*
1358	* There is a little problem with recursive RC (hypervisor) traps. We deal with
1359	* this by not allowing recursion without it being the subject of a guru
1360	* meditation. (We used to / tried to handle this but there isn't any reason
1361	* for it.)
1362	*
1363	* So, do NOT use this for handling RC traps!
1364	*
1365	* @returns VBox status code. (Anything but VINF_SUCCESS will cause guru.)
1366	* @param pVM Pointer to the VM.
1367	* @param pRegFrame Register frame.
1368	* @param uUser User arg.
1369	*/
1370	DECLCALLBACK(int) trpmRCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1371	{
1372	Log(("********************************************************\n"));
1373	Log(("trpmRCTrapInGeneric: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
1374	Log(("********************************************************\n"));
1375
1376	/*
1377	* This used to be kind of complicated, but since we stopped storing
1378	* the register frame on the stack and instead storing it directly
1379	* in the CPUMCPU::Guest structure, we just have to figure out which
1380	* status to hand on to the host and let the recompiler/IEM do its
1381	* job.
1382	*/
1383	switch (uUser)
1384	{
1385	case TRPM_TRAP_IN_MOV_GS:
1386	case TRPM_TRAP_IN_MOV_FS:
1387	case TRPM_TRAP_IN_MOV_ES:
1388	case TRPM_TRAP_IN_MOV_DS:
1389	TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_STALE_SELECTOR);
1390	break;
1391
1392	case TRPM_TRAP_IN_IRET:
1393	case TRPM_TRAP_IN_IRET \| TRPM_TRAP_IN_V86:
1394	TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_IRET_TRAP);
1395	break;
1396
1397	default:
1398	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1399	return VERR_TRPM_BAD_TRAP_IN_OP;
1400	}
1401
1402	AssertMsgFailed(("Impossible!\n"));
1403	return VERR_TRPM_IPE_3;
1404	}
1405

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source: vbox/trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp@ 45305

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