SELMRC.cpp@ 41908

Last change on this file since 41908 was 41908, checked in by vboxsync, 13 years ago
Check loaded selector register the GDT changes.
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1	/* $Id: SELMRC.cpp 41908 2012-06-25 01:19:18Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager, Guest Context.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_SELM
22	#include <VBox/vmm/selm.h>
23	#include <VBox/vmm/mm.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/trpm.h>
26	#include "SELMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/vmm.h>
29	#include <VBox/vmm/pgm.h>
30
31	#include <VBox/param.h>
32	#include <VBox/err.h>
33	#include <VBox/log.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38	/**
39	* Synchronizes one GDT entry (guest -> shadow).
40	*
41	* @returns VBox status code (appropriate for trap handling and GC return).
42	* @param pVM Pointer to the VM.
43	* @param pRegFrame Trap register frame.
44	* @param iGDTEntry The GDT entry to sync.
45	*/
46	static int selmGCSyncGDTEntry(PVM pVM, PCPUMCTXCORE pRegFrame, unsigned iGDTEntry)
47	{
48	PVMCPU pVCpu = VMMGetCpu0(pVM);
49
50	Log2(("GDT %04X LDTR=%04X\n", iGDTEntry, CPUMGetGuestLDTR(pVCpu)));
51
52	/*
53	* Validate the offset.
54	*/
55	VBOXGDTR GdtrGuest;
56	CPUMGetGuestGDTR(pVCpu, &GdtrGuest);
57	unsigned offEntry = iGDTEntry * sizeof(X86DESC);
58	if ( iGDTEntry >= SELM_GDT_ELEMENTS
59	\|\| offEntry > GdtrGuest.cbGdt)
60	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
61
62	/*
63	* Read the guest descriptor.
64	*/
65	X86DESC Desc;
66	int rc = MMGCRamRead(pVM, &Desc, (uint8_t *)(uintptr_t)GdtrGuest.pGdt + offEntry, sizeof(X86DESC));
67	if (RT_FAILURE(rc))
68	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
69
70	/*
71	* Check for conflicts.
72	*/
73	RTSEL Sel = iGDTEntry << X86_SEL_SHIFT;
74	Assert( !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] & ~X86_SEL_MASK)
75	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] & ~X86_SEL_MASK)
76	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] & ~X86_SEL_MASK)
77	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] & ~X86_SEL_MASK)
78	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] & ~X86_SEL_MASK));
79	if ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == Sel
80	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == Sel
81	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == Sel
82	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == Sel
83	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == Sel)
84	{
85	if (Desc.Gen.u1Present)
86	{
87	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: detected conflict!!\n", Sel, &Desc));
88	return VINF_SELM_SYNC_GDT;
89	}
90	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: potential conflict (still not present)!\n", Sel, &Desc));
91
92	/* Note: we can't continue below or else we'll change the shadow descriptor!! */
93	/* When the guest makes the selector present, then we'll do a GDT sync. */
94	return VINF_SUCCESS;
95	}
96
97	/*
98	* Code and data selectors are generally 1:1, with the
99	* 'little' adjustment we do for DPL 0 selectors.
100	*/
101	PX86DESC pShadowDescr = &pVM->selm.s.paGdtRC[iGDTEntry];
102	if (Desc.Gen.u1DescType)
103	{
104	/*
105	* Hack for A-bit against Trap E on read-only GDT.
106	*/
107	/** @todo Fix this by loading ds and cs before turning off WP. */
108	Desc.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
109
110	/*
111	* All DPL 0 code and data segments are squeezed into DPL 1.
112	*
113	* We're skipping conforming segments here because those
114	* cannot give us any trouble.
115	*/
116	if ( Desc.Gen.u2Dpl == 0
117	&& (Desc.Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
118	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
119	Desc.Gen.u2Dpl = 1;
120	}
121	else
122	{
123	/*
124	* System type selectors are marked not present.
125	* Recompiler or special handling is required for these.
126	*/
127	/** @todo what about interrupt gates and rawr0? */
128	Desc.Gen.u1Present = 0;
129	}
130	//Log(("O: base=%08X limit=%08X attr=%04X\n", X86DESC_BASE(pShadowDescr)), X86DESC_LIMIT(pShadowDescr), (pShadowDescr->au32[1] >> 8) & 0xFFFF ));
131	//Log(("N: base=%08X limit=%08X attr=%04X\n", X86DESC_BASE(Desc)), X86DESC_LIMIT(Desc), (Desc.au32[1] >> 8) & 0xFFFF ));
132	*pShadowDescr = Desc;
133
134	/*
135	* Detect and mark stale registers.
136	*/
137	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
138	PCPUMSELREG paSRegCtx = &pCtx->es;
139	PCPUMSELREG paSRegFrm = &pRegFrame->es;
140	for (unsigned i = 0; i <= X86_SREG_GS; i++)
141	if (Sel == (paSRegFrm[i].Sel & X86_SEL_MASK))
142	{
143	/** @todo we clear the valid flag here, maybe we shouldn't... but that would
144	* require implementing handling of stale registers in raw-mode.
145	* Tricky, at least for SS and CS. */
146	paSRegFrm[i].fFlags = CPUMSELREG_FLAGS_STALE;
147	paSRegCtx[i].fFlags = CPUMSELREG_FLAGS_STALE;
148	}
149
150	/*
151	* Check if we change the LDT selector.
152	*/
153	if (Sel == CPUMGetGuestLDTR(pVCpu)) /** @todo this isn't correct in two(+) ways! 1. It shouldn't be done until the LDTR is reloaded. 2. It caused the next instruction to be emulated. */
154	{
155	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
156	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
157	}
158
159	#ifdef LOG_ENABLED
160	if (Sel == (pRegFrame->cs.Sel & X86_SEL_MASK))
161	Log(("GDT write to selector in CS register %04X\n", pRegFrame->cs.Sel));
162	else if (Sel == (pRegFrame->ds.Sel & X86_SEL_MASK))
163	Log(("GDT write to selector in DS register %04X\n", pRegFrame->ds.Sel));
164	else if (Sel == (pRegFrame->es.Sel & X86_SEL_MASK))
165	Log(("GDT write to selector in ES register %04X\n", pRegFrame->es.Sel));
166	else if (Sel == (pRegFrame->fs.Sel & X86_SEL_MASK))
167	Log(("GDT write to selector in FS register %04X\n", pRegFrame->fs.Sel));
168	else if (Sel == (pRegFrame->gs.Sel & X86_SEL_MASK))
169	Log(("GDT write to selector in GS register %04X\n", pRegFrame->gs.Sel));
170	else if (Sel == (pRegFrame->ss.Sel & X86_SEL_MASK))
171	Log(("GDT write to selector in SS register %04X\n", pRegFrame->ss.Sel));
172	#endif
173
174	return VINF_SUCCESS;
175	}
176
177
178	/**
179	* \#PF Virtual Handler callback for Guest write access to the Guest's own GDT.
180	*
181	* @returns VBox status code (appropriate for trap handling and GC return).
182	* @param pVM Pointer to the VM.
183	* @param uErrorCode CPU Error code.
184	* @param pRegFrame Trap register frame.
185	* @param pvFault The fault address (cr2).
186	* @param pvRange The base address of the handled virtual range.
187	* @param offRange The offset of the access into this range.
188	* (If it's a EIP range this is the EIP, if not it's pvFault.)
189	*/
190	VMMRCDECL(int) selmRCGuestGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
191	{
192	PVMCPU pVCpu = VMMGetCpu0(pVM);
193	LogFlow(("selmRCGuestGDTWriteHandler errcode=%x fault=%RGv offRange=%08x\n", (uint32_t)uErrorCode, pvFault, offRange));
194	NOREF(pvRange);
195
196	/*
197	* First check if this is the LDT entry.
198	* LDT updates are problems since an invalid LDT entry will cause trouble during worldswitch.
199	*/
200	int rc;
201	if (CPUMGetGuestLDTR(pVCpu) / sizeof(X86DESC) == offRange / sizeof(X86DESC))
202	{
203	Log(("LDTR selector change -> fall back to HC!!\n"));
204	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
205	/** @todo We're not handling changed to the selectors in LDTR and TR correctly at all.
206	* We should ignore any changes to those and sync them only when they are loaded by the guest! */
207	}
208	else
209	{
210	/*
211	* Attempt to emulate the instruction and sync the affected entries.
212	*/
213	/** @todo should check if any affected selectors are loaded. */
214	uint32_t cb;
215	rc = EMInterpretInstructionEx(pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
216	if (RT_SUCCESS(rc) && cb)
217	{
218	unsigned iGDTE1 = offRange / sizeof(X86DESC);
219	int rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE1);
220	if (rc2 == VINF_SUCCESS)
221	{
222	Assert(cb);
223	unsigned iGDTE2 = (offRange + cb - 1) / sizeof(X86DESC);
224	if (iGDTE1 != iGDTE2)
225	rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE2);
226	if (rc2 == VINF_SUCCESS)
227	{
228	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTHandled);
229	return rc;
230	}
231	}
232	if (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2))
233	rc = rc2;
234	}
235	else
236	{
237	Assert(RT_FAILURE(rc));
238	if (rc == VERR_EM_INTERPRETER)
239	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
240	}
241	}
242	if ( rc != VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT
243	&& rc != VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT)
244	{
245	/* Not necessary when we need to go back to the host context to sync the LDT or TSS. */
246	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
247	}
248	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTUnhandled);
249	return rc;
250	}
251
252
253	/**
254	* \#PF Virtual Handler callback for Guest write access to the Guest's own LDT.
255	*
256	* @returns VBox status code (appropriate for trap handling and GC return).
257	* @param pVM Pointer to the VM.
258	* @param uErrorCode CPU Error code.
259	* @param pRegFrame Trap register frame.
260	* @param pvFault The fault address (cr2).
261	* @param pvRange The base address of the handled virtual range.
262	* @param offRange The offset of the access into this range.
263	* (If it's a EIP range this is the EIP, if not it's pvFault.)
264	*/
265	VMMRCDECL(int) selmRCGuestLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
266	{
267	/** @todo To be implemented. */
268	////LogCom(("selmRCGuestLDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
269	NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
270
271	VMCPU_FF_SET(VMMGetCpu0(pVM), VMCPU_FF_SELM_SYNC_LDT);
272	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestLDT);
273	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
274	}
275
276
277	/**
278	* Read wrapper used by selmRCGuestTSSWriteHandler.
279	* @returns VBox status code (appropriate for trap handling and GC return).
280	* @param pVM Pointer to the VM.
281	* @param pvDst Where to put the bits we read.
282	* @param pvSrc Guest address to read from.
283	* @param cb The number of bytes to read.
284	*/
285	DECLINLINE(int) selmRCReadTssBits(PVM pVM, void pvDst, void const pvSrc, size_t cb)
286	{
287	PVMCPU pVCpu = VMMGetCpu0(pVM);
288
289	int rc = MMGCRamRead(pVM, pvDst, (void *)pvSrc, cb);
290	if (RT_SUCCESS(rc))
291	return VINF_SUCCESS;
292
293	/** @todo use different fallback? */
294	rc = PGMPrefetchPage(pVCpu, (uintptr_t)pvSrc);
295	AssertMsg(rc == VINF_SUCCESS, ("PGMPrefetchPage %p failed with %Rrc\n", &pvSrc, rc));
296	if (rc == VINF_SUCCESS)
297	{
298	rc = MMGCRamRead(pVM, pvDst, (void *)pvSrc, cb);
299	AssertMsg(rc == VINF_SUCCESS, ("MMGCRamRead %p failed with %Rrc\n", &pvSrc, rc));
300	}
301	return rc;
302	}
303
304	/**
305	* \#PF Virtual Handler callback for Guest write access to the Guest's own current TSS.
306	*
307	* @returns VBox status code (appropriate for trap handling and GC return).
308	* @param pVM Pointer to the VM.
309	* @param uErrorCode CPU Error code.
310	* @param pRegFrame Trap register frame.
311	* @param pvFault The fault address (cr2).
312	* @param pvRange The base address of the handled virtual range.
313	* @param offRange The offset of the access into this range.
314	* (If it's a EIP range this is the EIP, if not it's pvFault.)
315	*/
316	VMMRCDECL(int) selmRCGuestTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
317	{
318	PVMCPU pVCpu = VMMGetCpu0(pVM);
319	LogFlow(("selmRCGuestTSSWriteHandler errcode=%x fault=%RGv offRange=%08x\n", (uint32_t)uErrorCode, pvFault, offRange));
320	NOREF(pvRange);
321
322	/*
323	* Try emulate the access.
324	*/
325	uint32_t cb;
326	int rc = EMInterpretInstructionEx(pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
327	if (RT_SUCCESS(rc) && cb)
328	{
329	rc = VINF_SUCCESS;
330
331	/*
332	* If it's on the same page as the esp0 and ss0 fields or actually one of them,
333	* then check if any of these has changed.
334	*/
335	PCVBOXTSS pGuestTss = (PVBOXTSS)(uintptr_t)pVM->selm.s.GCPtrGuestTss;
336	if ( PAGE_ADDRESS(&pGuestTss->esp0) == PAGE_ADDRESS(&pGuestTss->padding_ss0)
337	&& PAGE_ADDRESS(&pGuestTss->esp0) == PAGE_ADDRESS((uint8_t *)pGuestTss + offRange)
338	&& ( pGuestTss->esp0 != pVM->selm.s.Tss.esp1
339	\|\| pGuestTss->ss0 != (pVM->selm.s.Tss.ss1 & ~1)) /* undo raw-r0 */
340	)
341	{
342	Log(("selmRCGuestTSSWriteHandler: R0 stack: %RTsel:%RGv -> %RTsel:%RGv\n",
343	(RTSEL)(pVM->selm.s.Tss.ss1 & ~1), (RTGCPTR)pVM->selm.s.Tss.esp1, (RTSEL)pGuestTss->ss0, (RTGCPTR)pGuestTss->esp0));
344	pVM->selm.s.Tss.esp1 = pGuestTss->esp0;
345	pVM->selm.s.Tss.ss1 = pGuestTss->ss0 \| 1;
346	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandledChanged);
347	}
348	/* Handle misaligned TSS in a safe manner (just in case). */
349	else if ( offRange >= RT_UOFFSETOF(VBOXTSS, esp0)
350	&& offRange < RT_UOFFSETOF(VBOXTSS, padding_ss0))
351	{
352	struct
353	{
354	uint32_t esp0;
355	uint16_t ss0;
356	uint16_t padding_ss0;
357	} s;
358	AssertCompileSize(s, 8);
359	rc = selmRCReadTssBits(pVM, &s, &pGuestTss->esp0, sizeof(s));
360	if ( rc == VINF_SUCCESS
361	&& ( s.esp0 != pVM->selm.s.Tss.esp1
362	\|\| s.ss0 != (pVM->selm.s.Tss.ss1 & ~1)) /* undo raw-r0 */
363	)
364	{
365	Log(("selmRCGuestTSSWriteHandler: R0 stack: %RTsel:%RGv -> %RTsel:%RGv [x-page]\n",
366	(RTSEL)(pVM->selm.s.Tss.ss1 & ~1), (RTGCPTR)pVM->selm.s.Tss.esp1, (RTSEL)s.ss0, (RTGCPTR)s.esp0));
367	pVM->selm.s.Tss.esp1 = s.esp0;
368	pVM->selm.s.Tss.ss1 = s.ss0 \| 1;
369	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandledChanged);
370	}
371	}
372
373	/*
374	* If VME is enabled we need to check if the interrupt redirection bitmap
375	* needs updating.
376	*/
377	if ( offRange >= RT_UOFFSETOF(VBOXTSS, offIoBitmap)
378	&& (CPUMGetGuestCR4(pVCpu) & X86_CR4_VME))
379	{
380	if (offRange - RT_UOFFSETOF(VBOXTSS, offIoBitmap) < sizeof(pGuestTss->offIoBitmap))
381	{
382	uint16_t offIoBitmap = pGuestTss->offIoBitmap;
383	if (offIoBitmap != pVM->selm.s.offGuestIoBitmap)
384	{
385	Log(("TSS offIoBitmap changed: old=%#x new=%#x -> resync in ring-3\n", pVM->selm.s.offGuestIoBitmap, offIoBitmap));
386	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
387	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
388	}
389	else
390	Log(("TSS offIoBitmap: old=%#x new=%#x [unchanged]\n", pVM->selm.s.offGuestIoBitmap, offIoBitmap));
391	}
392	else
393	{
394	/** @todo not sure how the partial case is handled; probably not allowed */
395	uint32_t offIntRedirBitmap = pVM->selm.s.offGuestIoBitmap - sizeof(pVM->selm.s.Tss.IntRedirBitmap);
396	if ( offIntRedirBitmap <= offRange
397	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) >= offRange + cb
398	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) <= pVM->selm.s.cbGuestTss)
399	{
400	Log(("TSS IntRedirBitmap Changed: offIoBitmap=%x offIntRedirBitmap=%x cbTSS=%x offRange=%x cb=%x\n",
401	pVM->selm.s.offGuestIoBitmap, offIntRedirBitmap, pVM->selm.s.cbGuestTss, offRange, cb));
402
403	/** @todo only update the changed part. */
404	for (uint32_t i = 0; i < sizeof(pVM->selm.s.Tss.IntRedirBitmap) / 8; i++)
405	{
406	rc = selmRCReadTssBits(pVM, &pVM->selm.s.Tss.IntRedirBitmap[i * 8],
407	(uint8_t )pGuestTss + offIntRedirBitmap + i 8, 8);
408	if (rc != VINF_SUCCESS)
409	break;
410	}
411	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSRedir);
412	}
413	}
414	}
415
416	/* Return to ring-3 for a full resync if any of the above fails... (?) */
417	if (rc != VINF_SUCCESS)
418	{
419	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
420	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
421	if (RT_SUCCESS(rc))
422	rc = VINF_SUCCESS;
423	}
424
425	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandled);
426	}
427	else
428	{
429	Assert(RT_FAILURE(rc));
430	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
431	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSUnhandled);
432	if (rc == VERR_EM_INTERPRETER)
433	rc = VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT;
434	}
435	return rc;
436	}
437
438
439	/**
440	* \#PF Virtual Handler callback for Guest write access to the VBox shadow GDT.
441	*
442	* @returns VBox status code (appropriate for trap handling and GC return).
443	* @param pVM Pointer to the VM.
444	* @param uErrorCode CPU Error code.
445	* @param pRegFrame Trap register frame.
446	* @param pvFault The fault address (cr2).
447	* @param pvRange The base address of the handled virtual range.
448	* @param offRange The offset of the access into this range.
449	* (If it's a EIP range this is the EIP, if not it's pvFault.)
450	*/
451	VMMRCDECL(int) selmRCShadowGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
452	{
453	LogRel(("FATAL ERROR: selmRCShadowGDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
454	NOREF(pVM); NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
455	return VERR_SELM_SHADOW_GDT_WRITE;
456	}
457
458
459	/**
460	* \#PF Virtual Handler callback for Guest write access to the VBox shadow LDT.
461	*
462	* @returns VBox status code (appropriate for trap handling and GC return).
463	* @param pVM Pointer to the VM.
464	* @param uErrorCode CPU Error code.
465	* @param pRegFrame Trap register frame.
466	* @param pvFault The fault address (cr2).
467	* @param pvRange The base address of the handled virtual range.
468	* @param offRange The offset of the access into this range.
469	* (If it's a EIP range this is the EIP, if not it's pvFault.)
470	*/
471	VMMRCDECL(int) selmRCShadowLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
472	{
473	LogRel(("FATAL ERROR: selmRCShadowLDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
474	Assert(pvFault - (uintptr_t)pVM->selm.s.pvLdtRC < (unsigned)(65536U + PAGE_SIZE));
475	NOREF(pVM); NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
476	return VERR_SELM_SHADOW_LDT_WRITE;
477	}
478
479
480	/**
481	* \#PF Virtual Handler callback for Guest write access to the VBox shadow TSS.
482	*
483	* @returns VBox status code (appropriate for trap handling and GC return).
484	* @param pVM Pointer to the VM.
485	* @param uErrorCode CPU Error code.
486	* @param pRegFrame Trap register frame.
487	* @param pvFault The fault address (cr2).
488	* @param pvRange The base address of the handled virtual range.
489	* @param offRange The offset of the access into this range.
490	* (If it's a EIP range this is the EIP, if not it's pvFault.)
491	*/
492	VMMRCDECL(int) selmRCShadowTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
493	{
494	LogRel(("FATAL ERROR: selmRCShadowTSSWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
495	NOREF(pVM); NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
496	return VERR_SELM_SHADOW_TSS_WRITE;
497	}
498

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source: vbox/trunk/src/VBox/VMM/VMMRC/SELMRC.cpp@ 41908

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