SELMRC.cpp@ 41803

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1	/* $Id: SELMRC.cpp 41803 2012-06-17 17:20:33Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager, Guest Context.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_SELM
22	#include <VBox/vmm/selm.h>
23	#include <VBox/vmm/mm.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/trpm.h>
26	#include "SELMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/vmm.h>
29	#include <VBox/vmm/pgm.h>
30
31	#include <VBox/param.h>
32	#include <VBox/err.h>
33	#include <VBox/log.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38	/**
39	* Synchronizes one GDT entry (guest -> shadow).
40	*
41	* @returns VBox status code (appropriate for trap handling and GC return).
42	* @param pVM Pointer to the VM.
43	* @param pRegFrame Trap register frame.
44	* @param iGDTEntry The GDT entry to sync.
45	*/
46	static int selmGCSyncGDTEntry(PVM pVM, PCPUMCTXCORE pRegFrame, unsigned iGDTEntry)
47	{
48	PVMCPU pVCpu = VMMGetCpu0(pVM);
49
50	Log2(("GDT %04X LDTR=%04X\n", iGDTEntry, CPUMGetGuestLDTR(pVCpu)));
51
52	/*
53	* Validate the offset.
54	*/
55	VBOXGDTR GdtrGuest;
56	CPUMGetGuestGDTR(pVCpu, &GdtrGuest);
57	unsigned offEntry = iGDTEntry * sizeof(X86DESC);
58	if ( iGDTEntry >= SELM_GDT_ELEMENTS
59	\|\| offEntry > GdtrGuest.cbGdt)
60	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
61
62	/*
63	* Read the guest descriptor.
64	*/
65	X86DESC Desc;
66	int rc = MMGCRamRead(pVM, &Desc, (uint8_t *)(uintptr_t)GdtrGuest.pGdt + offEntry, sizeof(X86DESC));
67	if (RT_FAILURE(rc))
68	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
69
70	/*
71	* Check for conflicts.
72	*/
73	RTSEL Sel = iGDTEntry << X86_SEL_SHIFT;
74	Assert( !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] & ~X86_SEL_MASK)
75	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] & ~X86_SEL_MASK)
76	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] & ~X86_SEL_MASK)
77	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] & ~X86_SEL_MASK)
78	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] & ~X86_SEL_MASK));
79	if ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == Sel
80	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == Sel
81	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == Sel
82	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == Sel
83	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == Sel)
84	{
85	if (Desc.Gen.u1Present)
86	{
87	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: detected conflict!!\n", Sel, &Desc));
88	return VINF_SELM_SYNC_GDT;
89	}
90	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: potential conflict (still not present)!\n", Sel, &Desc));
91
92	/* Note: we can't continue below or else we'll change the shadow descriptor!! */
93	/* When the guest makes the selector present, then we'll do a GDT sync. */
94	return VINF_SUCCESS;
95	}
96
97	/*
98	* Code and data selectors are generally 1:1, with the
99	* 'little' adjustment we do for DPL 0 selectors.
100	*/
101	PX86DESC pShadowDescr = &pVM->selm.s.paGdtRC[iGDTEntry];
102	if (Desc.Gen.u1DescType)
103	{
104	/*
105	* Hack for A-bit against Trap E on read-only GDT.
106	*/
107	/** @todo Fix this by loading ds and cs before turning off WP. */
108	Desc.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
109
110	/*
111	* All DPL 0 code and data segments are squeezed into DPL 1.
112	*
113	* We're skipping conforming segments here because those
114	* cannot give us any trouble.
115	*/
116	if ( Desc.Gen.u2Dpl == 0
117	&& (Desc.Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
118	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
119	Desc.Gen.u2Dpl = 1;
120	}
121	else
122	{
123	/*
124	* System type selectors are marked not present.
125	* Recompiler or special handling is required for these.
126	*/
127	/** @todo what about interrupt gates and rawr0? */
128	Desc.Gen.u1Present = 0;
129	}
130	//Log(("O: base=%08X limit=%08X attr=%04X\n", X86DESC_BASE(pShadowDescr)), X86DESC_LIMIT(pShadowDescr), (pShadowDescr->au32[1] >> 8) & 0xFFFF ));
131	//Log(("N: base=%08X limit=%08X attr=%04X\n", X86DESC_BASE(Desc)), X86DESC_LIMIT(Desc), (Desc.au32[1] >> 8) & 0xFFFF ));
132	*pShadowDescr = Desc;
133
134	/* Check if we change the LDT selector */
135	if (Sel == CPUMGetGuestLDTR(pVCpu)) /** @todo this isn't correct in two(+) ways! 1. It shouldn't be done until the LDTR is reloaded. 2. It caused the next instruction to be emulated. */
136	{
137	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
138	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
139	}
140
141	#ifdef LOG_ENABLED
142	if (Sel == (pRegFrame->cs & X86_SEL_MASK))
143	Log(("GDT write to selector in CS register %04X\n", pRegFrame->cs));
144	else if (Sel == (pRegFrame->ds & X86_SEL_MASK))
145	Log(("GDT write to selector in DS register %04X\n", pRegFrame->ds));
146	else if (Sel == (pRegFrame->es & X86_SEL_MASK))
147	Log(("GDT write to selector in ES register %04X\n", pRegFrame->es));
148	else if (Sel == (pRegFrame->fs & X86_SEL_MASK))
149	Log(("GDT write to selector in FS register %04X\n", pRegFrame->fs));
150	else if (Sel == (pRegFrame->gs & X86_SEL_MASK))
151	Log(("GDT write to selector in GS register %04X\n", pRegFrame->gs));
152	else if (Sel == (pRegFrame->ss & X86_SEL_MASK))
153	Log(("GDT write to selector in SS register %04X\n", pRegFrame->ss));
154	#endif
155	return VINF_SUCCESS;
156	}
157
158
159	/**
160	* \#PF Virtual Handler callback for Guest write access to the Guest's own GDT.
161	*
162	* @returns VBox status code (appropriate for trap handling and GC return).
163	* @param pVM Pointer to the VM.
164	* @param uErrorCode CPU Error code.
165	* @param pRegFrame Trap register frame.
166	* @param pvFault The fault address (cr2).
167	* @param pvRange The base address of the handled virtual range.
168	* @param offRange The offset of the access into this range.
169	* (If it's a EIP range this is the EIP, if not it's pvFault.)
170	*/
171	VMMRCDECL(int) selmRCGuestGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
172	{
173	PVMCPU pVCpu = VMMGetCpu0(pVM);
174	LogFlow(("selmRCGuestGDTWriteHandler errcode=%x fault=%RGv offRange=%08x\n", (uint32_t)uErrorCode, pvFault, offRange));
175	NOREF(pvRange);
176
177	/*
178	* First check if this is the LDT entry.
179	* LDT updates are problems since an invalid LDT entry will cause trouble during worldswitch.
180	*/
181	int rc;
182	if (CPUMGetGuestLDTR(pVCpu) / sizeof(X86DESC) == offRange / sizeof(X86DESC))
183	{
184	Log(("LDTR selector change -> fall back to HC!!\n"));
185	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
186	/** @todo We're not handling changed to the selectors in LDTR and TR correctly at all.
187	* We should ignore any changes to those and sync them only when they are loaded by the guest! */
188	}
189	else
190	{
191	/*
192	* Attempt to emulate the instruction and sync the affected entries.
193	*/
194	/** @todo should check if any affected selectors are loaded. */
195	uint32_t cb;
196	rc = EMInterpretInstructionEx(pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
197	if (RT_SUCCESS(rc) && cb)
198	{
199	unsigned iGDTE1 = offRange / sizeof(X86DESC);
200	int rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE1);
201	if (rc2 == VINF_SUCCESS)
202	{
203	Assert(cb);
204	unsigned iGDTE2 = (offRange + cb - 1) / sizeof(X86DESC);
205	if (iGDTE1 != iGDTE2)
206	rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE2);
207	if (rc2 == VINF_SUCCESS)
208	{
209	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTHandled);
210	return rc;
211	}
212	}
213	if (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2))
214	rc = rc2;
215	}
216	else
217	{
218	Assert(RT_FAILURE(rc));
219	if (rc == VERR_EM_INTERPRETER)
220	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
221	}
222	}
223	if ( rc != VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT
224	&& rc != VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT)
225	{
226	/* Not necessary when we need to go back to the host context to sync the LDT or TSS. */
227	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
228	}
229	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTUnhandled);
230	return rc;
231	}
232
233
234	/**
235	* \#PF Virtual Handler callback for Guest write access to the Guest's own LDT.
236	*
237	* @returns VBox status code (appropriate for trap handling and GC return).
238	* @param pVM Pointer to the VM.
239	* @param uErrorCode CPU Error code.
240	* @param pRegFrame Trap register frame.
241	* @param pvFault The fault address (cr2).
242	* @param pvRange The base address of the handled virtual range.
243	* @param offRange The offset of the access into this range.
244	* (If it's a EIP range this is the EIP, if not it's pvFault.)
245	*/
246	VMMRCDECL(int) selmRCGuestLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
247	{
248	/** @todo To be implemented. */
249	////LogCom(("selmRCGuestLDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
250	NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
251
252	VMCPU_FF_SET(VMMGetCpu0(pVM), VMCPU_FF_SELM_SYNC_LDT);
253	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestLDT);
254	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
255	}
256
257
258	/**
259	* Read wrapper used by selmRCGuestTSSWriteHandler.
260	* @returns VBox status code (appropriate for trap handling and GC return).
261	* @param pVM Pointer to the VM.
262	* @param pvDst Where to put the bits we read.
263	* @param pvSrc Guest address to read from.
264	* @param cb The number of bytes to read.
265	*/
266	DECLINLINE(int) selmRCReadTssBits(PVM pVM, void pvDst, void const pvSrc, size_t cb)
267	{
268	PVMCPU pVCpu = VMMGetCpu0(pVM);
269
270	int rc = MMGCRamRead(pVM, pvDst, (void *)pvSrc, cb);
271	if (RT_SUCCESS(rc))
272	return VINF_SUCCESS;
273
274	/** @todo use different fallback? */
275	rc = PGMPrefetchPage(pVCpu, (uintptr_t)pvSrc);
276	AssertMsg(rc == VINF_SUCCESS, ("PGMPrefetchPage %p failed with %Rrc\n", &pvSrc, rc));
277	if (rc == VINF_SUCCESS)
278	{
279	rc = MMGCRamRead(pVM, pvDst, (void *)pvSrc, cb);
280	AssertMsg(rc == VINF_SUCCESS, ("MMGCRamRead %p failed with %Rrc\n", &pvSrc, rc));
281	}
282	return rc;
283	}
284
285	/**
286	* \#PF Virtual Handler callback for Guest write access to the Guest's own current TSS.
287	*
288	* @returns VBox status code (appropriate for trap handling and GC return).
289	* @param pVM Pointer to the VM.
290	* @param uErrorCode CPU Error code.
291	* @param pRegFrame Trap register frame.
292	* @param pvFault The fault address (cr2).
293	* @param pvRange The base address of the handled virtual range.
294	* @param offRange The offset of the access into this range.
295	* (If it's a EIP range this is the EIP, if not it's pvFault.)
296	*/
297	VMMRCDECL(int) selmRCGuestTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
298	{
299	PVMCPU pVCpu = VMMGetCpu0(pVM);
300	LogFlow(("selmRCGuestTSSWriteHandler errcode=%x fault=%RGv offRange=%08x\n", (uint32_t)uErrorCode, pvFault, offRange));
301	NOREF(pvRange);
302
303	/*
304	* Try emulate the access.
305	*/
306	uint32_t cb;
307	int rc = EMInterpretInstructionEx(pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
308	if (RT_SUCCESS(rc) && cb)
309	{
310	rc = VINF_SUCCESS;
311
312	/*
313	* If it's on the same page as the esp0 and ss0 fields or actually one of them,
314	* then check if any of these has changed.
315	*/
316	PCVBOXTSS pGuestTss = (PVBOXTSS)(uintptr_t)pVM->selm.s.GCPtrGuestTss;
317	if ( PAGE_ADDRESS(&pGuestTss->esp0) == PAGE_ADDRESS(&pGuestTss->padding_ss0)
318	&& PAGE_ADDRESS(&pGuestTss->esp0) == PAGE_ADDRESS((uint8_t *)pGuestTss + offRange)
319	&& ( pGuestTss->esp0 != pVM->selm.s.Tss.esp1
320	\|\| pGuestTss->ss0 != (pVM->selm.s.Tss.ss1 & ~1)) /* undo raw-r0 */
321	)
322	{
323	Log(("selmRCGuestTSSWriteHandler: R0 stack: %RTsel:%RGv -> %RTsel:%RGv\n",
324	(RTSEL)(pVM->selm.s.Tss.ss1 & ~1), (RTGCPTR)pVM->selm.s.Tss.esp1, (RTSEL)pGuestTss->ss0, (RTGCPTR)pGuestTss->esp0));
325	pVM->selm.s.Tss.esp1 = pGuestTss->esp0;
326	pVM->selm.s.Tss.ss1 = pGuestTss->ss0 \| 1;
327	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandledChanged);
328	}
329	/* Handle misaligned TSS in a safe manner (just in case). */
330	else if ( offRange >= RT_UOFFSETOF(VBOXTSS, esp0)
331	&& offRange < RT_UOFFSETOF(VBOXTSS, padding_ss0))
332	{
333	struct
334	{
335	uint32_t esp0;
336	uint16_t ss0;
337	uint16_t padding_ss0;
338	} s;
339	AssertCompileSize(s, 8);
340	rc = selmRCReadTssBits(pVM, &s, &pGuestTss->esp0, sizeof(s));
341	if ( rc == VINF_SUCCESS
342	&& ( s.esp0 != pVM->selm.s.Tss.esp1
343	\|\| s.ss0 != (pVM->selm.s.Tss.ss1 & ~1)) /* undo raw-r0 */
344	)
345	{
346	Log(("selmRCGuestTSSWriteHandler: R0 stack: %RTsel:%RGv -> %RTsel:%RGv [x-page]\n",
347	(RTSEL)(pVM->selm.s.Tss.ss1 & ~1), (RTGCPTR)pVM->selm.s.Tss.esp1, (RTSEL)s.ss0, (RTGCPTR)s.esp0));
348	pVM->selm.s.Tss.esp1 = s.esp0;
349	pVM->selm.s.Tss.ss1 = s.ss0 \| 1;
350	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandledChanged);
351	}
352	}
353
354	/*
355	* If VME is enabled we need to check if the interrupt redirection bitmap
356	* needs updating.
357	*/
358	if ( offRange >= RT_UOFFSETOF(VBOXTSS, offIoBitmap)
359	&& (CPUMGetGuestCR4(pVCpu) & X86_CR4_VME))
360	{
361	if (offRange - RT_UOFFSETOF(VBOXTSS, offIoBitmap) < sizeof(pGuestTss->offIoBitmap))
362	{
363	uint16_t offIoBitmap = pGuestTss->offIoBitmap;
364	if (offIoBitmap != pVM->selm.s.offGuestIoBitmap)
365	{
366	Log(("TSS offIoBitmap changed: old=%#x new=%#x -> resync in ring-3\n", pVM->selm.s.offGuestIoBitmap, offIoBitmap));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
368	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
369	}
370	else
371	Log(("TSS offIoBitmap: old=%#x new=%#x [unchanged]\n", pVM->selm.s.offGuestIoBitmap, offIoBitmap));
372	}
373	else
374	{
375	/** @todo not sure how the partial case is handled; probably not allowed */
376	uint32_t offIntRedirBitmap = pVM->selm.s.offGuestIoBitmap - sizeof(pVM->selm.s.Tss.IntRedirBitmap);
377	if ( offIntRedirBitmap <= offRange
378	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) >= offRange + cb
379	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) <= pVM->selm.s.cbGuestTss)
380	{
381	Log(("TSS IntRedirBitmap Changed: offIoBitmap=%x offIntRedirBitmap=%x cbTSS=%x offRange=%x cb=%x\n",
382	pVM->selm.s.offGuestIoBitmap, offIntRedirBitmap, pVM->selm.s.cbGuestTss, offRange, cb));
383
384	/** @todo only update the changed part. */
385	for (uint32_t i = 0; i < sizeof(pVM->selm.s.Tss.IntRedirBitmap) / 8; i++)
386	{
387	rc = selmRCReadTssBits(pVM, &pVM->selm.s.Tss.IntRedirBitmap[i * 8],
388	(uint8_t )pGuestTss + offIntRedirBitmap + i 8, 8);
389	if (rc != VINF_SUCCESS)
390	break;
391	}
392	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSRedir);
393	}
394	}
395	}
396
397	/* Return to ring-3 for a full resync if any of the above fails... (?) */
398	if (rc != VINF_SUCCESS)
399	{
400	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
401	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
402	if (RT_SUCCESS(rc))
403	rc = VINF_SUCCESS;
404	}
405
406	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandled);
407	}
408	else
409	{
410	Assert(RT_FAILURE(rc));
411	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
412	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSUnhandled);
413	if (rc == VERR_EM_INTERPRETER)
414	rc = VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT;
415	}
416	return rc;
417	}
418
419
420	/**
421	* \#PF Virtual Handler callback for Guest write access to the VBox shadow GDT.
422	*
423	* @returns VBox status code (appropriate for trap handling and GC return).
424	* @param pVM Pointer to the VM.
425	* @param uErrorCode CPU Error code.
426	* @param pRegFrame Trap register frame.
427	* @param pvFault The fault address (cr2).
428	* @param pvRange The base address of the handled virtual range.
429	* @param offRange The offset of the access into this range.
430	* (If it's a EIP range this is the EIP, if not it's pvFault.)
431	*/
432	VMMRCDECL(int) selmRCShadowGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
433	{
434	LogRel(("FATAL ERROR: selmRCShadowGDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
435	NOREF(pVM); NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
436	return VERR_SELM_SHADOW_GDT_WRITE;
437	}
438
439
440	/**
441	* \#PF Virtual Handler callback for Guest write access to the VBox shadow LDT.
442	*
443	* @returns VBox status code (appropriate for trap handling and GC return).
444	* @param pVM Pointer to the VM.
445	* @param uErrorCode CPU Error code.
446	* @param pRegFrame Trap register frame.
447	* @param pvFault The fault address (cr2).
448	* @param pvRange The base address of the handled virtual range.
449	* @param offRange The offset of the access into this range.
450	* (If it's a EIP range this is the EIP, if not it's pvFault.)
451	*/
452	VMMRCDECL(int) selmRCShadowLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
453	{
454	LogRel(("FATAL ERROR: selmRCShadowLDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
455	Assert(pvFault - (uintptr_t)pVM->selm.s.pvLdtRC < (unsigned)(65536U + PAGE_SIZE));
456	NOREF(pVM); NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
457	return VERR_SELM_SHADOW_LDT_WRITE;
458	}
459
460
461	/**
462	* \#PF Virtual Handler callback for Guest write access to the VBox shadow TSS.
463	*
464	* @returns VBox status code (appropriate for trap handling and GC return).
465	* @param pVM Pointer to the VM.
466	* @param uErrorCode CPU Error code.
467	* @param pRegFrame Trap register frame.
468	* @param pvFault The fault address (cr2).
469	* @param pvRange The base address of the handled virtual range.
470	* @param offRange The offset of the access into this range.
471	* (If it's a EIP range this is the EIP, if not it's pvFault.)
472	*/
473	VMMRCDECL(int) selmRCShadowTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
474	{
475	LogRel(("FATAL ERROR: selmRCShadowTSSWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
476	NOREF(pVM); NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(pvRange); NOREF(offRange);
477	return VERR_SELM_SHADOW_TSS_WRITE;
478	}
479

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source: vbox/trunk/src/VBox/VMM/VMMRC/SELMRC.cpp@ 41803

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