VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMRC/PDMRCDevice.cpp@ 42186

Last change on this file since 42186 was 41965, checked in by vboxsync, 12 years ago

VMM: ran scm. Mostly svn:keywords changes (adding Revision).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 30.9 KB
Line 
1/* $Id: PDMRCDevice.cpp 41965 2012-06-29 02:52:49Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, RC Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/vmm.h>
29#include <VBox/vmm/patm.h>
30
31#include <VBox/log.h>
32#include <VBox/err.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/string.h>
36
37#include "dtrace/VBoxVMM.h"
38#include "PDMInline.h"
39
40
41/*******************************************************************************
42* Global Variables *
43*******************************************************************************/
44RT_C_DECLS_BEGIN
45extern DECLEXPORT(const PDMDEVHLPRC) g_pdmRCDevHlp;
46extern DECLEXPORT(const PDMPICHLPRC) g_pdmRCPicHlp;
47extern DECLEXPORT(const PDMAPICHLPRC) g_pdmRCApicHlp;
48extern DECLEXPORT(const PDMIOAPICHLPRC) g_pdmRCIoApicHlp;
49extern DECLEXPORT(const PDMPCIHLPRC) g_pdmRCPciHlp;
50extern DECLEXPORT(const PDMHPETHLPRC) g_pdmRCHpetHlp;
51extern DECLEXPORT(const PDMDRVHLPRC) g_pdmRCDrvHlp;
52/** @todo missing PDMPCIRAWHLPRC */
53RT_C_DECLS_END
54
55
56/*******************************************************************************
57* Prototypes *
58*******************************************************************************/
59static int pdmRCDevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
60static int pdmRCDevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
61
62
63/*******************************************************************************
64* Internal Functions *
65*******************************************************************************/
66static bool pdmRCIsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc);
67
68
69/** @name Raw-Mode Context Device Helpers
70 * @{
71 */
72
73/** @interface_method_impl{PDMDEVHLPRC,pfnPCIPhysRead} */
74static DECLCALLBACK(int) pdmRCDevHlp_PCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
75{
76 PDMDEV_ASSERT_DEVINS(pDevIns);
77 LogFlow(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
78 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
79
80 PCIDevice *pPciDev = pDevIns->Internal.s.pPciDeviceRC;
81 AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
82
83 if (!PCIDevIsBusmaster(pPciDev))
84 {
85#ifdef DEBUG
86 LogFlow(("%s: %RU16:%RU16: No bus master (anymore), skipping read %p (%z)\n", __FUNCTION__,
87 PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbRead));
88#endif
89 return VINF_PDM_PCI_PHYS_READ_BM_DISABLED;
90 }
91
92 return pdmRCDevHlp_PhysRead(pDevIns, GCPhys, pvBuf, cbRead);
93}
94
95
96/** @interface_method_impl{PDMDEVHLPRC,pfnPCIPhysRead} */
97static DECLCALLBACK(int) pdmRCDevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
98{
99 PDMDEV_ASSERT_DEVINS(pDevIns);
100 LogFlow(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
101 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
102
103 PCIDevice *pPciDev = pDevIns->Internal.s.pPciDeviceRC;
104 AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
105
106 if (!PCIDevIsBusmaster(pPciDev))
107 {
108#ifdef DEBUG
109 LogFlow(("%s: %RU16:%RU16: No bus master (anymore), skipping write %p (%z)\n", __FUNCTION__,
110 PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbWrite));
111#endif
112 return VINF_PDM_PCI_PHYS_WRITE_BM_DISABLED;
113 }
114
115 return pdmRCDevHlp_PhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
116}
117
118
119/** @interface_method_impl{PDMDEVHLPRC,pfnPCISetIrq} */
120static DECLCALLBACK(void) pdmRCDevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
121{
122 PDMDEV_ASSERT_DEVINS(pDevIns);
123 LogFlow(("pdmRCDevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
124
125 PVM pVM = pDevIns->Internal.s.pVMRC;
126 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceRC;
127 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusRC;
128
129 pdmLock(pVM);
130 uint32_t uTagSrc;
131 if (iLevel & PDM_IRQ_LEVEL_HIGH)
132 {
133 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
134 if (iLevel == PDM_IRQ_LEVEL_HIGH)
135 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
136 else
137 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
138 }
139 else
140 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
141
142 if ( pPciDev
143 && pPciBus
144 && pPciBus->pDevInsRC)
145 {
146 pPciBus->pfnSetIrqRC(pPciBus->pDevInsRC, pPciDev, iIrq, iLevel, uTagSrc);
147
148 pdmUnlock(pVM);
149
150 if (iLevel == PDM_IRQ_LEVEL_LOW)
151 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
152 }
153 else
154 {
155 pdmUnlock(pVM);
156
157 /* queue for ring-3 execution. */
158 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueRC);
159 AssertReturnVoid(pTask);
160
161 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
162 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
163 pTask->u.SetIRQ.iIrq = iIrq;
164 pTask->u.SetIRQ.iLevel = iLevel;
165 pTask->u.SetIRQ.uTagSrc = uTagSrc;
166
167 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueRC, &pTask->Core, 0);
168 }
169
170 LogFlow(("pdmRCDevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
171}
172
173
174/** @interface_method_impl{PDMDRVHLPRC,pfnPCISetIrq} */
175static DECLCALLBACK(void) pdmRCDevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
176{
177 PDMDEV_ASSERT_DEVINS(pDevIns);
178 LogFlow(("pdmRCDevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
179 PVM pVM = pDevIns->Internal.s.pVMRC;
180
181 pdmLock(pVM);
182 uint32_t uTagSrc;
183 if (iLevel & PDM_IRQ_LEVEL_HIGH)
184 {
185 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
186 if (iLevel == PDM_IRQ_LEVEL_HIGH)
187 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
188 else
189 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
190 }
191 else
192 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
193
194 bool fRc = pdmRCIsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
195
196 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
197 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
198 pdmUnlock(pVM);
199 LogFlow(("pdmRCDevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
200}
201
202
203/** @interface_method_impl{PDMDEVHLPRC,pfnPhysRead} */
204static DECLCALLBACK(int) pdmRCDevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
205{
206 PDMDEV_ASSERT_DEVINS(pDevIns);
207 LogFlow(("pdmRCDevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
208 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
209
210 int rc = PGMPhysRead(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbRead);
211 AssertRC(rc); /** @todo track down the users for this bugger. */
212
213 Log(("pdmRCDevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
214 return rc;
215}
216
217
218/** @interface_method_impl{PDMDEVHLPRC,pfnPhysWrite} */
219static DECLCALLBACK(int) pdmRCDevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
220{
221 PDMDEV_ASSERT_DEVINS(pDevIns);
222 LogFlow(("pdmRCDevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
223 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
224
225 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbWrite);
226 AssertRC(rc); /** @todo track down the users for this bugger. */
227
228 Log(("pdmRCDevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
229 return rc;
230}
231
232
233/** @interface_method_impl{PDMDEVHLPRC,pfnA20IsEnabled} */
234static DECLCALLBACK(bool) pdmRCDevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
235{
236 PDMDEV_ASSERT_DEVINS(pDevIns);
237 LogFlow(("pdmRCDevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
238
239 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu0(pDevIns->Internal.s.pVMRC));
240
241 Log(("pdmRCDevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
242 return fEnabled;
243}
244
245
246/** @interface_method_impl{PDMDEVHLPRC,pfnVMState} */
247static DECLCALLBACK(VMSTATE) pdmRCDevHlp_VMState(PPDMDEVINS pDevIns)
248{
249 PDMDEV_ASSERT_DEVINS(pDevIns);
250
251 VMSTATE enmVMState = pDevIns->Internal.s.pVMRC->enmVMState;
252
253 LogFlow(("pdmRCDevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
254 return enmVMState;
255}
256
257
258/** @interface_method_impl{PDMDEVHLPRC,pfnVMSetError} */
259static DECLCALLBACK(int) pdmRCDevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
260{
261 PDMDEV_ASSERT_DEVINS(pDevIns);
262 va_list args;
263 va_start(args, pszFormat);
264 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
265 va_end(args);
266 return rc;
267}
268
269
270/** @interface_method_impl{PDMDEVHLPRC,pfnVMSetErrorV} */
271static DECLCALLBACK(int) pdmRCDevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
272{
273 PDMDEV_ASSERT_DEVINS(pDevIns);
274 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
275 return rc;
276}
277
278
279/** @interface_method_impl{PDMDEVHLPRC,pfnVMSetRuntimeError} */
280static DECLCALLBACK(int) pdmRCDevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
281{
282 PDMDEV_ASSERT_DEVINS(pDevIns);
283 va_list va;
284 va_start(va, pszFormat);
285 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFlags, pszErrorId, pszFormat, va);
286 va_end(va);
287 return rc;
288}
289
290
291/** @interface_method_impl{PDMDEVHLPRC,pfnVMSetErrorV} */
292static DECLCALLBACK(int) pdmRCDevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
293{
294 PDMDEV_ASSERT_DEVINS(pDevIns);
295 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFlags, pszErrorId, pszFormat, va);
296 return rc;
297}
298
299
300/** @interface_method_impl{PDMDEVHLPRC,pfnPATMSetMMIOPatchInfo} */
301static DECLCALLBACK(int) pdmRCDevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
302{
303 PDMDEV_ASSERT_DEVINS(pDevIns);
304 LogFlow(("pdmRCDevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
305
306 return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMRC, GCPhys, (RTRCPTR)(uintptr_t)pCachedData);
307}
308
309
310/** @interface_method_impl{PDMDEVHLPRC,pfnGetVM} */
311static DECLCALLBACK(PVM) pdmRCDevHlp_GetVM(PPDMDEVINS pDevIns)
312{
313 PDMDEV_ASSERT_DEVINS(pDevIns);
314 LogFlow(("pdmRCDevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
315 return pDevIns->Internal.s.pVMRC;
316}
317
318
319/** @interface_method_impl{PDMDEVHLPRC,pfnGetVMCPU} */
320static DECLCALLBACK(PVMCPU) pdmRCDevHlp_GetVMCPU(PPDMDEVINS pDevIns)
321{
322 PDMDEV_ASSERT_DEVINS(pDevIns);
323 LogFlow(("pdmRCDevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
324 return VMMGetCpu(pDevIns->Internal.s.pVMRC);
325}
326
327
328/** @interface_method_impl{PDMDEVHLPRC,pfnTMTimeVirtGet} */
329static DECLCALLBACK(uint64_t) pdmRCDevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
330{
331 PDMDEV_ASSERT_DEVINS(pDevIns);
332 LogFlow(("pdmRCDevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
333 return TMVirtualGet(pDevIns->Internal.s.pVMRC);
334}
335
336
337/** @interface_method_impl{PDMDEVHLPRC,pfnTMTimeVirtGetFreq} */
338static DECLCALLBACK(uint64_t) pdmRCDevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
339{
340 PDMDEV_ASSERT_DEVINS(pDevIns);
341 LogFlow(("pdmRCDevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
342 return TMVirtualGetFreq(pDevIns->Internal.s.pVMRC);
343}
344
345
346/** @interface_method_impl{PDMDEVHLPRC,pfnTMTimeVirtGetNano} */
347static DECLCALLBACK(uint64_t) pdmRCDevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
348{
349 PDMDEV_ASSERT_DEVINS(pDevIns);
350 LogFlow(("pdmRCDevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
351 return TMVirtualToNano(pDevIns->Internal.s.pVMRC, TMVirtualGet(pDevIns->Internal.s.pVMRC));
352}
353
354
355/** @interface_method_impl{PDMDEVHLPRC,pfnDBGFTraceBuf} */
356static DECLCALLBACK(RTTRACEBUF) pdmRCDevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
357{
358 PDMDEV_ASSERT_DEVINS(pDevIns);
359 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMRC->hTraceBufRC;
360 LogFlow(("pdmRCDevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
361 return hTraceBuf;
362}
363
364
365/**
366 * The Raw-Mode Context Device Helper Callbacks.
367 */
368extern DECLEXPORT(const PDMDEVHLPRC) g_pdmRCDevHlp =
369{
370 PDM_DEVHLPRC_VERSION,
371 pdmRCDevHlp_PCIPhysRead,
372 pdmRCDevHlp_PCIPhysWrite,
373 pdmRCDevHlp_PCISetIrq,
374 pdmRCDevHlp_ISASetIrq,
375 pdmRCDevHlp_PhysRead,
376 pdmRCDevHlp_PhysWrite,
377 pdmRCDevHlp_A20IsEnabled,
378 pdmRCDevHlp_VMState,
379 pdmRCDevHlp_VMSetError,
380 pdmRCDevHlp_VMSetErrorV,
381 pdmRCDevHlp_VMSetRuntimeError,
382 pdmRCDevHlp_VMSetRuntimeErrorV,
383 pdmRCDevHlp_PATMSetMMIOPatchInfo,
384 pdmRCDevHlp_GetVM,
385 pdmRCDevHlp_GetVMCPU,
386 pdmRCDevHlp_TMTimeVirtGet,
387 pdmRCDevHlp_TMTimeVirtGetFreq,
388 pdmRCDevHlp_TMTimeVirtGetNano,
389 pdmRCDevHlp_DBGFTraceBuf,
390 PDM_DEVHLPRC_VERSION
391};
392
393/** @} */
394
395
396
397
398/** @name PIC RC Helpers
399 * @{
400 */
401
402/** @interface_method_impl{PDMPICHLPGC,pfnSetInterruptFF} */
403static DECLCALLBACK(void) pdmRCPicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
404{
405 PDMDEV_ASSERT_DEVINS(pDevIns);
406 PVM pVM = pDevIns->Internal.s.pVMRC;
407
408 if (pVM->pdm.s.Apic.pfnLocalInterruptRC)
409 {
410 LogFlow(("pdmRCPicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
411 pDevIns, pDevIns->iInstance));
412 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
413 pVM->pdm.s.Apic.pfnLocalInterruptRC(pVM->pdm.s.Apic.pDevInsRC, 0, 1);
414 return;
415 }
416
417 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
418
419 LogFlow(("pdmRCPicHlp_SetInterruptFF: caller=%p/%d: VMMCPU_FF_INTERRUPT_PIC %d -> 1\n",
420 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
421
422 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
423}
424
425
426/** @interface_method_impl{PDMPICHLPGC,pfnClearInterruptFF} */
427static DECLCALLBACK(void) pdmRCPicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
428{
429 PDMDEV_ASSERT_DEVINS(pDevIns);
430 PVM pVM = pDevIns->Internal.s.CTX_SUFF(pVM);
431
432 if (pVM->pdm.s.Apic.pfnLocalInterruptRC)
433 {
434 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
435 LogFlow(("pdmRCPicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
436 pDevIns, pDevIns->iInstance));
437 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
438 pVM->pdm.s.Apic.pfnLocalInterruptRC(pVM->pdm.s.Apic.pDevInsRC, 0, 0);
439 return;
440 }
441
442 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
443
444 LogFlow(("pdmRCPicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
445 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
446
447 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
448}
449
450
451/** @interface_method_impl{PDMPICHLPGC,pfnLock} */
452static DECLCALLBACK(int) pdmRCPicHlp_Lock(PPDMDEVINS pDevIns, int rc)
453{
454 PDMDEV_ASSERT_DEVINS(pDevIns);
455 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
456}
457
458
459/** @interface_method_impl{PDMPICHLPGC,pfnUnlock} */
460static DECLCALLBACK(void) pdmRCPicHlp_Unlock(PPDMDEVINS pDevIns)
461{
462 PDMDEV_ASSERT_DEVINS(pDevIns);
463 pdmUnlock(pDevIns->Internal.s.pVMRC);
464}
465
466
467/**
468 * The Raw-Mode Context PIC Helper Callbacks.
469 */
470extern DECLEXPORT(const PDMPICHLPRC) g_pdmRCPicHlp =
471{
472 PDM_PICHLPRC_VERSION,
473 pdmRCPicHlp_SetInterruptFF,
474 pdmRCPicHlp_ClearInterruptFF,
475 pdmRCPicHlp_Lock,
476 pdmRCPicHlp_Unlock,
477 PDM_PICHLPRC_VERSION
478};
479
480/** @} */
481
482
483
484
485/** @name APIC RC Helpers
486 * @{
487 */
488
489/** @interface_method_impl{PDMAPICHLPRC,pfnSetInterruptFF} */
490static DECLCALLBACK(void) pdmRCApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
491{
492 PDMDEV_ASSERT_DEVINS(pDevIns);
493 PVM pVM = pDevIns->Internal.s.pVMRC;
494 PVMCPU pVCpu = &pVM->aCpus[idCpu];
495
496 AssertReturnVoid(idCpu < pVM->cCpus);
497
498 LogFlow(("pdmRCApicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 1\n",
499 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
500 switch (enmType)
501 {
502 case PDMAPICIRQ_HARDWARE:
503 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
504 break;
505 case PDMAPICIRQ_NMI:
506 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
507 break;
508 case PDMAPICIRQ_SMI:
509 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
510 break;
511 case PDMAPICIRQ_EXTINT:
512 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
513 break;
514 default:
515 AssertMsgFailed(("enmType=%d\n", enmType));
516 break;
517 }
518}
519
520
521/** @interface_method_impl{PDMAPICHLPRC,pfnClearInterruptFF} */
522static DECLCALLBACK(void) pdmRCApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
523{
524 PDMDEV_ASSERT_DEVINS(pDevIns);
525 PVM pVM = pDevIns->Internal.s.pVMRC;
526 PVMCPU pVCpu = &pVM->aCpus[idCpu];
527
528 AssertReturnVoid(idCpu < pVM->cCpus);
529
530 LogFlow(("pdmRCApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
531 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
532
533 /* Note: NMI/SMI can't be cleared. */
534 switch (enmType)
535 {
536 case PDMAPICIRQ_HARDWARE:
537 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
538 break;
539 case PDMAPICIRQ_EXTINT:
540 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
541 break;
542 default:
543 AssertMsgFailed(("enmType=%d\n", enmType));
544 break;
545 }
546}
547
548
549/** @interface_method_impl{PDMAPICHLPRC,pfnCalcIrqTag} */
550static DECLCALLBACK(uint32_t) pdmRCApicHlp_CalcIrqTag(PPDMDEVINS pDevIns, uint8_t u8Level)
551{
552 PDMDEV_ASSERT_DEVINS(pDevIns);
553 PVM pVM = pDevIns->Internal.s.pVMRC;
554
555 pdmLock(pVM);
556
557 uint32_t uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
558 if (u8Level == PDM_IRQ_LEVEL_HIGH)
559 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
560 else
561 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
562
563
564 pdmUnlock(pVM);
565 LogFlow(("pdmRCApicHlp_CalcIrqTag: caller=%p/%d: returns %#x (u8Level=%d)\n",
566 pDevIns, pDevIns->iInstance, uTagSrc, u8Level));
567 return uTagSrc;
568}
569
570
571/** @interface_method_impl{PDMAPICHLPRC,pfnChangeFeature} */
572static DECLCALLBACK(void) pdmRCApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
573{
574 PDMDEV_ASSERT_DEVINS(pDevIns);
575 LogFlow(("pdmRCApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
576 switch (enmVersion)
577 {
578 case PDMAPICVERSION_NONE:
579 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
580 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
581 break;
582 case PDMAPICVERSION_APIC:
583 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
584 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
585 break;
586 case PDMAPICVERSION_X2APIC:
587 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
588 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
589 break;
590 default:
591 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
592 }
593}
594
595
596/** @interface_method_impl{PDMAPICHLPRC,pfnLock} */
597static DECLCALLBACK(int) pdmRCApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
598{
599 PDMDEV_ASSERT_DEVINS(pDevIns);
600 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
601}
602
603
604/** @interface_method_impl{PDMAPICHLPRC,pfnUnlock} */
605static DECLCALLBACK(void) pdmRCApicHlp_Unlock(PPDMDEVINS pDevIns)
606{
607 PDMDEV_ASSERT_DEVINS(pDevIns);
608 pdmUnlock(pDevIns->Internal.s.pVMRC);
609}
610
611
612/** @interface_method_impl{PDMAPICHLPRC,pfnGetCpuId} */
613static DECLCALLBACK(VMCPUID) pdmRCApicHlp_GetCpuId(PPDMDEVINS pDevIns)
614{
615 PDMDEV_ASSERT_DEVINS(pDevIns);
616 return VMMGetCpuId(pDevIns->Internal.s.pVMRC);
617}
618
619
620/**
621 * The Raw-Mode Context APIC Helper Callbacks.
622 */
623extern DECLEXPORT(const PDMAPICHLPRC) g_pdmRCApicHlp =
624{
625 PDM_APICHLPRC_VERSION,
626 pdmRCApicHlp_SetInterruptFF,
627 pdmRCApicHlp_ClearInterruptFF,
628 pdmRCApicHlp_CalcIrqTag,
629 pdmRCApicHlp_ChangeFeature,
630 pdmRCApicHlp_Lock,
631 pdmRCApicHlp_Unlock,
632 pdmRCApicHlp_GetCpuId,
633 PDM_APICHLPRC_VERSION
634};
635
636/** @} */
637
638
639
640
641/** @name I/O APIC RC Helpers
642 * @{
643 */
644
645/** @interface_method_impl{PDMIOAPICHLPRC,pfnApicBusDeliver} */
646static DECLCALLBACK(int) pdmRCIoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
647 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc)
648{
649 PDMDEV_ASSERT_DEVINS(pDevIns);
650 PVM pVM = pDevIns->Internal.s.pVMRC;
651 LogFlow(("pdmRCIoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
652 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
653 Assert(pVM->pdm.s.Apic.pDevInsRC);
654 if (pVM->pdm.s.Apic.pfnBusDeliverRC)
655 return pVM->pdm.s.Apic.pfnBusDeliverRC(pVM->pdm.s.Apic.pDevInsRC, u8Dest, u8DestMode, u8DeliveryMode, iVector,
656 u8Polarity, u8TriggerMode, uTagSrc);
657 return VINF_SUCCESS;
658}
659
660
661/** @interface_method_impl{PDMIOAPICHLPRC,pfnLock} */
662static DECLCALLBACK(int) pdmRCIoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
663{
664 PDMDEV_ASSERT_DEVINS(pDevIns);
665 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
666}
667
668
669/** @interface_method_impl{PDMIOAPICHLPRC,pfnUnlock} */
670static DECLCALLBACK(void) pdmRCIoApicHlp_Unlock(PPDMDEVINS pDevIns)
671{
672 PDMDEV_ASSERT_DEVINS(pDevIns);
673 pdmUnlock(pDevIns->Internal.s.pVMRC);
674}
675
676
677/**
678 * The Raw-Mode Context I/O APIC Helper Callbacks.
679 */
680extern DECLEXPORT(const PDMIOAPICHLPRC) g_pdmRCIoApicHlp =
681{
682 PDM_IOAPICHLPRC_VERSION,
683 pdmRCIoApicHlp_ApicBusDeliver,
684 pdmRCIoApicHlp_Lock,
685 pdmRCIoApicHlp_Unlock,
686 PDM_IOAPICHLPRC_VERSION
687};
688
689/** @} */
690
691
692
693
694/** @name PCI Bus RC Helpers
695 * @{
696 */
697
698/** @interface_method_impl{PDMPCIHLPRC,pfnIsaSetIrq} */
699static DECLCALLBACK(void) pdmRCPciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
700{
701 PDMDEV_ASSERT_DEVINS(pDevIns);
702 Log4(("pdmRCPciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
703 PVM pVM = pDevIns->Internal.s.pVMRC;
704
705 pdmLock(pVM);
706 pdmRCIsaSetIrq(pDevIns->Internal.s.pVMRC, iIrq, iLevel, uTagSrc);
707 pdmUnlock(pVM);
708}
709
710
711/** @interface_method_impl{PDMPCIHLPRC,pfnIoApicSetIrq} */
712static DECLCALLBACK(void) pdmRCPciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
713{
714 PDMDEV_ASSERT_DEVINS(pDevIns);
715 Log4(("pdmRCPciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
716 PVM pVM = pDevIns->Internal.s.pVMRC;
717
718 if (pVM->pdm.s.IoApic.pDevInsRC)
719 {
720 pdmLock(pVM);
721 pVM->pdm.s.IoApic.pfnSetIrqRC(pVM->pdm.s.IoApic.pDevInsRC, iIrq, iLevel, uTagSrc);
722 pdmUnlock(pVM);
723 }
724 else if (pVM->pdm.s.IoApic.pDevInsR3)
725 {
726 /* queue for ring-3 execution. */
727 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueRC);
728 if (pTask)
729 {
730 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
731 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
732 pTask->u.SetIRQ.iIrq = iIrq;
733 pTask->u.SetIRQ.iLevel = iLevel;
734 pTask->u.SetIRQ.uTagSrc = uTagSrc;
735
736 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueRC, &pTask->Core, 0);
737 }
738 else
739 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
740 }
741}
742
743
744/** @interface_method_impl{PDMPCIHLPRC,pfnIoApicSendMsi} */
745static DECLCALLBACK(void) pdmRCPciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
746{
747 PDMDEV_ASSERT_DEVINS(pDevIns);
748 Log4(("pdmRCPciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
749 PVM pVM = pDevIns->Internal.s.pVMRC;
750
751 if (pVM->pdm.s.IoApic.pDevInsRC)
752 {
753 pdmLock(pVM);
754 pVM->pdm.s.IoApic.pfnSendMsiRC(pVM->pdm.s.IoApic.pDevInsRC, GCPhys, uValue, uTagSrc);
755 pdmUnlock(pVM);
756 }
757 else
758 {
759 AssertFatalMsgFailed(("Lazy bastarts!"));
760 }
761}
762
763
764/** @interface_method_impl{PDMPCIHLPRC,pfnLock} */
765static DECLCALLBACK(int) pdmRCPciHlp_Lock(PPDMDEVINS pDevIns, int rc)
766{
767 PDMDEV_ASSERT_DEVINS(pDevIns);
768 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
769}
770
771
772/** @interface_method_impl{PDMPCIHLPRC,pfnUnlock} */
773static DECLCALLBACK(void) pdmRCPciHlp_Unlock(PPDMDEVINS pDevIns)
774{
775 PDMDEV_ASSERT_DEVINS(pDevIns);
776 pdmUnlock(pDevIns->Internal.s.pVMRC);
777}
778
779
780/**
781 * The Raw-Mode Context PCI Bus Helper Callbacks.
782 */
783extern DECLEXPORT(const PDMPCIHLPRC) g_pdmRCPciHlp =
784{
785 PDM_PCIHLPRC_VERSION,
786 pdmRCPciHlp_IsaSetIrq,
787 pdmRCPciHlp_IoApicSetIrq,
788 pdmRCPciHlp_IoApicSendMsi,
789 pdmRCPciHlp_Lock,
790 pdmRCPciHlp_Unlock,
791 PDM_PCIHLPRC_VERSION, /* the end */
792};
793
794/** @} */
795
796
797
798
799/** @name HPET RC Helpers
800 * @{
801 */
802
803
804/**
805 * The Raw-Mode Context HPET Helper Callbacks.
806 */
807extern DECLEXPORT(const PDMHPETHLPRC) g_pdmRCHpetHlp =
808{
809 PDM_HPETHLPRC_VERSION,
810 PDM_HPETHLPRC_VERSION, /* the end */
811};
812
813/** @} */
814
815
816
817
818/** @name Raw-Mode Context Driver Helpers
819 * @{
820 */
821
822/** @interface_method_impl{PDMDRVHLPRC,pfnVMSetError} */
823static DECLCALLBACK(int) pdmRCDrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
824{
825 PDMDRV_ASSERT_DRVINS(pDrvIns);
826 va_list args;
827 va_start(args, pszFormat);
828 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
829 va_end(args);
830 return rc;
831}
832
833
834/** @interface_method_impl{PDMDRVHLPRC,pfnVMSetErrorV} */
835static DECLCALLBACK(int) pdmRCDrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
836{
837 PDMDRV_ASSERT_DRVINS(pDrvIns);
838 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
839 return rc;
840}
841
842
843/** @interface_method_impl{PDMDRVHLPRC,pfnVMSetRuntimeError} */
844static DECLCALLBACK(int) pdmRCDrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
845{
846 PDMDRV_ASSERT_DRVINS(pDrvIns);
847 va_list va;
848 va_start(va, pszFormat);
849 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMRC, fFlags, pszErrorId, pszFormat, va);
850 va_end(va);
851 return rc;
852}
853
854
855/** @interface_method_impl{PDMDRVHLPRC,pfnVMSetErrorV} */
856static DECLCALLBACK(int) pdmRCDrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
857{
858 PDMDRV_ASSERT_DRVINS(pDrvIns);
859 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMRC, fFlags, pszErrorId, pszFormat, va);
860 return rc;
861}
862
863
864/** @interface_method_impl{PDMDRVHLPRC,pfnAssertEMT} */
865static DECLCALLBACK(bool) pdmRCDrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
866{
867 PDMDRV_ASSERT_DRVINS(pDrvIns);
868 if (VM_IS_EMT(pDrvIns->Internal.s.pVMRC))
869 return true;
870
871 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
872 RTAssertPanic();
873 return false;
874}
875
876
877/** @interface_method_impl{PDMDRVHLPRC,pfnAssertOther} */
878static DECLCALLBACK(bool) pdmRCDrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
879{
880 PDMDRV_ASSERT_DRVINS(pDrvIns);
881 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMRC))
882 return true;
883
884 /* Note: While we don't have any other threads but EMT(0) in RC, might
885 still have drive code compiled in which it shouldn't execute. */
886 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
887 RTAssertPanic();
888 return false;
889}
890
891
892/** @interface_method_impl{PDMDRVHLPRC,pfnFTSetCheckpoint} */
893static DECLCALLBACK(int) pdmRCDrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
894{
895 PDMDRV_ASSERT_DRVINS(pDrvIns);
896 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMRC, enmType);
897}
898
899
900/**
901 * The Raw-Mode Context Driver Helper Callbacks.
902 */
903extern DECLEXPORT(const PDMDRVHLPRC) g_pdmRCDrvHlp =
904{
905 PDM_DRVHLPRC_VERSION,
906 pdmRCDrvHlp_VMSetError,
907 pdmRCDrvHlp_VMSetErrorV,
908 pdmRCDrvHlp_VMSetRuntimeError,
909 pdmRCDrvHlp_VMSetRuntimeErrorV,
910 pdmRCDrvHlp_AssertEMT,
911 pdmRCDrvHlp_AssertOther,
912 pdmRCDrvHlp_FTSetCheckpoint,
913 PDM_DRVHLPRC_VERSION
914};
915
916/** @} */
917
918
919
920
921/**
922 * Sets an irq on the PIC and I/O APIC.
923 *
924 * @returns true if delivered, false if postponed.
925 * @param pVM Pointer to the VM.
926 * @param iIrq The irq.
927 * @param iLevel The new level.
928 * @param uTagSrc The IRQ tag and source.
929 *
930 * @remarks The caller holds the PDM lock.
931 */
932static bool pdmRCIsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc)
933{
934 if (RT_LIKELY( ( pVM->pdm.s.IoApic.pDevInsRC
935 || !pVM->pdm.s.IoApic.pDevInsR3)
936 && ( pVM->pdm.s.Pic.pDevInsRC
937 || !pVM->pdm.s.Pic.pDevInsR3)))
938 {
939 if (pVM->pdm.s.Pic.pDevInsRC)
940 pVM->pdm.s.Pic.pfnSetIrqRC(pVM->pdm.s.Pic.pDevInsRC, iIrq, iLevel, uTagSrc);
941 if (pVM->pdm.s.IoApic.pDevInsRC)
942 pVM->pdm.s.IoApic.pfnSetIrqRC(pVM->pdm.s.IoApic.pDevInsRC, iIrq, iLevel, uTagSrc);
943 return true;
944 }
945
946 /* queue for ring-3 execution. */
947 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueRC);
948 AssertReturn(pTask, false);
949
950 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
951 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
952 pTask->u.SetIRQ.iIrq = iIrq;
953 pTask->u.SetIRQ.iLevel = iLevel;
954 pTask->u.SetIRQ.uTagSrc = uTagSrc;
955
956 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueRC, &pTask->Core, 0);
957 return false;
958}
959
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette