CPUMRCA.asm@ 47167

Last change on this file since 47167 was 42771, checked in by vboxsync, 12 years ago
TRPM,CPUM: Added sanity assertions before resuming guest execution.
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File size: 9.5 KB

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1	; $Id: CPUMRCA.asm 42771 2012-08-11 20:15:47Z vboxsync $
2	;; @file
3	; CPUM - Raw-mode Context Assembly Routines.
4	;
5
6	; Copyright (C) 2006-2012 Oracle Corporation
7	;
8	; This file is part of VirtualBox Open Source Edition (OSE), as
9	; available from http://www.virtualbox.org. This file is free software;
10	; you can redistribute it and/or modify it under the terms of the GNU
11	; General Public License (GPL) as published by the Free Software
12	; Foundation, in version 2 as it comes in the "COPYING" file of the
13	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	;
16
17	;*******************************************************************************
18	;* Header Files *
19	;*******************************************************************************
20	%include "VMMRC.mac"
21	%include "VBox/vmm/vm.mac"
22	%include "VBox/err.mac"
23	%include "VBox/vmm/stam.mac"
24	%include "CPUMInternal.mac"
25	%include "iprt/x86.mac"
26	%include "VBox/vmm/cpum.mac"
27
28
29	;*******************************************************************************
30	;* External Symbols *
31	;*******************************************************************************
32	extern IMPNAME(g_CPUM) ; VMM GC Builtin import
33	extern IMPNAME(g_VM) ; VMM GC Builtin import
34	extern NAME(cpumRCHandleNPAndGP) ; CPUMGC.cpp
35	extern NAME(CPUMRCAssertPreExecutionSanity)
36
37
38	;
39	; Enables write protection of Hypervisor memory pages.
40	; !note! Must be commented out for Trap8 debug handler.
41	;
42	%define ENABLE_WRITE_PROTECTION 1
43
44	BEGINCODE
45
46
47	;;
48	; Calls a guest trap/interrupt handler directly
49	; Assumes a trap stack frame has already been setup on the guest's stack!
50	;
51	; @param pRegFrame [esp + 4] Original trap/interrupt context
52	; @param selCS [esp + 8] Code selector of handler
53	; @param pHandler [esp + 12] GC virtual address of handler
54	; @param eflags [esp + 16] Callee's EFLAGS
55	; @param selSS [esp + 20] Stack selector for handler
56	; @param pEsp [esp + 24] Stack address for handler
57	;
58	; @remark This call never returns!
59	;
60	; VMMRCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
61	align 16
62	BEGINPROC_EXPORTED CPUMGCCallGuestTrapHandler
63	mov ebp, esp
64
65	; construct iret stack frame
66	push dword [ebp + 20] ; SS
67	push dword [ebp + 24] ; ESP
68	push dword [ebp + 16] ; EFLAGS
69	push dword [ebp + 8] ; CS
70	push dword [ebp + 12] ; EIP
71
72	;
73	; enable WP
74	;
75	%ifdef ENABLE_WRITE_PROTECTION
76	mov eax, cr0
77	or eax, X86_CR0_WRITE_PROTECT
78	mov cr0, eax
79	%endif
80
81	; restore CPU context (all except cs, eip, ss, esp & eflags; which are restored or overwritten by iret)
82	mov ebp, [ebp + 4] ; pRegFrame
83	mov ebx, [ebp + CPUMCTXCORE.ebx]
84	mov ecx, [ebp + CPUMCTXCORE.ecx]
85	mov edx, [ebp + CPUMCTXCORE.edx]
86	mov esi, [ebp + CPUMCTXCORE.esi]
87	mov edi, [ebp + CPUMCTXCORE.edi]
88
89	;; @todo load segment registers before enabling WP.
90	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_GS \| CPUM_HANDLER_CTXCORE_IN_EBP
91	mov gs, [ebp + CPUMCTXCORE.gs.Sel]
92	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_FS \| CPUM_HANDLER_CTXCORE_IN_EBP
93	mov fs, [ebp + CPUMCTXCORE.fs.Sel]
94	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_ES \| CPUM_HANDLER_CTXCORE_IN_EBP
95	mov es, [ebp + CPUMCTXCORE.es.Sel]
96	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_DS \| CPUM_HANDLER_CTXCORE_IN_EBP
97	mov ds, [ebp + CPUMCTXCORE.ds.Sel]
98
99	mov eax, [ebp + CPUMCTXCORE.eax]
100	mov ebp, [ebp + CPUMCTXCORE.ebp]
101
102	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
103	iret
104	ENDPROC CPUMGCCallGuestTrapHandler
105
106
107	;;
108	; Performs an iret to V86 code
109	; Assumes a trap stack frame has already been setup on the guest's stack!
110	;
111	; @param pRegFrame Original trap/interrupt context
112	;
113	; This function does not return!
114	;
115	;VMMRCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
116	align 16
117	BEGINPROC CPUMGCCallV86Code
118	mov ebp, [esp + 4] ; pRegFrame
119
120	; construct iret stack frame
121	push dword [ebp + CPUMCTXCORE.gs.Sel]
122	push dword [ebp + CPUMCTXCORE.fs.Sel]
123	push dword [ebp + CPUMCTXCORE.ds.Sel]
124	push dword [ebp + CPUMCTXCORE.es.Sel]
125	push dword [ebp + CPUMCTXCORE.ss.Sel]
126	push dword [ebp + CPUMCTXCORE.esp]
127	push dword [ebp + CPUMCTXCORE.eflags]
128	push dword [ebp + CPUMCTXCORE.cs.Sel]
129	push dword [ebp + CPUMCTXCORE.eip]
130
131	;
132	; enable WP
133	;
134	%ifdef ENABLE_WRITE_PROTECTION
135	mov eax, cr0
136	or eax, X86_CR0_WRITE_PROTECT
137	mov cr0, eax
138	%endif
139
140	; restore CPU context (all except cs, eip, ss, esp, eflags, ds, es, fs & gs; which are restored or overwritten by iret)
141	mov eax, [ebp + CPUMCTXCORE.eax]
142	mov ebx, [ebp + CPUMCTXCORE.ebx]
143	mov ecx, [ebp + CPUMCTXCORE.ecx]
144	mov edx, [ebp + CPUMCTXCORE.edx]
145	mov esi, [ebp + CPUMCTXCORE.esi]
146	mov edi, [ebp + CPUMCTXCORE.edi]
147	mov ebp, [ebp + CPUMCTXCORE.ebp]
148
149	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
150	iret
151	ENDPROC CPUMGCCallV86Code
152
153
154	;;
155	; This is a main entry point for resuming (or starting) guest
156	; code execution.
157	;
158	; We get here directly from VMMSwitcher.asm (jmp at the end
159	; of VMMSwitcher_HostToGuest).
160	;
161	; This call never returns!
162	;
163	; @param edx Pointer to CPUM structure.
164	;
165	align 16
166	BEGINPROC_EXPORTED CPUMGCResumeGuest
167	%ifdef VBOX_STRICT
168	; Call CPUM to check sanity.
169	push edx
170	mov edx, IMP(g_VM)
171	push edx
172	call NAME(CPUMRCAssertPreExecutionSanity)
173	add esp, 4
174	pop edx
175	%endif
176
177	; Convert to CPUMCPU pointer
178	add edx, [edx + CPUM.offCPUMCPU0]
179	;
180	; Setup iretd
181	;
182	push dword [edx + CPUMCPU.Guest.ss.Sel]
183	push dword [edx + CPUMCPU.Guest.esp]
184	push dword [edx + CPUMCPU.Guest.eflags]
185	push dword [edx + CPUMCPU.Guest.cs.Sel]
186	push dword [edx + CPUMCPU.Guest.eip]
187
188	;
189	; Restore registers.
190	;
191	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_ES
192	mov es, [edx + CPUMCPU.Guest.es.Sel]
193	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_FS
194	mov fs, [edx + CPUMCPU.Guest.fs.Sel]
195	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_GS
196	mov gs, [edx + CPUMCPU.Guest.gs.Sel]
197
198	%ifdef VBOX_WITH_STATISTICS
199	;
200	; Statistics.
201	;
202	push edx
203	mov edx, IMP(g_VM)
204	lea edx, [edx + VM.StatTotalQemuToGC]
205	STAM_PROFILE_ADV_STOP edx
206
207	mov edx, IMP(g_VM)
208	lea edx, [edx + VM.StatTotalInGC]
209	STAM_PROFILE_ADV_START edx
210	pop edx
211	%endif
212
213	;
214	; enable WP
215	;
216	%ifdef ENABLE_WRITE_PROTECTION
217	mov eax, cr0
218	or eax, X86_CR0_WRITE_PROTECT
219	mov cr0, eax
220	%endif
221
222	;
223	; Continue restore.
224	;
225	mov esi, [edx + CPUMCPU.Guest.esi]
226	mov edi, [edx + CPUMCPU.Guest.edi]
227	mov ebp, [edx + CPUMCPU.Guest.ebp]
228	mov ebx, [edx + CPUMCPU.Guest.ebx]
229	mov ecx, [edx + CPUMCPU.Guest.ecx]
230	mov eax, [edx + CPUMCPU.Guest.eax]
231	push dword [edx + CPUMCPU.Guest.ds.Sel]
232	mov edx, [edx + CPUMCPU.Guest.edx]
233	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_DS
234	pop ds
235
236	; restart execution.
237	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
238	iretd
239	ENDPROC CPUMGCResumeGuest
240
241
242	;;
243	; This is a main entry point for resuming (or starting) guest
244	; code execution for raw V86 mode
245	;
246	; We get here directly from VMMSwitcher.asm (jmp at the end
247	; of VMMSwitcher_HostToGuest).
248	;
249	; This call never returns!
250	;
251	; @param edx Pointer to CPUM structure.
252	;
253	align 16
254	BEGINPROC_EXPORTED CPUMGCResumeGuestV86
255	%ifdef VBOX_STRICT
256	; Call CPUM to check sanity.
257	push edx
258	mov edx, IMP(g_VM)
259	push edx
260	call NAME(CPUMRCAssertPreExecutionSanity)
261	add esp, 4
262	pop edx
263	%endif
264
265	; Convert to CPUMCPU pointer
266	add edx, [edx + CPUM.offCPUMCPU0]
267	;
268	; Setup iretd
269	;
270	push dword [edx + CPUMCPU.Guest.gs.Sel]
271	push dword [edx + CPUMCPU.Guest.fs.Sel]
272	push dword [edx + CPUMCPU.Guest.ds.Sel]
273	push dword [edx + CPUMCPU.Guest.es.Sel]
274
275	push dword [edx + CPUMCPU.Guest.ss.Sel]
276	push dword [edx + CPUMCPU.Guest.esp]
277
278	push dword [edx + CPUMCPU.Guest.eflags]
279	push dword [edx + CPUMCPU.Guest.cs.Sel]
280	push dword [edx + CPUMCPU.Guest.eip]
281
282	;
283	; Restore registers.
284	;
285
286	%ifdef VBOX_WITH_STATISTICS
287	;
288	; Statistics.
289	;
290	push edx
291	mov edx, IMP(g_VM)
292	lea edx, [edx + VM.StatTotalQemuToGC]
293	STAM_PROFILE_ADV_STOP edx
294
295	mov edx, IMP(g_VM)
296	lea edx, [edx + VM.StatTotalInGC]
297	STAM_PROFILE_ADV_START edx
298	pop edx
299	%endif
300
301	;
302	; enable WP
303	;
304	%ifdef ENABLE_WRITE_PROTECTION
305	mov eax, cr0
306	or eax, X86_CR0_WRITE_PROTECT
307	mov cr0, eax
308	%endif
309
310	;
311	; Continue restore.
312	;
313	mov esi, [edx + CPUMCPU.Guest.esi]
314	mov edi, [edx + CPUMCPU.Guest.edi]
315	mov ebp, [edx + CPUMCPU.Guest.ebp]
316	mov ecx, [edx + CPUMCPU.Guest.ecx]
317	mov ebx, [edx + CPUMCPU.Guest.ebx]
318	mov eax, [edx + CPUMCPU.Guest.eax]
319	mov edx, [edx + CPUMCPU.Guest.edx]
320
321	; restart execution.
322	TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
323	iretd
324	ENDPROC CPUMGCResumeGuestV86
325

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source: vbox/trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm@ 47167

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