1 | ; $Id: CPUMRCA.asm 37955 2011-07-14 12:23:02Z vboxsync $
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2 | ;; @file
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3 | ; CPUM - Guest Context Assembly Routines.
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4 | ;
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5 |
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6 | ; Copyright (C) 2006-2007 Oracle Corporation
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7 | ;
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8 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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9 | ; available from http://www.virtualbox.org. This file is free software;
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10 | ; you can redistribute it and/or modify it under the terms of the GNU
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11 | ; General Public License (GPL) as published by the Free Software
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12 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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13 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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14 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | ;
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16 |
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17 | ;*******************************************************************************
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18 | ;* Header Files *
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19 | ;*******************************************************************************
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20 | %include "VMMRC.mac"
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21 | %include "VBox/vmm/vm.mac"
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22 | %include "VBox/err.mac"
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23 | %include "VBox/vmm/stam.mac"
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24 | %include "CPUMInternal.mac"
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25 | %include "iprt/x86.mac"
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26 | %include "VBox/vmm/cpum.mac"
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27 |
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28 |
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29 | ;*******************************************************************************
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30 | ;* External Symbols *
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31 | ;*******************************************************************************
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32 | extern IMPNAME(g_CPUM) ; VMM GC Builtin import
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33 | extern IMPNAME(g_VM) ; VMM GC Builtin import
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34 | extern NAME(cpumGCHandleNPAndGP) ; CPUMGC.cpp
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35 |
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36 | ;
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37 | ; Enables write protection of Hypervisor memory pages.
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38 | ; !note! Must be commented out for Trap8 debug handler.
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39 | ;
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40 | %define ENABLE_WRITE_PROTECTION 1
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41 |
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42 | BEGINCODE
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43 |
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44 |
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45 | ;;
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46 | ; Restores GC context before doing iret.
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47 | ;
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48 | ; @param [esp + 4] Pointer to interrupt stack frame, i.e. pointer
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49 | ; to the a struct with this layout:
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50 | ; 00h eip
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51 | ; 04h cs
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52 | ; 08h eflags
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53 | ; 0ch esp
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54 | ; 10h ss
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55 | ; 14h es (V86 only)
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56 | ; 18h ds (V86 only)
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57 | ; 1Ch fs (V86 only)
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58 | ; 20h gs (V86 only)
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59 | ;
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60 | ; @uses everything but cs, ss, esp, and eflags.
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61 | ;
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62 | ; @remark Assumes we're restoring in Ring-0 a context which is not Ring-0.
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63 | ; Further assumes flat stack and valid ds.
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64 |
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65 | BEGINPROC CPUMGCRestoreInt
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66 | ;
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67 | ; Update iret frame.
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68 | ;
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69 | mov eax, [esp + 4] ; get argument
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70 | mov edx, IMP(g_CPUM)
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71 | ; Convert to CPUMCPU pointer
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72 | add edx, [edx + CPUM.offCPUMCPU0]
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73 |
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74 | mov ecx, [edx + CPUMCPU.Guest.eip]
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75 | mov [eax + 0h], ecx
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76 | mov ecx, [edx + CPUMCPU.Guest.cs]
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77 | mov [eax + 4h], ecx
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78 | mov ecx, [edx + CPUMCPU.Guest.eflags]
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79 | mov [eax + 8h], ecx
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80 | mov ecx, [edx + CPUMCPU.Guest.esp]
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81 | mov [eax + 0ch], ecx
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82 | mov ecx, [edx + CPUMCPU.Guest.ss]
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83 | mov [eax + 10h], ecx
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84 |
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85 | test dword [edx + CPUMCPU.Guest.eflags], X86_EFL_VM
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86 | jnz short CPUMGCRestoreInt_V86
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87 |
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88 | ;
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89 | ; Load registers.
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90 | ;
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91 | ; todo: potential trouble loading invalid es,fs,gs,ds because
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92 | ; of a VMM imposed exception?
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93 | mov es, [edx + CPUMCPU.Guest.es]
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94 | mov fs, [edx + CPUMCPU.Guest.fs]
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95 | mov gs, [edx + CPUMCPU.Guest.gs]
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96 | mov esi, [edx + CPUMCPU.Guest.esi]
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97 | mov edi, [edx + CPUMCPU.Guest.edi]
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98 | mov ebp, [edx + CPUMCPU.Guest.ebp]
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99 | mov ebx, [edx + CPUMCPU.Guest.ebx]
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100 | mov ecx, [edx + CPUMCPU.Guest.ecx]
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101 | mov eax, [edx + CPUMCPU.Guest.eax]
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102 | push dword [edx + CPUMCPU.Guest.ds]
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103 | mov edx, [edx + CPUMCPU.Guest.edx]
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104 | pop ds
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105 |
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106 | ret
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107 |
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108 | CPUMGCRestoreInt_V86:
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109 | ; iret restores ds, es, fs & gs
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110 | mov ecx, [edx + CPUMCPU.Guest.es]
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111 | mov [eax + 14h], ecx
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112 | mov ecx, [edx + CPUMCPU.Guest.ds]
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113 | mov [eax + 18h], ecx
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114 | mov ecx, [edx + CPUMCPU.Guest.fs]
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115 | mov [eax + 1Ch], ecx
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116 | mov ecx, [edx + CPUMCPU.Guest.gs]
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117 | mov [eax + 20h], ecx
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118 | mov esi, [edx + CPUMCPU.Guest.esi]
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119 | mov edi, [edx + CPUMCPU.Guest.edi]
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120 | mov ebp, [edx + CPUMCPU.Guest.ebp]
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121 | mov ebx, [edx + CPUMCPU.Guest.ebx]
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122 | mov ecx, [edx + CPUMCPU.Guest.ecx]
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123 | mov eax, [edx + CPUMCPU.Guest.eax]
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124 | mov edx, [edx + CPUMCPU.Guest.edx]
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125 | ret
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126 |
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127 | ENDPROC CPUMGCRestoreInt
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128 |
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129 |
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130 | ;;
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131 | ; Calls a guest trap/interrupt handler directly
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132 | ; Assumes a trap stack frame has already been setup on the guest's stack!
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133 | ;
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134 | ; @param pRegFrame [esp + 4] Original trap/interrupt context
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135 | ; @param selCS [esp + 8] Code selector of handler
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136 | ; @param pHandler [esp + 12] GC virtual address of handler
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137 | ; @param eflags [esp + 16] Callee's EFLAGS
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138 | ; @param selSS [esp + 20] Stack selector for handler
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139 | ; @param pEsp [esp + 24] Stack address for handler
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140 | ;
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141 | ; @remark This call never returns!
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142 | ;
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143 | ; VMMRCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
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144 | align 16
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145 | BEGINPROC_EXPORTED CPUMGCCallGuestTrapHandler
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146 | mov ebp, esp
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147 |
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148 | ; construct iret stack frame
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149 | push dword [ebp + 20] ; SS
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150 | push dword [ebp + 24] ; ESP
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151 | push dword [ebp + 16] ; EFLAGS
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152 | push dword [ebp + 8] ; CS
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153 | push dword [ebp + 12] ; EIP
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154 |
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155 | ;
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156 | ; enable WP
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157 | ;
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158 | %ifdef ENABLE_WRITE_PROTECTION
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159 | mov eax, cr0
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160 | or eax, X86_CR0_WRITE_PROTECT
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161 | mov cr0, eax
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162 | %endif
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163 |
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164 | ; restore CPU context (all except cs, eip, ss, esp & eflags; which are restored or overwritten by iret)
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165 | mov ebp, [ebp + 4] ; pRegFrame
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166 | mov ebx, [ebp + CPUMCTXCORE.ebx]
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167 | mov ecx, [ebp + CPUMCTXCORE.ecx]
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168 | mov edx, [ebp + CPUMCTXCORE.edx]
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169 | mov esi, [ebp + CPUMCTXCORE.esi]
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170 | mov edi, [ebp + CPUMCTXCORE.edi]
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171 |
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172 | ;; @todo load segment registers *before* enabling WP.
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173 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS | CPUM_HANDLER_CTXCORE_IN_EBP
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174 | mov gs, [ebp + CPUMCTXCORE.gs]
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175 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS | CPUM_HANDLER_CTXCORE_IN_EBP
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176 | mov fs, [ebp + CPUMCTXCORE.fs]
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177 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES | CPUM_HANDLER_CTXCORE_IN_EBP
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178 | mov es, [ebp + CPUMCTXCORE.es]
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179 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS | CPUM_HANDLER_CTXCORE_IN_EBP
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180 | mov ds, [ebp + CPUMCTXCORE.ds]
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181 |
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182 | mov eax, [ebp + CPUMCTXCORE.eax]
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183 | mov ebp, [ebp + CPUMCTXCORE.ebp]
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184 |
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185 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
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186 | iret
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187 | ENDPROC CPUMGCCallGuestTrapHandler
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188 |
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189 |
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190 | ;;
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191 | ; Performs an iret to V86 code
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192 | ; Assumes a trap stack frame has already been setup on the guest's stack!
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193 | ;
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194 | ; @param pRegFrame Original trap/interrupt context
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195 | ;
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196 | ; This function does not return!
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197 | ;
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198 | ;VMMRCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
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199 | align 16
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200 | BEGINPROC CPUMGCCallV86Code
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201 | mov ebp, [esp + 4] ; pRegFrame
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202 |
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203 | ; construct iret stack frame
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204 | push dword [ebp + CPUMCTXCORE.gs]
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205 | push dword [ebp + CPUMCTXCORE.fs]
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206 | push dword [ebp + CPUMCTXCORE.ds]
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207 | push dword [ebp + CPUMCTXCORE.es]
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208 | push dword [ebp + CPUMCTXCORE.ss]
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209 | push dword [ebp + CPUMCTXCORE.esp]
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210 | push dword [ebp + CPUMCTXCORE.eflags]
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211 | push dword [ebp + CPUMCTXCORE.cs]
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212 | push dword [ebp + CPUMCTXCORE.eip]
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213 |
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214 | ;
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215 | ; enable WP
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216 | ;
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217 | %ifdef ENABLE_WRITE_PROTECTION
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218 | mov eax, cr0
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219 | or eax, X86_CR0_WRITE_PROTECT
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220 | mov cr0, eax
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221 | %endif
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222 |
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223 | ; restore CPU context (all except cs, eip, ss, esp, eflags, ds, es, fs & gs; which are restored or overwritten by iret)
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224 | mov eax, [ebp + CPUMCTXCORE.eax]
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225 | mov ebx, [ebp + CPUMCTXCORE.ebx]
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226 | mov ecx, [ebp + CPUMCTXCORE.ecx]
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227 | mov edx, [ebp + CPUMCTXCORE.edx]
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228 | mov esi, [ebp + CPUMCTXCORE.esi]
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229 | mov edi, [ebp + CPUMCTXCORE.edi]
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230 | mov ebp, [ebp + CPUMCTXCORE.ebp]
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231 |
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232 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
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233 | iret
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234 | ENDPROC CPUMGCCallV86Code
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235 |
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236 |
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237 | ;;
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238 | ; This is a main entry point for resuming (or starting) guest
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239 | ; code execution.
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240 | ;
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241 | ; We get here directly from VMMSwitcher.asm (jmp at the end
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242 | ; of VMMSwitcher_HostToGuest).
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243 | ;
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244 | ; This call never returns!
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245 | ;
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246 | ; @param edx Pointer to CPUM structure.
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247 | ;
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248 | align 16
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249 | BEGINPROC_EXPORTED CPUMGCResumeGuest
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250 | ; Convert to CPUMCPU pointer
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251 | add edx, [edx + CPUM.offCPUMCPU0]
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252 | ;
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253 | ; Setup iretd
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254 | ;
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255 | push dword [edx + CPUMCPU.Guest.ss]
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256 | push dword [edx + CPUMCPU.Guest.esp]
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257 | push dword [edx + CPUMCPU.Guest.eflags]
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258 | push dword [edx + CPUMCPU.Guest.cs]
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259 | push dword [edx + CPUMCPU.Guest.eip]
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260 |
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261 | ;
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262 | ; Restore registers.
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263 | ;
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264 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES
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265 | mov es, [edx + CPUMCPU.Guest.es]
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266 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS
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267 | mov fs, [edx + CPUMCPU.Guest.fs]
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268 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS
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269 | mov gs, [edx + CPUMCPU.Guest.gs]
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270 |
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271 | %ifdef VBOX_WITH_STATISTICS
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272 | ;
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273 | ; Statistics.
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274 | ;
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275 | push edx
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276 | mov edx, IMP(g_VM)
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277 | lea edx, [edx + VM.StatTotalQemuToGC]
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278 | STAM_PROFILE_ADV_STOP edx
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279 |
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280 | mov edx, IMP(g_VM)
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281 | lea edx, [edx + VM.StatTotalInGC]
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282 | STAM_PROFILE_ADV_START edx
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283 | pop edx
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284 | %endif
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285 |
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286 | ;
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287 | ; enable WP
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288 | ;
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289 | %ifdef ENABLE_WRITE_PROTECTION
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290 | mov eax, cr0
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291 | or eax, X86_CR0_WRITE_PROTECT
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292 | mov cr0, eax
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293 | %endif
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294 |
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295 | ;
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296 | ; Continue restore.
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297 | ;
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298 | mov esi, [edx + CPUMCPU.Guest.esi]
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299 | mov edi, [edx + CPUMCPU.Guest.edi]
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300 | mov ebp, [edx + CPUMCPU.Guest.ebp]
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301 | mov ebx, [edx + CPUMCPU.Guest.ebx]
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302 | mov ecx, [edx + CPUMCPU.Guest.ecx]
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303 | mov eax, [edx + CPUMCPU.Guest.eax]
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304 | push dword [edx + CPUMCPU.Guest.ds]
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305 | mov edx, [edx + CPUMCPU.Guest.edx]
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306 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS
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307 | pop ds
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308 |
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309 | ; restart execution.
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310 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
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311 | iretd
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312 | ENDPROC CPUMGCResumeGuest
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313 |
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314 |
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315 | ;;
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316 | ; This is a main entry point for resuming (or starting) guest
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317 | ; code execution for raw V86 mode
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318 | ;
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319 | ; We get here directly from VMMSwitcher.asm (jmp at the end
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320 | ; of VMMSwitcher_HostToGuest).
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321 | ;
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322 | ; This call never returns!
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323 | ;
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324 | ; @param edx Pointer to CPUM structure.
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325 | ;
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326 | align 16
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327 | BEGINPROC_EXPORTED CPUMGCResumeGuestV86
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328 | ; Convert to CPUMCPU pointer
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329 | add edx, [edx + CPUM.offCPUMCPU0]
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330 | ;
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331 | ; Setup iretd
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332 | ;
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333 | push dword [edx + CPUMCPU.Guest.gs]
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334 | push dword [edx + CPUMCPU.Guest.fs]
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335 | push dword [edx + CPUMCPU.Guest.ds]
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336 | push dword [edx + CPUMCPU.Guest.es]
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337 |
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338 | push dword [edx + CPUMCPU.Guest.ss]
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339 | push dword [edx + CPUMCPU.Guest.esp]
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340 |
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341 | push dword [edx + CPUMCPU.Guest.eflags]
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342 | push dword [edx + CPUMCPU.Guest.cs]
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343 | push dword [edx + CPUMCPU.Guest.eip]
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344 |
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345 | ;
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346 | ; Restore registers.
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347 | ;
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348 |
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349 | %ifdef VBOX_WITH_STATISTICS
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350 | ;
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351 | ; Statistics.
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352 | ;
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353 | push edx
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354 | mov edx, IMP(g_VM)
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355 | lea edx, [edx + VM.StatTotalQemuToGC]
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356 | STAM_PROFILE_ADV_STOP edx
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357 |
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358 | mov edx, IMP(g_VM)
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359 | lea edx, [edx + VM.StatTotalInGC]
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360 | STAM_PROFILE_ADV_START edx
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361 | pop edx
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362 | %endif
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363 |
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364 | ;
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365 | ; enable WP
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366 | ;
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367 | %ifdef ENABLE_WRITE_PROTECTION
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368 | mov eax, cr0
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369 | or eax, X86_CR0_WRITE_PROTECT
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370 | mov cr0, eax
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371 | %endif
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372 |
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373 | ;
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374 | ; Continue restore.
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375 | ;
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376 | mov esi, [edx + CPUMCPU.Guest.esi]
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377 | mov edi, [edx + CPUMCPU.Guest.edi]
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378 | mov ebp, [edx + CPUMCPU.Guest.ebp]
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379 | mov ecx, [edx + CPUMCPU.Guest.ecx]
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380 | mov ebx, [edx + CPUMCPU.Guest.ebx]
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381 | mov eax, [edx + CPUMCPU.Guest.eax]
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382 | mov edx, [edx + CPUMCPU.Guest.edx]
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383 |
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384 | ; restart execution.
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385 | TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
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386 | iretd
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387 | ENDPROC CPUMGCResumeGuestV86
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388 |
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