VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp@ 62489

Last change on this file since 62489 was 62478, checked in by vboxsync, 8 years ago

(C) 2016

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 10.0 KB
Line 
1/* $Id: CPUMRC.cpp 62478 2016-07-22 18:29:06Z vboxsync $ */
2/** @file
3 * CPUM - Raw-mode Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/vmm.h>
25#include <VBox/vmm/patm.h>
26#include <VBox/vmm/trpm.h>
27#include <VBox/vmm/em.h>
28#include "CPUMInternal.h"
29#include <VBox/vmm/vm.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <VBox/log.h>
33#include <iprt/asm-amd64-x86.h>
34
35
36/*********************************************************************************************************************************
37* Internal Functions *
38*********************************************************************************************************************************/
39RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
40DECLCALLBACK(int) cpumRCHandleNPAndGP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
41RT_C_DECLS_END
42
43
44/**
45 * Deal with traps occurring during segment loading and IRET when resuming guest
46 * context execution.
47 *
48 * @returns VBox status code.
49 * @param pVM The cross context VM structure.
50 * @param pRegFrame The register frame.
51 * @param uUser User argument. In this case a combination of the
52 * CPUM_HANDLER_* \#defines.
53 */
54DECLCALLBACK(int) cpumRCHandleNPAndGP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
55{
56 Log(("********************************************************\n"));
57 Log(("cpumRCHandleNPAndGP: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
58 Log(("********************************************************\n"));
59
60 /*
61 * Take action based on what's happened.
62 */
63 switch (uUser & CPUM_HANDLER_TYPEMASK)
64 {
65 case CPUM_HANDLER_GS:
66 case CPUM_HANDLER_DS:
67 case CPUM_HANDLER_ES:
68 case CPUM_HANDLER_FS:
69 TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_STALE_SELECTOR);
70 break;
71
72 case CPUM_HANDLER_IRET:
73 TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_IRET_TRAP);
74 break;
75 }
76
77 AssertMsgFailed(("uUser=%#x eip=%#x\n", uUser, pRegFrame->eip));
78 return VERR_TRPM_DONT_PANIC;
79}
80
81
82/**
83 * Called by TRPM and CPUM assembly code to make sure the guest state is
84 * ready for execution.
85 *
86 * @param pVM The cross context VM structure.
87 */
88DECLASM(void) CPUMRCAssertPreExecutionSanity(PVM pVM)
89{
90#ifdef VBOX_STRICT
91 /*
92 * Check some important assumptions before resuming guest execution.
93 */
94 PVMCPU pVCpu = VMMGetCpu0(pVM);
95 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
96 uint8_t const uRawCpl = CPUMGetGuestCPL(pVCpu);
97 uint32_t const u32EFlags = CPUMRawGetEFlags(pVCpu);
98 bool const fPatch = PATMIsPatchGCAddr(pVM, pCtx->eip);
99 AssertMsg(pCtx->eflags.Bits.u1IF, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
100 AssertMsg(pCtx->eflags.Bits.u2IOPL < RT_MAX(uRawCpl, 1U),
101 ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
102 if (!(u32EFlags & X86_EFL_VM))
103 {
104 AssertMsg((u32EFlags & X86_EFL_IF) || fPatch,("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
105 AssertMsg((pCtx->cs.Sel & X86_SEL_RPL) > 0, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
106 AssertMsg((pCtx->ss.Sel & X86_SEL_RPL) > 0, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
107 }
108 AssertMsg(CPUMIsGuestInRawMode(pVCpu), ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
109 //Log2(("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
110#endif
111}
112
113
114/**
115 * Get the current privilege level of the guest.
116 *
117 * @returns CPL
118 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
119 * @param pRegFrame Pointer to the register frame.
120 *
121 * @todo r=bird: This is very similar to CPUMGetGuestCPL and I cannot quite
122 * see why this variant of the code is necessary.
123 */
124VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
125{
126 /*
127 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
128 *
129 * Note! We used to check CS.DPL here, assuming it was always equal to
130 * CPL even if a conforming segment was loaded. But this truned out to
131 * only apply to older AMD-V. With VT-x we had an ACP2 regression
132 * during install after a far call to ring 2 with VT-x. Then on newer
133 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
134 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
135 *
136 * So, forget CS.DPL, always use SS.DPL.
137 *
138 * Note! The SS RPL is always equal to the CPL, while the CS RPL
139 * isn't necessarily equal if the segment is conforming.
140 * See section 4.11.1 in the AMD manual.
141 */
142 uint32_t uCpl;
143 if (!pRegFrame->eflags.Bits.u1VM)
144 {
145 uCpl = (pRegFrame->ss.Sel & X86_SEL_RPL);
146#ifdef VBOX_WITH_RAW_MODE_NOT_R0
147# ifdef VBOX_WITH_RAW_RING1
148 if (pVCpu->cpum.s.fRawEntered)
149 {
150 if ( uCpl == 2
151 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) )
152 uCpl = 1;
153 else if (uCpl == 1)
154 uCpl = 0;
155 }
156 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
157# else
158 if (uCpl == 1)
159 uCpl = 0;
160# endif
161#endif
162 }
163 else
164 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
165
166 return uCpl;
167}
168
169
170#ifdef VBOX_WITH_RAW_RING1
171/**
172 * Transforms the guest CPU state to raw-ring mode.
173 *
174 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
175 *
176 * Used by emInterpretIret() after the new state has been loaded.
177 *
178 * @param pVCpu The cross context virtual CPU structure.
179 * @param pCtxCore The context core (for trap usage).
180 * @see @ref pg_raw
181 * @remarks Will be probably obsoleted by #5653 (it will leave and reenter raw
182 * mode instead, I think).
183 */
184VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
185{
186 /*
187 * Are we in Ring-0?
188 */
189 if ( pCtxCore->ss.Sel
190 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
191 && !pCtxCore->eflags.Bits.u1VM)
192 {
193 /*
194 * Set CPL to Ring-1.
195 */
196 pCtxCore->ss.Sel |= 1;
197 if ( pCtxCore->cs.Sel
198 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
199 pCtxCore->cs.Sel |= 1;
200 }
201 else
202 {
203 if ( EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM))
204 && !pCtxCore->eflags.Bits.u1VM
205 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
206 {
207 /* Set CPL to Ring-2. */
208 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
209 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
210 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
211 }
212 }
213
214 /*
215 * Assert sanity.
216 */
217 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
218 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
219 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
220
221 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
222}
223#endif /* VBOX_WITH_RAW_RING1 */
224
225
226/**
227 * Called by trpmGCExitTrap when VMCPU_FF_CPUM is set (by CPUMRZ.cpp).
228 *
229 * We can be called unecessarily here if we returned to ring-3 for some other
230 * reason before we tried to resume executed guest code. This is detected and
231 * ignored.
232 *
233 * @param pVCpu The cross context CPU structure for the calling EMT.
234 */
235VMMRCDECL(void) CPUMRCProcessForceFlag(PVMCPU pVCpu)
236{
237 /* Only modify CR0 if we're in the post IEM state (host state saved, guest no longer active). */
238 if ((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST)) == CPUM_USED_FPU_HOST)
239 {
240 /*
241 * Doing the same CR0 calculation as in AMD64andLegacy.mac so that we'll
242 * catch guest FPU accesses and load the FPU/SSE/AVX register state as needed.
243 */
244 uint32_t cr0 = ASMGetCR0();
245 cr0 |= pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM;
246 cr0 |= X86_CR0_TS | X86_CR0_MP;
247 ASMSetCR0(cr0);
248 Log6(("CPUMRCProcessForceFlag: cr0=%#x\n", cr0));
249 }
250 else
251 Log6(("CPUMRCProcessForceFlag: no change - cr0=%#x\n", ASMGetCR0()));
252}
253
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette