| 1 | /* $Id: CPUMRC.cpp 54674 2015-03-06 18:02:31Z vboxsync $ */
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| 2 | /** @file
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| 3 | * CPUM - Raw-mode Context Code.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2015 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 |
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| 19 | /*******************************************************************************
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| 20 | * Header Files *
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| 21 | *******************************************************************************/
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| 22 | #define LOG_GROUP LOG_GROUP_CPUM
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| 23 | #include <VBox/vmm/cpum.h>
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| 24 | #include <VBox/vmm/vmm.h>
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| 25 | #include <VBox/vmm/patm.h>
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| 26 | #include <VBox/vmm/trpm.h>
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| 27 | #include <VBox/vmm/em.h>
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| 28 | #include "CPUMInternal.h"
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| 29 | #include <VBox/vmm/vm.h>
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| 30 | #include <VBox/err.h>
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| 31 | #include <iprt/assert.h>
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| 32 | #include <VBox/log.h>
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| 33 |
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| 34 |
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| 35 | /*******************************************************************************
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| 36 | * Internal Functions *
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| 37 | *******************************************************************************/
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| 38 | RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
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| 39 | DECLCALLBACK(int) cpumRCHandleNPAndGP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
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| 40 | RT_C_DECLS_END
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| 41 |
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| 42 |
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| 43 | /**
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| 44 | * Deal with traps occurring during segment loading and IRET when resuming guest
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| 45 | * context execution.
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| 46 | *
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| 47 | * @returns VBox status code.
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| 48 | * @param pVM Pointer to the VM.
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| 49 | * @param pRegFrame The register frame.
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| 50 | * @param uUser User argument. In this case a combination of the
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| 51 | * CPUM_HANDLER_* \#defines.
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| 52 | */
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| 53 | DECLCALLBACK(int) cpumRCHandleNPAndGP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
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| 54 | {
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| 55 | Log(("********************************************************\n"));
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| 56 | Log(("cpumRCHandleNPAndGP: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
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| 57 | Log(("********************************************************\n"));
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| 58 |
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| 59 | /*
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| 60 | * Take action based on what's happened.
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| 61 | */
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| 62 | switch (uUser & CPUM_HANDLER_TYPEMASK)
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| 63 | {
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| 64 | case CPUM_HANDLER_GS:
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| 65 | case CPUM_HANDLER_DS:
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| 66 | case CPUM_HANDLER_ES:
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| 67 | case CPUM_HANDLER_FS:
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| 68 | TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_STALE_SELECTOR);
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| 69 | break;
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| 70 |
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| 71 | case CPUM_HANDLER_IRET:
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| 72 | TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_IRET_TRAP);
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| 73 | break;
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| 74 | }
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| 75 |
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| 76 | AssertMsgFailed(("uUser=%#x eip=%#x\n", uUser, pRegFrame->eip));
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| 77 | return VERR_TRPM_DONT_PANIC;
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| 78 | }
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| 79 |
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| 80 |
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| 81 | /**
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| 82 | * Called by TRPM and CPUM assembly code to make sure the guest state is
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| 83 | * ready for execution.
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| 84 | *
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| 85 | * @param pVM The VM handle.
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| 86 | */
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| 87 | DECLASM(void) CPUMRCAssertPreExecutionSanity(PVM pVM)
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| 88 | {
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| 89 | /*
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| 90 | * Check some important assumptions before resuming guest execution.
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| 91 | */
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| 92 | PVMCPU pVCpu = VMMGetCpu0(pVM);
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| 93 | PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
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| 94 | uint8_t const uRawCpl = CPUMGetGuestCPL(pVCpu);
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| 95 | uint32_t const u32EFlags = CPUMRawGetEFlags(pVCpu);
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| 96 | bool const fPatch = PATMIsPatchGCAddr(pVM, pCtx->eip);
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| 97 | AssertMsg(pCtx->eflags.Bits.u1IF, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
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| 98 | AssertMsg(pCtx->eflags.Bits.u2IOPL < RT_MAX(uRawCpl, 1U),
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| 99 | ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
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| 100 | if (!(u32EFlags & X86_EFL_VM))
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| 101 | {
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| 102 | AssertMsg((u32EFlags & X86_EFL_IF) || fPatch,("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
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| 103 | AssertMsg((pCtx->cs.Sel & X86_SEL_RPL) > 0, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
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| 104 | AssertMsg((pCtx->ss.Sel & X86_SEL_RPL) > 0, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
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| 105 | }
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| 106 | AssertMsg(CPUMIsGuestInRawMode(pVCpu), ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
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| 107 | //Log2(("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
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| 108 | }
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| 109 |
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| 110 |
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| 111 | /**
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| 112 | * Get the current privilege level of the guest.
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| 113 | *
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| 114 | * @returns CPL
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| 115 | * @param pVCpu The current virtual CPU.
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| 116 | * @param pRegFrame Pointer to the register frame.
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| 117 | *
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| 118 | * @todo r=bird: This is very similar to CPUMGetGuestCPL and I cannot quite
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| 119 | * see why this variant of the code is necessary.
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| 120 | */
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| 121 | VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
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| 122 | {
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| 123 | /*
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| 124 | * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
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| 125 | *
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| 126 | * Note! We used to check CS.DPL here, assuming it was always equal to
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| 127 | * CPL even if a conforming segment was loaded. But this truned out to
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| 128 | * only apply to older AMD-V. With VT-x we had an ACP2 regression
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| 129 | * during install after a far call to ring 2 with VT-x. Then on newer
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| 130 | * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
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| 131 | * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
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| 132 | *
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| 133 | * So, forget CS.DPL, always use SS.DPL.
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| 134 | *
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| 135 | * Note! The SS RPL is always equal to the CPL, while the CS RPL
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| 136 | * isn't necessarily equal if the segment is conforming.
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| 137 | * See section 4.11.1 in the AMD manual.
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| 138 | */
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| 139 | uint32_t uCpl;
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| 140 | if (!pRegFrame->eflags.Bits.u1VM)
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| 141 | {
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| 142 | uCpl = (pRegFrame->ss.Sel & X86_SEL_RPL);
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| 143 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
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| 144 | # ifdef VBOX_WITH_RAW_RING1
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| 145 | if (pVCpu->cpum.s.fRawEntered)
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| 146 | {
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| 147 | if ( uCpl == 2
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| 148 | && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) )
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| 149 | uCpl = 1;
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| 150 | else if (uCpl == 1)
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| 151 | uCpl = 0;
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| 152 | }
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| 153 | Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
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| 154 | # else
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| 155 | if (uCpl == 1)
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| 156 | uCpl = 0;
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| 157 | # endif
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| 158 | #endif
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| 159 | }
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| 160 | else
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| 161 | uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
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| 162 |
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| 163 | return uCpl;
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| 164 | }
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| 165 |
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| 166 |
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| 167 | #ifdef VBOX_WITH_RAW_RING1
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| 168 | /**
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| 169 | * Transforms the guest CPU state to raw-ring mode.
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| 170 | *
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| 171 | * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
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| 172 | *
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| 173 | * Used by emInterpretIret() after the new state has been loaded.
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| 174 | *
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| 175 | * @param pVCpu Pointer to the VMCPU.
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| 176 | * @param pCtxCore The context core (for trap usage).
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| 177 | * @see @ref pg_raw
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| 178 | * @remarks Will be probably obsoleted by #5653 (it will leave and reenter raw
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| 179 | * mode instead, I think).
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| 180 | */
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| 181 | VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
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| 182 | {
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| 183 | /*
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| 184 | * Are we in Ring-0?
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| 185 | */
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| 186 | if ( pCtxCore->ss.Sel
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| 187 | && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
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| 188 | && !pCtxCore->eflags.Bits.u1VM)
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| 189 | {
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| 190 | /*
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| 191 | * Set CPL to Ring-1.
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| 192 | */
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| 193 | pCtxCore->ss.Sel |= 1;
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| 194 | if ( pCtxCore->cs.Sel
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| 195 | && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
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| 196 | pCtxCore->cs.Sel |= 1;
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| 197 | }
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| 198 | else
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| 199 | {
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| 200 | if ( EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM))
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| 201 | && !pCtxCore->eflags.Bits.u1VM
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| 202 | && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
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| 203 | {
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| 204 | /* Set CPL to Ring-2. */
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| 205 | pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
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| 206 | if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
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| 207 | pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
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| 208 | }
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| 209 | }
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| 210 |
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| 211 | /*
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| 212 | * Assert sanity.
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| 213 | */
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| 214 | AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
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| 215 | AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
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| 216 | ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
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| 217 |
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| 218 | pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
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| 219 | }
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| 220 | #endif /* VBOX_WITH_RAW_RING1 */
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| 221 |
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