VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/VMMTests.cpp@ 44360

Last change on this file since 44360 was 43864, checked in by vboxsync, 12 years ago

VMM: a few compile fixes for VBOX_WITH_RAW_MODE disabled

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1/* $Id: VMMTests.cpp 43864 2012-11-13 14:16:42Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core, Tests.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18//#define NO_SUPCALLR0VMM
19
20/*******************************************************************************
21* Header Files *
22*******************************************************************************/
23#define LOG_GROUP LOG_GROUP_VMM
24#include <iprt/asm-amd64-x86.h> /* for SUPGetCpuHzFromGIP */
25#include <VBox/vmm/vmm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/cpum.h>
28#include <VBox/dbg.h>
29#include <VBox/vmm/mm.h>
30#include <VBox/vmm/trpm.h>
31#include <VBox/vmm/selm.h>
32#include "VMMInternal.h"
33#include <VBox/vmm/vm.h>
34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <VBox/vmm/hm.h>
37
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/time.h>
41#include <iprt/stream.h>
42#include <iprt/string.h>
43#include <iprt/x86.h>
44
45static void vmmR3TestClearStack(PVMCPU pVCpu)
46{
47 /* We leave the first 64 bytes of the stack alone because of strict
48 ring-0 long jump code uses it. */
49 memset(pVCpu->vmm.s.pbEMTStackR3 + 64, 0xaa, VMM_STACK_SIZE - 64);
50}
51
52
53#ifdef VBOX_WITH_RAW_MODE
54
55/**
56 * Performs a testcase.
57 *
58 * @returns return value from the test.
59 * @param pVM Pointer to the VM.
60 * @param enmTestcase The testcase operation to perform.
61 * @param uVariation The testcase variation id.
62 */
63static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
64{
65 PVMCPU pVCpu = &pVM->aCpus[0];
66
67 RTRCPTR RCPtrEP;
68 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
69 if (RT_FAILURE(rc))
70 return rc;
71
72 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
73 vmmR3TestClearStack(pVCpu);
74 CPUMPushHyper(pVCpu, uVariation);
75 CPUMPushHyper(pVCpu, enmTestcase);
76 CPUMPushHyper(pVCpu, pVM->pVMRC);
77 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
78 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
79 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
80 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
81 if (RT_LIKELY(rc == VINF_SUCCESS))
82 rc = pVCpu->vmm.s.iLastGZRc;
83 return rc;
84}
85
86
87/**
88 * Performs a trap test.
89 *
90 * @returns Return value from the trap test.
91 * @param pVM Pointer to the VM.
92 * @param u8Trap The trap number to test.
93 * @param uVariation The testcase variation.
94 * @param rcExpect The expected result.
95 * @param u32Eax The expected eax value.
96 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
97 * @param pszDesc The test description.
98 */
99static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
100{
101 PVMCPU pVCpu = &pVM->aCpus[0];
102
103 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
104
105 RTRCPTR RCPtrEP;
106 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
107 if (RT_FAILURE(rc))
108 return rc;
109
110 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
111 vmmR3TestClearStack(pVCpu);
112 CPUMPushHyper(pVCpu, uVariation);
113 CPUMPushHyper(pVCpu, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
114 CPUMPushHyper(pVCpu, pVM->pVMRC);
115 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
116 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
117 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
118 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
119 if (RT_LIKELY(rc == VINF_SUCCESS))
120 rc = pVCpu->vmm.s.iLastGZRc;
121 bool fDump = false;
122 if (rc != rcExpect)
123 {
124 RTPrintf("VMM: FAILURE - rc=%Rrc expected %Rrc\n", rc, rcExpect);
125 if (rc != VERR_NOT_IMPLEMENTED)
126 fDump = true;
127 }
128 else if ( rcExpect != VINF_SUCCESS
129 && u8Trap != 8 /* double fault doesn't dare set TrapNo. */
130 && u8Trap != 3 /* guest only, we're not in guest. */
131 && u8Trap != 1 /* guest only, we're not in guest. */
132 && u8Trap != TRPMGetTrapNo(pVCpu))
133 {
134 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVCpu), u8Trap);
135 fDump = true;
136 }
137 else if (pszFaultEIP)
138 {
139 RTRCPTR RCPtrFault;
140 int rc2 = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &RCPtrFault);
141 if (RT_FAILURE(rc2))
142 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Rrc!\n", pszFaultEIP, rc);
143 else if (RCPtrFault != CPUMGetHyperEIP(pVCpu))
144 {
145 RTPrintf("VMM: FAILURE - EIP=%08RX32 expected %RRv (%s)\n", CPUMGetHyperEIP(pVCpu), RCPtrFault, pszFaultEIP);
146 fDump = true;
147 }
148 }
149 else if (rcExpect != VINF_SUCCESS)
150 {
151 if (CPUMGetHyperSS(pVCpu) == SELMGetHyperDS(pVM))
152 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVCpu), SELMGetHyperDS(pVM));
153 if (CPUMGetHyperES(pVCpu) == SELMGetHyperDS(pVM))
154 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVCpu), SELMGetHyperDS(pVM));
155 if (CPUMGetHyperDS(pVCpu) == SELMGetHyperDS(pVM))
156 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVCpu), SELMGetHyperDS(pVM));
157 if (CPUMGetHyperFS(pVCpu) == SELMGetHyperDS(pVM))
158 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVCpu), SELMGetHyperDS(pVM));
159 if (CPUMGetHyperGS(pVCpu) == SELMGetHyperDS(pVM))
160 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVCpu), SELMGetHyperDS(pVM));
161 if (CPUMGetHyperEDI(pVCpu) == 0x01234567)
162 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVCpu), 0x01234567);
163 if (CPUMGetHyperESI(pVCpu) == 0x42000042)
164 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVCpu), 0x42000042);
165 if (CPUMGetHyperEBP(pVCpu) == 0xffeeddcc)
166 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVCpu), 0xffeeddcc);
167 if (CPUMGetHyperEBX(pVCpu) == 0x89abcdef)
168 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVCpu), 0x89abcdef);
169 if (CPUMGetHyperECX(pVCpu) == 0xffffaaaa)
170 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVCpu), 0xffffaaaa);
171 if (CPUMGetHyperEDX(pVCpu) == 0x77778888)
172 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVCpu), 0x77778888);
173 if (CPUMGetHyperEAX(pVCpu) == u32Eax)
174 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVCpu), u32Eax);
175 }
176 if (fDump)
177 VMMR3FatalDump(pVM, pVCpu, rc);
178 return rc;
179}
180
181#endif /* VBOX_WITH_RAW_MODE */
182
183
184/* execute the switch. */
185VMMR3DECL(int) VMMDoTest(PVM pVM)
186{
187 int rc = VINF_SUCCESS;
188
189#ifdef VBOX_WITH_RAW_MODE
190 PVMCPU pVCpu = &pVM->aCpus[0];
191
192# ifdef NO_SUPCALLR0VMM
193 RTPrintf("NO_SUPCALLR0VMM\n");
194 return rc;
195# endif
196
197 /*
198 * Setup stack for calling VMMGCEntry().
199 */
200 RTRCPTR RCPtrEP;
201 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
202 if (RT_SUCCESS(rc))
203 {
204 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
205
206 /*
207 * Test various crashes which we must be able to recover from.
208 */
209 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
210 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
211
212# if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
213 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
214 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
215 bool f;
216 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
217# if !defined(DEBUG_bird)
218 if (RT_SUCCESS(rc) && f)
219# endif
220 {
221 /* see triple fault warnings in SELM and VMMGC.cpp. */
222 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
223 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
224 }
225# endif
226
227 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
228 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
229 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
230
231 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
232 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
233 vmmR3DoTrapTest(pVM, 0xe, 2, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler");
234 /* This test is no longer relevant as fs and gs are loaded with NULL
235 selectors and we will always return to HC if a #GP occurs while
236 returning to guest code.
237 vmmR3DoTrapTest(pVM, 0xe, 4, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler and bad fs");
238 */
239
240 /*
241 * Set a debug register and perform a context switch.
242 */
243 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
244 if (rc != VINF_SUCCESS)
245 {
246 RTPrintf("VMM: Nop test failed, rc=%Rrc not VINF_SUCCESS\n", rc);
247 return rc;
248 }
249
250 /* a harmless breakpoint */
251 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
252 DBGFADDRESS Addr;
253 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
254 RTUINT iBp0;
255 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
256 AssertReleaseRC(rc);
257 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
258 if (rc != VINF_SUCCESS)
259 {
260 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Rrc!\n", rc);
261 return rc;
262 }
263
264 /* a bad one at VMMGCEntry */
265 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
266 DBGFR3AddrFromFlat(pVM, &Addr, RCPtrEP);
267 RTUINT iBp1;
268 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
269 AssertReleaseRC(rc);
270 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
271 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
272 {
273 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
274 return rc;
275 }
276
277 /* resume the breakpoint */
278 RTPrintf("VMM: resuming hyper after breakpoint\n");
279 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
280 rc = VMMR3ResumeHyper(pVM, pVCpu);
281 if (rc != VINF_SUCCESS)
282 {
283 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Rrc = KNOWN BUG\n", rc); /** @todo fix VMMR3ResumeHyper */
284 return rc;
285 }
286
287 /* engage the breakpoint again and try single stepping. */
288 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
289 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
290 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
291 {
292 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
293 return rc;
294 }
295
296 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVCpu);
297 RTPrintf("%RGr=>", OldPc);
298 unsigned i;
299 for (i = 0; i < 8; i++)
300 {
301 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
302 rc = VMMR3ResumeHyper(pVM, pVCpu);
303 if (rc != VINF_EM_DBG_HYPER_STEPPED)
304 {
305 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Rrc\n", rc);
306 return rc;
307 }
308 RTGCUINTREG Pc = CPUMGetHyperEIP(pVCpu);
309 RTPrintf("%RGr=>", Pc);
310 if (Pc == OldPc)
311 {
312 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
313 return VERR_GENERAL_FAILURE;
314 }
315 OldPc = Pc;
316 }
317 RTPrintf("ok\n");
318
319 /* done, clear it */
320 if ( RT_FAILURE(DBGFR3BpClear(pVM, iBp0))
321 || RT_FAILURE(DBGFR3BpClear(pVM, iBp1)))
322 {
323 RTPrintf("VMM: Failed to clear breakpoints!\n");
324 return VERR_GENERAL_FAILURE;
325 }
326 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
327 if (rc != VINF_SUCCESS)
328 {
329 RTPrintf("VMM: NOP failed, rc=%Rrc\n", rc);
330 return rc;
331 }
332
333 /*
334 * Interrupt masking.
335 */
336 RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
337 for (i = 0; i < 10000; i++)
338 {
339 uint64_t StartTick = ASMReadTSC();
340 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
341 if (rc != VINF_SUCCESS)
342 {
343 RTPrintf("VMM: Interrupt masking failed: rc=%Rrc\n", rc);
344 return rc;
345 }
346 uint64_t Ticks = ASMReadTSC() - StartTick;
347 if (Ticks < (SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000))
348 RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000);
349 }
350
351 /*
352 * Interrupt forwarding.
353 */
354 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
355 CPUMPushHyper(pVCpu, 0);
356 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
357 CPUMPushHyper(pVCpu, pVM->pVMRC);
358 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
359 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
360 Log(("trampoline=%x\n", pVM->vmm.s.pfnCallTrampolineRC));
361
362 /*
363 * Switch and do da thing.
364 */
365 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
366 i = 0;
367 uint64_t tsBegin = RTTimeNanoTS();
368 uint64_t TickStart = ASMReadTSC();
369 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
370 do
371 {
372 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
373 if (RT_LIKELY(rc == VINF_SUCCESS))
374 rc = pVCpu->vmm.s.iLastGZRc;
375 if (RT_FAILURE(rc))
376 {
377 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
378 VMMR3FatalDump(pVM, pVCpu, rc);
379 return rc;
380 }
381 i++;
382 if (!(i % 32))
383 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
384 i, CPUMGetHyperESI(pVCpu), CPUMGetHyperEDI(pVCpu), CPUMGetHyperEBX(pVCpu)));
385 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
386 uint64_t TickEnd = ASMReadTSC();
387 uint64_t tsEnd = RTTimeNanoTS();
388
389 uint64_t Elapsed = tsEnd - tsBegin;
390 uint64_t PerIteration = Elapsed / (uint64_t)i;
391 uint64_t cTicksElapsed = TickEnd - TickStart;
392 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
393
394 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
395 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
396 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
397 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
398
399 /*
400 * These forced actions are not necessary for the test and trigger breakpoints too.
401 */
402 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
403 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
404
405 /*
406 * Profile switching.
407 */
408 RTPrintf("VMM: profiling switcher...\n");
409 Log(("VMM: profiling switcher...\n"));
410 uint64_t TickMin = ~0;
411 tsBegin = RTTimeNanoTS();
412 TickStart = ASMReadTSC();
413 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
414 for (i = 0; i < 1000000; i++)
415 {
416 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
417 CPUMPushHyper(pVCpu, 0);
418 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_NOP);
419 CPUMPushHyper(pVCpu, pVM->pVMRC);
420 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
421 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
422
423 uint64_t TickThisStart = ASMReadTSC();
424 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
425 if (RT_LIKELY(rc == VINF_SUCCESS))
426 rc = pVCpu->vmm.s.iLastGZRc;
427 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
428 if (RT_FAILURE(rc))
429 {
430 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
431 VMMR3FatalDump(pVM, pVCpu, rc);
432 return rc;
433 }
434 if (TickThisElapsed < TickMin)
435 TickMin = TickThisElapsed;
436 }
437 TickEnd = ASMReadTSC();
438 tsEnd = RTTimeNanoTS();
439
440 Elapsed = tsEnd - tsBegin;
441 PerIteration = Elapsed / (uint64_t)i;
442 cTicksElapsed = TickEnd - TickStart;
443 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
444
445 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
446 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
447 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
448 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
449
450 rc = VINF_SUCCESS;
451 }
452 else
453 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
454#endif
455 return rc;
456}
457
458#define SYNC_SEL(pHyperCtx, reg) \
459 if (pHyperCtx->reg.Sel) \
460 { \
461 DBGFSELINFO selInfo; \
462 int rc2 = SELMR3GetShadowSelectorInfo(pVM, pHyperCtx->reg.Sel, &selInfo); \
463 AssertRC(rc2); \
464 \
465 pHyperCtx->reg.u64Base = selInfo.GCPtrBase; \
466 pHyperCtx->reg.u32Limit = selInfo.cbLimit; \
467 pHyperCtx->reg.Attr.n.u1Present = selInfo.u.Raw.Gen.u1Present; \
468 pHyperCtx->reg.Attr.n.u1DefBig = selInfo.u.Raw.Gen.u1DefBig; \
469 pHyperCtx->reg.Attr.n.u1Granularity = selInfo.u.Raw.Gen.u1Granularity; \
470 pHyperCtx->reg.Attr.n.u4Type = selInfo.u.Raw.Gen.u4Type; \
471 pHyperCtx->reg.Attr.n.u2Dpl = selInfo.u.Raw.Gen.u2Dpl; \
472 pHyperCtx->reg.Attr.n.u1DescType = selInfo.u.Raw.Gen.u1DescType; \
473 pHyperCtx->reg.Attr.n.u1Long = selInfo.u.Raw.Gen.u1Long; \
474 }
475
476/* execute the switch. */
477VMMR3DECL(int) VMMDoHmTest(PVM pVM)
478{
479 uint32_t i;
480 int rc;
481 PCPUMCTX pHyperCtx, pGuestCtx;
482 RTGCPHYS CR3Phys = 0x0; /* fake address */
483 PVMCPU pVCpu = &pVM->aCpus[0];
484
485 if (!HMR3IsAllowed(pVM))
486 {
487 RTPrintf("VMM: Hardware accelerated test not available!\n");
488 return VERR_ACCESS_DENIED;
489 }
490
491 /*
492 * These forced actions are not necessary for the test and trigger breakpoints too.
493 */
494 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
495 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
496
497 /* Enable mapping of the hypervisor into the shadow page table. */
498 uint32_t cb;
499 rc = PGMR3MappingsSize(pVM, &cb);
500 AssertRCReturn(rc, rc);
501
502 /* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
503 rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
504 AssertRCReturn(rc, rc);
505
506 pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
507
508 pHyperCtx->cr0 = X86_CR0_PE | X86_CR0_WP | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
509 pHyperCtx->cr4 = X86_CR4_PGE | X86_CR4_OSFSXR | X86_CR4_OSXMMEEXCPT;
510 PGMChangeMode(pVCpu, pHyperCtx->cr0, pHyperCtx->cr4, pHyperCtx->msrEFER);
511 PGMSyncCR3(pVCpu, pHyperCtx->cr0, CR3Phys, pHyperCtx->cr4, true);
512
513 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
514 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
515 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
516 VM_FF_CLEAR(pVM, VM_FF_REQUEST);
517
518 /*
519 * Setup stack for calling VMMGCEntry().
520 */
521 RTRCPTR RCPtrEP;
522 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
523 if (RT_SUCCESS(rc))
524 {
525 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
526
527 pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
528
529 /* Fill in hidden selector registers for the hypervisor state. */
530 SYNC_SEL(pHyperCtx, cs);
531 SYNC_SEL(pHyperCtx, ds);
532 SYNC_SEL(pHyperCtx, es);
533 SYNC_SEL(pHyperCtx, fs);
534 SYNC_SEL(pHyperCtx, gs);
535 SYNC_SEL(pHyperCtx, ss);
536 SYNC_SEL(pHyperCtx, tr);
537
538 /*
539 * Profile switching.
540 */
541 RTPrintf("VMM: profiling switcher...\n");
542 Log(("VMM: profiling switcher...\n"));
543 uint64_t TickMin = ~0;
544 uint64_t tsBegin = RTTimeNanoTS();
545 uint64_t TickStart = ASMReadTSC();
546 for (i = 0; i < 1000000; i++)
547 {
548 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
549 CPUMPushHyper(pVCpu, 0);
550 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HM_NOP);
551 CPUMPushHyper(pVCpu, pVM->pVMRC);
552 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
553 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
554
555 pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
556 pGuestCtx = CPUMQueryGuestCtxPtr(pVCpu);
557
558 /* Copy the hypervisor context to make sure we have a valid guest context. */
559 *pGuestCtx = *pHyperCtx;
560 pGuestCtx->cr3 = CR3Phys;
561
562 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
563 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
564 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
565
566 uint64_t TickThisStart = ASMReadTSC();
567 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HM_RUN, 0);
568 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
569 if (RT_FAILURE(rc))
570 {
571 Log(("VMM: R0 returned fatal %Rrc in iteration %d\n", rc, i));
572 VMMR3FatalDump(pVM, pVCpu, rc);
573 return rc;
574 }
575 if (TickThisElapsed < TickMin)
576 TickMin = TickThisElapsed;
577 }
578 uint64_t TickEnd = ASMReadTSC();
579 uint64_t tsEnd = RTTimeNanoTS();
580
581 uint64_t Elapsed = tsEnd - tsBegin;
582 uint64_t PerIteration = Elapsed / (uint64_t)i;
583 uint64_t cTicksElapsed = TickEnd - TickStart;
584 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
585
586 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
587 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
588 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
589 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
590
591 rc = VINF_SUCCESS;
592 }
593 else
594 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
595
596 return rc;
597}
598
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