1 | /* $Id: VMMSwitcher.cpp 70949 2018-02-10 15:41:14Z vboxsync $ */
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2 | /** @file
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3 | * VMM - The Virtual Machine Monitor, World Switcher(s).
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2017 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*********************************************************************************************************************************
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20 | * Header Files *
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21 | *********************************************************************************************************************************/
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22 | #define LOG_GROUP LOG_GROUP_VMM
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23 | #include <VBox/vmm/vmm.h>
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24 | #include <VBox/vmm/pgm.h>
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25 | #include <VBox/vmm/hm.h>
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26 | #include <VBox/vmm/selm.h>
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27 | #include <VBox/vmm/mm.h>
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28 | #include <VBox/sup.h>
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29 | #include "VMMInternal.h"
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30 | #include "VMMSwitcher.h"
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31 | #include <VBox/vmm/vm.h>
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32 | #include <VBox/dis.h>
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33 |
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34 | #include <VBox/err.h>
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35 | #include <VBox/param.h>
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36 | #include <iprt/assert.h>
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37 | #include <iprt/alloc.h>
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38 | #include <iprt/asm.h>
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39 | #include <iprt/asm-amd64-x86.h>
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40 | #include <iprt/string.h>
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41 | #include <iprt/ctype.h>
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42 |
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43 |
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44 | /*********************************************************************************************************************************
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45 | * Global Variables *
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46 | *********************************************************************************************************************************/
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47 | #if defined(VBOX_WITH_RAW_MODE) || HC_ARCH_BITS != 64
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48 |
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49 | /** Array of switcher definitions.
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50 | * The type and index shall match!
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51 | */
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52 | static PVMMSWITCHERDEF g_apRawModeSwitchers[VMMSWITCHER_MAX] =
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53 | {
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54 | NULL, /* invalid entry */
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55 | # ifdef VBOX_WITH_RAW_MODE
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56 | # ifndef RT_ARCH_AMD64
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57 | &vmmR3Switcher32BitTo32Bit_Def,
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58 | &vmmR3Switcher32BitToPAE_Def,
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59 | NULL, //&vmmR3Switcher32BitToAMD64_Def,
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60 | &vmmR3SwitcherPAETo32Bit_Def,
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61 | &vmmR3SwitcherPAEToPAE_Def,
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62 | NULL, //&vmmR3SwitcherPAEToAMD64_Def,
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63 | NULL, //&vmmR3SwitcherPAETo32Bit_Def,
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64 | NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
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65 | NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
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66 | # else /* RT_ARCH_AMD64 */
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67 | NULL, //&vmmR3Switcher32BitTo32Bit_Def,
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68 | NULL, //&vmmR3Switcher32BitToPAE_Def,
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69 | NULL, //&vmmR3Switcher32BitToAMD64_Def,
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70 | NULL, //&vmmR3SwitcherPAETo32Bit_Def,
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71 | NULL, //&vmmR3SwitcherPAEToPAE_Def,
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72 | NULL, //&vmmR3SwitcherPAEToAMD64_Def,
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73 | &vmmR3SwitcherAMD64To32Bit_Def,
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74 | &vmmR3SwitcherAMD64ToPAE_Def,
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75 | NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
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76 | # endif /* RT_ARCH_AMD64 */
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77 | # else /* !VBOX_WITH_RAW_MODE */
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78 | NULL,
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79 | NULL,
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80 | NULL,
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81 | NULL,
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82 | NULL,
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83 | NULL,
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84 | NULL,
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85 | NULL,
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86 | NULL,
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87 | # endif /* !VBOX_WITH_RAW_MODE */
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88 | # ifndef RT_ARCH_AMD64
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89 | &vmmR3SwitcherX86Stub_Def,
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90 | NULL,
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91 | # else
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92 | NULL,
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93 | &vmmR3SwitcherAMD64Stub_Def,
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94 | # endif
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95 | };
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96 |
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97 | /** Array of switcher definitions.
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98 | * The type and index shall match!
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99 | */
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100 | static PVMMSWITCHERDEF g_apHmSwitchers[VMMSWITCHER_MAX] =
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101 | {
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102 | NULL, /* invalid entry */
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103 | # if HC_ARCH_BITS == 32
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104 | NULL, //&vmmR3Switcher32BitTo32Bit_Def,
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105 | NULL, //&vmmR3Switcher32BitToPAE_Def,
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106 | &vmmR3Switcher32BitToAMD64_Def,
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107 | NULL, //&vmmR3SwitcherPAETo32Bit_Def,
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108 | NULL, //&vmmR3SwitcherPAEToPAE_Def,
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109 | &vmmR3SwitcherPAEToAMD64_Def,
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110 | NULL, //&vmmR3SwitcherPAETo32Bit_Def,
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111 | NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
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112 | NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
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113 | # else /* !VBOX_WITH_RAW_MODE */
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114 | NULL,
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115 | NULL,
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116 | NULL,
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117 | NULL,
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118 | NULL,
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119 | NULL,
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120 | NULL,
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121 | NULL,
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122 | NULL,
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123 | # endif /* !VBOX_WITH_RAW_MODE */
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124 | # ifndef RT_ARCH_AMD64
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125 | &vmmR3SwitcherX86Stub_Def,
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126 | NULL,
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127 | # else
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128 | NULL,
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129 | &vmmR3SwitcherAMD64Stub_Def,
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130 | # endif
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131 | };
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132 |
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133 | #endif /* VBOX_WITH_RAW_MODE || HC_ARCH_BITS != 64 */
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134 |
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135 |
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136 | # ifdef VBOX_WITH_64ON32_IDT
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137 | /**
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138 | * Initializes the 64-bit IDT for 64-bit guest on 32-bit host switchers.
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139 | *
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140 | * This is only used as a debugging aid when we cannot find out why something
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141 | * goes haywire in the intermediate context.
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142 | *
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143 | * @param pVM The cross context VM structure.
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144 | * @param pSwitcher The switcher descriptor.
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145 | * @param pbDst Where the switcher code was just copied.
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146 | * @param HCPhysDst The host physical address corresponding to @a pbDst.
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147 | */
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148 | static void vmmR3Switcher32On64IdtInit(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
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149 | {
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150 | AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode);
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151 | AssertRelease(pSwitcher->cbCode < _64K);
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152 | RTSEL uCs64 = SELMGetHyperCS64(pVM);
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153 |
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154 | PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
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155 | for (uint32_t i = 0 ; i < 256; i++)
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156 | {
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157 | AssertRelease(((uint64_t *)&paIdt[i])[0] < pSwitcher->cbCode);
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158 | AssertRelease(((uint64_t *)&paIdt[i])[1] == 0);
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159 | uint64_t uHandler = HCPhysDst + paIdt[i].u16OffsetLow;
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160 | paIdt[i].u16OffsetLow = (uint16_t)uHandler;
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161 | paIdt[i].u16Sel = uCs64;
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162 | paIdt[i].u3IST = 0;
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163 | paIdt[i].u5Reserved = 0;
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164 | paIdt[i].u4Type = AMD64_SEL_TYPE_SYS_INT_GATE;
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165 | paIdt[i].u1DescType = 0 /* system */;
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166 | paIdt[i].u2Dpl = 3;
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167 | paIdt[i].u1Present = 1;
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168 | paIdt[i].u16OffsetHigh = (uint16_t)(uHandler >> 16);
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169 | paIdt[i].u32Reserved = (uint32_t)(uHandler >> 32);
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170 | }
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171 |
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172 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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173 | {
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174 | uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
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175 | CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
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176 | }
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177 | }
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178 |
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179 |
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180 | /**
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181 | * Relocates the 64-bit IDT for 64-bit guest on 32-bit host switchers.
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182 | *
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183 | * @param pVM The cross context VM structure.
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184 | * @param pSwitcher The switcher descriptor.
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185 | * @param pbDst Where the switcher code was just copied.
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186 | * @param HCPhysDst The host physical address corresponding to @a pbDst.
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187 | */
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188 | static void vmmR3Switcher32On64IdtRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
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189 | {
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190 | AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode && pSwitcher->cbCode < _64K);
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191 |
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192 | /* The intermediate context doesn't move, but the CS may. */
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193 | RTSEL uCs64 = SELMGetHyperCS64(pVM);
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194 | PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
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195 | for (uint32_t i = 0 ; i < 256; i++)
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196 | paIdt[i].u16Sel = uCs64;
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197 |
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198 | /* Just in case... */
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199 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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200 | {
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201 | uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
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202 | CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
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203 | }
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204 | }
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205 | # endif /* VBOX_WITH_64ON32_IDT */
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206 |
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207 |
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208 | /**
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209 | * VMMR3Init worker that initiates the switcher code (aka core code).
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210 | *
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211 | * This is core per VM code which might need fixups and/or for ease of use are
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212 | * put on linear contiguous backing.
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213 | *
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214 | * @returns VBox status code.
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215 | * @param pVM The cross context VM structure.
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216 | */
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217 | int vmmR3SwitcherInit(PVM pVM)
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218 | {
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219 | #if !defined(VBOX_WITH_RAW_MODE) && (HC_ARCH_BITS == 64)
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220 | RT_NOREF(pVM);
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221 | return VINF_SUCCESS;
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222 | #else
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223 |
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224 | /*
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225 | * Calc the size.
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226 | */
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227 | const PVMMSWITCHERDEF *papSwitchers = VM_IS_RAW_MODE_ENABLED(pVM) ? g_apRawModeSwitchers : g_apHmSwitchers;
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228 | unsigned cbCoreCode = 0;
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229 | for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
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230 | {
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231 | pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
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232 | PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
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233 | if (pSwitcher)
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234 | {
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235 | AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
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236 | cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
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237 | }
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238 | }
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239 |
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240 | /*
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241 | * Allocate contiguous pages for switchers and deal with
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242 | * conflicts in the intermediate mapping of the code.
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243 | */
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244 | pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
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245 | pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
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246 | int rc = VERR_NO_MEMORY;
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247 | if (pVM->vmm.s.pvCoreCodeR3)
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248 | {
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249 | rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
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250 | if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
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251 | {
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252 | /* try more allocations - Solaris, Linux. */
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253 | const unsigned cTries = 8234;
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254 | struct VMMInitBadTry
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255 | {
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256 | RTR0PTR pvR0;
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257 | void *pvR3;
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258 | RTHCPHYS HCPhys;
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259 | RTUINT cb;
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260 | } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
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261 | AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
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262 | unsigned i = 0;
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263 | do
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264 | {
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265 | paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
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266 | paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
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267 | paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
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268 | i++;
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269 | pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
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270 | pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
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271 | pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
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272 | if (!pVM->vmm.s.pvCoreCodeR3)
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273 | break;
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274 | rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
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275 | } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
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276 | && i < cTries - 1);
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277 |
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278 | /* cleanup */
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279 | if (RT_FAILURE(rc))
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280 | {
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281 | paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
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282 | paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
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283 | paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
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284 | paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
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285 | i++;
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286 | LogRel(("VMM: Failed to allocated and map core code: rc=%Rrc\n", rc));
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287 | }
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288 | while (i-- > 0)
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289 | {
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290 | LogRel(("VMM: Core code alloc attempt #%d: pvR3=%p pvR0=%RKv HCPhys=%RHp\n",
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291 | i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
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292 | SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
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293 | }
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294 | RTMemTmpFree(paBadTries);
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295 | }
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296 | }
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297 | if (RT_SUCCESS(rc))
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298 | {
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299 | /*
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300 | * Copy the code.
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301 | */
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302 | for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
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303 | {
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304 | PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
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305 | if (pSwitcher)
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306 | {
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307 | uint8_t *pbDst = (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher];
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308 | memcpy(pbDst, pSwitcher->pvCode, pSwitcher->cbCode);
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309 | # ifdef VBOX_WITH_64ON32_IDT
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310 | if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
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311 | || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
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312 | vmmR3Switcher32On64IdtInit(pVM, pSwitcher, pbDst,
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313 | pVM->vmm.s.HCPhysCoreCode + pVM->vmm.s.aoffSwitchers[iSwitcher]);
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314 | # endif
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315 | }
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316 | }
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317 |
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318 | /*
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319 | * Map the code into the GC address space.
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320 | */
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321 | RTGCPTR GCPtr;
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322 | rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
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323 | cbCoreCode, "Core Code", &GCPtr);
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324 | if (RT_SUCCESS(rc))
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325 | {
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326 | pVM->vmm.s.pvCoreCodeRC = GCPtr;
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327 | MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
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328 | LogRel(("VMM: CoreCode: R3=%RHv R0=%RKv RC=%RRv Phys=%RHp cb=%#x\n",
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329 | pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
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330 |
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331 | /*
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332 | * Finally, PGM probably has selected a switcher already but we need
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333 | * to get the routine addresses, so we'll reselect it.
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334 | * This may legally fail so, we're ignoring the rc.
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335 | * Note! See HMIsEnabled hack in selector function.
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336 | */
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337 | VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
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338 | return rc;
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339 | }
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340 |
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341 | /* shit */
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342 | AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
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343 | SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
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344 | }
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345 | else
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346 | VMSetError(pVM, rc, RT_SRC_POS,
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347 | N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
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348 | cbCoreCode);
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349 |
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350 | pVM->vmm.s.pvCoreCodeR3 = NULL;
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351 | pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
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352 | pVM->vmm.s.pvCoreCodeRC = 0;
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353 | return rc;
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354 | #endif
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355 | }
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356 |
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357 | /**
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358 | * Relocate the switchers, called by VMMR#Relocate.
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359 | *
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360 | * @param pVM The cross context VM structure.
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361 | * @param offDelta The relocation delta.
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362 | */
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363 | void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
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364 | {
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365 | #if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64)
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366 | /*
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367 | * Relocate all the switchers.
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368 | */
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369 | const PVMMSWITCHERDEF *papSwitchers = VM_IS_RAW_MODE_ENABLED(pVM) ? g_apRawModeSwitchers : g_apHmSwitchers;
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370 | for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
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371 | {
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372 | PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
|
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373 | if (pSwitcher && pSwitcher->pfnRelocate)
|
---|
374 | {
|
---|
375 | unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
|
---|
376 | pSwitcher->pfnRelocate(pVM,
|
---|
377 | pSwitcher,
|
---|
378 | pVM->vmm.s.pvCoreCodeR0 + off,
|
---|
379 | (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
|
---|
380 | pVM->vmm.s.pvCoreCodeRC + off,
|
---|
381 | pVM->vmm.s.HCPhysCoreCode + off);
|
---|
382 | # ifdef VBOX_WITH_64ON32_IDT
|
---|
383 | if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
|
---|
384 | || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
|
---|
385 | vmmR3Switcher32On64IdtRelocate(pVM, pSwitcher,
|
---|
386 | (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
|
---|
387 | pVM->vmm.s.HCPhysCoreCode + off);
|
---|
388 | # endif
|
---|
389 | }
|
---|
390 | }
|
---|
391 |
|
---|
392 | /*
|
---|
393 | * Recalc the RC address for the current switcher.
|
---|
394 | */
|
---|
395 | PVMMSWITCHERDEF pSwitcher = papSwitchers[pVM->vmm.s.enmSwitcher];
|
---|
396 | if (pSwitcher)
|
---|
397 | {
|
---|
398 | RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
|
---|
399 | pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
|
---|
400 | pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
|
---|
401 | pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
|
---|
402 | pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
|
---|
403 | }
|
---|
404 | else
|
---|
405 | AssertRelease(!VM_IS_RAW_MODE_ENABLED(pVM));
|
---|
406 |
|
---|
407 | #else
|
---|
408 | NOREF(pVM);
|
---|
409 | #endif
|
---|
410 | NOREF(offDelta);
|
---|
411 | }
|
---|
412 |
|
---|
413 |
|
---|
414 | #if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64)
|
---|
415 |
|
---|
416 | /**
|
---|
417 | * Generic switcher code relocator.
|
---|
418 | *
|
---|
419 | * @param pVM The cross context VM structure.
|
---|
420 | * @param pSwitcher The switcher definition.
|
---|
421 | * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
|
---|
422 | * @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
|
---|
423 | * @param GCPtrCode The guest context address corresponding to pu8Code.
|
---|
424 | * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
|
---|
425 | * @param SelCS The hypervisor CS selector.
|
---|
426 | * @param SelDS The hypervisor DS selector.
|
---|
427 | * @param SelTSS The hypervisor TSS selector.
|
---|
428 | * @param GCPtrGDT The GC address of the hypervisor GDT.
|
---|
429 | * @param SelCS64 The 64-bit mode hypervisor CS selector.
|
---|
430 | */
|
---|
431 | static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher,
|
---|
432 | RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
|
---|
433 | RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
|
---|
434 | {
|
---|
435 | union
|
---|
436 | {
|
---|
437 | const uint8_t *pu8;
|
---|
438 | const uint16_t *pu16;
|
---|
439 | const uint32_t *pu32;
|
---|
440 | const uint64_t *pu64;
|
---|
441 | const void *pv;
|
---|
442 | uintptr_t u;
|
---|
443 | } u;
|
---|
444 | u.pv = pSwitcher->pvFixups;
|
---|
445 |
|
---|
446 | /*
|
---|
447 | * Process fixups.
|
---|
448 | */
|
---|
449 | uint8_t u8;
|
---|
450 | while ((u8 = *u.pu8++) != FIX_THE_END)
|
---|
451 | {
|
---|
452 | /*
|
---|
453 | * Get the source (where to write the fixup).
|
---|
454 | */
|
---|
455 | uint32_t offSrc = *u.pu32++;
|
---|
456 | Assert(offSrc < pSwitcher->cbCode);
|
---|
457 | union
|
---|
458 | {
|
---|
459 | uint8_t *pu8;
|
---|
460 | uint16_t *pu16;
|
---|
461 | uint32_t *pu32;
|
---|
462 | uint64_t *pu64;
|
---|
463 | uintptr_t u;
|
---|
464 | } uSrc;
|
---|
465 | uSrc.pu8 = pu8CodeR3 + offSrc;
|
---|
466 |
|
---|
467 | /* The fixup target and method depends on the type. */
|
---|
468 | switch (u8)
|
---|
469 | {
|
---|
470 | /*
|
---|
471 | * 32-bit relative, source in HC and target in GC.
|
---|
472 | */
|
---|
473 | case FIX_HC_2_GC_NEAR_REL:
|
---|
474 | {
|
---|
475 | Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
|
---|
476 | uint32_t offTrg = *u.pu32++;
|
---|
477 | Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
|
---|
478 | *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
|
---|
479 | break;
|
---|
480 | }
|
---|
481 |
|
---|
482 | /*
|
---|
483 | * 32-bit relative, source in HC and target in ID.
|
---|
484 | */
|
---|
485 | case FIX_HC_2_ID_NEAR_REL:
|
---|
486 | {
|
---|
487 | Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
|
---|
488 | uint32_t offTrg = *u.pu32++;
|
---|
489 | Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
|
---|
490 | *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
|
---|
491 | break;
|
---|
492 | }
|
---|
493 |
|
---|
494 | /*
|
---|
495 | * 32-bit relative, source in GC and target in HC.
|
---|
496 | */
|
---|
497 | case FIX_GC_2_HC_NEAR_REL:
|
---|
498 | {
|
---|
499 | Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
|
---|
500 | uint32_t offTrg = *u.pu32++;
|
---|
501 | Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
|
---|
502 | *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
|
---|
503 | break;
|
---|
504 | }
|
---|
505 |
|
---|
506 | /*
|
---|
507 | * 32-bit relative, source in GC and target in ID.
|
---|
508 | */
|
---|
509 | case FIX_GC_2_ID_NEAR_REL:
|
---|
510 | {
|
---|
511 | AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
|
---|
512 | uint32_t offTrg = *u.pu32++;
|
---|
513 | Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
|
---|
514 | *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
|
---|
515 | break;
|
---|
516 | }
|
---|
517 |
|
---|
518 | /*
|
---|
519 | * 32-bit relative, source in ID and target in HC.
|
---|
520 | */
|
---|
521 | case FIX_ID_2_HC_NEAR_REL:
|
---|
522 | {
|
---|
523 | Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
|
---|
524 | uint32_t offTrg = *u.pu32++;
|
---|
525 | Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
|
---|
526 | *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
|
---|
527 | break;
|
---|
528 | }
|
---|
529 |
|
---|
530 | /*
|
---|
531 | * 32-bit relative, source in ID and target in HC.
|
---|
532 | */
|
---|
533 | case FIX_ID_2_GC_NEAR_REL:
|
---|
534 | {
|
---|
535 | Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
|
---|
536 | uint32_t offTrg = *u.pu32++;
|
---|
537 | Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
|
---|
538 | *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
|
---|
539 | break;
|
---|
540 | }
|
---|
541 |
|
---|
542 | /*
|
---|
543 | * 16:32 far jump, target in GC.
|
---|
544 | */
|
---|
545 | case FIX_GC_FAR32:
|
---|
546 | {
|
---|
547 | uint32_t offTrg = *u.pu32++;
|
---|
548 | Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
|
---|
549 | *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
|
---|
550 | *uSrc.pu16++ = SelCS;
|
---|
551 | break;
|
---|
552 | }
|
---|
553 |
|
---|
554 | /*
|
---|
555 | * Make 32-bit GC pointer given CPUM offset.
|
---|
556 | */
|
---|
557 | case FIX_GC_CPUM_OFF:
|
---|
558 | {
|
---|
559 | uint32_t offCPUM = *u.pu32++;
|
---|
560 | Assert(offCPUM < sizeof(pVM->cpum));
|
---|
561 | *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
|
---|
562 | break;
|
---|
563 | }
|
---|
564 |
|
---|
565 | /*
|
---|
566 | * Make 32-bit GC pointer given CPUMCPU offset.
|
---|
567 | */
|
---|
568 | case FIX_GC_CPUMCPU_OFF:
|
---|
569 | {
|
---|
570 | uint32_t offCPUM = *u.pu32++;
|
---|
571 | Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
|
---|
572 | *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
|
---|
573 | break;
|
---|
574 | }
|
---|
575 |
|
---|
576 | /*
|
---|
577 | * Make 32-bit GC pointer given VM offset.
|
---|
578 | */
|
---|
579 | case FIX_GC_VM_OFF:
|
---|
580 | {
|
---|
581 | uint32_t offVM = *u.pu32++;
|
---|
582 | Assert(offVM < sizeof(VM));
|
---|
583 | *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
|
---|
584 | break;
|
---|
585 | }
|
---|
586 |
|
---|
587 | /*
|
---|
588 | * Make 32-bit HC pointer given CPUM offset.
|
---|
589 | */
|
---|
590 | case FIX_HC_CPUM_OFF:
|
---|
591 | {
|
---|
592 | uint32_t offCPUM = *u.pu32++;
|
---|
593 | Assert(offCPUM < sizeof(pVM->cpum));
|
---|
594 | *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
|
---|
595 | break;
|
---|
596 | }
|
---|
597 |
|
---|
598 | /*
|
---|
599 | * Make 32-bit R0 pointer given VM offset.
|
---|
600 | */
|
---|
601 | case FIX_HC_VM_OFF:
|
---|
602 | {
|
---|
603 | uint32_t offVM = *u.pu32++;
|
---|
604 | Assert(offVM < sizeof(VM));
|
---|
605 | *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
|
---|
606 | break;
|
---|
607 | }
|
---|
608 |
|
---|
609 | /*
|
---|
610 | * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
|
---|
611 | */
|
---|
612 | case FIX_INTER_32BIT_CR3:
|
---|
613 | {
|
---|
614 |
|
---|
615 | *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
|
---|
616 | break;
|
---|
617 | }
|
---|
618 |
|
---|
619 | /*
|
---|
620 | * Store the PAE CR3 (32-bit) for the intermediate memory context.
|
---|
621 | */
|
---|
622 | case FIX_INTER_PAE_CR3:
|
---|
623 | {
|
---|
624 |
|
---|
625 | *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
|
---|
626 | break;
|
---|
627 | }
|
---|
628 |
|
---|
629 | /*
|
---|
630 | * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
|
---|
631 | */
|
---|
632 | case FIX_INTER_AMD64_CR3:
|
---|
633 | {
|
---|
634 |
|
---|
635 | *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
|
---|
636 | break;
|
---|
637 | }
|
---|
638 |
|
---|
639 | /*
|
---|
640 | * Store Hypervisor CS (16-bit).
|
---|
641 | */
|
---|
642 | case FIX_HYPER_CS:
|
---|
643 | {
|
---|
644 | *uSrc.pu16 = SelCS;
|
---|
645 | break;
|
---|
646 | }
|
---|
647 |
|
---|
648 | /*
|
---|
649 | * Store Hypervisor DS (16-bit).
|
---|
650 | */
|
---|
651 | case FIX_HYPER_DS:
|
---|
652 | {
|
---|
653 | *uSrc.pu16 = SelDS;
|
---|
654 | break;
|
---|
655 | }
|
---|
656 |
|
---|
657 | /*
|
---|
658 | * Store Hypervisor TSS (16-bit).
|
---|
659 | */
|
---|
660 | case FIX_HYPER_TSS:
|
---|
661 | {
|
---|
662 | *uSrc.pu16 = SelTSS;
|
---|
663 | break;
|
---|
664 | }
|
---|
665 |
|
---|
666 | /*
|
---|
667 | * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
|
---|
668 | */
|
---|
669 | case FIX_GC_TSS_GDTE_DW2:
|
---|
670 | {
|
---|
671 | RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
|
---|
672 | *uSrc.pu32 = (uint32_t)GCPtr;
|
---|
673 | break;
|
---|
674 | }
|
---|
675 |
|
---|
676 | /*
|
---|
677 | * Store the EFER or mask for the 32->64 bit switcher.
|
---|
678 | */
|
---|
679 | case FIX_EFER_OR_MASK:
|
---|
680 | {
|
---|
681 | uint32_t u32OrMask = MSR_K6_EFER_LME | MSR_K6_EFER_SCE;
|
---|
682 | /*
|
---|
683 | * We don't care if cpuid 0x8000001 isn't supported as that implies
|
---|
684 | * long mode isn't supported either, so this switched would never be used.
|
---|
685 | */
|
---|
686 | if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
|
---|
687 | u32OrMask |= MSR_K6_EFER_NXE;
|
---|
688 |
|
---|
689 | *uSrc.pu32 = u32OrMask;
|
---|
690 | break;
|
---|
691 | }
|
---|
692 |
|
---|
693 | #if 0 /* Reusable for XSAVE. */
|
---|
694 | /*
|
---|
695 | * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
|
---|
696 | */
|
---|
697 | case FIX_NO_FXSAVE_JMP:
|
---|
698 | {
|
---|
699 | uint32_t offTrg = *u.pu32++;
|
---|
700 | Assert(offTrg < pSwitcher->cbCode);
|
---|
701 | if (!CPUMSupportsXSave(pVM))
|
---|
702 | {
|
---|
703 | *uSrc.pu8++ = 0xe9; /* jmp rel32 */
|
---|
704 | *uSrc.pu32++ = offTrg - (offSrc + 5);
|
---|
705 | }
|
---|
706 | else
|
---|
707 | {
|
---|
708 | *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
|
---|
709 | *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
|
---|
710 | }
|
---|
711 | break;
|
---|
712 | }
|
---|
713 | #endif
|
---|
714 |
|
---|
715 | /*
|
---|
716 | * Insert relative jump to specified target it SYSENTER isn't used by the host.
|
---|
717 | */
|
---|
718 | case FIX_NO_SYSENTER_JMP:
|
---|
719 | {
|
---|
720 | uint32_t offTrg = *u.pu32++;
|
---|
721 | Assert(offTrg < pSwitcher->cbCode);
|
---|
722 | if (!CPUMIsHostUsingSysEnter(pVM))
|
---|
723 | {
|
---|
724 | *uSrc.pu8++ = 0xe9; /* jmp rel32 */
|
---|
725 | *uSrc.pu32++ = offTrg - (offSrc + 5);
|
---|
726 | }
|
---|
727 | else
|
---|
728 | {
|
---|
729 | *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
|
---|
730 | *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
|
---|
731 | }
|
---|
732 | break;
|
---|
733 | }
|
---|
734 |
|
---|
735 | /*
|
---|
736 | * Insert relative jump to specified target it SYSCALL isn't used by the host.
|
---|
737 | */
|
---|
738 | case FIX_NO_SYSCALL_JMP:
|
---|
739 | {
|
---|
740 | uint32_t offTrg = *u.pu32++;
|
---|
741 | Assert(offTrg < pSwitcher->cbCode);
|
---|
742 | if (!CPUMIsHostUsingSysCall(pVM))
|
---|
743 | {
|
---|
744 | *uSrc.pu8++ = 0xe9; /* jmp rel32 */
|
---|
745 | *uSrc.pu32++ = offTrg - (offSrc + 5);
|
---|
746 | }
|
---|
747 | else
|
---|
748 | {
|
---|
749 | *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
|
---|
750 | *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
|
---|
751 | }
|
---|
752 | break;
|
---|
753 | }
|
---|
754 |
|
---|
755 | /*
|
---|
756 | * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
|
---|
757 | */
|
---|
758 | case FIX_HC_32BIT:
|
---|
759 | {
|
---|
760 | uint32_t offTrg = *u.pu32++;
|
---|
761 | Assert(offSrc < pSwitcher->cbCode);
|
---|
762 | Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
|
---|
763 | *uSrc.pu32 = R0PtrCode + offTrg;
|
---|
764 | break;
|
---|
765 | }
|
---|
766 |
|
---|
767 | # if defined(RT_ARCH_AMD64)
|
---|
768 | /*
|
---|
769 | * 64-bit HC Code Selector (no argument).
|
---|
770 | */
|
---|
771 | case FIX_HC_64BIT_CS:
|
---|
772 | {
|
---|
773 | Assert(offSrc < pSwitcher->cbCode);
|
---|
774 | AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
|
---|
775 | break;
|
---|
776 | }
|
---|
777 |
|
---|
778 | /*
|
---|
779 | * 64-bit HC pointer to the CPUM instance data (no argument).
|
---|
780 | */
|
---|
781 | case FIX_HC_64BIT_CPUM:
|
---|
782 | {
|
---|
783 | Assert(offSrc < pSwitcher->cbCode);
|
---|
784 | *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
|
---|
785 | break;
|
---|
786 | }
|
---|
787 | # endif
|
---|
788 | /*
|
---|
789 | * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
|
---|
790 | */
|
---|
791 | case FIX_HC_64BIT:
|
---|
792 | {
|
---|
793 | uint32_t offTrg = *u.pu32++;
|
---|
794 | Assert(offSrc < pSwitcher->cbCode);
|
---|
795 | Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
|
---|
796 | *uSrc.pu64 = R0PtrCode + offTrg;
|
---|
797 | break;
|
---|
798 | }
|
---|
799 |
|
---|
800 | # ifdef RT_ARCH_X86
|
---|
801 | case FIX_GC_64_BIT_CPUM_OFF:
|
---|
802 | {
|
---|
803 | uint32_t offCPUM = *u.pu32++;
|
---|
804 | Assert(offCPUM < sizeof(pVM->cpum));
|
---|
805 | *uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
|
---|
806 | break;
|
---|
807 | }
|
---|
808 | # endif
|
---|
809 |
|
---|
810 | /*
|
---|
811 | * 32-bit ID pointer to (ID) target within the code (32-bit offset).
|
---|
812 | */
|
---|
813 | case FIX_ID_32BIT:
|
---|
814 | {
|
---|
815 | uint32_t offTrg = *u.pu32++;
|
---|
816 | Assert(offSrc < pSwitcher->cbCode);
|
---|
817 | Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
|
---|
818 | *uSrc.pu32 = u32IDCode + offTrg;
|
---|
819 | break;
|
---|
820 | }
|
---|
821 |
|
---|
822 | /*
|
---|
823 | * 64-bit ID pointer to (ID) target within the code (32-bit offset).
|
---|
824 | */
|
---|
825 | case FIX_ID_64BIT:
|
---|
826 | case FIX_HC_64BIT_NOCHECK:
|
---|
827 | {
|
---|
828 | uint32_t offTrg = *u.pu32++;
|
---|
829 | Assert(offSrc < pSwitcher->cbCode);
|
---|
830 | Assert(u8 == FIX_HC_64BIT_NOCHECK || offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
|
---|
831 | *uSrc.pu64 = u32IDCode + offTrg;
|
---|
832 | break;
|
---|
833 | }
|
---|
834 |
|
---|
835 | /*
|
---|
836 | * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
|
---|
837 | */
|
---|
838 | case FIX_ID_FAR32_TO_64BIT_MODE:
|
---|
839 | {
|
---|
840 | uint32_t offTrg = *u.pu32++;
|
---|
841 | Assert(offSrc < pSwitcher->cbCode);
|
---|
842 | Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
|
---|
843 | *uSrc.pu32++ = u32IDCode + offTrg;
|
---|
844 | *uSrc.pu16 = SelCS64;
|
---|
845 | AssertRelease(SelCS64);
|
---|
846 | break;
|
---|
847 | }
|
---|
848 |
|
---|
849 | # ifdef VBOX_WITH_NMI
|
---|
850 | /*
|
---|
851 | * 32-bit address to the APIC base.
|
---|
852 | */
|
---|
853 | case FIX_GC_APIC_BASE_32BIT:
|
---|
854 | {
|
---|
855 | *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
|
---|
856 | break;
|
---|
857 | }
|
---|
858 | # endif
|
---|
859 |
|
---|
860 | default:
|
---|
861 | AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
|
---|
862 | break;
|
---|
863 | }
|
---|
864 | }
|
---|
865 |
|
---|
866 | # ifdef LOG_ENABLED
|
---|
867 | /*
|
---|
868 | * If Log2 is enabled disassemble the switcher code.
|
---|
869 | *
|
---|
870 | * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
|
---|
871 | */
|
---|
872 | if (LogIs2Enabled())
|
---|
873 | {
|
---|
874 | RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
|
---|
875 | " R0PtrCode = %p\n"
|
---|
876 | " pu8CodeR3 = %p\n"
|
---|
877 | " GCPtrCode = %RGv\n"
|
---|
878 | " u32IDCode = %08x\n"
|
---|
879 | " pVMRC = %RRv\n"
|
---|
880 | " pCPUMRC = %RRv\n"
|
---|
881 | " pVMR3 = %p\n"
|
---|
882 | " pCPUMR3 = %p\n"
|
---|
883 | " GCPtrGDT = %RGv\n"
|
---|
884 | " InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
|
---|
885 | " HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
|
---|
886 | " SelCS = %04x\n"
|
---|
887 | " SelDS = %04x\n"
|
---|
888 | " SelCS64 = %04x\n"
|
---|
889 | " SelTSS = %04x\n",
|
---|
890 | pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
|
---|
891 | R0PtrCode,
|
---|
892 | pu8CodeR3,
|
---|
893 | GCPtrCode,
|
---|
894 | u32IDCode,
|
---|
895 | VM_RC_ADDR(pVM, pVM),
|
---|
896 | VM_RC_ADDR(pVM, &pVM->cpum),
|
---|
897 | pVM,
|
---|
898 | &pVM->cpum,
|
---|
899 | GCPtrGDT,
|
---|
900 | PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
|
---|
901 | PGMGetHyperCR3(VMMGetCpu(pVM)),
|
---|
902 | SelCS, SelDS, SelCS64, SelTSS);
|
---|
903 |
|
---|
904 | uint32_t offCode = 0;
|
---|
905 | while (offCode < pSwitcher->cbCode)
|
---|
906 | {
|
---|
907 | /*
|
---|
908 | * Figure out where this is.
|
---|
909 | */
|
---|
910 | const char *pszDesc = NULL;
|
---|
911 | RTUINTPTR uBase;
|
---|
912 | uint32_t cbCode;
|
---|
913 | if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
|
---|
914 | {
|
---|
915 | pszDesc = "HCCode0";
|
---|
916 | uBase = R0PtrCode;
|
---|
917 | offCode = pSwitcher->offHCCode0;
|
---|
918 | cbCode = pSwitcher->cbHCCode0;
|
---|
919 | }
|
---|
920 | else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
|
---|
921 | {
|
---|
922 | pszDesc = "HCCode1";
|
---|
923 | uBase = R0PtrCode;
|
---|
924 | offCode = pSwitcher->offHCCode1;
|
---|
925 | cbCode = pSwitcher->cbHCCode1;
|
---|
926 | }
|
---|
927 | else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
|
---|
928 | {
|
---|
929 | pszDesc = "GCCode";
|
---|
930 | uBase = GCPtrCode;
|
---|
931 | offCode = pSwitcher->offGCCode;
|
---|
932 | cbCode = pSwitcher->cbGCCode;
|
---|
933 | }
|
---|
934 | else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
|
---|
935 | {
|
---|
936 | pszDesc = "IDCode0";
|
---|
937 | uBase = u32IDCode;
|
---|
938 | offCode = pSwitcher->offIDCode0;
|
---|
939 | cbCode = pSwitcher->cbIDCode0;
|
---|
940 | }
|
---|
941 | else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
|
---|
942 | {
|
---|
943 | pszDesc = "IDCode1";
|
---|
944 | uBase = u32IDCode;
|
---|
945 | offCode = pSwitcher->offIDCode1;
|
---|
946 | cbCode = pSwitcher->cbIDCode1;
|
---|
947 | }
|
---|
948 | else
|
---|
949 | {
|
---|
950 | RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
|
---|
951 | offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
|
---|
952 | offCode++;
|
---|
953 | continue;
|
---|
954 | }
|
---|
955 |
|
---|
956 | /*
|
---|
957 | * Disassemble it.
|
---|
958 | */
|
---|
959 | RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
|
---|
960 |
|
---|
961 | while (cbCode > 0)
|
---|
962 | {
|
---|
963 | /* try label it */
|
---|
964 | if (pSwitcher->offR0ToRawMode == offCode)
|
---|
965 | RTLogPrintf(" *R0ToRawMode:\n");
|
---|
966 | if (pSwitcher->offRCToHost == offCode)
|
---|
967 | RTLogPrintf(" *RCToHost:\n");
|
---|
968 | if (pSwitcher->offRCCallTrampoline == offCode)
|
---|
969 | RTLogPrintf(" *RCCallTrampoline:\n");
|
---|
970 | if (pSwitcher->offRCToHostAsm == offCode)
|
---|
971 | RTLogPrintf(" *RCToHostAsm:\n");
|
---|
972 | if (pSwitcher->offRCToHostAsmNoReturn == offCode)
|
---|
973 | RTLogPrintf(" *RCToHostAsmNoReturn:\n");
|
---|
974 |
|
---|
975 | /* disas */
|
---|
976 | uint32_t cbInstr = 0;
|
---|
977 | DISCPUSTATE Cpu;
|
---|
978 | char szDisas[256];
|
---|
979 | int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
|
---|
980 | if (RT_SUCCESS(rc))
|
---|
981 | {
|
---|
982 | Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
|
---|
983 | DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
|
---|
984 | DIS_FMT_FLAGS_ADDR_LEFT | DIS_FMT_FLAGS_BYTES_LEFT | DIS_FMT_FLAGS_BYTES_SPACED
|
---|
985 | | DIS_FMT_FLAGS_RELATIVE_BRANCH,
|
---|
986 | NULL, NULL);
|
---|
987 | }
|
---|
988 | if (RT_SUCCESS(rc))
|
---|
989 | RTLogPrintf(" %04x: %s\n", offCode, szDisas);
|
---|
990 | else
|
---|
991 | {
|
---|
992 | RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
|
---|
993 | offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
|
---|
994 | cbInstr = 1;
|
---|
995 | }
|
---|
996 | offCode += cbInstr;
|
---|
997 | cbCode -= RT_MIN(cbInstr, cbCode);
|
---|
998 | }
|
---|
999 | }
|
---|
1000 | }
|
---|
1001 | # endif
|
---|
1002 | }
|
---|
1003 |
|
---|
1004 | /**
|
---|
1005 | * Wrapper around SELMGetHyperGDT() that avoids calling it when raw-mode context
|
---|
1006 | * is not initialized.
|
---|
1007 | *
|
---|
1008 | * @returns Raw-mode contet GDT address. Null pointer if not applicable.
|
---|
1009 | * @param pVM The cross context VM structure.
|
---|
1010 | */
|
---|
1011 | static RTRCPTR vmmR3SwitcherGetHyperGDT(PVM pVM)
|
---|
1012 | {
|
---|
1013 | if (HMIsRawModeCtxNeeded(pVM))
|
---|
1014 | return SELMGetHyperGDT(pVM);
|
---|
1015 | # if HC_ARCH_BITS != 32
|
---|
1016 | AssertFailed(); /* This path is only applicable to some 32-bit hosts. */
|
---|
1017 | # endif
|
---|
1018 | return NIL_RTRCPTR;
|
---|
1019 | }
|
---|
1020 |
|
---|
1021 | /**
|
---|
1022 | * Relocator for the 32-Bit to 32-Bit world switcher.
|
---|
1023 | */
|
---|
1024 | DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1025 | {
|
---|
1026 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1027 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
|
---|
1028 | }
|
---|
1029 |
|
---|
1030 |
|
---|
1031 | /**
|
---|
1032 | * Relocator for the 32-Bit to PAE world switcher.
|
---|
1033 | */
|
---|
1034 | DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1035 | {
|
---|
1036 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1037 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
|
---|
1038 | }
|
---|
1039 |
|
---|
1040 |
|
---|
1041 | /**
|
---|
1042 | * Relocator for the 32-Bit to AMD64 world switcher.
|
---|
1043 | */
|
---|
1044 | DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1045 | {
|
---|
1046 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1047 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
|
---|
1048 | }
|
---|
1049 |
|
---|
1050 |
|
---|
1051 | /**
|
---|
1052 | * Relocator for the PAE to 32-Bit world switcher.
|
---|
1053 | */
|
---|
1054 | DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1055 | {
|
---|
1056 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1057 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
|
---|
1058 | }
|
---|
1059 |
|
---|
1060 |
|
---|
1061 | /**
|
---|
1062 | * Relocator for the PAE to PAE world switcher.
|
---|
1063 | */
|
---|
1064 | DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1065 | {
|
---|
1066 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1067 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
|
---|
1068 | }
|
---|
1069 |
|
---|
1070 | /**
|
---|
1071 | * Relocator for the PAE to AMD64 world switcher.
|
---|
1072 | */
|
---|
1073 | DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1074 | {
|
---|
1075 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1076 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
|
---|
1077 | }
|
---|
1078 |
|
---|
1079 |
|
---|
1080 | /**
|
---|
1081 | * Relocator for the AMD64 to 32-bit world switcher.
|
---|
1082 | */
|
---|
1083 | DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1084 | {
|
---|
1085 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1086 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
|
---|
1087 | }
|
---|
1088 |
|
---|
1089 |
|
---|
1090 | /**
|
---|
1091 | * Relocator for the AMD64 to PAE world switcher.
|
---|
1092 | */
|
---|
1093 | DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
|
---|
1094 | {
|
---|
1095 | vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
|
---|
1096 | SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
|
---|
1097 | }
|
---|
1098 |
|
---|
1099 |
|
---|
1100 | /**
|
---|
1101 | * Selects the switcher to be used for switching to raw-mode context.
|
---|
1102 | *
|
---|
1103 | * @returns VBox status code.
|
---|
1104 | * @param pVM The cross context VM structure.
|
---|
1105 | * @param enmSwitcher The new switcher.
|
---|
1106 | * @remark This function may be called before the VMM is initialized.
|
---|
1107 | */
|
---|
1108 | VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
|
---|
1109 | {
|
---|
1110 | /*
|
---|
1111 | * Validate input.
|
---|
1112 | */
|
---|
1113 | if ( enmSwitcher < VMMSWITCHER_INVALID
|
---|
1114 | || enmSwitcher >= VMMSWITCHER_MAX)
|
---|
1115 | {
|
---|
1116 | AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
|
---|
1117 | return VERR_INVALID_PARAMETER;
|
---|
1118 | }
|
---|
1119 |
|
---|
1120 | /*
|
---|
1121 | * Override it if HM is active.
|
---|
1122 | */
|
---|
1123 | if (!VM_IS_RAW_MODE_ENABLED(pVM))
|
---|
1124 | pVM->vmm.s.enmSwitcher = HC_ARCH_BITS == 64 ? VMMSWITCHER_AMD64_STUB : VMMSWITCHER_X86_STUB;
|
---|
1125 |
|
---|
1126 | /*
|
---|
1127 | * Select the new switcher.
|
---|
1128 | */
|
---|
1129 | const PVMMSWITCHERDEF *papSwitchers = VM_IS_RAW_MODE_ENABLED(pVM) ? g_apRawModeSwitchers : g_apHmSwitchers;
|
---|
1130 | PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
|
---|
1131 | if (pSwitcher)
|
---|
1132 | {
|
---|
1133 | Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
|
---|
1134 | pVM->vmm.s.enmSwitcher = enmSwitcher;
|
---|
1135 |
|
---|
1136 | RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
|
---|
1137 | pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
|
---|
1138 |
|
---|
1139 | RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
|
---|
1140 | pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
|
---|
1141 | pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
|
---|
1142 | pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
|
---|
1143 | pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
|
---|
1144 | return VINF_SUCCESS;
|
---|
1145 | }
|
---|
1146 |
|
---|
1147 | return VERR_NOT_IMPLEMENTED;
|
---|
1148 | }
|
---|
1149 |
|
---|
1150 | #endif /* #defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64) */
|
---|
1151 |
|
---|
1152 |
|
---|
1153 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
|
---|
1154 | /**
|
---|
1155 | * Gets the switcher to be used for switching to GC.
|
---|
1156 | *
|
---|
1157 | * This is for 64-on-32 with HM. Caller is HMR3Relocate().
|
---|
1158 | *
|
---|
1159 | * @returns host to guest ring 0 switcher entrypoint
|
---|
1160 | * @param pVM The cross context VM structure.
|
---|
1161 | * @param enmSwitcher The new switcher.
|
---|
1162 | */
|
---|
1163 | VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
|
---|
1164 | {
|
---|
1165 | /*
|
---|
1166 | * Validate input.
|
---|
1167 | */
|
---|
1168 | AssertMsgReturn( enmSwitcher == VMMSWITCHER_32_TO_AMD64
|
---|
1169 | || enmSwitcher == VMMSWITCHER_PAE_TO_AMD64,
|
---|
1170 | ("%d\n", enmSwitcher),
|
---|
1171 | NIL_RTR0PTR);
|
---|
1172 | AssertReturn(HMIsEnabled(pVM), NIL_RTR0PTR);
|
---|
1173 |
|
---|
1174 | /*
|
---|
1175 | * Select the new switcher.
|
---|
1176 | */
|
---|
1177 | const PVMMSWITCHERDEF *papSwitchers = g_apHmSwitchers;
|
---|
1178 | PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
|
---|
1179 | if (pSwitcher)
|
---|
1180 | {
|
---|
1181 | /** @todo fix the pvCoreCodeR0 type */
|
---|
1182 | RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher];
|
---|
1183 | return pbCodeR0 + pSwitcher->offR0ToRawMode;
|
---|
1184 | }
|
---|
1185 | return NIL_RTR0PTR;
|
---|
1186 | }
|
---|
1187 | #endif
|
---|
1188 |
|
---|