VMMSwitcher.cpp@ 42024

Last change on this file since 42024 was 42024, checked in by vboxsync, 12 years ago
VMM: RDTSCP support on Intel. Segregated some common CPU features from the AMD superset into Extended features as they're now available on Intel too.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 37.3 KB

Line
1	/* $Id: VMMSwitcher.cpp 42024 2012-07-05 12:10:53Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_VMM
22	#include <VBox/vmm/vmm.h>
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/sup.h>
27	#include "VMMInternal.h"
28	#include "VMMSwitcher.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/dis.h>
31
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/alloc.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Global Variables *
44	*******************************************************************************/
45	/** Array of switcher definitions.
46	* The type and index shall match!
47	*/
48	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
49	{
50	NULL, /* invalid entry */
51	#ifdef VBOX_WITH_RAW_MODE
52	# ifndef RT_ARCH_AMD64
53	&vmmR3Switcher32BitTo32Bit_Def,
54	&vmmR3Switcher32BitToPAE_Def,
55	&vmmR3Switcher32BitToAMD64_Def,
56	&vmmR3SwitcherPAETo32Bit_Def,
57	&vmmR3SwitcherPAEToPAE_Def,
58	&vmmR3SwitcherPAEToAMD64_Def,
59	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
60	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
61	&vmmR3SwitcherAMD64ToPAE_Def,
62	# else
63	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64	# endif
65	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
66	# else /* RT_ARCH_AMD64 */
67	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68	NULL, //&vmmR3Switcher32BitToPAE_Def,
69	NULL, //&vmmR3Switcher32BitToAMD64_Def,
70	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71	NULL, //&vmmR3SwitcherPAEToPAE_Def,
72	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
73	&vmmR3SwitcherAMD64To32Bit_Def,
74	&vmmR3SwitcherAMD64ToPAE_Def,
75	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
76	# endif /* RT_ARCH_AMD64 */
77	#else /* !VBOX_WITH_RAW_MODE */
78	NULL,
79	NULL,
80	NULL,
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL
87	#endif /* !VBOX_WITH_RAW_MODE */
88	};
89
90
91	/**
92	* VMMR3Init worker that initiates the switcher code (aka core code).
93	*
94	* This is core per VM code which might need fixups and/or for ease of use are
95	* put on linear contiguous backing.
96	*
97	* @returns VBox status code.
98	* @param pVM Pointer to the VM.
99	*/
100	int vmmR3SwitcherInit(PVM pVM)
101	{
102	#ifndef VBOX_WITH_RAW_MODE
103	return VINF_SUCCESS;
104	#else
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate contiguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	#endif
226	}
227
228	/**
229	* Relocate the switchers, called by VMMR#Relocate.
230	*
231	* @param pVM Pointer to the VM.
232	* @param offDelta The relocation delta.
233	*/
234	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
235	{
236	#ifdef VBOX_WITH_RAW_MODE
237	/*
238	* Relocate all the switchers.
239	*/
240	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
241	{
242	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
243	if (pSwitcher && pSwitcher->pfnRelocate)
244	{
245	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
246	pSwitcher->pfnRelocate(pVM,
247	pSwitcher,
248	pVM->vmm.s.pvCoreCodeR0 + off,
249	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
250	pVM->vmm.s.pvCoreCodeRC + off,
251	pVM->vmm.s.HCPhysCoreCode + off);
252	}
253	}
254
255	/*
256	* Recalc the RC address for the current switcher.
257	*/
258	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
259	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
260	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
261	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
262	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
263	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
264
265	// AssertFailed();
266	#else
267	NOREF(pVM);
268	#endif
269	NOREF(offDelta);
270	}
271
272
273	/**
274	* Generic switcher code relocator.
275	*
276	* @param pVM Pointer to the VM.
277	* @param pSwitcher The switcher definition.
278	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
279	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
280	* @param GCPtrCode The guest context address corresponding to pu8Code.
281	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
282	* @param SelCS The hypervisor CS selector.
283	* @param SelDS The hypervisor DS selector.
284	* @param SelTSS The hypervisor TSS selector.
285	* @param GCPtrGDT The GC address of the hypervisor GDT.
286	* @param SelCS64 The 64-bit mode hypervisor CS selector.
287	*/
288	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
289	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
290	{
291	union
292	{
293	const uint8_t *pu8;
294	const uint16_t *pu16;
295	const uint32_t *pu32;
296	const uint64_t *pu64;
297	const void *pv;
298	uintptr_t u;
299	} u;
300	u.pv = pSwitcher->pvFixups;
301
302	/*
303	* Process fixups.
304	*/
305	uint8_t u8;
306	while ((u8 = *u.pu8++) != FIX_THE_END)
307	{
308	/*
309	* Get the source (where to write the fixup).
310	*/
311	uint32_t offSrc = *u.pu32++;
312	Assert(offSrc < pSwitcher->cbCode);
313	union
314	{
315	uint8_t *pu8;
316	uint16_t *pu16;
317	uint32_t *pu32;
318	uint64_t *pu64;
319	uintptr_t u;
320	} uSrc;
321	uSrc.pu8 = pu8CodeR3 + offSrc;
322
323	/* The fixup target and method depends on the type. */
324	switch (u8)
325	{
326	/*
327	* 32-bit relative, source in HC and target in GC.
328	*/
329	case FIX_HC_2_GC_NEAR_REL:
330	{
331	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
332	uint32_t offTrg = *u.pu32++;
333	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
334	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
335	break;
336	}
337
338	/*
339	* 32-bit relative, source in HC and target in ID.
340	*/
341	case FIX_HC_2_ID_NEAR_REL:
342	{
343	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
344	uint32_t offTrg = *u.pu32++;
345	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
346	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
347	break;
348	}
349
350	/*
351	* 32-bit relative, source in GC and target in HC.
352	*/
353	case FIX_GC_2_HC_NEAR_REL:
354	{
355	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
356	uint32_t offTrg = *u.pu32++;
357	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
358	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
359	break;
360	}
361
362	/*
363	* 32-bit relative, source in GC and target in ID.
364	*/
365	case FIX_GC_2_ID_NEAR_REL:
366	{
367	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
368	uint32_t offTrg = *u.pu32++;
369	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
370	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
371	break;
372	}
373
374	/*
375	* 32-bit relative, source in ID and target in HC.
376	*/
377	case FIX_ID_2_HC_NEAR_REL:
378	{
379	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
380	uint32_t offTrg = *u.pu32++;
381	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
382	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
383	break;
384	}
385
386	/*
387	* 32-bit relative, source in ID and target in HC.
388	*/
389	case FIX_ID_2_GC_NEAR_REL:
390	{
391	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
392	uint32_t offTrg = *u.pu32++;
393	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
394	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
395	break;
396	}
397
398	/*
399	* 16:32 far jump, target in GC.
400	*/
401	case FIX_GC_FAR32:
402	{
403	uint32_t offTrg = *u.pu32++;
404	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
405	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
406	*uSrc.pu16++ = SelCS;
407	break;
408	}
409
410	/*
411	* Make 32-bit GC pointer given CPUM offset.
412	*/
413	case FIX_GC_CPUM_OFF:
414	{
415	uint32_t offCPUM = *u.pu32++;
416	Assert(offCPUM < sizeof(pVM->cpum));
417	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
418	break;
419	}
420
421	/*
422	* Make 32-bit GC pointer given CPUMCPU offset.
423	*/
424	case FIX_GC_CPUMCPU_OFF:
425	{
426	uint32_t offCPUM = *u.pu32++;
427	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
428	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
429	break;
430	}
431
432	/*
433	* Make 32-bit GC pointer given VM offset.
434	*/
435	case FIX_GC_VM_OFF:
436	{
437	uint32_t offVM = *u.pu32++;
438	Assert(offVM < sizeof(VM));
439	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
440	break;
441	}
442
443	/*
444	* Make 32-bit HC pointer given CPUM offset.
445	*/
446	case FIX_HC_CPUM_OFF:
447	{
448	uint32_t offCPUM = *u.pu32++;
449	Assert(offCPUM < sizeof(pVM->cpum));
450	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
451	break;
452	}
453
454	/*
455	* Make 32-bit R0 pointer given VM offset.
456	*/
457	case FIX_HC_VM_OFF:
458	{
459	uint32_t offVM = *u.pu32++;
460	Assert(offVM < sizeof(VM));
461	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
462	break;
463	}
464
465	/*
466	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
467	*/
468	case FIX_INTER_32BIT_CR3:
469	{
470
471	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
472	break;
473	}
474
475	/*
476	* Store the PAE CR3 (32-bit) for the intermediate memory context.
477	*/
478	case FIX_INTER_PAE_CR3:
479	{
480
481	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
482	break;
483	}
484
485	/*
486	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
487	*/
488	case FIX_INTER_AMD64_CR3:
489	{
490
491	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
492	break;
493	}
494
495	/*
496	* Store Hypervisor CS (16-bit).
497	*/
498	case FIX_HYPER_CS:
499	{
500	*uSrc.pu16 = SelCS;
501	break;
502	}
503
504	/*
505	* Store Hypervisor DS (16-bit).
506	*/
507	case FIX_HYPER_DS:
508	{
509	*uSrc.pu16 = SelDS;
510	break;
511	}
512
513	/*
514	* Store Hypervisor TSS (16-bit).
515	*/
516	case FIX_HYPER_TSS:
517	{
518	*uSrc.pu16 = SelTSS;
519	break;
520	}
521
522	/*
523	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
524	*/
525	case FIX_GC_TSS_GDTE_DW2:
526	{
527	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
528	*uSrc.pu32 = (uint32_t)GCPtr;
529	break;
530	}
531
532	/*
533	* Store the EFER or mask for the 32->64 bit switcher.
534	*/
535	case FIX_EFER_OR_MASK:
536	{
537	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
538	/*
539	* We don't care if cpuid 0x8000001 isn't supported as that implies
540	* long mode isn't supported either, so this switched would never be used.
541	*/
542	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
543	u32OrMask \|= MSR_K6_EFER_NXE;
544
545	*uSrc.pu32 = u32OrMask;
546	break;
547	}
548
549	/*
550	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
551	*/
552	case FIX_NO_FXSAVE_JMP:
553	{
554	uint32_t offTrg = *u.pu32++;
555	Assert(offTrg < pSwitcher->cbCode);
556	if (!CPUMSupportsFXSR(pVM))
557	{
558	uSrc.pu8++ = 0xe9; / jmp rel32 */
559	*uSrc.pu32++ = offTrg - (offSrc + 5);
560	}
561	else
562	{
563	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
564	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
565	}
566	break;
567	}
568
569	/*
570	* Insert relative jump to specified target it SYSENTER isn't used by the host.
571	*/
572	case FIX_NO_SYSENTER_JMP:
573	{
574	uint32_t offTrg = *u.pu32++;
575	Assert(offTrg < pSwitcher->cbCode);
576	if (!CPUMIsHostUsingSysEnter(pVM))
577	{
578	uSrc.pu8++ = 0xe9; / jmp rel32 */
579	*uSrc.pu32++ = offTrg - (offSrc + 5);
580	}
581	else
582	{
583	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
584	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
585	}
586	break;
587	}
588
589	/*
590	* Insert relative jump to specified target it SYSCALL isn't used by the host.
591	*/
592	case FIX_NO_SYSCALL_JMP:
593	{
594	uint32_t offTrg = *u.pu32++;
595	Assert(offTrg < pSwitcher->cbCode);
596	if (!CPUMIsHostUsingSysCall(pVM))
597	{
598	uSrc.pu8++ = 0xe9; / jmp rel32 */
599	*uSrc.pu32++ = offTrg - (offSrc + 5);
600	}
601	else
602	{
603	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
604	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
605	}
606	break;
607	}
608
609	/*
610	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
611	*/
612	case FIX_HC_32BIT:
613	{
614	uint32_t offTrg = *u.pu32++;
615	Assert(offSrc < pSwitcher->cbCode);
616	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
617	*uSrc.pu32 = R0PtrCode + offTrg;
618	break;
619	}
620
621	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
622	/*
623	* 64-bit HC Code Selector (no argument).
624	*/
625	case FIX_HC_64BIT_CS:
626	{
627	Assert(offSrc < pSwitcher->cbCode);
628	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
629	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
630	# else
631	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
632	# endif
633	break;
634	}
635
636	/*
637	* 64-bit HC pointer to the CPUM instance data (no argument).
638	*/
639	case FIX_HC_64BIT_CPUM:
640	{
641	Assert(offSrc < pSwitcher->cbCode);
642	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
643	break;
644	}
645	#endif
646	/*
647	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
648	*/
649	case FIX_HC_64BIT:
650	{
651	uint32_t offTrg = *u.pu32++;
652	Assert(offSrc < pSwitcher->cbCode);
653	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
654	*uSrc.pu64 = R0PtrCode + offTrg;
655	break;
656	}
657
658	#ifdef RT_ARCH_X86
659	case FIX_GC_64_BIT_CPUM_OFF:
660	{
661	uint32_t offCPUM = *u.pu32++;
662	Assert(offCPUM < sizeof(pVM->cpum));
663	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
664	break;
665	}
666	#endif
667
668	/*
669	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
670	*/
671	case FIX_ID_32BIT:
672	{
673	uint32_t offTrg = *u.pu32++;
674	Assert(offSrc < pSwitcher->cbCode);
675	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
676	*uSrc.pu32 = u32IDCode + offTrg;
677	break;
678	}
679
680	/*
681	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
682	*/
683	case FIX_ID_64BIT:
684	case FIX_HC_64BIT_NOCHECK:
685	{
686	uint32_t offTrg = *u.pu32++;
687	Assert(offSrc < pSwitcher->cbCode);
688	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
689	*uSrc.pu64 = u32IDCode + offTrg;
690	break;
691	}
692
693	/*
694	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
695	*/
696	case FIX_ID_FAR32_TO_64BIT_MODE:
697	{
698	uint32_t offTrg = *u.pu32++;
699	Assert(offSrc < pSwitcher->cbCode);
700	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
701	*uSrc.pu32++ = u32IDCode + offTrg;
702	*uSrc.pu16 = SelCS64;
703	AssertRelease(SelCS64);
704	break;
705	}
706
707	#ifdef VBOX_WITH_NMI
708	/*
709	* 32-bit address to the APIC base.
710	*/
711	case FIX_GC_APIC_BASE_32BIT:
712	{
713	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
714	break;
715	}
716	#endif
717
718	default:
719	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
720	break;
721	}
722	}
723
724	#ifdef LOG_ENABLED
725	/*
726	* If Log2 is enabled disassemble the switcher code.
727	*
728	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
729	*/
730	if (LogIs2Enabled())
731	{
732	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
733	" R0PtrCode = %p\n"
734	" pu8CodeR3 = %p\n"
735	" GCPtrCode = %RGv\n"
736	" u32IDCode = %08x\n"
737	" pVMRC = %RRv\n"
738	" pCPUMRC = %RRv\n"
739	" pVMR3 = %p\n"
740	" pCPUMR3 = %p\n"
741	" GCPtrGDT = %RGv\n"
742	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
743	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
744	" SelCS = %04x\n"
745	" SelDS = %04x\n"
746	" SelCS64 = %04x\n"
747	" SelTSS = %04x\n",
748	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
749	R0PtrCode,
750	pu8CodeR3,
751	GCPtrCode,
752	u32IDCode,
753	VM_RC_ADDR(pVM, pVM),
754	VM_RC_ADDR(pVM, &pVM->cpum),
755	pVM,
756	&pVM->cpum,
757	GCPtrGDT,
758	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
759	PGMGetHyperCR3(VMMGetCpu(pVM)),
760	SelCS, SelDS, SelCS64, SelTSS);
761
762	uint32_t offCode = 0;
763	while (offCode < pSwitcher->cbCode)
764	{
765	/*
766	* Figure out where this is.
767	*/
768	const char *pszDesc = NULL;
769	RTUINTPTR uBase;
770	uint32_t cbCode;
771	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
772	{
773	pszDesc = "HCCode0";
774	uBase = R0PtrCode;
775	offCode = pSwitcher->offHCCode0;
776	cbCode = pSwitcher->cbHCCode0;
777	}
778	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
779	{
780	pszDesc = "HCCode1";
781	uBase = R0PtrCode;
782	offCode = pSwitcher->offHCCode1;
783	cbCode = pSwitcher->cbHCCode1;
784	}
785	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
786	{
787	pszDesc = "GCCode";
788	uBase = GCPtrCode;
789	offCode = pSwitcher->offGCCode;
790	cbCode = pSwitcher->cbGCCode;
791	}
792	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
793	{
794	pszDesc = "IDCode0";
795	uBase = u32IDCode;
796	offCode = pSwitcher->offIDCode0;
797	cbCode = pSwitcher->cbIDCode0;
798	}
799	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
800	{
801	pszDesc = "IDCode1";
802	uBase = u32IDCode;
803	offCode = pSwitcher->offIDCode1;
804	cbCode = pSwitcher->cbIDCode1;
805	}
806	else
807	{
808	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
809	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
810	offCode++;
811	continue;
812	}
813
814	/*
815	* Disassemble it.
816	*/
817	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
818
819	while (cbCode > 0)
820	{
821	/* try label it */
822	if (pSwitcher->offR0ToRawMode == offCode)
823	RTLogPrintf(" *R0ToRawMode:\n");
824	if (pSwitcher->offRCToHost == offCode)
825	RTLogPrintf(" *RCToHost:\n");
826	if (pSwitcher->offRCCallTrampoline == offCode)
827	RTLogPrintf(" *RCCallTrampoline:\n");
828	if (pSwitcher->offRCToHostAsm == offCode)
829	RTLogPrintf(" *RCToHostAsm:\n");
830	if (pSwitcher->offRCToHostAsmNoReturn == offCode)
831	RTLogPrintf(" *RCToHostAsmNoReturn:\n");
832
833	/* disas */
834	uint32_t cbInstr = 0;
835	DISCPUSTATE Cpu;
836	char szDisas[256];
837	int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
838	if (RT_SUCCESS(rc))
839	{
840	Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
841	DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
842	DIS_FMT_FLAGS_ADDR_LEFT \| DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_BYTES_SPACED
843	\| DIS_FMT_FLAGS_RELATIVE_BRANCH,
844	NULL, NULL);
845	}
846	if (RT_SUCCESS(rc))
847	RTLogPrintf(" %04x: %s\n", offCode, szDisas);
848	else
849	{
850	RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
851	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
852	cbInstr = 1;
853	}
854	offCode += cbInstr;
855	cbCode -= RT_MIN(cbInstr, cbCode);
856	}
857	}
858	}
859	#endif
860	}
861
862
863	/**
864	* Relocator for the 32-Bit to 32-Bit world switcher.
865	*/
866	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
867	{
868	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
869	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
870	}
871
872
873	/**
874	* Relocator for the 32-Bit to PAE world switcher.
875	*/
876	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
877	{
878	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
879	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
880	}
881
882
883	/**
884	* Relocator for the 32-Bit to AMD64 world switcher.
885	*/
886	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
887	{
888	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
889	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
890	}
891
892
893	/**
894	* Relocator for the PAE to 32-Bit world switcher.
895	*/
896	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
897	{
898	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
899	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
900	}
901
902
903	/**
904	* Relocator for the PAE to PAE world switcher.
905	*/
906	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
907	{
908	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
909	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
910	}
911
912	/**
913	* Relocator for the PAE to AMD64 world switcher.
914	*/
915	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
916	{
917	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
918	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
919	}
920
921
922	/**
923	* Relocator for the AMD64 to 32-bit world switcher.
924	*/
925	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
926	{
927	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
928	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
929	}
930
931
932	/**
933	* Relocator for the AMD64 to PAE world switcher.
934	*/
935	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
936	{
937	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
938	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
939	}
940
941
942	/**
943	* Selects the switcher to be used for switching to raw-mode context.
944	*
945	* @returns VBox status code.
946	* @param pVM Pointer to the VM.
947	* @param enmSwitcher The new switcher.
948	* @remark This function may be called before the VMM is initialized.
949	*/
950	VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
951	{
952	/*
953	* Validate input.
954	*/
955	if ( enmSwitcher < VMMSWITCHER_INVALID
956	\|\| enmSwitcher >= VMMSWITCHER_MAX)
957	{
958	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
959	return VERR_INVALID_PARAMETER;
960	}
961
962	/* Do nothing if the switcher is disabled. */
963	if (pVM->vmm.s.fSwitcherDisabled)
964	return VINF_SUCCESS;
965
966	/*
967	* Select the new switcher.
968	*/
969	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
970	if (pSwitcher)
971	{
972	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
973	pVM->vmm.s.enmSwitcher = enmSwitcher;
974
975	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
976	pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
977
978	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
979	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
980	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
981	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
982	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
983	return VINF_SUCCESS;
984	}
985
986	return VERR_NOT_IMPLEMENTED;
987	}
988
989
990	/**
991	* Disable the switcher logic permanently.
992	*
993	* @returns VBox status code.
994	* @param pVM Pointer to the VM.
995	*/
996	VMMR3_INT_DECL(int) VMMR3DisableSwitcher(PVM pVM)
997	{
998	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
999	* @code
1000	* mov eax, VERR_VMM_DUMMY_SWITCHER
1001	* ret
1002	* @endcode
1003	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1004	*/
1005	pVM->vmm.s.fSwitcherDisabled = true;
1006	return VINF_SUCCESS;
1007	}
1008
1009
1010	/**
1011	* Gets the switcher to be used for switching to GC.
1012	*
1013	* @returns host to guest ring 0 switcher entrypoint
1014	* @param pVM Pointer to the VM.
1015	* @param enmSwitcher The new switcher.
1016	*/
1017	VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1018	{
1019	/*
1020	* Validate input.
1021	*/
1022	if ( enmSwitcher < VMMSWITCHER_INVALID
1023	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1024	{
1025	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1026	return NIL_RTR0PTR;
1027	}
1028
1029	/*
1030	* Select the new switcher.
1031	*/
1032	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1033	if (pSwitcher)
1034	{
1035	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1036	return pbCodeR0 + pSwitcher->offR0ToRawMode;
1037	}
1038	return NIL_RTR0PTR;
1039	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 42024

Download in other formats: