VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 69405

Last change on this file since 69405 was 69111, checked in by vboxsync, 7 years ago

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1/* $Id: VMMSwitcher.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor, World Switcher(s).
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_VMM
23#include <VBox/vmm/vmm.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/selm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/sup.h>
29#include "VMMInternal.h"
30#include "VMMSwitcher.h"
31#include <VBox/vmm/vm.h>
32#include <VBox/dis.h>
33
34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <iprt/assert.h>
37#include <iprt/alloc.h>
38#include <iprt/asm.h>
39#include <iprt/asm-amd64-x86.h>
40#include <iprt/string.h>
41#include <iprt/ctype.h>
42
43
44/*********************************************************************************************************************************
45* Global Variables *
46*********************************************************************************************************************************/
47#if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64)
48/** Array of switcher definitions.
49 * The type and index shall match!
50 */
51static PVMMSWITCHERDEF g_apRawModeSwitchers[VMMSWITCHER_MAX] =
52{
53 NULL, /* invalid entry */
54# ifdef VBOX_WITH_RAW_MODE
55# ifndef RT_ARCH_AMD64
56 &vmmR3Switcher32BitTo32Bit_Def,
57 &vmmR3Switcher32BitToPAE_Def,
58 NULL, //&vmmR3Switcher32BitToAMD64_Def,
59 &vmmR3SwitcherPAETo32Bit_Def,
60 &vmmR3SwitcherPAEToPAE_Def,
61 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
62 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
63 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
65# else /* RT_ARCH_AMD64 */
66 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
67 NULL, //&vmmR3Switcher32BitToPAE_Def,
68 NULL, //&vmmR3Switcher32BitToAMD64_Def,
69 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
70 NULL, //&vmmR3SwitcherPAEToPAE_Def,
71 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
72 &vmmR3SwitcherAMD64To32Bit_Def,
73 &vmmR3SwitcherAMD64ToPAE_Def,
74 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
75# endif /* RT_ARCH_AMD64 */
76# else /* !VBOX_WITH_RAW_MODE */
77 NULL,
78 NULL,
79 NULL,
80 NULL,
81 NULL,
82 NULL,
83 NULL,
84 NULL,
85 NULL,
86# endif /* !VBOX_WITH_RAW_MODE */
87# ifndef RT_ARCH_AMD64
88 &vmmR3SwitcherX86Stub_Def,
89 NULL,
90# else
91 NULL,
92 &vmmR3SwitcherAMD64Stub_Def,
93# endif
94};
95#endif /* VBOX_WITH_RAW_MODE || (HC_ARCH_BITS != 64) */
96
97
98/** Array of switcher definitions.
99 * The type and index shall match!
100 */
101static PVMMSWITCHERDEF g_apHmSwitchers[VMMSWITCHER_MAX] =
102{
103 NULL, /* invalid entry */
104#if HC_ARCH_BITS == 32
105 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
106 NULL, //&vmmR3Switcher32BitToPAE_Def,
107 &vmmR3Switcher32BitToAMD64_Def,
108 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
109 NULL, //&vmmR3SwitcherPAEToPAE_Def,
110 &vmmR3SwitcherPAEToAMD64_Def,
111 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
112 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
113 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
114#else /* !VBOX_WITH_RAW_MODE */
115 NULL,
116 NULL,
117 NULL,
118 NULL,
119 NULL,
120 NULL,
121 NULL,
122 NULL,
123 NULL,
124#endif /* !VBOX_WITH_RAW_MODE */
125#ifndef RT_ARCH_AMD64
126 &vmmR3SwitcherX86Stub_Def,
127 NULL,
128#else
129 NULL,
130 &vmmR3SwitcherAMD64Stub_Def,
131#endif
132};
133
134
135# ifdef VBOX_WITH_64ON32_IDT
136/**
137 * Initializes the 64-bit IDT for 64-bit guest on 32-bit host switchers.
138 *
139 * This is only used as a debugging aid when we cannot find out why something
140 * goes haywire in the intermediate context.
141 *
142 * @param pVM The cross context VM structure.
143 * @param pSwitcher The switcher descriptor.
144 * @param pbDst Where the switcher code was just copied.
145 * @param HCPhysDst The host physical address corresponding to @a pbDst.
146 */
147static void vmmR3Switcher32On64IdtInit(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
148{
149 AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode);
150 AssertRelease(pSwitcher->cbCode < _64K);
151 RTSEL uCs64 = SELMGetHyperCS64(pVM);
152
153 PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
154 for (uint32_t i = 0 ; i < 256; i++)
155 {
156 AssertRelease(((uint64_t *)&paIdt[i])[0] < pSwitcher->cbCode);
157 AssertRelease(((uint64_t *)&paIdt[i])[1] == 0);
158 uint64_t uHandler = HCPhysDst + paIdt[i].u16OffsetLow;
159 paIdt[i].u16OffsetLow = (uint16_t)uHandler;
160 paIdt[i].u16Sel = uCs64;
161 paIdt[i].u3IST = 0;
162 paIdt[i].u5Reserved = 0;
163 paIdt[i].u4Type = AMD64_SEL_TYPE_SYS_INT_GATE;
164 paIdt[i].u1DescType = 0 /* system */;
165 paIdt[i].u2Dpl = 3;
166 paIdt[i].u1Present = 1;
167 paIdt[i].u16OffsetHigh = (uint16_t)(uHandler >> 16);
168 paIdt[i].u32Reserved = (uint32_t)(uHandler >> 32);
169 }
170
171 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
172 {
173 uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
174 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
175 }
176}
177
178
179/**
180 * Relocates the 64-bit IDT for 64-bit guest on 32-bit host switchers.
181 *
182 * @param pVM The cross context VM structure.
183 * @param pSwitcher The switcher descriptor.
184 * @param pbDst Where the switcher code was just copied.
185 * @param HCPhysDst The host physical address corresponding to @a pbDst.
186 */
187static void vmmR3Switcher32On64IdtRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
188{
189 AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode && pSwitcher->cbCode < _64K);
190
191 /* The intermediate context doesn't move, but the CS may. */
192 RTSEL uCs64 = SELMGetHyperCS64(pVM);
193 PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
194 for (uint32_t i = 0 ; i < 256; i++)
195 paIdt[i].u16Sel = uCs64;
196
197 /* Just in case... */
198 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
199 {
200 uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
201 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
202 }
203}
204# endif /* VBOX_WITH_64ON32_IDT */
205
206
207/**
208 * VMMR3Init worker that initiates the switcher code (aka core code).
209 *
210 * This is core per VM code which might need fixups and/or for ease of use are
211 * put on linear contiguous backing.
212 *
213 * @returns VBox status code.
214 * @param pVM The cross context VM structure.
215 */
216int vmmR3SwitcherInit(PVM pVM)
217{
218#if !defined(VBOX_WITH_RAW_MODE) && (HC_ARCH_BITS == 64)
219 RT_NOREF(pVM);
220 return VINF_SUCCESS;
221#else
222
223 /*
224 * Calc the size.
225 */
226 const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
227 unsigned cbCoreCode = 0;
228 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
229 {
230 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
231 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
232 if (pSwitcher)
233 {
234 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
235 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
236 }
237 }
238
239 /*
240 * Allocate contiguous pages for switchers and deal with
241 * conflicts in the intermediate mapping of the code.
242 */
243 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
244 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
245 int rc = VERR_NO_MEMORY;
246 if (pVM->vmm.s.pvCoreCodeR3)
247 {
248 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
249 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
250 {
251 /* try more allocations - Solaris, Linux. */
252 const unsigned cTries = 8234;
253 struct VMMInitBadTry
254 {
255 RTR0PTR pvR0;
256 void *pvR3;
257 RTHCPHYS HCPhys;
258 RTUINT cb;
259 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
260 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
261 unsigned i = 0;
262 do
263 {
264 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
265 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
266 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
267 i++;
268 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
269 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
270 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
271 if (!pVM->vmm.s.pvCoreCodeR3)
272 break;
273 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
274 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
275 && i < cTries - 1);
276
277 /* cleanup */
278 if (RT_FAILURE(rc))
279 {
280 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
281 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
282 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
283 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
284 i++;
285 LogRel(("VMM: Failed to allocated and map core code: rc=%Rrc\n", rc));
286 }
287 while (i-- > 0)
288 {
289 LogRel(("VMM: Core code alloc attempt #%d: pvR3=%p pvR0=%RKv HCPhys=%RHp\n",
290 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
291 SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
292 }
293 RTMemTmpFree(paBadTries);
294 }
295 }
296 if (RT_SUCCESS(rc))
297 {
298 /*
299 * Copy the code.
300 */
301 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
302 {
303 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
304 if (pSwitcher)
305 {
306 uint8_t *pbDst = (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher];
307 memcpy(pbDst, pSwitcher->pvCode, pSwitcher->cbCode);
308# ifdef VBOX_WITH_64ON32_IDT
309 if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
310 || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
311 vmmR3Switcher32On64IdtInit(pVM, pSwitcher, pbDst,
312 pVM->vmm.s.HCPhysCoreCode + pVM->vmm.s.aoffSwitchers[iSwitcher]);
313# endif
314 }
315 }
316
317 /*
318 * Map the code into the GC address space.
319 */
320 RTGCPTR GCPtr;
321 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
322 cbCoreCode, "Core Code", &GCPtr);
323 if (RT_SUCCESS(rc))
324 {
325 pVM->vmm.s.pvCoreCodeRC = GCPtr;
326 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
327 LogRel(("VMM: CoreCode: R3=%RHv R0=%RKv RC=%RRv Phys=%RHp cb=%#x\n",
328 pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
329
330 /*
331 * Finally, PGM probably has selected a switcher already but we need
332 * to get the routine addresses, so we'll reselect it.
333 * This may legally fail so, we're ignoring the rc.
334 * Note! See HMIsEnabled hack in selector function.
335 */
336 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
337 return rc;
338 }
339
340 /* shit */
341 AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
342 SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
343 }
344 else
345 VMSetError(pVM, rc, RT_SRC_POS,
346 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
347 cbCoreCode);
348
349 pVM->vmm.s.pvCoreCodeR3 = NULL;
350 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
351 pVM->vmm.s.pvCoreCodeRC = 0;
352 return rc;
353#endif
354}
355
356/**
357 * Relocate the switchers, called by VMMR#Relocate.
358 *
359 * @param pVM The cross context VM structure.
360 * @param offDelta The relocation delta.
361 */
362void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
363{
364#if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64)
365 /*
366 * Relocate all the switchers.
367 */
368 const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
369 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
370 {
371 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
372 if (pSwitcher && pSwitcher->pfnRelocate)
373 {
374 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
375 pSwitcher->pfnRelocate(pVM,
376 pSwitcher,
377 pVM->vmm.s.pvCoreCodeR0 + off,
378 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
379 pVM->vmm.s.pvCoreCodeRC + off,
380 pVM->vmm.s.HCPhysCoreCode + off);
381# ifdef VBOX_WITH_64ON32_IDT
382 if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
383 || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
384 vmmR3Switcher32On64IdtRelocate(pVM, pSwitcher,
385 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
386 pVM->vmm.s.HCPhysCoreCode + off);
387# endif
388 }
389 }
390
391 /*
392 * Recalc the RC address for the current switcher.
393 */
394 PVMMSWITCHERDEF pSwitcher = papSwitchers[pVM->vmm.s.enmSwitcher];
395 if (pSwitcher)
396 {
397 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
398 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
399 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
400 pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
401 pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
402 }
403 else
404 AssertRelease(HMIsEnabled(pVM));
405
406#else
407 NOREF(pVM);
408#endif
409 NOREF(offDelta);
410}
411
412
413#if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64)
414
415/**
416 * Generic switcher code relocator.
417 *
418 * @param pVM The cross context VM structure.
419 * @param pSwitcher The switcher definition.
420 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
421 * @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
422 * @param GCPtrCode The guest context address corresponding to pu8Code.
423 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
424 * @param SelCS The hypervisor CS selector.
425 * @param SelDS The hypervisor DS selector.
426 * @param SelTSS The hypervisor TSS selector.
427 * @param GCPtrGDT The GC address of the hypervisor GDT.
428 * @param SelCS64 The 64-bit mode hypervisor CS selector.
429 */
430static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher,
431 RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
432 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
433{
434 union
435 {
436 const uint8_t *pu8;
437 const uint16_t *pu16;
438 const uint32_t *pu32;
439 const uint64_t *pu64;
440 const void *pv;
441 uintptr_t u;
442 } u;
443 u.pv = pSwitcher->pvFixups;
444
445 /*
446 * Process fixups.
447 */
448 uint8_t u8;
449 while ((u8 = *u.pu8++) != FIX_THE_END)
450 {
451 /*
452 * Get the source (where to write the fixup).
453 */
454 uint32_t offSrc = *u.pu32++;
455 Assert(offSrc < pSwitcher->cbCode);
456 union
457 {
458 uint8_t *pu8;
459 uint16_t *pu16;
460 uint32_t *pu32;
461 uint64_t *pu64;
462 uintptr_t u;
463 } uSrc;
464 uSrc.pu8 = pu8CodeR3 + offSrc;
465
466 /* The fixup target and method depends on the type. */
467 switch (u8)
468 {
469 /*
470 * 32-bit relative, source in HC and target in GC.
471 */
472 case FIX_HC_2_GC_NEAR_REL:
473 {
474 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
475 uint32_t offTrg = *u.pu32++;
476 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
477 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
478 break;
479 }
480
481 /*
482 * 32-bit relative, source in HC and target in ID.
483 */
484 case FIX_HC_2_ID_NEAR_REL:
485 {
486 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
487 uint32_t offTrg = *u.pu32++;
488 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
489 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
490 break;
491 }
492
493 /*
494 * 32-bit relative, source in GC and target in HC.
495 */
496 case FIX_GC_2_HC_NEAR_REL:
497 {
498 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
499 uint32_t offTrg = *u.pu32++;
500 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
501 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
502 break;
503 }
504
505 /*
506 * 32-bit relative, source in GC and target in ID.
507 */
508 case FIX_GC_2_ID_NEAR_REL:
509 {
510 AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
511 uint32_t offTrg = *u.pu32++;
512 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
513 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
514 break;
515 }
516
517 /*
518 * 32-bit relative, source in ID and target in HC.
519 */
520 case FIX_ID_2_HC_NEAR_REL:
521 {
522 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
523 uint32_t offTrg = *u.pu32++;
524 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
525 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
526 break;
527 }
528
529 /*
530 * 32-bit relative, source in ID and target in HC.
531 */
532 case FIX_ID_2_GC_NEAR_REL:
533 {
534 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
535 uint32_t offTrg = *u.pu32++;
536 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
537 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
538 break;
539 }
540
541 /*
542 * 16:32 far jump, target in GC.
543 */
544 case FIX_GC_FAR32:
545 {
546 uint32_t offTrg = *u.pu32++;
547 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
548 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
549 *uSrc.pu16++ = SelCS;
550 break;
551 }
552
553 /*
554 * Make 32-bit GC pointer given CPUM offset.
555 */
556 case FIX_GC_CPUM_OFF:
557 {
558 uint32_t offCPUM = *u.pu32++;
559 Assert(offCPUM < sizeof(pVM->cpum));
560 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
561 break;
562 }
563
564 /*
565 * Make 32-bit GC pointer given CPUMCPU offset.
566 */
567 case FIX_GC_CPUMCPU_OFF:
568 {
569 uint32_t offCPUM = *u.pu32++;
570 Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
571 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
572 break;
573 }
574
575 /*
576 * Make 32-bit GC pointer given VM offset.
577 */
578 case FIX_GC_VM_OFF:
579 {
580 uint32_t offVM = *u.pu32++;
581 Assert(offVM < sizeof(VM));
582 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
583 break;
584 }
585
586 /*
587 * Make 32-bit HC pointer given CPUM offset.
588 */
589 case FIX_HC_CPUM_OFF:
590 {
591 uint32_t offCPUM = *u.pu32++;
592 Assert(offCPUM < sizeof(pVM->cpum));
593 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
594 break;
595 }
596
597 /*
598 * Make 32-bit R0 pointer given VM offset.
599 */
600 case FIX_HC_VM_OFF:
601 {
602 uint32_t offVM = *u.pu32++;
603 Assert(offVM < sizeof(VM));
604 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
605 break;
606 }
607
608 /*
609 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
610 */
611 case FIX_INTER_32BIT_CR3:
612 {
613
614 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
615 break;
616 }
617
618 /*
619 * Store the PAE CR3 (32-bit) for the intermediate memory context.
620 */
621 case FIX_INTER_PAE_CR3:
622 {
623
624 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
625 break;
626 }
627
628 /*
629 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
630 */
631 case FIX_INTER_AMD64_CR3:
632 {
633
634 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
635 break;
636 }
637
638 /*
639 * Store Hypervisor CS (16-bit).
640 */
641 case FIX_HYPER_CS:
642 {
643 *uSrc.pu16 = SelCS;
644 break;
645 }
646
647 /*
648 * Store Hypervisor DS (16-bit).
649 */
650 case FIX_HYPER_DS:
651 {
652 *uSrc.pu16 = SelDS;
653 break;
654 }
655
656 /*
657 * Store Hypervisor TSS (16-bit).
658 */
659 case FIX_HYPER_TSS:
660 {
661 *uSrc.pu16 = SelTSS;
662 break;
663 }
664
665 /*
666 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
667 */
668 case FIX_GC_TSS_GDTE_DW2:
669 {
670 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
671 *uSrc.pu32 = (uint32_t)GCPtr;
672 break;
673 }
674
675 /*
676 * Store the EFER or mask for the 32->64 bit switcher.
677 */
678 case FIX_EFER_OR_MASK:
679 {
680 uint32_t u32OrMask = MSR_K6_EFER_LME | MSR_K6_EFER_SCE;
681 /*
682 * We don't care if cpuid 0x8000001 isn't supported as that implies
683 * long mode isn't supported either, so this switched would never be used.
684 */
685 if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
686 u32OrMask |= MSR_K6_EFER_NXE;
687
688 *uSrc.pu32 = u32OrMask;
689 break;
690 }
691
692#if 0 /* Reusable for XSAVE. */
693 /*
694 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
695 */
696 case FIX_NO_FXSAVE_JMP:
697 {
698 uint32_t offTrg = *u.pu32++;
699 Assert(offTrg < pSwitcher->cbCode);
700 if (!CPUMSupportsXSave(pVM))
701 {
702 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
703 *uSrc.pu32++ = offTrg - (offSrc + 5);
704 }
705 else
706 {
707 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
708 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
709 }
710 break;
711 }
712#endif
713
714 /*
715 * Insert relative jump to specified target it SYSENTER isn't used by the host.
716 */
717 case FIX_NO_SYSENTER_JMP:
718 {
719 uint32_t offTrg = *u.pu32++;
720 Assert(offTrg < pSwitcher->cbCode);
721 if (!CPUMIsHostUsingSysEnter(pVM))
722 {
723 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
724 *uSrc.pu32++ = offTrg - (offSrc + 5);
725 }
726 else
727 {
728 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
729 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
730 }
731 break;
732 }
733
734 /*
735 * Insert relative jump to specified target it SYSCALL isn't used by the host.
736 */
737 case FIX_NO_SYSCALL_JMP:
738 {
739 uint32_t offTrg = *u.pu32++;
740 Assert(offTrg < pSwitcher->cbCode);
741 if (!CPUMIsHostUsingSysCall(pVM))
742 {
743 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
744 *uSrc.pu32++ = offTrg - (offSrc + 5);
745 }
746 else
747 {
748 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
749 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
750 }
751 break;
752 }
753
754 /*
755 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
756 */
757 case FIX_HC_32BIT:
758 {
759 uint32_t offTrg = *u.pu32++;
760 Assert(offSrc < pSwitcher->cbCode);
761 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
762 *uSrc.pu32 = R0PtrCode + offTrg;
763 break;
764 }
765
766# if defined(RT_ARCH_AMD64)
767 /*
768 * 64-bit HC Code Selector (no argument).
769 */
770 case FIX_HC_64BIT_CS:
771 {
772 Assert(offSrc < pSwitcher->cbCode);
773 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
774 break;
775 }
776
777 /*
778 * 64-bit HC pointer to the CPUM instance data (no argument).
779 */
780 case FIX_HC_64BIT_CPUM:
781 {
782 Assert(offSrc < pSwitcher->cbCode);
783 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
784 break;
785 }
786# endif
787 /*
788 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
789 */
790 case FIX_HC_64BIT:
791 {
792 uint32_t offTrg = *u.pu32++;
793 Assert(offSrc < pSwitcher->cbCode);
794 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
795 *uSrc.pu64 = R0PtrCode + offTrg;
796 break;
797 }
798
799# ifdef RT_ARCH_X86
800 case FIX_GC_64_BIT_CPUM_OFF:
801 {
802 uint32_t offCPUM = *u.pu32++;
803 Assert(offCPUM < sizeof(pVM->cpum));
804 *uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
805 break;
806 }
807# endif
808
809 /*
810 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
811 */
812 case FIX_ID_32BIT:
813 {
814 uint32_t offTrg = *u.pu32++;
815 Assert(offSrc < pSwitcher->cbCode);
816 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
817 *uSrc.pu32 = u32IDCode + offTrg;
818 break;
819 }
820
821 /*
822 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
823 */
824 case FIX_ID_64BIT:
825 case FIX_HC_64BIT_NOCHECK:
826 {
827 uint32_t offTrg = *u.pu32++;
828 Assert(offSrc < pSwitcher->cbCode);
829 Assert(u8 == FIX_HC_64BIT_NOCHECK || offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
830 *uSrc.pu64 = u32IDCode + offTrg;
831 break;
832 }
833
834 /*
835 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
836 */
837 case FIX_ID_FAR32_TO_64BIT_MODE:
838 {
839 uint32_t offTrg = *u.pu32++;
840 Assert(offSrc < pSwitcher->cbCode);
841 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
842 *uSrc.pu32++ = u32IDCode + offTrg;
843 *uSrc.pu16 = SelCS64;
844 AssertRelease(SelCS64);
845 break;
846 }
847
848# ifdef VBOX_WITH_NMI
849 /*
850 * 32-bit address to the APIC base.
851 */
852 case FIX_GC_APIC_BASE_32BIT:
853 {
854 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
855 break;
856 }
857# endif
858
859 default:
860 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
861 break;
862 }
863 }
864
865# ifdef LOG_ENABLED
866 /*
867 * If Log2 is enabled disassemble the switcher code.
868 *
869 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
870 */
871 if (LogIs2Enabled())
872 {
873 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
874 " R0PtrCode = %p\n"
875 " pu8CodeR3 = %p\n"
876 " GCPtrCode = %RGv\n"
877 " u32IDCode = %08x\n"
878 " pVMRC = %RRv\n"
879 " pCPUMRC = %RRv\n"
880 " pVMR3 = %p\n"
881 " pCPUMR3 = %p\n"
882 " GCPtrGDT = %RGv\n"
883 " InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
884 " HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
885 " SelCS = %04x\n"
886 " SelDS = %04x\n"
887 " SelCS64 = %04x\n"
888 " SelTSS = %04x\n",
889 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
890 R0PtrCode,
891 pu8CodeR3,
892 GCPtrCode,
893 u32IDCode,
894 VM_RC_ADDR(pVM, pVM),
895 VM_RC_ADDR(pVM, &pVM->cpum),
896 pVM,
897 &pVM->cpum,
898 GCPtrGDT,
899 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
900 PGMGetHyperCR3(VMMGetCpu(pVM)),
901 SelCS, SelDS, SelCS64, SelTSS);
902
903 uint32_t offCode = 0;
904 while (offCode < pSwitcher->cbCode)
905 {
906 /*
907 * Figure out where this is.
908 */
909 const char *pszDesc = NULL;
910 RTUINTPTR uBase;
911 uint32_t cbCode;
912 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
913 {
914 pszDesc = "HCCode0";
915 uBase = R0PtrCode;
916 offCode = pSwitcher->offHCCode0;
917 cbCode = pSwitcher->cbHCCode0;
918 }
919 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
920 {
921 pszDesc = "HCCode1";
922 uBase = R0PtrCode;
923 offCode = pSwitcher->offHCCode1;
924 cbCode = pSwitcher->cbHCCode1;
925 }
926 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
927 {
928 pszDesc = "GCCode";
929 uBase = GCPtrCode;
930 offCode = pSwitcher->offGCCode;
931 cbCode = pSwitcher->cbGCCode;
932 }
933 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
934 {
935 pszDesc = "IDCode0";
936 uBase = u32IDCode;
937 offCode = pSwitcher->offIDCode0;
938 cbCode = pSwitcher->cbIDCode0;
939 }
940 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
941 {
942 pszDesc = "IDCode1";
943 uBase = u32IDCode;
944 offCode = pSwitcher->offIDCode1;
945 cbCode = pSwitcher->cbIDCode1;
946 }
947 else
948 {
949 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
950 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
951 offCode++;
952 continue;
953 }
954
955 /*
956 * Disassemble it.
957 */
958 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
959
960 while (cbCode > 0)
961 {
962 /* try label it */
963 if (pSwitcher->offR0ToRawMode == offCode)
964 RTLogPrintf(" *R0ToRawMode:\n");
965 if (pSwitcher->offRCToHost == offCode)
966 RTLogPrintf(" *RCToHost:\n");
967 if (pSwitcher->offRCCallTrampoline == offCode)
968 RTLogPrintf(" *RCCallTrampoline:\n");
969 if (pSwitcher->offRCToHostAsm == offCode)
970 RTLogPrintf(" *RCToHostAsm:\n");
971 if (pSwitcher->offRCToHostAsmNoReturn == offCode)
972 RTLogPrintf(" *RCToHostAsmNoReturn:\n");
973
974 /* disas */
975 uint32_t cbInstr = 0;
976 DISCPUSTATE Cpu;
977 char szDisas[256];
978 int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
979 if (RT_SUCCESS(rc))
980 {
981 Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
982 DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
983 DIS_FMT_FLAGS_ADDR_LEFT | DIS_FMT_FLAGS_BYTES_LEFT | DIS_FMT_FLAGS_BYTES_SPACED
984 | DIS_FMT_FLAGS_RELATIVE_BRANCH,
985 NULL, NULL);
986 }
987 if (RT_SUCCESS(rc))
988 RTLogPrintf(" %04x: %s\n", offCode, szDisas);
989 else
990 {
991 RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
992 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
993 cbInstr = 1;
994 }
995 offCode += cbInstr;
996 cbCode -= RT_MIN(cbInstr, cbCode);
997 }
998 }
999 }
1000# endif
1001}
1002
1003/**
1004 * Wrapper around SELMGetHyperGDT() that avoids calling it when raw-mode context
1005 * is not initialized.
1006 *
1007 * @returns Raw-mode contet GDT address. Null pointer if not applicable.
1008 * @param pVM The cross context VM structure.
1009 */
1010static RTRCPTR vmmR3SwitcherGetHyperGDT(PVM pVM)
1011{
1012 if (HMIsRawModeCtxNeeded(pVM))
1013 return SELMGetHyperGDT(pVM);
1014# if HC_ARCH_BITS != 32
1015 AssertFailed(); /* This path is only applicable to some 32-bit hosts. */
1016# endif
1017 return NIL_RTRCPTR;
1018}
1019
1020/**
1021 * Relocator for the 32-Bit to 32-Bit world switcher.
1022 */
1023DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1024{
1025 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1026 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1027}
1028
1029
1030/**
1031 * Relocator for the 32-Bit to PAE world switcher.
1032 */
1033DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1034{
1035 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1036 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1037}
1038
1039
1040/**
1041 * Relocator for the 32-Bit to AMD64 world switcher.
1042 */
1043DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1044{
1045 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1046 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1047}
1048
1049
1050/**
1051 * Relocator for the PAE to 32-Bit world switcher.
1052 */
1053DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1054{
1055 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1056 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1057}
1058
1059
1060/**
1061 * Relocator for the PAE to PAE world switcher.
1062 */
1063DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1064{
1065 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1066 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1067}
1068
1069/**
1070 * Relocator for the PAE to AMD64 world switcher.
1071 */
1072DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1073{
1074 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1075 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1076}
1077
1078
1079/**
1080 * Relocator for the AMD64 to 32-bit world switcher.
1081 */
1082DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1083{
1084 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1085 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1086}
1087
1088
1089/**
1090 * Relocator for the AMD64 to PAE world switcher.
1091 */
1092DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1093{
1094 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1095 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1096}
1097
1098
1099/**
1100 * Selects the switcher to be used for switching to raw-mode context.
1101 *
1102 * @returns VBox status code.
1103 * @param pVM The cross context VM structure.
1104 * @param enmSwitcher The new switcher.
1105 * @remark This function may be called before the VMM is initialized.
1106 */
1107VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1108{
1109 /*
1110 * Validate input.
1111 */
1112 if ( enmSwitcher < VMMSWITCHER_INVALID
1113 || enmSwitcher >= VMMSWITCHER_MAX)
1114 {
1115 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1116 return VERR_INVALID_PARAMETER;
1117 }
1118
1119 /*
1120 * Override it if HM is active.
1121 */
1122 if (HMIsEnabled(pVM))
1123 pVM->vmm.s.enmSwitcher = HC_ARCH_BITS == 64 ? VMMSWITCHER_AMD64_STUB : VMMSWITCHER_X86_STUB;
1124
1125 /*
1126 * Select the new switcher.
1127 */
1128 const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
1129 PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
1130 if (pSwitcher)
1131 {
1132 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1133 pVM->vmm.s.enmSwitcher = enmSwitcher;
1134
1135 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1136 pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
1137
1138 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1139 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
1140 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
1141 pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
1142 pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
1143 return VINF_SUCCESS;
1144 }
1145
1146 return VERR_NOT_IMPLEMENTED;
1147}
1148
1149#endif /* #defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64) */
1150
1151
1152/**
1153 * Gets the switcher to be used for switching to GC.
1154 *
1155 * @returns host to guest ring 0 switcher entrypoint
1156 * @param pVM The cross context VM structure.
1157 * @param enmSwitcher The new switcher.
1158 */
1159VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1160{
1161 /*
1162 * Validate input.
1163 */
1164 AssertMsgReturn( enmSwitcher == VMMSWITCHER_32_TO_AMD64
1165 || enmSwitcher == VMMSWITCHER_PAE_TO_AMD64,
1166 ("%d\n", enmSwitcher),
1167 NIL_RTR0PTR);
1168 AssertReturn(HMIsEnabled(pVM), NIL_RTR0PTR);
1169
1170 /*
1171 * Select the new switcher.
1172 */
1173 const PVMMSWITCHERDEF *papSwitchers = g_apHmSwitchers;
1174 PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
1175 if (pSwitcher)
1176 {
1177 /** @todo fix the pvCoreCodeR0 type */
1178 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1179 return pbCodeR0 + pSwitcher->offR0ToRawMode;
1180 }
1181 return NIL_RTR0PTR;
1182}
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