VMM.cpp@ 47786

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1	/* $Id: VMM.cpp 46861 2013-06-28 10:29:10Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor Core.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	//#define NO_SUPCALLR0VMM
19
20	/** @page pg_vmm VMM - The Virtual Machine Monitor
21	*
22	* The VMM component is two things at the moment, it's a component doing a few
23	* management and routing tasks, and it's the whole virtual machine monitor
24	* thing. For hysterical reasons, it is not doing all the management that one
25	* would expect, this is instead done by @ref pg_vm. We'll address this
26	* misdesign eventually.
27	*
28	* @see grp_vmm, grp_vm
29	*
30	*
31	* @section sec_vmmstate VMM State
32	*
33	* @image html VM_Statechart_Diagram.gif
34	*
35	* To be written.
36	*
37	*
38	* @subsection subsec_vmm_init VMM Initialization
39	*
40	* To be written.
41	*
42	*
43	* @subsection subsec_vmm_term VMM Termination
44	*
45	* To be written.
46	*
47	*
48	* @sections sec_vmm_limits VMM Limits
49	*
50	* There are various resource limits imposed by the VMM and it's
51	* sub-components. We'll list some of them here.
52	*
53	* On 64-bit hosts:
54	* - Max 8191 VMs. Imposed by GVMM's handle allocation (GVMM_MAX_HANDLES),
55	* can be increased up to 64K - 1.
56	* - Max 16TB - 64KB of the host memory can be used for backing VM RAM and
57	* ROM pages. The limit is imposed by the 32-bit page ID used by GMM.
58	* - A VM can be assigned all the memory we can use (16TB), however, the
59	* Main API will restrict this to 2TB (MM_RAM_MAX_IN_MB).
60	* - Max 32 virtual CPUs (VMM_MAX_CPU_COUNT).
61	*
62	* On 32-bit hosts:
63	* - Max 127 VMs. Imposed by GMM's per page structure.
64	* - Max 64GB - 64KB of the host memory can be used for backing VM RAM and
65	* ROM pages. The limit is imposed by the 28-bit page ID used
66	* internally in GMM. It is also limited by PAE.
67	* - A VM can be assigned all the memory GMM can allocate, however, the
68	* Main API will restrict this to 3584MB (MM_RAM_MAX_IN_MB).
69	* - Max 32 virtual CPUs (VMM_MAX_CPU_COUNT).
70	*
71	*/
72
73	/*******************************************************************************
74	* Header Files *
75	*******************************************************************************/
76	#define LOG_GROUP LOG_GROUP_VMM
77	#include <VBox/vmm/vmm.h>
78	#include <VBox/vmm/vmapi.h>
79	#include <VBox/vmm/pgm.h>
80	#include <VBox/vmm/cfgm.h>
81	#include <VBox/vmm/pdmqueue.h>
82	#include <VBox/vmm/pdmcritsect.h>
83	#include <VBox/vmm/pdmcritsectrw.h>
84	#include <VBox/vmm/pdmapi.h>
85	#include <VBox/vmm/cpum.h>
86	#include <VBox/vmm/mm.h>
87	#include <VBox/vmm/iom.h>
88	#include <VBox/vmm/trpm.h>
89	#include <VBox/vmm/selm.h>
90	#include <VBox/vmm/em.h>
91	#include <VBox/sup.h>
92	#include <VBox/vmm/dbgf.h>
93	#include <VBox/vmm/csam.h>
94	#include <VBox/vmm/patm.h>
95	#ifdef VBOX_WITH_REM
96	# include <VBox/vmm/rem.h>
97	#endif
98	#include <VBox/vmm/ssm.h>
99	#include <VBox/vmm/ftm.h>
100	#include <VBox/vmm/tm.h>
101	#include "VMMInternal.h"
102	#include "VMMSwitcher.h"
103	#include <VBox/vmm/vm.h>
104	#include <VBox/vmm/uvm.h>
105
106	#include <VBox/err.h>
107	#include <VBox/param.h>
108	#include <VBox/version.h>
109	#include <VBox/vmm/hm.h>
110	#include <iprt/assert.h>
111	#include <iprt/alloc.h>
112	#include <iprt/asm.h>
113	#include <iprt/time.h>
114	#include <iprt/semaphore.h>
115	#include <iprt/stream.h>
116	#include <iprt/string.h>
117	#include <iprt/stdarg.h>
118	#include <iprt/ctype.h>
119	#include <iprt/x86.h>
120
121
122
123	/*******************************************************************************
124	* Defined Constants And Macros *
125	*******************************************************************************/
126	/** The saved state version. */
127	#define VMM_SAVED_STATE_VERSION 4
128	/** The saved state version used by v3.0 and earlier. (Teleportation) */
129	#define VMM_SAVED_STATE_VERSION_3_0 3
130
131
132	/*******************************************************************************
133	* Internal Functions *
134	*******************************************************************************/
135	static int vmmR3InitStacks(PVM pVM);
136	static int vmmR3InitLoggers(PVM pVM);
137	static void vmmR3InitRegisterStats(PVM pVM);
138	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
139	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
140	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
141	static int vmmR3ServiceCallRing3Request(PVM pVM, PVMCPU pVCpu);
142	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143
144
145	/**
146	* Initializes the VMM.
147	*
148	* @returns VBox status code.
149	* @param pVM Pointer to the VM.
150	*/
151	VMMR3_INT_DECL(int) VMMR3Init(PVM pVM)
152	{
153	LogFlow(("VMMR3Init\n"));
154
155	/*
156	* Assert alignment, sizes and order.
157	*/
158	AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
159	AssertCompile(sizeof(pVM->vmm.s) <= sizeof(pVM->vmm.padding));
160	AssertCompile(sizeof(pVM->aCpus[0].vmm.s) <= sizeof(pVM->aCpus[0].vmm.padding));
161
162	/*
163	* Init basic VM VMM members.
164	*/
165	pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
166	pVM->vmm.s.pahEvtRendezvousEnterOrdered = NULL;
167	pVM->vmm.s.hEvtRendezvousEnterOneByOne = NIL_RTSEMEVENT;
168	pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce = NIL_RTSEMEVENTMULTI;
169	pVM->vmm.s.hEvtMulRendezvousDone = NIL_RTSEMEVENTMULTI;
170	pVM->vmm.s.hEvtRendezvousDoneCaller = NIL_RTSEMEVENT;
171
172	/** @cfgm{YieldEMTInterval, uint32_t, 1, UINT32_MAX, 23, ms}
173	* The EMT yield interval. The EMT yielding is a hack we employ to play a
174	* bit nicer with the rest of the system (like for instance the GUI).
175	*/
176	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies,
177	23 /* Value arrived at after experimenting with the grub boot prompt. */);
178	AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Rrc\n", rc), rc);
179
180
181	/** @cfgm{VMM/UsePeriodicPreemptionTimers, boolean, true}
182	* Controls whether we employ per-cpu preemption timers to limit the time
183	* spent executing guest code. This option is not available on all
184	* platforms and we will silently ignore this setting then. If we are
185	* running in VT-x mode, we will use the VMX-preemption timer instead of
186	* this one when possible.
187	*/
188	PCFGMNODE pCfgVMM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "VMM");
189	rc = CFGMR3QueryBoolDef(pCfgVMM, "UsePeriodicPreemptionTimers", &pVM->vmm.s.fUsePeriodicPreemptionTimers, true);
190	AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"VMM/UsePeriodicPreemptionTimers\", rc=%Rrc\n", rc), rc);
191
192	/*
193	* Initialize the VMM rendezvous semaphores.
194	*/
195	pVM->vmm.s.pahEvtRendezvousEnterOrdered = (PRTSEMEVENT)MMR3HeapAlloc(pVM, MM_TAG_VMM, sizeof(RTSEMEVENT) * pVM->cCpus);
196	if (!pVM->vmm.s.pahEvtRendezvousEnterOrdered)
197	return VERR_NO_MEMORY;
198	for (VMCPUID i = 0; i < pVM->cCpus; i++)
199	pVM->vmm.s.pahEvtRendezvousEnterOrdered[i] = NIL_RTSEMEVENT;
200	for (VMCPUID i = 0; i < pVM->cCpus; i++)
201	{
202	rc = RTSemEventCreate(&pVM->vmm.s.pahEvtRendezvousEnterOrdered[i]);
203	AssertRCReturn(rc, rc);
204	}
205	rc = RTSemEventCreate(&pVM->vmm.s.hEvtRendezvousEnterOneByOne);
206	AssertRCReturn(rc, rc);
207	rc = RTSemEventMultiCreate(&pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce);
208	AssertRCReturn(rc, rc);
209	rc = RTSemEventMultiCreate(&pVM->vmm.s.hEvtMulRendezvousDone);
210	AssertRCReturn(rc, rc);
211	rc = RTSemEventCreate(&pVM->vmm.s.hEvtRendezvousDoneCaller);
212	AssertRCReturn(rc, rc);
213
214	/*
215	* Register the saved state data unit.
216	*/
217	rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
218	NULL, NULL, NULL,
219	NULL, vmmR3Save, NULL,
220	NULL, vmmR3Load, NULL);
221	if (RT_FAILURE(rc))
222	return rc;
223
224	/*
225	* Register the Ring-0 VM handle with the session for fast ioctl calls.
226	*/
227	rc = SUPR3SetVMForFastIOCtl(pVM->pVMR0);
228	if (RT_FAILURE(rc))
229	return rc;
230
231	/*
232	* Init various sub-components.
233	*/
234	rc = vmmR3SwitcherInit(pVM);
235	if (RT_SUCCESS(rc))
236	{
237	rc = vmmR3InitStacks(pVM);
238	if (RT_SUCCESS(rc))
239	{
240	rc = vmmR3InitLoggers(pVM);
241
242	#ifdef VBOX_WITH_NMI
243	/*
244	* Allocate mapping for the host APIC.
245	*/
246	if (RT_SUCCESS(rc))
247	{
248	rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
249	AssertRC(rc);
250	}
251	#endif
252	if (RT_SUCCESS(rc))
253	{
254	/*
255	* Debug info and statistics.
256	*/
257	DBGFR3InfoRegisterInternal(pVM, "fflags", "Displays the current Forced actions Flags.", vmmR3InfoFF);
258	vmmR3InitRegisterStats(pVM);
259	vmmInitFormatTypes();
260
261	return VINF_SUCCESS;
262	}
263	}
264	/** @todo: Need failure cleanup. */
265
266	//more todo in here?
267	//if (RT_SUCCESS(rc))
268	//{
269	//}
270	//int rc2 = vmmR3TermCoreCode(pVM);
271	//AssertRC(rc2));
272	}
273
274	return rc;
275	}
276
277
278	/**
279	* Allocate & setup the VMM RC stack(s) (for EMTs).
280	*
281	* The stacks are also used for long jumps in Ring-0.
282	*
283	* @returns VBox status code.
284	* @param pVM Pointer to the VM.
285	*
286	* @remarks The optional guard page gets it protection setup up during R3 init
287	* completion because of init order issues.
288	*/
289	static int vmmR3InitStacks(PVM pVM)
290	{
291	int rc = VINF_SUCCESS;
292	#ifdef VMM_R0_SWITCH_STACK
293	uint32_t fFlags = MMHYPER_AONR_FLAGS_KERNEL_MAPPING;
294	#else
295	uint32_t fFlags = 0;
296	#endif
297
298	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
299	{
300	PVMCPU pVCpu = &pVM->aCpus[idCpu];
301
302	#ifdef VBOX_STRICT_VMM_STACK
303	rc = MMR3HyperAllocOnceNoRelEx(pVM, PAGE_SIZE + VMM_STACK_SIZE + PAGE_SIZE,
304	#else
305	rc = MMR3HyperAllocOnceNoRelEx(pVM, VMM_STACK_SIZE,
306	#endif
307	PAGE_SIZE, MM_TAG_VMM, fFlags, (void **)&pVCpu->vmm.s.pbEMTStackR3);
308	if (RT_SUCCESS(rc))
309	{
310	#ifdef VBOX_STRICT_VMM_STACK
311	pVCpu->vmm.s.pbEMTStackR3 += PAGE_SIZE;
312	#endif
313	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
314	/* MMHyperR3ToR0 returns R3 when not doing hardware assisted virtualization. */
315	if (!HMIsEnabled(pVM))
316	pVCpu->vmm.s.CallRing3JmpBufR0.pvSavedStack = NIL_RTR0PTR;
317	else
318	#endif
319	pVCpu->vmm.s.CallRing3JmpBufR0.pvSavedStack = MMHyperR3ToR0(pVM, pVCpu->vmm.s.pbEMTStackR3);
320	pVCpu->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVCpu->vmm.s.pbEMTStackR3);
321	pVCpu->vmm.s.pbEMTStackBottomRC = pVCpu->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
322	AssertRelease(pVCpu->vmm.s.pbEMTStackRC);
323
324	CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC);
325	}
326	}
327
328	return rc;
329	}
330
331
332	/**
333	* Initialize the loggers.
334	*
335	* @returns VBox status code.
336	* @param pVM Pointer to the VM.
337	*/
338	static int vmmR3InitLoggers(PVM pVM)
339	{
340	int rc;
341	#define RTLogCalcSizeForR0(cGroups, fFlags) (RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[cGroups]) + PAGE_SIZE)
342
343	/*
344	* Allocate RC & R0 Logger instances (they are finalized in the relocator).
345	*/
346	#ifdef LOG_ENABLED
347	PRTLOGGER pLogger = RTLogDefaultInstance();
348	if (pLogger)
349	{
350	if (!HMIsEnabled(pVM))
351	{
352	pVM->vmm.s.cbRCLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
353	rc = MMR3HyperAllocOnceNoRel(pVM, pVM->vmm.s.cbRCLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCLoggerR3);
354	if (RT_FAILURE(rc))
355	return rc;
356	pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
357	}
358
359	# ifdef VBOX_WITH_R0_LOGGING
360	size_t const cbLogger = RTLogCalcSizeForR0(pLogger->cGroups, 0);
361	for (VMCPUID i = 0; i < pVM->cCpus; i++)
362	{
363	PVMCPU pVCpu = &pVM->aCpus[i];
364	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbLogger, PAGE_SIZE, MM_TAG_VMM, MMHYPER_AONR_FLAGS_KERNEL_MAPPING,
365	(void **)&pVCpu->vmm.s.pR0LoggerR3);
366	if (RT_FAILURE(rc))
367	return rc;
368	pVCpu->vmm.s.pR0LoggerR3->pVM = pVM->pVMR0;
369	//pVCpu->vmm.s.pR0LoggerR3->fCreated = false;
370	pVCpu->vmm.s.pR0LoggerR3->cbLogger = (uint32_t)cbLogger;
371	pVCpu->vmm.s.pR0LoggerR0 = MMHyperR3ToR0(pVM, pVCpu->vmm.s.pR0LoggerR3);
372	}
373	# endif
374	}
375	#endif /* LOG_ENABLED */
376
377	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
378	/*
379	* Allocate RC release logger instances (finalized in the relocator).
380	*/
381	if (!HMIsEnabled(pVM))
382	{
383	PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
384	if (pRelLogger)
385	{
386	pVM->vmm.s.cbRCRelLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
387	rc = MMR3HyperAllocOnceNoRel(pVM, pVM->vmm.s.cbRCRelLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCRelLoggerR3);
388	if (RT_FAILURE(rc))
389	return rc;
390	pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
391	}
392	}
393	#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
394	return VINF_SUCCESS;
395	}
396
397
398	/**
399	* VMMR3Init worker that register the statistics with STAM.
400	*
401	* @param pVM The shared VM structure.
402	*/
403	static void vmmR3InitRegisterStats(PVM pVM)
404	{
405	/*
406	* Statistics.
407	*/
408	STAM_REG(pVM, &pVM->vmm.s.StatRunRC, STAMTYPE_COUNTER, "/VMM/RunRC", STAMUNIT_OCCURENCES, "Number of context switches.");
409	STAM_REG(pVM, &pVM->vmm.s.StatRZRetNormal, STAMTYPE_COUNTER, "/VMM/RZRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
410	STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterrupt, STAMTYPE_COUNTER, "/VMM/RZRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
411	STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
412	STAM_REG(pVM, &pVM->vmm.s.StatRZRetGuestTrap, STAMTYPE_COUNTER, "/VMM/RZRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
413	STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitch, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
414	STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
415	STAM_REG(pVM, &pVM->vmm.s.StatRZRetStaleSelector, STAMTYPE_COUNTER, "/VMM/RZRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
416	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIRETTrap, STAMTYPE_COUNTER, "/VMM/RZRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
417	STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
418	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIOBlockEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/EmulateIOBlock", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_IO_BLOCK returns.");
419	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
420	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIORead, STAMTYPE_COUNTER, "/VMM/RZRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_IOPORT_READ returns.");
421	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_IOPORT_WRITE returns.");
422	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIORead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_MMIO_READ returns.");
423	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_MMIO_WRITE returns.");
424	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_MMIO_READ_WRITE returns.");
425	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
426	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
427	STAM_REG(pVM, &pVM->vmm.s.StatRZRetLDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
428	STAM_REG(pVM, &pVM->vmm.s.StatRZRetGDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
429	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
430	STAM_REG(pVM, &pVM->vmm.s.StatRZRetTSSFault, STAMTYPE_COUNTER, "/VMM/RZRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
431	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPDFault, STAMTYPE_COUNTER, "/VMM/RZRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
432	STAM_REG(pVM, &pVM->vmm.s.StatRZRetCSAMTask, STAMTYPE_COUNTER, "/VMM/RZRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
433	STAM_REG(pVM, &pVM->vmm.s.StatRZRetSyncCR3, STAMTYPE_COUNTER, "/VMM/RZRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
434	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMisc, STAMTYPE_COUNTER, "/VMM/RZRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
435	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchInt3, STAMTYPE_COUNTER, "/VMM/RZRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
436	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchPF, STAMTYPE_COUNTER, "/VMM/RZRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
437	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchGP, STAMTYPE_COUNTER, "/VMM/RZRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
438	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/RZRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
439	STAM_REG(pVM, &pVM->vmm.s.StatRZRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/RZRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
440	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
441	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3Unknown, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Unknown", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
442	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3TMVirt, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/TMVirt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
443	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3HandyPages, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Handy", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
444	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3PDMQueues, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/PDMQueue", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
445	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3Rendezvous, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Rendezvous", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
446	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3Timer, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Timer", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
447	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3DMA, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/DMA", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
448	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3CritSect, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/CritSect", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
449	STAM_REG(pVM, &pVM->vmm.s.StatRZRetTimerPending, STAMTYPE_COUNTER, "/VMM/RZRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
450	STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptPending, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
451	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/RZRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
452	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/RZRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
453	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPGMFlushPending, STAMTYPE_COUNTER, "/VMM/RZRet/PGMFlushPending", STAMUNIT_OCCURENCES, "Number of VINF_PGM_POOL_FLUSH_PENDING returns.");
454	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPendingRequest, STAMTYPE_COUNTER, "/VMM/RZRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
455	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchTPR, STAMTYPE_COUNTER, "/VMM/RZRet/PatchTPR", STAMUNIT_OCCURENCES, "Number of VINF_EM_HM_PATCH_TPR_INSTR returns.");
456	STAM_REG(pVM, &pVM->vmm.s.StatRZRetCallRing3, STAMTYPE_COUNTER, "/VMM/RZCallR3/Misc", STAMUNIT_OCCURENCES, "Number of Other ring-3 calls.");
457	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PDM_LOCK calls.");
458	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMCritSectEnter, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMCritSectEnter", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PDM_CRITSECT_ENTER calls.");
459	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_LOCK calls.");
460	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMPoolGrow", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_POOL_GROW calls.");
461	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMMapChunk, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMMapChunk", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_MAP_CHUNK calls.");
462	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMAllocHandy, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMAllocHandy", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES calls.");
463	STAM_REG(pVM, &pVM->vmm.s.StatRZCallRemReplay, STAMTYPE_COUNTER, "/VMM/RZCallR3/REMReplay", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_REM_REPLAY_HANDLER_NOTIFICATIONS calls.");
464	STAM_REG(pVM, &pVM->vmm.s.StatRZCallLogFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMMLogFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_VMM_LOGGER_FLUSH calls.");
465	STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMSetError", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_VM_SET_ERROR calls.");
466	STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetRuntimeError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMRuntimeError", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_VM_SET_RUNTIME_ERROR calls.");
467
468	#ifdef VBOX_WITH_STATISTICS
469	for (VMCPUID i = 0; i < pVM->cCpus; i++)
470	{
471	STAMR3RegisterF(pVM, &pVM->aCpus[i].vmm.s.CallRing3JmpBufR0.cbUsedMax, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Max amount of stack used.", "/VMM/Stack/CPU%u/Max", i);
472	STAMR3RegisterF(pVM, &pVM->aCpus[i].vmm.s.CallRing3JmpBufR0.cbUsedAvg, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Average stack usage.", "/VMM/Stack/CPU%u/Avg", i);
473	STAMR3RegisterF(pVM, &pVM->aCpus[i].vmm.s.CallRing3JmpBufR0.cUsedTotal, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of stack usages.", "/VMM/Stack/CPU%u/Uses", i);
474	}
475	#endif
476	}
477
478
479	/**
480	* Initializes the R0 VMM.
481	*
482	* @returns VBox status code.
483	* @param pVM Pointer to the VM.
484	*/
485	VMMR3_INT_DECL(int) VMMR3InitR0(PVM pVM)
486	{
487	int rc;
488	PVMCPU pVCpu = VMMGetCpu(pVM);
489	Assert(pVCpu && pVCpu->idCpu == 0);
490
491	#ifdef LOG_ENABLED
492	/*
493	* Initialize the ring-0 logger if we haven't done so yet.
494	*/
495	if ( pVCpu->vmm.s.pR0LoggerR3
496	&& !pVCpu->vmm.s.pR0LoggerR3->fCreated)
497	{
498	rc = VMMR3UpdateLoggers(pVM);
499	if (RT_FAILURE(rc))
500	return rc;
501	}
502	#endif
503
504	/*
505	* Call Ring-0 entry with init code.
506	*/
507	for (;;)
508	{
509	#ifdef NO_SUPCALLR0VMM
510	//rc = VERR_GENERAL_FAILURE;
511	rc = VINF_SUCCESS;
512	#else
513	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_VMMR0_INIT,
514	RT_MAKE_U64(VMMGetSvnRev(), vmmGetBuildType()), NULL);
515	#endif
516	/*
517	* Flush the logs.
518	*/
519	#ifdef LOG_ENABLED
520	if ( pVCpu->vmm.s.pR0LoggerR3
521	&& pVCpu->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
522	RTLogFlushR0(NULL, &pVCpu->vmm.s.pR0LoggerR3->Logger);
523	#endif
524	if (rc != VINF_VMM_CALL_HOST)
525	break;
526	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
527	if (RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
528	break;
529	/* Resume R0 */
530	}
531
532	if (RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
533	{
534	LogRel(("R0 init failed, rc=%Rra\n", rc));
535	if (RT_SUCCESS(rc))
536	rc = VERR_IPE_UNEXPECTED_INFO_STATUS;
537	}
538	return rc;
539	}
540
541
542	#ifdef VBOX_WITH_RAW_MODE
543	/**
544	* Initializes the RC VMM.
545	*
546	* @returns VBox status code.
547	* @param pVM Pointer to the VM.
548	*/
549	VMMR3_INT_DECL(int) VMMR3InitRC(PVM pVM)
550	{
551	PVMCPU pVCpu = VMMGetCpu(pVM);
552	Assert(pVCpu && pVCpu->idCpu == 0);
553
554	/* In VMX mode, there's no need to init RC. */
555	if (HMIsEnabled(pVM))
556	return VINF_SUCCESS;
557
558	AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
559
560	/*
561	* Call VMMGCInit():
562	* -# resolve the address.
563	* -# setup stackframe and EIP to use the trampoline.
564	* -# do a generic hypervisor call.
565	*/
566	RTRCPTR RCPtrEP;
567	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
568	if (RT_SUCCESS(rc))
569	{
570	CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
571	uint64_t u64TS = RTTimeProgramStartNanoTS();
572	CPUMPushHyper(pVCpu, (uint32_t)(u64TS >> 32)); /* Param 4: The program startup TS - Hi. */
573	CPUMPushHyper(pVCpu, (uint32_t)u64TS); /* Param 4: The program startup TS - Lo. */
574	CPUMPushHyper(pVCpu, vmmGetBuildType()); /* Param 3: Version argument. */
575	CPUMPushHyper(pVCpu, VMMGetSvnRev()); /* Param 2: Version argument. */
576	CPUMPushHyper(pVCpu, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
577	CPUMPushHyper(pVCpu, pVM->pVMRC); /* Param 0: pVM */
578	CPUMPushHyper(pVCpu, 6 * sizeof(RTRCPTR)); /* trampoline param: stacksize. */
579	CPUMPushHyper(pVCpu, RCPtrEP); /* Call EIP. */
580	CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
581	Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
582
583	for (;;)
584	{
585	#ifdef NO_SUPCALLR0VMM
586	//rc = VERR_GENERAL_FAILURE;
587	rc = VINF_SUCCESS;
588	#else
589	rc = SUPR3CallVMMR0(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_CALL_HYPERVISOR, NULL);
590	#endif
591	#ifdef LOG_ENABLED
592	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
593	if ( pLogger
594	&& pLogger->offScratch > 0)
595	RTLogFlushRC(NULL, pLogger);
596	#endif
597	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
598	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
599	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
600	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
601	#endif
602	if (rc != VINF_VMM_CALL_HOST)
603	break;
604	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
605	if (RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
606	break;
607	}
608
609	if (RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
610	{
611	VMMR3FatalDump(pVM, pVCpu, rc);
612	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
613	rc = VERR_IPE_UNEXPECTED_INFO_STATUS;
614	}
615	AssertRC(rc);
616	}
617	return rc;
618	}
619	#endif /* VBOX_WITH_RAW_MODE */
620
621
622	/**
623	* Called when an init phase completes.
624	*
625	* @returns VBox status code.
626	* @param pVM Pointer to the VM.
627	* @param enmWhat Which init phase.
628	*/
629	VMMR3_INT_DECL(int) VMMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
630	{
631	int rc = VINF_SUCCESS;
632
633	switch (enmWhat)
634	{
635	case VMINITCOMPLETED_RING3:
636	{
637	/*
638	* CPUM's post-initialization (APIC base MSR caching).
639	*/
640	rc = CPUMR3InitCompleted(pVM);
641	AssertRCReturn(rc, rc);
642
643	/*
644	* Set page attributes to r/w for stack pages.
645	*/
646	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
647	{
648	rc = PGMMapSetPage(pVM, pVM->aCpus[idCpu].vmm.s.pbEMTStackRC, VMM_STACK_SIZE,
649	X86_PTE_P \| X86_PTE_A \| X86_PTE_D \| X86_PTE_RW);
650	AssertRCReturn(rc, rc);
651	}
652
653	/*
654	* Create the EMT yield timer.
655	*/
656	rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
657	AssertRCReturn(rc, rc);
658
659	rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
660	AssertRCReturn(rc, rc);
661
662	#ifdef VBOX_WITH_NMI
663	/*
664	* Map the host APIC into GC - This is AMD/Intel + Host OS specific!
665	*/
666	rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
667	X86_PTE_P \| X86_PTE_RW \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A \| X86_PTE_D);
668	AssertRCReturn(rc, rc);
669	#endif
670
671	#ifdef VBOX_STRICT_VMM_STACK
672	/*
673	* Setup the stack guard pages: Two inaccessible pages at each sides of the
674	* stack to catch over/under-flows.
675	*/
676	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
677	{
678	uint8_t *pbEMTStackR3 = pVM->aCpus[idCpu].vmm.s.pbEMTStackR3;
679
680	memset(pbEMTStackR3 - PAGE_SIZE, 0xcc, PAGE_SIZE);
681	MMR3HyperSetGuard(pVM, pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, true /fSet/);
682
683	memset(pbEMTStackR3 + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
684	MMR3HyperSetGuard(pVM, pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, true /fSet/);
685	}
686	pVM->vmm.s.fStackGuardsStationed = true;
687	#endif
688	break;
689	}
690
691	case VMINITCOMPLETED_HM:
692	{
693	/*
694	* Disable the periodic preemption timers if we can use the
695	* VMX-preemption timer instead.
696	*/
697	if ( pVM->vmm.s.fUsePeriodicPreemptionTimers
698	&& HMR3IsVmxPreemptionTimerUsed(pVM))
699	pVM->vmm.s.fUsePeriodicPreemptionTimers = false;
700	LogRel(("VMM: fUsePeriodicPreemptionTimers=%RTbool\n", pVM->vmm.s.fUsePeriodicPreemptionTimers));
701
702	/*
703	* CPUM's post-initialization (print CPUIDs).
704	*/
705	CPUMR3LogCpuIds(pVM);
706	break;
707	}
708
709	default: /* shuts up gcc */
710	break;
711	}
712
713	return rc;
714	}
715
716
717	/**
718	* Terminate the VMM bits.
719	*
720	* @returns VINF_SUCCESS.
721	* @param pVM Pointer to the VM.
722	*/
723	VMMR3_INT_DECL(int) VMMR3Term(PVM pVM)
724	{
725	PVMCPU pVCpu = VMMGetCpu(pVM);
726	Assert(pVCpu && pVCpu->idCpu == 0);
727
728	/*
729	* Call Ring-0 entry with termination code.
730	*/
731	int rc;
732	for (;;)
733	{
734	#ifdef NO_SUPCALLR0VMM
735	//rc = VERR_GENERAL_FAILURE;
736	rc = VINF_SUCCESS;
737	#else
738	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_VMMR0_TERM, 0, NULL);
739	#endif
740	/*
741	* Flush the logs.
742	*/
743	#ifdef LOG_ENABLED
744	if ( pVCpu->vmm.s.pR0LoggerR3
745	&& pVCpu->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
746	RTLogFlushR0(NULL, &pVCpu->vmm.s.pR0LoggerR3->Logger);
747	#endif
748	if (rc != VINF_VMM_CALL_HOST)
749	break;
750	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
751	if (RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
752	break;
753	/* Resume R0 */
754	}
755	if (RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
756	{
757	LogRel(("VMMR3Term: R0 term failed, rc=%Rra. (warning)\n", rc));
758	if (RT_SUCCESS(rc))
759	rc = VERR_IPE_UNEXPECTED_INFO_STATUS;
760	}
761
762	for (VMCPUID i = 0; i < pVM->cCpus; i++)
763	{
764	RTSemEventDestroy(pVM->vmm.s.pahEvtRendezvousEnterOrdered[i]);
765	pVM->vmm.s.pahEvtRendezvousEnterOrdered[i] = NIL_RTSEMEVENT;
766	}
767	RTSemEventDestroy(pVM->vmm.s.hEvtRendezvousEnterOneByOne);
768	pVM->vmm.s.hEvtRendezvousEnterOneByOne = NIL_RTSEMEVENT;
769	RTSemEventMultiDestroy(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce);
770	pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce = NIL_RTSEMEVENTMULTI;
771	RTSemEventMultiDestroy(pVM->vmm.s.hEvtMulRendezvousDone);
772	pVM->vmm.s.hEvtMulRendezvousDone = NIL_RTSEMEVENTMULTI;
773	RTSemEventDestroy(pVM->vmm.s.hEvtRendezvousDoneCaller);
774	pVM->vmm.s.hEvtRendezvousDoneCaller = NIL_RTSEMEVENT;
775
776	#ifdef VBOX_STRICT_VMM_STACK
777	/*
778	* Make the two stack guard pages present again.
779	*/
780	if (pVM->vmm.s.fStackGuardsStationed)
781	{
782	for (VMCPUID i = 0; i < pVM->cCpus; i++)
783	{
784	uint8_t *pbEMTStackR3 = pVM->aCpus[i].vmm.s.pbEMTStackR3;
785	MMR3HyperSetGuard(pVM, pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, false /fSet/);
786	MMR3HyperSetGuard(pVM, pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, false /fSet/);
787	}
788	pVM->vmm.s.fStackGuardsStationed = false;
789	}
790	#endif
791
792	vmmTermFormatTypes();
793	return rc;
794	}
795
796
797	/**
798	* Applies relocations to data and code managed by this
799	* component. This function will be called at init and
800	* whenever the VMM need to relocate it self inside the GC.
801	*
802	* The VMM will need to apply relocations to the core code.
803	*
804	* @param pVM Pointer to the VM.
805	* @param offDelta The relocation delta.
806	*/
807	VMMR3_INT_DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
808	{
809	LogFlow(("VMMR3Relocate: offDelta=%RGv\n", offDelta));
810
811	/*
812	* Recalc the RC address.
813	*/
814	#ifdef VBOX_WITH_RAW_MODE
815	pVM->vmm.s.pvCoreCodeRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pvCoreCodeR3);
816	#endif
817
818	/*
819	* The stack.
820	*/
821	for (VMCPUID i = 0; i < pVM->cCpus; i++)
822	{
823	PVMCPU pVCpu = &pVM->aCpus[i];
824
825	CPUMSetHyperESP(pVCpu, CPUMGetHyperESP(pVCpu) + offDelta);
826
827	pVCpu->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVCpu->vmm.s.pbEMTStackR3);
828	pVCpu->vmm.s.pbEMTStackBottomRC = pVCpu->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
829	}
830
831	/*
832	* All the switchers.
833	*/
834	vmmR3SwitcherRelocate(pVM, offDelta);
835
836	/*
837	* Get other RC entry points.
838	*/
839	if (!HMIsEnabled(pVM))
840	{
841	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMRCResumeGuest);
842	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Rra\n", rc));
843
844	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMRCResumeGuestV86);
845	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Rra\n", rc));
846	}
847
848	/*
849	* Update the logger.
850	*/
851	VMMR3UpdateLoggers(pVM);
852	}
853
854
855	/**
856	* Updates the settings for the RC and R0 loggers.
857	*
858	* @returns VBox status code.
859	* @param pVM Pointer to the VM.
860	*/
861	VMMR3_INT_DECL(int) VMMR3UpdateLoggers(PVM pVM)
862	{
863	/*
864	* Simply clone the logger instance (for RC).
865	*/
866	int rc = VINF_SUCCESS;
867	RTRCPTR RCPtrLoggerFlush = 0;
868
869	if ( pVM->vmm.s.pRCLoggerR3
870	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
871	\|\| pVM->vmm.s.pRCRelLoggerR3
872	#endif
873	)
874	{
875	Assert(!HMIsEnabled(pVM));
876	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &RCPtrLoggerFlush);
877	AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Rra\n", rc));
878	}
879
880	if (pVM->vmm.s.pRCLoggerR3)
881	{
882	Assert(!HMIsEnabled(pVM));
883	RTRCPTR RCPtrLoggerWrapper = 0;
884	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &RCPtrLoggerWrapper);
885	AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Rra\n", rc));
886
887	pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
888	rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pRCLoggerR3, pVM->vmm.s.cbRCLogger,
889	RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
890	AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Rra\n", rc));
891	}
892
893	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
894	if (pVM->vmm.s.pRCRelLoggerR3)
895	{
896	Assert(!HMIsEnabled(pVM));
897	RTRCPTR RCPtrLoggerWrapper = 0;
898	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &RCPtrLoggerWrapper);
899	AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Rra\n", rc));
900
901	pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
902	rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRCRelLoggerR3, pVM->vmm.s.cbRCRelLogger,
903	RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
904	AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Rra\n", rc));
905	}
906	#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
907
908	#ifdef LOG_ENABLED
909	/*
910	* For the ring-0 EMT logger, we use a per-thread logger instance
911	* in ring-0. Only initialize it once.
912	*/
913	PRTLOGGER const pDefault = RTLogDefaultInstance();
914	for (VMCPUID i = 0; i < pVM->cCpus; i++)
915	{
916	PVMCPU pVCpu = &pVM->aCpus[i];
917	PVMMR0LOGGER pR0LoggerR3 = pVCpu->vmm.s.pR0LoggerR3;
918	if (pR0LoggerR3)
919	{
920	if (!pR0LoggerR3->fCreated)
921	{
922	RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
923	rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
924	AssertReleaseMsgRCReturn(rc, ("vmmR0LoggerWrapper not found! rc=%Rra\n", rc), rc);
925
926	RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
927	rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
928	AssertReleaseMsgRCReturn(rc, ("vmmR0LoggerFlush not found! rc=%Rra\n", rc), rc);
929
930	rc = RTLogCreateForR0(&pR0LoggerR3->Logger, pR0LoggerR3->cbLogger,
931	pVCpu->vmm.s.pR0LoggerR0 + RT_OFFSETOF(VMMR0LOGGER, Logger),
932	pfnLoggerWrapper, pfnLoggerFlush,
933	RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
934	AssertReleaseMsgRCReturn(rc, ("RTLogCreateForR0 failed! rc=%Rra\n", rc), rc);
935
936	RTR0PTR pfnLoggerPrefix = NIL_RTR0PTR;
937	rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerPrefix", &pfnLoggerPrefix);
938	AssertReleaseMsgRCReturn(rc, ("vmmR0LoggerPrefix not found! rc=%Rra\n", rc), rc);
939	rc = RTLogSetCustomPrefixCallbackForR0(&pR0LoggerR3->Logger,
940	pVCpu->vmm.s.pR0LoggerR0 + RT_OFFSETOF(VMMR0LOGGER, Logger),
941	pfnLoggerPrefix, NIL_RTR0PTR);
942	AssertReleaseMsgRCReturn(rc, ("RTLogSetCustomPrefixCallback failed! rc=%Rra\n", rc), rc);
943
944	pR0LoggerR3->idCpu = i;
945	pR0LoggerR3->fCreated = true;
946	pR0LoggerR3->fFlushingDisabled = false;
947
948	}
949
950	rc = RTLogCopyGroupsAndFlagsForR0(&pR0LoggerR3->Logger, pVCpu->vmm.s.pR0LoggerR0 + RT_OFFSETOF(VMMR0LOGGER, Logger),
951	pDefault, RTLOGFLAGS_BUFFERED, UINT32_MAX);
952	AssertRC(rc);
953	}
954	}
955	#endif
956	return rc;
957	}
958
959
960	/**
961	* Gets the pointer to a buffer containing the R0/RC RTAssertMsg1Weak output.
962	*
963	* @returns Pointer to the buffer.
964	* @param pVM Pointer to the VM.
965	*/
966	VMMR3DECL(const char *) VMMR3GetRZAssertMsg1(PVM pVM)
967	{
968	if (HMIsEnabled(pVM))
969	return pVM->vmm.s.szRing0AssertMsg1;
970
971	RTRCPTR RCPtr;
972	int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg1", &RCPtr);
973	if (RT_SUCCESS(rc))
974	return (const char *)MMHyperRCToR3(pVM, RCPtr);
975
976	return NULL;
977	}
978
979
980	/**
981	* Returns the VMCPU of the specified virtual CPU.
982	*
983	* @returns The VMCPU pointer. NULL if @a idCpu or @a pUVM is invalid.
984	*
985	* @param pUVM The user mode VM handle.
986	* @param idCpu The ID of the virtual CPU.
987	*/
988	VMMR3DECL(PVMCPU) VMMR3GetCpuByIdU(PUVM pUVM, RTCPUID idCpu)
989	{
990	UVM_ASSERT_VALID_EXT_RETURN(pUVM, NULL);
991	AssertReturn(idCpu < pUVM->cCpus, NULL);
992	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, NULL);
993	return &pUVM->pVM->aCpus[idCpu];
994	}
995
996
997	/**
998	* Gets the pointer to a buffer containing the R0/RC RTAssertMsg2Weak output.
999	*
1000	* @returns Pointer to the buffer.
1001	* @param pVM Pointer to the VM.
1002	*/
1003	VMMR3DECL(const char *) VMMR3GetRZAssertMsg2(PVM pVM)
1004	{
1005	if (HMIsEnabled(pVM))
1006	return pVM->vmm.s.szRing0AssertMsg2;
1007
1008	RTRCPTR RCPtr;
1009	int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg2", &RCPtr);
1010	if (RT_SUCCESS(rc))
1011	return (const char *)MMHyperRCToR3(pVM, RCPtr);
1012
1013	return NULL;
1014	}
1015
1016
1017	/**
1018	* Execute state save operation.
1019	*
1020	* @returns VBox status code.
1021	* @param pVM Pointer to the VM.
1022	* @param pSSM SSM operation handle.
1023	*/
1024	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1025	{
1026	LogFlow(("vmmR3Save:\n"));
1027
1028	/*
1029	* Save the started/stopped state of all CPUs except 0 as it will always
1030	* be running. This avoids breaking the saved state version. :-)
1031	*/
1032	for (VMCPUID i = 1; i < pVM->cCpus; i++)
1033	SSMR3PutBool(pSSM, VMCPUSTATE_IS_STARTED(VMCPU_GET_STATE(&pVM->aCpus[i])));
1034
1035	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1036	}
1037
1038
1039	/**
1040	* Execute state load operation.
1041	*
1042	* @returns VBox status code.
1043	* @param pVM Pointer to the VM.
1044	* @param pSSM SSM operation handle.
1045	* @param uVersion Data layout version.
1046	* @param uPass The data pass.
1047	*/
1048	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1049	{
1050	LogFlow(("vmmR3Load:\n"));
1051	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1052
1053	/*
1054	* Validate version.
1055	*/
1056	if ( uVersion != VMM_SAVED_STATE_VERSION
1057	&& uVersion != VMM_SAVED_STATE_VERSION_3_0)
1058	{
1059	AssertMsgFailed(("vmmR3Load: Invalid version uVersion=%u!\n", uVersion));
1060	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1061	}
1062
1063	if (uVersion <= VMM_SAVED_STATE_VERSION_3_0)
1064	{
1065	/* Ignore the stack bottom, stack pointer and stack bits. */
1066	RTRCPTR RCPtrIgnored;
1067	SSMR3GetRCPtr(pSSM, &RCPtrIgnored);
1068	SSMR3GetRCPtr(pSSM, &RCPtrIgnored);
1069	#ifdef RT_OS_DARWIN
1070	if ( SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(3,0,0)
1071	&& SSMR3HandleVersion(pSSM) < VBOX_FULL_VERSION_MAKE(3,1,0)
1072	&& SSMR3HandleRevision(pSSM) >= 48858
1073	&& ( !strcmp(SSMR3HandleHostOSAndArch(pSSM), "darwin.x86")
1074	\|\| !strcmp(SSMR3HandleHostOSAndArch(pSSM), "") )
1075	)
1076	SSMR3Skip(pSSM, 16384);
1077	else
1078	SSMR3Skip(pSSM, 8192);
1079	#else
1080	SSMR3Skip(pSSM, 8192);
1081	#endif
1082	}
1083
1084	/*
1085	* Restore the VMCPU states. VCPU 0 is always started.
1086	*/
1087	VMCPU_SET_STATE(&pVM->aCpus[0], VMCPUSTATE_STARTED);
1088	for (VMCPUID i = 1; i < pVM->cCpus; i++)
1089	{
1090	bool fStarted;
1091	int rc = SSMR3GetBool(pSSM, &fStarted);
1092	if (RT_FAILURE(rc))
1093	return rc;
1094	VMCPU_SET_STATE(&pVM->aCpus[i], fStarted ? VMCPUSTATE_STARTED : VMCPUSTATE_STOPPED);
1095	}
1096
1097	/* terminator */
1098	uint32_t u32;
1099	int rc = SSMR3GetU32(pSSM, &u32);
1100	if (RT_FAILURE(rc))
1101	return rc;
1102	if (u32 != UINT32_MAX)
1103	{
1104	AssertMsgFailed(("u32=%#x\n", u32));
1105	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1106	}
1107	return VINF_SUCCESS;
1108	}
1109
1110
1111	#ifdef VBOX_WITH_RAW_MODE
1112	/**
1113	* Resolve a builtin RC symbol.
1114	*
1115	* Called by PDM when loading or relocating RC modules.
1116	*
1117	* @returns VBox status
1118	* @param pVM Pointer to the VM.
1119	* @param pszSymbol Symbol to resolv
1120	* @param pRCPtrValue Where to store the symbol value.
1121	*
1122	* @remark This has to work before VMMR3Relocate() is called.
1123	*/
1124	VMMR3_INT_DECL(int) VMMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
1125	{
1126	if (!strcmp(pszSymbol, "g_Logger"))
1127	{
1128	if (pVM->vmm.s.pRCLoggerR3)
1129	pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
1130	*pRCPtrValue = pVM->vmm.s.pRCLoggerRC;
1131	}
1132	else if (!strcmp(pszSymbol, "g_RelLogger"))
1133	{
1134	# ifdef VBOX_WITH_RC_RELEASE_LOGGING
1135	if (pVM->vmm.s.pRCRelLoggerR3)
1136	pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
1137	*pRCPtrValue = pVM->vmm.s.pRCRelLoggerRC;
1138	# else
1139	*pRCPtrValue = NIL_RTRCPTR;
1140	# endif
1141	}
1142	else
1143	return VERR_SYMBOL_NOT_FOUND;
1144	return VINF_SUCCESS;
1145	}
1146	#endif /* VBOX_WITH_RAW_MODE */
1147
1148
1149	/**
1150	* Suspends the CPU yielder.
1151	*
1152	* @param pVM Pointer to the VM.
1153	*/
1154	VMMR3_INT_DECL(void) VMMR3YieldSuspend(PVM pVM)
1155	{
1156	VMCPU_ASSERT_EMT(&pVM->aCpus[0]);
1157	if (!pVM->vmm.s.cYieldResumeMillies)
1158	{
1159	uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1160	uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1161	if (u64Now >= u64Expire \|\| u64Expire == ~(uint64_t)0)
1162	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1163	else
1164	pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1165	TMTimerStop(pVM->vmm.s.pYieldTimer);
1166	}
1167	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1168	}
1169
1170
1171	/**
1172	* Stops the CPU yielder.
1173	*
1174	* @param pVM Pointer to the VM.
1175	*/
1176	VMMR3_INT_DECL(void) VMMR3YieldStop(PVM pVM)
1177	{
1178	if (!pVM->vmm.s.cYieldResumeMillies)
1179	TMTimerStop(pVM->vmm.s.pYieldTimer);
1180	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1181	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1182	}
1183
1184
1185	/**
1186	* Resumes the CPU yielder when it has been a suspended or stopped.
1187	*
1188	* @param pVM Pointer to the VM.
1189	*/
1190	VMMR3_INT_DECL(void) VMMR3YieldResume(PVM pVM)
1191	{
1192	if (pVM->vmm.s.cYieldResumeMillies)
1193	{
1194	TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1195	pVM->vmm.s.cYieldResumeMillies = 0;
1196	}
1197	}
1198
1199
1200	/**
1201	* Internal timer callback function.
1202	*
1203	* @param pVM The VM.
1204	* @param pTimer The timer handle.
1205	* @param pvUser User argument specified upon timer creation.
1206	*/
1207	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1208	{
1209	NOREF(pvUser);
1210
1211	/*
1212	* This really needs some careful tuning. While we shouldn't be too greedy since
1213	* that'll cause the rest of the system to stop up, we shouldn't be too nice either
1214	* because that'll cause us to stop up.
1215	*
1216	* The current logic is to use the default interval when there is no lag worth
1217	* mentioning, but when we start accumulating lag we don't bother yielding at all.
1218	*
1219	* (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1220	* so the lag is up to date.)
1221	*/
1222	const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1223	if ( u64Lag < 50000000 /* 50ms */
1224	\|\| ( u64Lag < 1000000000 /* 1s */
1225	&& RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1226	)
1227	{
1228	uint64_t u64Elapsed = RTTimeNanoTS();
1229	pVM->vmm.s.u64LastYield = u64Elapsed;
1230
1231	RTThreadYield();
1232
1233	#ifdef LOG_ENABLED
1234	u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1235	Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1236	#endif
1237	}
1238	TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1239	}
1240
1241
1242	#ifdef VBOX_WITH_RAW_MODE
1243	/**
1244	* Executes guest code in the raw-mode context.
1245	*
1246	* @param pVM Pointer to the VM.
1247	* @param pVCpu Pointer to the VMCPU.
1248	*/
1249	VMMR3_INT_DECL(int) VMMR3RawRunGC(PVM pVM, PVMCPU pVCpu)
1250	{
1251	Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1252
1253	AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
1254
1255	/*
1256	* Set the hypervisor to resume executing a CPUM resume function
1257	* in CPUMRCA.asm.
1258	*/
1259	CPUMSetHyperState(pVCpu,
1260	CPUMGetGuestEFlags(pVCpu) & X86_EFL_VM
1261	? pVM->vmm.s.pfnCPUMRCResumeGuestV86
1262	: pVM->vmm.s.pfnCPUMRCResumeGuest, /* eip */
1263	pVCpu->vmm.s.pbEMTStackBottomRC, /* esp */
1264	0, /* eax */
1265	VM_RC_ADDR(pVM, &pVCpu->cpum) /* edx */);
1266
1267	/*
1268	* We hide log flushes (outer) and hypervisor interrupts (inner).
1269	*/
1270	for (;;)
1271	{
1272	#ifdef VBOX_STRICT
1273	if (RT_UNLIKELY(!CPUMGetHyperCR3(pVCpu) \|\| CPUMGetHyperCR3(pVCpu) != PGMGetHyperCR3(pVCpu)))
1274	EMR3FatalError(pVCpu, VERR_VMM_HYPER_CR3_MISMATCH);
1275	PGMMapCheck(pVM);
1276	# ifdef VBOX_WITH_SAFE_STR
1277	SELMR3CheckShadowTR(pVM);
1278	# endif
1279	#endif
1280	int rc;
1281	do
1282	{
1283	#ifdef NO_SUPCALLR0VMM
1284	rc = VERR_GENERAL_FAILURE;
1285	#else
1286	rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
1287	if (RT_LIKELY(rc == VINF_SUCCESS))
1288	rc = pVCpu->vmm.s.iLastGZRc;
1289	#endif
1290	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1291
1292	/*
1293	* Flush the logs.
1294	*/
1295	#ifdef LOG_ENABLED
1296	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
1297	if ( pLogger
1298	&& pLogger->offScratch > 0)
1299	RTLogFlushRC(NULL, pLogger);
1300	#endif
1301	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1302	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
1303	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1304	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
1305	#endif
1306	if (rc != VINF_VMM_CALL_HOST)
1307	{
1308	Log2(("VMMR3RawRunGC: returns %Rrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1309	return rc;
1310	}
1311	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
1312	if (RT_FAILURE(rc))
1313	return rc;
1314	/* Resume GC */
1315	}
1316	}
1317	#endif /* VBOX_WITH_RAW_MODE */
1318
1319
1320	/**
1321	* Executes guest code (Intel VT-x and AMD-V).
1322	*
1323	* @param pVM Pointer to the VM.
1324	* @param pVCpu Pointer to the VMCPU.
1325	*/
1326	VMMR3_INT_DECL(int) VMMR3HmRunGC(PVM pVM, PVMCPU pVCpu)
1327	{
1328	Log2(("VMMR3HmRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1329
1330	for (;;)
1331	{
1332	int rc;
1333	do
1334	{
1335	#ifdef NO_SUPCALLR0VMM
1336	rc = VERR_GENERAL_FAILURE;
1337	#else
1338	rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HM_RUN, pVCpu->idCpu);
1339	if (RT_LIKELY(rc == VINF_SUCCESS))
1340	rc = pVCpu->vmm.s.iLastGZRc;
1341	#endif
1342	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1343
1344	#if 0 /* todo triggers too often */
1345	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TO_R3));
1346	#endif
1347
1348	#ifdef LOG_ENABLED
1349	/*
1350	* Flush the log
1351	*/
1352	PVMMR0LOGGER pR0LoggerR3 = pVCpu->vmm.s.pR0LoggerR3;
1353	if ( pR0LoggerR3
1354	&& pR0LoggerR3->Logger.offScratch > 0)
1355	RTLogFlushR0(NULL, &pR0LoggerR3->Logger);
1356	#endif /* !LOG_ENABLED */
1357	if (rc != VINF_VMM_CALL_HOST)
1358	{
1359	Log2(("VMMR3HmRunGC: returns %Rrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1360	return rc;
1361	}
1362	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
1363	if (RT_FAILURE(rc))
1364	return rc;
1365	/* Resume R0 */
1366	}
1367	}
1368
1369	/**
1370	* VCPU worker for VMMSendSipi.
1371	*
1372	* @param pVM Pointer to the VM.
1373	* @param idCpu Virtual CPU to perform SIPI on
1374	* @param uVector SIPI vector
1375	*/
1376	DECLCALLBACK(int) vmmR3SendSipi(PVM pVM, VMCPUID idCpu, uint32_t uVector)
1377	{
1378	PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1379	VMCPU_ASSERT_EMT(pVCpu);
1380
1381	/** @todo what are we supposed to do if the processor is already running? */
1382	if (EMGetState(pVCpu) != EMSTATE_WAIT_SIPI)
1383	return VERR_ACCESS_DENIED;
1384
1385
1386	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1387
1388	pCtx->cs.Sel = uVector << 8;
1389	pCtx->cs.ValidSel = uVector << 8;
1390	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1391	pCtx->cs.u64Base = uVector << 12;
1392	pCtx->cs.u32Limit = UINT32_C(0x0000ffff);
1393	pCtx->rip = 0;
1394
1395	Log(("vmmR3SendSipi for VCPU %d with vector %x\n", idCpu, uVector));
1396
1397	# if 1 /* If we keep the EMSTATE_WAIT_SIPI method, then move this to EM.cpp. */
1398	EMSetState(pVCpu, EMSTATE_HALTED);
1399	return VINF_EM_RESCHEDULE;
1400	# else /* And if we go the VMCPU::enmState way it can stay here. */
1401	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STOPPED);
1402	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1403	return VINF_SUCCESS;
1404	# endif
1405	}
1406
1407	DECLCALLBACK(int) vmmR3SendInitIpi(PVM pVM, VMCPUID idCpu)
1408	{
1409	PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1410	VMCPU_ASSERT_EMT(pVCpu);
1411
1412	Log(("vmmR3SendInitIpi for VCPU %d\n", idCpu));
1413
1414	PGMR3ResetCpu(pVM, pVCpu);
1415	CPUMR3ResetCpu(pVCpu);
1416
1417	return VINF_EM_WAIT_SIPI;
1418	}
1419
1420	/**
1421	* Sends SIPI to the virtual CPU by setting CS:EIP into vector-dependent state
1422	* and unhalting processor
1423	*
1424	* @param pVM Pointer to the VM.
1425	* @param idCpu Virtual CPU to perform SIPI on
1426	* @param uVector SIPI vector
1427	*/
1428	VMMR3_INT_DECL(void) VMMR3SendSipi(PVM pVM, VMCPUID idCpu, uint32_t uVector)
1429	{
1430	AssertReturnVoid(idCpu < pVM->cCpus);
1431
1432	int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendSipi, 3, pVM, idCpu, uVector);
1433	AssertRC(rc);
1434	}
1435
1436	/**
1437	* Sends init IPI to the virtual CPU.
1438	*
1439	* @param pVM Pointer to the VM.
1440	* @param idCpu Virtual CPU to perform int IPI on
1441	*/
1442	VMMR3_INT_DECL(void) VMMR3SendInitIpi(PVM pVM, VMCPUID idCpu)
1443	{
1444	AssertReturnVoid(idCpu < pVM->cCpus);
1445
1446	int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendInitIpi, 2, pVM, idCpu);
1447	AssertRC(rc);
1448	}
1449
1450	/**
1451	* Registers the guest memory range that can be used for patching
1452	*
1453	* @returns VBox status code.
1454	* @param pVM Pointer to the VM.
1455	* @param pPatchMem Patch memory range
1456	* @param cbPatchMem Size of the memory range
1457	*/
1458	VMMR3DECL(int) VMMR3RegisterPatchMemory(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1459	{
1460	VM_ASSERT_EMT(pVM);
1461	if (HMIsEnabled(pVM))
1462	return HMR3EnablePatching(pVM, pPatchMem, cbPatchMem);
1463
1464	return VERR_NOT_SUPPORTED;
1465	}
1466
1467	/**
1468	* Deregisters the guest memory range that can be used for patching
1469	*
1470	* @returns VBox status code.
1471	* @param pVM Pointer to the VM.
1472	* @param pPatchMem Patch memory range
1473	* @param cbPatchMem Size of the memory range
1474	*/
1475	VMMR3DECL(int) VMMR3DeregisterPatchMemory(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1476	{
1477	if (HMIsEnabled(pVM))
1478	return HMR3DisablePatching(pVM, pPatchMem, cbPatchMem);
1479
1480	return VINF_SUCCESS;
1481	}
1482
1483
1484	/**
1485	* Count returns and have the last non-caller EMT wake up the caller.
1486	*
1487	* @returns VBox strict informational status code for EM scheduling. No failures
1488	* will be returned here, those are for the caller only.
1489	*
1490	* @param pVM Pointer to the VM.
1491	*/
1492	DECL_FORCE_INLINE(int) vmmR3EmtRendezvousNonCallerReturn(PVM pVM)
1493	{
1494	int rcRet = ASMAtomicReadS32(&pVM->vmm.s.i32RendezvousStatus);
1495	uint32_t cReturned = ASMAtomicIncU32(&pVM->vmm.s.cRendezvousEmtsReturned);
1496	if (cReturned == pVM->cCpus - 1U)
1497	{
1498	int rc = RTSemEventSignal(pVM->vmm.s.hEvtRendezvousDoneCaller);
1499	AssertLogRelRC(rc);
1500	}
1501
1502	AssertLogRelMsgReturn( rcRet <= VINF_SUCCESS
1503	\|\| (rcRet >= VINF_EM_FIRST && rcRet <= VINF_EM_LAST),
1504	("%Rrc\n", rcRet),
1505	VERR_IPE_UNEXPECTED_INFO_STATUS);
1506	return RT_SUCCESS(rcRet) ? rcRet : VINF_SUCCESS;
1507	}
1508
1509
1510	/**
1511	* Common worker for VMMR3EmtRendezvous and VMMR3EmtRendezvousFF.
1512	*
1513	* @returns VBox strict informational status code for EM scheduling. No failures
1514	* will be returned here, those are for the caller only. When
1515	* fIsCaller is set, VINF_SUCCESS is always returned.
1516	*
1517	* @param pVM Pointer to the VM.
1518	* @param pVCpu The VMCPU structure for the calling EMT.
1519	* @param fIsCaller Whether we're the VMMR3EmtRendezvous caller or
1520	* not.
1521	* @param fFlags The flags.
1522	* @param pfnRendezvous The callback.
1523	* @param pvUser The user argument for the callback.
1524	*/
1525	static int vmmR3EmtRendezvousCommon(PVM pVM, PVMCPU pVCpu, bool fIsCaller,
1526	uint32_t fFlags, PFNVMMEMTRENDEZVOUS pfnRendezvous, void *pvUser)
1527	{
1528	int rc;
1529
1530	/*
1531	* Enter, the last EMT triggers the next callback phase.
1532	*/
1533	uint32_t cEntered = ASMAtomicIncU32(&pVM->vmm.s.cRendezvousEmtsEntered);
1534	if (cEntered != pVM->cCpus)
1535	{
1536	if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE)
1537	{
1538	/* Wait for our turn. */
1539	rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousEnterOneByOne, RT_INDEFINITE_WAIT);
1540	AssertLogRelRC(rc);
1541	}
1542	else if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE)
1543	{
1544	/* Wait for the last EMT to arrive and wake everyone up. */
1545	rc = RTSemEventMultiWait(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce, RT_INDEFINITE_WAIT);
1546	AssertLogRelRC(rc);
1547	}
1548	else if ( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING
1549	\|\| (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING)
1550	{
1551	/* Wait for our turn. */
1552	rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu], RT_INDEFINITE_WAIT);
1553	AssertLogRelRC(rc);
1554	}
1555	else
1556	{
1557	Assert((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE);
1558
1559	/*
1560	* The execute once is handled specially to optimize the code flow.
1561	*
1562	* The last EMT to arrive will perform the callback and the other
1563	* EMTs will wait on the Done/DoneCaller semaphores (instead of
1564	* the EnterOneByOne/AllAtOnce) in the meanwhile. When the callback
1565	* returns, that EMT will initiate the normal return sequence.
1566	*/
1567	if (!fIsCaller)
1568	{
1569	rc = RTSemEventMultiWait(pVM->vmm.s.hEvtMulRendezvousDone, RT_INDEFINITE_WAIT);
1570	AssertLogRelRC(rc);
1571
1572	return vmmR3EmtRendezvousNonCallerReturn(pVM);
1573	}
1574	return VINF_SUCCESS;
1575	}
1576	}
1577	else
1578	{
1579	/*
1580	* All EMTs are waiting, clear the FF and take action according to the
1581	* execution method.
1582	*/
1583	VM_FF_CLEAR(pVM, VM_FF_EMT_RENDEZVOUS);
1584
1585	if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE)
1586	{
1587	/* Wake up everyone. */
1588	rc = RTSemEventMultiSignal(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce);
1589	AssertLogRelRC(rc);
1590	}
1591	else if ( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING
1592	\|\| (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING)
1593	{
1594	/* Figure out who to wake up and wake it up. If it's ourself, then
1595	it's easy otherwise wait for our turn. */
1596	VMCPUID iFirst = (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING
1597	? 0
1598	: pVM->cCpus - 1U;
1599	if (pVCpu->idCpu != iFirst)
1600	{
1601	rc = RTSemEventSignal(pVM->vmm.s.pahEvtRendezvousEnterOrdered[iFirst]);
1602	AssertLogRelRC(rc);
1603	rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu], RT_INDEFINITE_WAIT);
1604	AssertLogRelRC(rc);
1605	}
1606	}
1607	/* else: execute the handler on the current EMT and wake up one or more threads afterwards. */
1608	}
1609
1610
1611	/*
1612	* Do the callback and update the status if necessary.
1613	*/
1614	if ( !(fFlags & VMMEMTRENDEZVOUS_FLAGS_STOP_ON_ERROR)
1615	\|\| RT_SUCCESS(ASMAtomicUoReadS32(&pVM->vmm.s.i32RendezvousStatus)) )
1616	{
1617	VBOXSTRICTRC rcStrict = pfnRendezvous(pVM, pVCpu, pvUser);
1618	if (rcStrict != VINF_SUCCESS)
1619	{
1620	AssertLogRelMsg( rcStrict <= VINF_SUCCESS
1621	\|\| (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST),
1622	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1623	int32_t i32RendezvousStatus;
1624	do
1625	{
1626	i32RendezvousStatus = ASMAtomicUoReadS32(&pVM->vmm.s.i32RendezvousStatus);
1627	if ( rcStrict == i32RendezvousStatus
1628	\|\| RT_FAILURE(i32RendezvousStatus)
1629	\|\| ( i32RendezvousStatus != VINF_SUCCESS
1630	&& rcStrict > i32RendezvousStatus))
1631	break;
1632	} while (!ASMAtomicCmpXchgS32(&pVM->vmm.s.i32RendezvousStatus, VBOXSTRICTRC_VAL(rcStrict), i32RendezvousStatus));
1633	}
1634	}
1635
1636	/*
1637	* Increment the done counter and take action depending on whether we're
1638	* the last to finish callback execution.
1639	*/
1640	uint32_t cDone = ASMAtomicIncU32(&pVM->vmm.s.cRendezvousEmtsDone);
1641	if ( cDone != pVM->cCpus
1642	&& (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE)
1643	{
1644	/* Signal the next EMT? */
1645	if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE)
1646	{
1647	rc = RTSemEventSignal(pVM->vmm.s.hEvtRendezvousEnterOneByOne);
1648	AssertLogRelRC(rc);
1649	}
1650	else if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING)
1651	{
1652	Assert(cDone == pVCpu->idCpu + 1U);
1653	rc = RTSemEventSignal(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu + 1U]);
1654	AssertLogRelRC(rc);
1655	}
1656	else if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING)
1657	{
1658	Assert(pVM->cCpus - cDone == pVCpu->idCpu);
1659	rc = RTSemEventSignal(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVM->cCpus - cDone - 1U]);
1660	AssertLogRelRC(rc);
1661	}
1662
1663	/* Wait for the rest to finish (the caller waits on hEvtRendezvousDoneCaller). */
1664	if (!fIsCaller)
1665	{
1666	rc = RTSemEventMultiWait(pVM->vmm.s.hEvtMulRendezvousDone, RT_INDEFINITE_WAIT);
1667	AssertLogRelRC(rc);
1668	}
1669	}
1670	else
1671	{
1672	/* Callback execution is all done, tell the rest to return. */
1673	rc = RTSemEventMultiSignal(pVM->vmm.s.hEvtMulRendezvousDone);
1674	AssertLogRelRC(rc);
1675	}
1676
1677	if (!fIsCaller)
1678	return vmmR3EmtRendezvousNonCallerReturn(pVM);
1679	return VINF_SUCCESS;
1680	}
1681
1682
1683	/**
1684	* Called in response to VM_FF_EMT_RENDEZVOUS.
1685	*
1686	* @returns VBox strict status code - EM scheduling. No errors will be returned
1687	* here, nor will any non-EM scheduling status codes be returned.
1688	*
1689	* @param pVM Pointer to the VM.
1690	* @param pVCpu The handle of the calling EMT.
1691	*
1692	* @thread EMT
1693	*/
1694	VMMR3_INT_DECL(int) VMMR3EmtRendezvousFF(PVM pVM, PVMCPU pVCpu)
1695	{
1696	Assert(!pVCpu->vmm.s.fInRendezvous);
1697	pVCpu->vmm.s.fInRendezvous = true;
1698	int rc = vmmR3EmtRendezvousCommon(pVM, pVCpu, false /* fIsCaller */, pVM->vmm.s.fRendezvousFlags,
1699	pVM->vmm.s.pfnRendezvous, pVM->vmm.s.pvRendezvousUser);
1700	pVCpu->vmm.s.fInRendezvous = false;
1701	return rc;
1702	}
1703
1704
1705	/**
1706	* EMT rendezvous.
1707	*
1708	* Gathers all the EMTs and execute some code on each of them, either in a one
1709	* by one fashion or all at once.
1710	*
1711	* @returns VBox strict status code. This will be the first error,
1712	* VINF_SUCCESS, or an EM scheduling status code.
1713	*
1714	* @param pVM Pointer to the VM.
1715	* @param fFlags Flags indicating execution methods. See
1716	* grp_VMMR3EmtRendezvous_fFlags.
1717	* @param pfnRendezvous The callback.
1718	* @param pvUser User argument for the callback.
1719	*
1720	* @thread Any.
1721	*/
1722	VMMR3DECL(int) VMMR3EmtRendezvous(PVM pVM, uint32_t fFlags, PFNVMMEMTRENDEZVOUS pfnRendezvous, void *pvUser)
1723	{
1724	/*
1725	* Validate input.
1726	*/
1727	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1728	AssertMsg( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_INVALID
1729	&& (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) <= VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING
1730	&& !(fFlags & ~VMMEMTRENDEZVOUS_FLAGS_VALID_MASK), ("%#x\n", fFlags));
1731	AssertMsg( !(fFlags & VMMEMTRENDEZVOUS_FLAGS_STOP_ON_ERROR)
1732	\|\| ( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE
1733	&& (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE),
1734	("type %u\n", fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK));
1735
1736	VBOXSTRICTRC rcStrict;
1737	PVMCPU pVCpu = VMMGetCpu(pVM);
1738	if (!pVCpu)
1739	/*
1740	* Forward the request to an EMT thread.
1741	*/
1742	rcStrict = VMR3ReqCallWait(pVM, VMCPUID_ANY,
1743	(PFNRT)VMMR3EmtRendezvous, 4, pVM, fFlags, pfnRendezvous, pvUser);
1744	else if (pVM->cCpus == 1)
1745	{
1746	/*
1747	* Shortcut for the single EMT case.
1748	*/
1749	AssertLogRelReturn(!pVCpu->vmm.s.fInRendezvous, VERR_DEADLOCK);
1750	pVCpu->vmm.s.fInRendezvous = true;
1751	rcStrict = pfnRendezvous(pVM, pVCpu, pvUser);
1752	pVCpu->vmm.s.fInRendezvous = false;
1753	}
1754	else
1755	{
1756	/*
1757	* Spin lock. If busy, wait for the other EMT to finish while keeping a
1758	* lookout of the RENDEZVOUS FF.
1759	*/
1760	int rc;
1761	rcStrict = VINF_SUCCESS;
1762	if (RT_UNLIKELY(!ASMAtomicCmpXchgU32(&pVM->vmm.s.u32RendezvousLock, 0x77778888, 0)))
1763	{
1764	AssertLogRelReturn(!pVCpu->vmm.s.fInRendezvous, VERR_DEADLOCK);
1765
1766	while (!ASMAtomicCmpXchgU32(&pVM->vmm.s.u32RendezvousLock, 0x77778888, 0))
1767	{
1768	if (VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1769	{
1770	rc = VMMR3EmtRendezvousFF(pVM, pVCpu);
1771	if ( rc != VINF_SUCCESS
1772	&& ( rcStrict == VINF_SUCCESS
1773	\|\| rcStrict > rc))
1774	rcStrict = rc;
1775	/** @todo Perhaps deal with termination here? */
1776	}
1777	ASMNopPause();
1778	}
1779	}
1780	Assert(!VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS));
1781	Assert(!pVCpu->vmm.s.fInRendezvous);
1782	pVCpu->vmm.s.fInRendezvous = true;
1783
1784	/*
1785	* Clear the slate. This is a semaphore ping-pong orgy. :-)
1786	*/
1787	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1788	{
1789	rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[i], 0);
1790	AssertLogRelMsg(rc == VERR_TIMEOUT \|\| rc == VINF_SUCCESS, ("%Rrc\n", rc));
1791	}
1792	rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousEnterOneByOne, 0); AssertLogRelMsg(rc == VERR_TIMEOUT \|\| rc == VINF_SUCCESS, ("%Rrc\n", rc));
1793	rc = RTSemEventMultiReset(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce); AssertLogRelRC(rc);
1794	rc = RTSemEventMultiReset(pVM->vmm.s.hEvtMulRendezvousDone); AssertLogRelRC(rc);
1795	rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousDoneCaller, 0); AssertLogRelMsg(rc == VERR_TIMEOUT \|\| rc == VINF_SUCCESS, ("%Rrc\n", rc));
1796	ASMAtomicWriteU32(&pVM->vmm.s.cRendezvousEmtsEntered, 0);
1797	ASMAtomicWriteU32(&pVM->vmm.s.cRendezvousEmtsDone, 0);
1798	ASMAtomicWriteU32(&pVM->vmm.s.cRendezvousEmtsReturned, 0);
1799	ASMAtomicWriteS32(&pVM->vmm.s.i32RendezvousStatus, VINF_SUCCESS);
1800	ASMAtomicWritePtr((void * volatile )&pVM->vmm.s.pfnRendezvous, (void )(uintptr_t)pfnRendezvous);
1801	ASMAtomicWritePtr(&pVM->vmm.s.pvRendezvousUser, pvUser);
1802	ASMAtomicWriteU32(&pVM->vmm.s.fRendezvousFlags, fFlags);
1803
1804	/*
1805	* Set the FF and poke the other EMTs.
1806	*/
1807	VM_FF_SET(pVM, VM_FF_EMT_RENDEZVOUS);
1808	VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_POKE);
1809
1810	/*
1811	* Do the same ourselves.
1812	*/
1813	vmmR3EmtRendezvousCommon(pVM, pVCpu, true /* fIsCaller */, fFlags, pfnRendezvous, pvUser);
1814
1815	/*
1816	* The caller waits for the other EMTs to be done and return before doing
1817	* the cleanup. This makes away with wakeup / reset races we would otherwise
1818	* risk in the multiple release event semaphore code (hEvtRendezvousDoneCaller).
1819	*/
1820	rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousDoneCaller, RT_INDEFINITE_WAIT);
1821	AssertLogRelRC(rc);
1822
1823	/*
1824	* Get the return code and clean up a little bit.
1825	*/
1826	int rcMy = pVM->vmm.s.i32RendezvousStatus;
1827	ASMAtomicWriteNullPtr((void * volatile *)&pVM->vmm.s.pfnRendezvous);
1828
1829	ASMAtomicWriteU32(&pVM->vmm.s.u32RendezvousLock, 0);
1830	pVCpu->vmm.s.fInRendezvous = false;
1831
1832	/*
1833	* Merge rcStrict and rcMy.
1834	*/
1835	AssertRC(VBOXSTRICTRC_VAL(rcStrict));
1836	if ( rcMy != VINF_SUCCESS
1837	&& ( rcStrict == VINF_SUCCESS
1838	\|\| rcStrict > rcMy))
1839	rcStrict = rcMy;
1840	}
1841
1842	AssertLogRelMsgReturn( rcStrict <= VINF_SUCCESS
1843	\|\| (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST),
1844	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
1845	VERR_IPE_UNEXPECTED_INFO_STATUS);
1846	return VBOXSTRICTRC_VAL(rcStrict);
1847	}
1848
1849
1850	/**
1851	* Disables/enables EMT rendezvous.
1852	*
1853	* This is used to make sure EMT rendezvous does not take place while
1854	* processing a priority request.
1855	*
1856	* @returns Old rendezvous-disabled state.
1857	* @param pVCpu The handle of the calling EMT.
1858	* @param fDisabled True if disabled, false if enabled.
1859	*/
1860	VMMR3_INT_DECL(bool) VMMR3EmtRendezvousSetDisabled(PVMCPU pVCpu, bool fDisabled)
1861	{
1862	VMCPU_ASSERT_EMT(pVCpu);
1863	bool fOld = pVCpu->vmm.s.fInRendezvous;
1864	pVCpu->vmm.s.fInRendezvous = fDisabled;
1865	return fOld;
1866	}
1867
1868
1869	/**
1870	* Read from the ring 0 jump buffer stack
1871	*
1872	* @returns VBox status code.
1873	*
1874	* @param pVM Pointer to the VM.
1875	* @param idCpu The ID of the source CPU context (for the address).
1876	* @param R0Addr Where to start reading.
1877	* @param pvBuf Where to store the data we've read.
1878	* @param cbRead The number of bytes to read.
1879	*/
1880	VMMR3_INT_DECL(int) VMMR3ReadR0Stack(PVM pVM, VMCPUID idCpu, RTHCUINTPTR R0Addr, void *pvBuf, size_t cbRead)
1881	{
1882	PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1883	AssertReturn(pVCpu, VERR_INVALID_PARAMETER);
1884
1885	#ifdef VMM_R0_SWITCH_STACK
1886	RTHCUINTPTR off = R0Addr - MMHyperCCToR0(pVM, pVCpu->vmm.s.pbEMTStackR3);
1887	#else
1888	RTHCUINTPTR off = pVCpu->vmm.s.CallRing3JmpBufR0.cbSavedStack - (pVCpu->vmm.s.CallRing3JmpBufR0.SpCheck - R0Addr);
1889	#endif
1890	if ( off > VMM_STACK_SIZE
1891	\|\| off + cbRead >= VMM_STACK_SIZE)
1892	return VERR_INVALID_POINTER;
1893
1894	memcpy(pvBuf, &pVCpu->vmm.s.pbEMTStackR3[off], cbRead);
1895	return VINF_SUCCESS;
1896	}
1897
1898	#ifdef VBOX_WITH_RAW_MODE
1899
1900	/**
1901	* Calls a RC function.
1902	*
1903	* @param pVM Pointer to the VM.
1904	* @param RCPtrEntry The address of the RC function.
1905	* @param cArgs The number of arguments in the ....
1906	* @param ... Arguments to the function.
1907	*/
1908	VMMR3DECL(int) VMMR3CallRC(PVM pVM, RTRCPTR RCPtrEntry, unsigned cArgs, ...)
1909	{
1910	va_list args;
1911	va_start(args, cArgs);
1912	int rc = VMMR3CallRCV(pVM, RCPtrEntry, cArgs, args);
1913	va_end(args);
1914	return rc;
1915	}
1916
1917
1918	/**
1919	* Calls a RC function.
1920	*
1921	* @param pVM Pointer to the VM.
1922	* @param RCPtrEntry The address of the RC function.
1923	* @param cArgs The number of arguments in the ....
1924	* @param args Arguments to the function.
1925	*/
1926	VMMR3DECL(int) VMMR3CallRCV(PVM pVM, RTRCPTR RCPtrEntry, unsigned cArgs, va_list args)
1927	{
1928	/* Raw mode implies 1 VCPU. */
1929	AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
1930	PVMCPU pVCpu = &pVM->aCpus[0];
1931
1932	Log2(("VMMR3CallGCV: RCPtrEntry=%RRv cArgs=%d\n", RCPtrEntry, cArgs));
1933
1934	/*
1935	* Setup the call frame using the trampoline.
1936	*/
1937	CPUMSetHyperState(pVCpu,
1938	pVM->vmm.s.pfnCallTrampolineRC, /* eip */
1939	pVCpu->vmm.s.pbEMTStackBottomRC - cArgs * sizeof(RTGCUINTPTR32), /* esp */
1940	RCPtrEntry, /* eax */
1941	cArgs /* edx */
1942	);
1943
1944	memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
1945	PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVCpu->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE) - cArgs;
1946	int i = cArgs;
1947	while (i-- > 0)
1948	*pFrame++ = va_arg(args, RTGCUINTPTR32);
1949
1950	CPUMPushHyper(pVCpu, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
1951	CPUMPushHyper(pVCpu, RCPtrEntry); /* what to call */
1952
1953	/*
1954	* We hide log flushes (outer) and hypervisor interrupts (inner).
1955	*/
1956	for (;;)
1957	{
1958	int rc;
1959	Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
1960	do
1961	{
1962	#ifdef NO_SUPCALLR0VMM
1963	rc = VERR_GENERAL_FAILURE;
1964	#else
1965	rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
1966	if (RT_LIKELY(rc == VINF_SUCCESS))
1967	rc = pVCpu->vmm.s.iLastGZRc;
1968	#endif
1969	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1970
1971	/*
1972	* Flush the loggers.
1973	*/
1974	#ifdef LOG_ENABLED
1975	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
1976	if ( pLogger
1977	&& pLogger->offScratch > 0)
1978	RTLogFlushRC(NULL, pLogger);
1979	#endif
1980	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1981	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
1982	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1983	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
1984	#endif
1985	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
1986	VMMR3FatalDump(pVM, pVCpu, rc);
1987	if (rc != VINF_VMM_CALL_HOST)
1988	{
1989	Log2(("VMMR3CallGCV: returns %Rrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1990	return rc;
1991	}
1992	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
1993	if (RT_FAILURE(rc))
1994	return rc;
1995	}
1996	}
1997
1998	#endif /* VBOX_WITH_RAW_MODE */
1999
2000	/**
2001	* Wrapper for SUPR3CallVMMR0Ex which will deal with VINF_VMM_CALL_HOST returns.
2002	*
2003	* @returns VBox status code.
2004	* @param pVM Pointer to the VM.
2005	* @param uOperation Operation to execute.
2006	* @param u64Arg Constant argument.
2007	* @param pReqHdr Pointer to a request header. See SUPR3CallVMMR0Ex for
2008	* details.
2009	*/
2010	VMMR3DECL(int) VMMR3CallR0(PVM pVM, uint32_t uOperation, uint64_t u64Arg, PSUPVMMR0REQHDR pReqHdr)
2011	{
2012	PVMCPU pVCpu = VMMGetCpu(pVM);
2013	AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
2014
2015	/*
2016	* Call Ring-0 entry with init code.
2017	*/
2018	int rc;
2019	for (;;)
2020	{
2021	#ifdef NO_SUPCALLR0VMM
2022	rc = VERR_GENERAL_FAILURE;
2023	#else
2024	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, uOperation, u64Arg, pReqHdr);
2025	#endif
2026	/*
2027	* Flush the logs.
2028	*/
2029	#ifdef LOG_ENABLED
2030	if ( pVCpu->vmm.s.pR0LoggerR3
2031	&& pVCpu->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
2032	RTLogFlushR0(NULL, &pVCpu->vmm.s.pR0LoggerR3->Logger);
2033	#endif
2034	if (rc != VINF_VMM_CALL_HOST)
2035	break;
2036	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
2037	if (RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
2038	break;
2039	/* Resume R0 */
2040	}
2041
2042	AssertLogRelMsgReturn(rc == VINF_SUCCESS \|\| RT_FAILURE(rc),
2043	("uOperation=%u rc=%Rrc\n", uOperation, rc),
2044	VERR_IPE_UNEXPECTED_INFO_STATUS);
2045	return rc;
2046	}
2047
2048
2049	#ifdef VBOX_WITH_RAW_MODE
2050	/**
2051	* Resumes executing hypervisor code when interrupted by a queue flush or a
2052	* debug event.
2053	*
2054	* @returns VBox status code.
2055	* @param pVM Pointer to the VM.
2056	* @param pVCpu Pointer to the VMCPU.
2057	*/
2058	VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM, PVMCPU pVCpu)
2059	{
2060	Log(("VMMR3ResumeHyper: eip=%RRv esp=%RRv\n", CPUMGetHyperEIP(pVCpu), CPUMGetHyperESP(pVCpu)));
2061	AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
2062
2063	/*
2064	* We hide log flushes (outer) and hypervisor interrupts (inner).
2065	*/
2066	for (;;)
2067	{
2068	int rc;
2069	Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
2070	do
2071	{
2072	# ifdef NO_SUPCALLR0VMM
2073	rc = VERR_GENERAL_FAILURE;
2074	# else
2075	rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
2076	if (RT_LIKELY(rc == VINF_SUCCESS))
2077	rc = pVCpu->vmm.s.iLastGZRc;
2078	# endif
2079	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2080
2081	/*
2082	* Flush the loggers.
2083	*/
2084	# ifdef LOG_ENABLED
2085	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2086	if ( pLogger
2087	&& pLogger->offScratch > 0)
2088	RTLogFlushRC(NULL, pLogger);
2089	# endif
2090	# ifdef VBOX_WITH_RC_RELEASE_LOGGING
2091	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2092	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2093	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2094	# endif
2095	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2096	VMMR3FatalDump(pVM, pVCpu, rc);
2097	if (rc != VINF_VMM_CALL_HOST)
2098	{
2099	Log(("VMMR3ResumeHyper: returns %Rrc\n", rc));
2100	return rc;
2101	}
2102	rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
2103	if (RT_FAILURE(rc))
2104	return rc;
2105	}
2106	}
2107	#endif /* VBOX_WITH_RAW_MODE */
2108
2109
2110	/**
2111	* Service a call to the ring-3 host code.
2112	*
2113	* @returns VBox status code.
2114	* @param pVM Pointer to the VM.
2115	* @param pVCpu Pointer to the VMCPU.
2116	* @remark Careful with critsects.
2117	*/
2118	static int vmmR3ServiceCallRing3Request(PVM pVM, PVMCPU pVCpu)
2119	{
2120	/*
2121	* We must also check for pending critsect exits or else we can deadlock
2122	* when entering other critsects here.
2123	*/
2124	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
2125	PDMCritSectBothFF(pVCpu);
2126
2127	switch (pVCpu->vmm.s.enmCallRing3Operation)
2128	{
2129	/*
2130	* Acquire a critical section.
2131	*/
2132	case VMMCALLRING3_PDM_CRIT_SECT_ENTER:
2133	{
2134	pVCpu->vmm.s.rcCallRing3 = PDMR3CritSectEnterEx((PPDMCRITSECT)(uintptr_t)pVCpu->vmm.s.u64CallRing3Arg,
2135	true /fCallRing3/);
2136	break;
2137	}
2138
2139	/*
2140	* Enter a r/w critical section exclusively.
2141	*/
2142	case VMMCALLRING3_PDM_CRIT_SECT_RW_ENTER_EXCL:
2143	{
2144	pVCpu->vmm.s.rcCallRing3 = PDMR3CritSectRwEnterExclEx((PPDMCRITSECTRW)(uintptr_t)pVCpu->vmm.s.u64CallRing3Arg,
2145	true /fCallRing3/);
2146	break;
2147	}
2148
2149	/*
2150	* Enter a r/w critical section shared.
2151	*/
2152	case VMMCALLRING3_PDM_CRIT_SECT_RW_ENTER_SHARED:
2153	{
2154	pVCpu->vmm.s.rcCallRing3 = PDMR3CritSectRwEnterSharedEx((PPDMCRITSECTRW)(uintptr_t)pVCpu->vmm.s.u64CallRing3Arg,
2155	true /fCallRing3/);
2156	break;
2157	}
2158
2159	/*
2160	* Acquire the PDM lock.
2161	*/
2162	case VMMCALLRING3_PDM_LOCK:
2163	{
2164	pVCpu->vmm.s.rcCallRing3 = PDMR3LockCall(pVM);
2165	break;
2166	}
2167
2168	/*
2169	* Grow the PGM pool.
2170	*/
2171	case VMMCALLRING3_PGM_POOL_GROW:
2172	{
2173	pVCpu->vmm.s.rcCallRing3 = PGMR3PoolGrow(pVM);
2174	break;
2175	}
2176
2177	/*
2178	* Maps an page allocation chunk into ring-3 so ring-0 can use it.
2179	*/
2180	case VMMCALLRING3_PGM_MAP_CHUNK:
2181	{
2182	pVCpu->vmm.s.rcCallRing3 = PGMR3PhysChunkMap(pVM, pVCpu->vmm.s.u64CallRing3Arg);
2183	break;
2184	}
2185
2186	/*
2187	* Allocates more handy pages.
2188	*/
2189	case VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES:
2190	{
2191	pVCpu->vmm.s.rcCallRing3 = PGMR3PhysAllocateHandyPages(pVM);
2192	break;
2193	}
2194
2195	/*
2196	* Allocates a large page.
2197	*/
2198	case VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE:
2199	{
2200	pVCpu->vmm.s.rcCallRing3 = PGMR3PhysAllocateLargeHandyPage(pVM, pVCpu->vmm.s.u64CallRing3Arg);
2201	break;
2202	}
2203
2204	/*
2205	* Acquire the PGM lock.
2206	*/
2207	case VMMCALLRING3_PGM_LOCK:
2208	{
2209	pVCpu->vmm.s.rcCallRing3 = PGMR3LockCall(pVM);
2210	break;
2211	}
2212
2213	/*
2214	* Acquire the MM hypervisor heap lock.
2215	*/
2216	case VMMCALLRING3_MMHYPER_LOCK:
2217	{
2218	pVCpu->vmm.s.rcCallRing3 = MMR3LockCall(pVM);
2219	break;
2220	}
2221
2222	#ifdef VBOX_WITH_REM
2223	/*
2224	* Flush REM handler notifications.
2225	*/
2226	case VMMCALLRING3_REM_REPLAY_HANDLER_NOTIFICATIONS:
2227	{
2228	REMR3ReplayHandlerNotifications(pVM);
2229	pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2230	break;
2231	}
2232	#endif
2233
2234	/*
2235	* This is a noop. We just take this route to avoid unnecessary
2236	* tests in the loops.
2237	*/
2238	case VMMCALLRING3_VMM_LOGGER_FLUSH:
2239	pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2240	LogAlways(("FLUSH\n"));
2241	break;
2242
2243	/*
2244	* Set the VM error message.
2245	*/
2246	case VMMCALLRING3_VM_SET_ERROR:
2247	VMR3SetErrorWorker(pVM);
2248	pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2249	break;
2250
2251	/*
2252	* Set the VM runtime error message.
2253	*/
2254	case VMMCALLRING3_VM_SET_RUNTIME_ERROR:
2255	pVCpu->vmm.s.rcCallRing3 = VMR3SetRuntimeErrorWorker(pVM);
2256	break;
2257
2258	/*
2259	* Signal a ring 0 hypervisor assertion.
2260	* Cancel the longjmp operation that's in progress.
2261	*/
2262	case VMMCALLRING3_VM_R0_ASSERTION:
2263	pVCpu->vmm.s.enmCallRing3Operation = VMMCALLRING3_INVALID;
2264	pVCpu->vmm.s.CallRing3JmpBufR0.fInRing3Call = false;
2265	#ifdef RT_ARCH_X86
2266	pVCpu->vmm.s.CallRing3JmpBufR0.eip = 0;
2267	#else
2268	pVCpu->vmm.s.CallRing3JmpBufR0.rip = 0;
2269	#endif
2270	#ifdef VMM_R0_SWITCH_STACK
2271	(uint64_t )pVCpu->vmm.s.pbEMTStackR3 = 0; /* clear marker */
2272	#endif
2273	LogRel(("%s", pVM->vmm.s.szRing0AssertMsg1));
2274	LogRel(("%s", pVM->vmm.s.szRing0AssertMsg2));
2275	return VERR_VMM_RING0_ASSERTION;
2276
2277	/*
2278	* A forced switch to ring 0 for preemption purposes.
2279	*/
2280	case VMMCALLRING3_VM_R0_PREEMPT:
2281	pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2282	break;
2283
2284	case VMMCALLRING3_FTM_SET_CHECKPOINT:
2285	pVCpu->vmm.s.rcCallRing3 = FTMR3SetCheckpoint(pVM, (FTMCHECKPOINTTYPE)pVCpu->vmm.s.u64CallRing3Arg);
2286	break;
2287
2288	default:
2289	AssertMsgFailed(("enmCallRing3Operation=%d\n", pVCpu->vmm.s.enmCallRing3Operation));
2290	return VERR_VMM_UNKNOWN_RING3_CALL;
2291	}
2292
2293	pVCpu->vmm.s.enmCallRing3Operation = VMMCALLRING3_INVALID;
2294	return VINF_SUCCESS;
2295	}
2296
2297
2298	/**
2299	* Displays the Force action Flags.
2300	*
2301	* @param pVM Pointer to the VM.
2302	* @param pHlp The output helpers.
2303	* @param pszArgs The additional arguments (ignored).
2304	*/
2305	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2306	{
2307	int c;
2308	uint32_t f;
2309	NOREF(pszArgs);
2310
2311	#define PRINT_FLAG(prf,flag) do { \
2312	if (f & (prf##flag)) \
2313	{ \
2314	static const char *s_psz = #flag; \
2315	if (!(c % 6)) \
2316	pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz); \
2317	else \
2318	pHlp->pfnPrintf(pHlp, ", %s", s_psz); \
2319	c++; \
2320	f &= ~(prf##flag); \
2321	} \
2322	} while (0)
2323
2324	#define PRINT_GROUP(prf,grp,sfx) do { \
2325	if (f & (prf##grp##sfx)) \
2326	{ \
2327	static const char *s_psz = #grp; \
2328	if (!(c % 5)) \
2329	pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : " Groups:\n", s_psz); \
2330	else \
2331	pHlp->pfnPrintf(pHlp, ", %s", s_psz); \
2332	c++; \
2333	} \
2334	} while (0)
2335
2336	/*
2337	* The global flags.
2338	*/
2339	const uint32_t fGlobalForcedActions = pVM->fGlobalForcedActions;
2340	pHlp->pfnPrintf(pHlp, "Global FFs: %#RX32", fGlobalForcedActions);
2341
2342	/* show the flag mnemonics */
2343	c = 0;
2344	f = fGlobalForcedActions;
2345	PRINT_FLAG(VM_FF_,TM_VIRTUAL_SYNC);
2346	PRINT_FLAG(VM_FF_,PDM_QUEUES);
2347	PRINT_FLAG(VM_FF_,PDM_DMA);
2348	PRINT_FLAG(VM_FF_,DBGF);
2349	PRINT_FLAG(VM_FF_,REQUEST);
2350	PRINT_FLAG(VM_FF_,CHECK_VM_STATE);
2351	PRINT_FLAG(VM_FF_,RESET);
2352	PRINT_FLAG(VM_FF_,EMT_RENDEZVOUS);
2353	PRINT_FLAG(VM_FF_,PGM_NEED_HANDY_PAGES);
2354	PRINT_FLAG(VM_FF_,PGM_NO_MEMORY);
2355	PRINT_FLAG(VM_FF_,PGM_POOL_FLUSH_PENDING);
2356	PRINT_FLAG(VM_FF_,REM_HANDLER_NOTIFY);
2357	PRINT_FLAG(VM_FF_,DEBUG_SUSPEND);
2358	if (f)
2359	pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2360	else
2361	pHlp->pfnPrintf(pHlp, "\n");
2362
2363	/* the groups */
2364	c = 0;
2365	f = fGlobalForcedActions;
2366	PRINT_GROUP(VM_FF_,EXTERNAL_SUSPENDED,_MASK);
2367	PRINT_GROUP(VM_FF_,EXTERNAL_HALTED,_MASK);
2368	PRINT_GROUP(VM_FF_,HIGH_PRIORITY_PRE,_MASK);
2369	PRINT_GROUP(VM_FF_,HIGH_PRIORITY_PRE_RAW,_MASK);
2370	PRINT_GROUP(VM_FF_,HIGH_PRIORITY_POST,_MASK);
2371	PRINT_GROUP(VM_FF_,NORMAL_PRIORITY_POST,_MASK);
2372	PRINT_GROUP(VM_FF_,NORMAL_PRIORITY,_MASK);
2373	PRINT_GROUP(VM_FF_,ALL_REM,_MASK);
2374	if (c)
2375	pHlp->pfnPrintf(pHlp, "\n");
2376
2377	/*
2378	* Per CPU flags.
2379	*/
2380	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2381	{
2382	const uint32_t fLocalForcedActions = pVM->aCpus[i].fLocalForcedActions;
2383	pHlp->pfnPrintf(pHlp, "CPU %u FFs: %#RX32", i, fLocalForcedActions);
2384
2385	/* show the flag mnemonics */
2386	c = 0;
2387	f = fLocalForcedActions;
2388	PRINT_FLAG(VMCPU_FF_,INTERRUPT_APIC);
2389	PRINT_FLAG(VMCPU_FF_,INTERRUPT_PIC);
2390	PRINT_FLAG(VMCPU_FF_,TIMER);
2391	PRINT_FLAG(VMCPU_FF_,PDM_CRITSECT);
2392	PRINT_FLAG(VMCPU_FF_,PGM_SYNC_CR3);
2393	PRINT_FLAG(VMCPU_FF_,PGM_SYNC_CR3_NON_GLOBAL);
2394	PRINT_FLAG(VMCPU_FF_,TLB_FLUSH);
2395	PRINT_FLAG(VMCPU_FF_,INHIBIT_INTERRUPTS);
2396	PRINT_FLAG(VMCPU_FF_,TO_R3);
2397	#ifdef VBOX_WITH_RAW_MODE
2398	PRINT_FLAG(VMCPU_FF_,TRPM_SYNC_IDT);
2399	PRINT_FLAG(VMCPU_FF_,SELM_SYNC_TSS);
2400	PRINT_FLAG(VMCPU_FF_,SELM_SYNC_GDT);
2401	PRINT_FLAG(VMCPU_FF_,SELM_SYNC_LDT);
2402	PRINT_FLAG(VMCPU_FF_,CSAM_SCAN_PAGE);
2403	PRINT_FLAG(VMCPU_FF_,CSAM_PENDING_ACTION);
2404	#endif
2405	if (f)
2406	pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2407	else
2408	pHlp->pfnPrintf(pHlp, "\n");
2409
2410	if (fLocalForcedActions & VMCPU_FF_INHIBIT_INTERRUPTS)
2411	pHlp->pfnPrintf(pHlp, " intr inhibit RIP: %RGp\n", EMGetInhibitInterruptsPC(&pVM->aCpus[i]));
2412
2413	/* the groups */
2414	c = 0;
2415	f = fLocalForcedActions;
2416	PRINT_GROUP(VMCPU_FF_,EXTERNAL_SUSPENDED,_MASK);
2417	PRINT_GROUP(VMCPU_FF_,EXTERNAL_HALTED,_MASK);
2418	PRINT_GROUP(VMCPU_FF_,HIGH_PRIORITY_PRE,_MASK);
2419	PRINT_GROUP(VMCPU_FF_,HIGH_PRIORITY_PRE_RAW,_MASK);
2420	PRINT_GROUP(VMCPU_FF_,HIGH_PRIORITY_POST,_MASK);
2421	PRINT_GROUP(VMCPU_FF_,NORMAL_PRIORITY_POST,_MASK);
2422	PRINT_GROUP(VMCPU_FF_,NORMAL_PRIORITY,_MASK);
2423	PRINT_GROUP(VMCPU_FF_,RESUME_GUEST,_MASK);
2424	PRINT_GROUP(VMCPU_FF_,HM_TO_R3,_MASK);
2425	PRINT_GROUP(VMCPU_FF_,ALL_REM,_MASK);
2426	if (c)
2427	pHlp->pfnPrintf(pHlp, "\n");
2428	}
2429
2430	#undef PRINT_FLAG
2431	#undef PRINT_GROUP
2432	}
2433

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source: vbox/trunk/src/VBox/VMM/VMMR3/VMM.cpp@ 47786

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