VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/VMM.cpp@ 43858

Last change on this file since 43858 was 43667, checked in by vboxsync, 12 years ago

VMM: APIC refactor, cache APIC base MSR during init phase.
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1/* $Id: VMM.cpp 43667 2012-10-17 11:54:39Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18//#define NO_SUPCALLR0VMM
19
20/** @page pg_vmm VMM - The Virtual Machine Monitor
21 *
22 * The VMM component is two things at the moment, it's a component doing a few
23 * management and routing tasks, and it's the whole virtual machine monitor
24 * thing. For hysterical reasons, it is not doing all the management that one
25 * would expect, this is instead done by @ref pg_vm. We'll address this
26 * misdesign eventually.
27 *
28 * @see grp_vmm, grp_vm
29 *
30 *
31 * @section sec_vmmstate VMM State
32 *
33 * @image html VM_Statechart_Diagram.gif
34 *
35 * To be written.
36 *
37 *
38 * @subsection subsec_vmm_init VMM Initialization
39 *
40 * To be written.
41 *
42 *
43 * @subsection subsec_vmm_term VMM Termination
44 *
45 * To be written.
46 *
47 *
48 * @sections sec_vmm_limits VMM Limits
49 *
50 * There are various resource limits imposed by the VMM and it's
51 * sub-components. We'll list some of them here.
52 *
53 * On 64-bit hosts:
54 * - Max 8191 VMs. Imposed by GVMM's handle allocation (GVMM_MAX_HANDLES),
55 * can be increased up to 64K - 1.
56 * - Max 16TB - 64KB of the host memory can be used for backing VM RAM and
57 * ROM pages. The limit is imposed by the 32-bit page ID used by GMM.
58 * - A VM can be assigned all the memory we can use (16TB), however, the
59 * Main API will restrict this to 2TB (MM_RAM_MAX_IN_MB).
60 * - Max 32 virtual CPUs (VMM_MAX_CPU_COUNT).
61 *
62 * On 32-bit hosts:
63 * - Max 127 VMs. Imposed by GMM's per page structure.
64 * - Max 64GB - 64KB of the host memory can be used for backing VM RAM and
65 * ROM pages. The limit is imposed by the 28-bit page ID used
66 * internally in GMM. It is also limited by PAE.
67 * - A VM can be assigned all the memory GMM can allocate, however, the
68 * Main API will restrict this to 3584MB (MM_RAM_MAX_IN_MB).
69 * - Max 32 virtual CPUs (VMM_MAX_CPU_COUNT).
70 *
71 */
72
73/*******************************************************************************
74* Header Files *
75*******************************************************************************/
76#define LOG_GROUP LOG_GROUP_VMM
77#include <VBox/vmm/vmm.h>
78#include <VBox/vmm/vmapi.h>
79#include <VBox/vmm/pgm.h>
80#include <VBox/vmm/cfgm.h>
81#include <VBox/vmm/pdmqueue.h>
82#include <VBox/vmm/pdmcritsect.h>
83#include <VBox/vmm/pdmapi.h>
84#include <VBox/vmm/cpum.h>
85#include <VBox/vmm/mm.h>
86#include <VBox/vmm/iom.h>
87#include <VBox/vmm/trpm.h>
88#include <VBox/vmm/selm.h>
89#include <VBox/vmm/em.h>
90#include <VBox/sup.h>
91#include <VBox/vmm/dbgf.h>
92#include <VBox/vmm/csam.h>
93#include <VBox/vmm/patm.h>
94#ifdef VBOX_WITH_REM
95# include <VBox/vmm/rem.h>
96#endif
97#include <VBox/vmm/ssm.h>
98#include <VBox/vmm/tm.h>
99#include "VMMInternal.h"
100#include "VMMSwitcher.h"
101#include <VBox/vmm/vm.h>
102#include <VBox/vmm/ftm.h>
103
104#include <VBox/err.h>
105#include <VBox/param.h>
106#include <VBox/version.h>
107#include <VBox/vmm/hm.h>
108#include <iprt/assert.h>
109#include <iprt/alloc.h>
110#include <iprt/asm.h>
111#include <iprt/time.h>
112#include <iprt/semaphore.h>
113#include <iprt/stream.h>
114#include <iprt/string.h>
115#include <iprt/stdarg.h>
116#include <iprt/ctype.h>
117#include <iprt/x86.h>
118
119
120
121/*******************************************************************************
122* Defined Constants And Macros *
123*******************************************************************************/
124/** The saved state version. */
125#define VMM_SAVED_STATE_VERSION 4
126/** The saved state version used by v3.0 and earlier. (Teleportation) */
127#define VMM_SAVED_STATE_VERSION_3_0 3
128
129
130/*******************************************************************************
131* Internal Functions *
132*******************************************************************************/
133static int vmmR3InitStacks(PVM pVM);
134static int vmmR3InitLoggers(PVM pVM);
135static void vmmR3InitRegisterStats(PVM pVM);
136static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
137static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
138static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
139static int vmmR3ServiceCallRing3Request(PVM pVM, PVMCPU pVCpu);
140static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141
142
143/**
144 * Initializes the VMM.
145 *
146 * @returns VBox status code.
147 * @param pVM Pointer to the VM.
148 */
149VMMR3_INT_DECL(int) VMMR3Init(PVM pVM)
150{
151 LogFlow(("VMMR3Init\n"));
152
153 /*
154 * Assert alignment, sizes and order.
155 */
156 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
157 AssertCompile(sizeof(pVM->vmm.s) <= sizeof(pVM->vmm.padding));
158 AssertCompile(sizeof(pVM->aCpus[0].vmm.s) <= sizeof(pVM->aCpus[0].vmm.padding));
159
160 /*
161 * Init basic VM VMM members.
162 */
163 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
164 pVM->vmm.s.pahEvtRendezvousEnterOrdered = NULL;
165 pVM->vmm.s.hEvtRendezvousEnterOneByOne = NIL_RTSEMEVENT;
166 pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce = NIL_RTSEMEVENTMULTI;
167 pVM->vmm.s.hEvtMulRendezvousDone = NIL_RTSEMEVENTMULTI;
168 pVM->vmm.s.hEvtRendezvousDoneCaller = NIL_RTSEMEVENT;
169
170 /** @cfgm{YieldEMTInterval, uint32_t, 1, UINT32_MAX, 23, ms}
171 * The EMT yield interval. The EMT yielding is a hack we employ to play a
172 * bit nicer with the rest of the system (like for instance the GUI).
173 */
174 int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies,
175 23 /* Value arrived at after experimenting with the grub boot prompt. */);
176 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Rrc\n", rc), rc);
177
178
179 /** @cfgm{VMM/UsePeriodicPreemptionTimers, boolean, true}
180 * Controls whether we employ per-cpu preemption timers to limit the time
181 * spent executing guest code. This option is not available on all
182 * platforms and we will silently ignore this setting then. If we are
183 * running in VT-x mode, we will use the VMX-preemption timer instead of
184 * this one when possible.
185 */
186 PCFGMNODE pCfgVMM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "VMM");
187 rc = CFGMR3QueryBoolDef(pCfgVMM, "UsePeriodicPreemptionTimers", &pVM->vmm.s.fUsePeriodicPreemptionTimers, true);
188 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"VMM/UsePeriodicPreemptionTimers\", rc=%Rrc\n", rc), rc);
189
190 /*
191 * Initialize the VMM rendezvous semaphores.
192 */
193 pVM->vmm.s.pahEvtRendezvousEnterOrdered = (PRTSEMEVENT)MMR3HeapAlloc(pVM, MM_TAG_VMM, sizeof(RTSEMEVENT) * pVM->cCpus);
194 if (!pVM->vmm.s.pahEvtRendezvousEnterOrdered)
195 return VERR_NO_MEMORY;
196 for (VMCPUID i = 0; i < pVM->cCpus; i++)
197 pVM->vmm.s.pahEvtRendezvousEnterOrdered[i] = NIL_RTSEMEVENT;
198 for (VMCPUID i = 0; i < pVM->cCpus; i++)
199 {
200 rc = RTSemEventCreate(&pVM->vmm.s.pahEvtRendezvousEnterOrdered[i]);
201 AssertRCReturn(rc, rc);
202 }
203 rc = RTSemEventCreate(&pVM->vmm.s.hEvtRendezvousEnterOneByOne);
204 AssertRCReturn(rc, rc);
205 rc = RTSemEventMultiCreate(&pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce);
206 AssertRCReturn(rc, rc);
207 rc = RTSemEventMultiCreate(&pVM->vmm.s.hEvtMulRendezvousDone);
208 AssertRCReturn(rc, rc);
209 rc = RTSemEventCreate(&pVM->vmm.s.hEvtRendezvousDoneCaller);
210 AssertRCReturn(rc, rc);
211
212 /* GC switchers are enabled by default. Turned off by HM. */
213 pVM->vmm.s.fSwitcherDisabled = false;
214
215 /*
216 * Register the saved state data unit.
217 */
218 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
219 NULL, NULL, NULL,
220 NULL, vmmR3Save, NULL,
221 NULL, vmmR3Load, NULL);
222 if (RT_FAILURE(rc))
223 return rc;
224
225 /*
226 * Register the Ring-0 VM handle with the session for fast ioctl calls.
227 */
228 rc = SUPR3SetVMForFastIOCtl(pVM->pVMR0);
229 if (RT_FAILURE(rc))
230 return rc;
231
232 /*
233 * Init various sub-components.
234 */
235 rc = vmmR3SwitcherInit(pVM);
236 if (RT_SUCCESS(rc))
237 {
238 rc = vmmR3InitStacks(pVM);
239 if (RT_SUCCESS(rc))
240 {
241 rc = vmmR3InitLoggers(pVM);
242
243#ifdef VBOX_WITH_NMI
244 /*
245 * Allocate mapping for the host APIC.
246 */
247 if (RT_SUCCESS(rc))
248 {
249 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
250 AssertRC(rc);
251 }
252#endif
253 if (RT_SUCCESS(rc))
254 {
255 /*
256 * Debug info and statistics.
257 */
258 DBGFR3InfoRegisterInternal(pVM, "fflags", "Displays the current Forced actions Flags.", vmmR3InfoFF);
259 vmmR3InitRegisterStats(pVM);
260 vmmInitFormatTypes();
261
262 return VINF_SUCCESS;
263 }
264 }
265 /** @todo: Need failure cleanup. */
266
267 //more todo in here?
268 //if (RT_SUCCESS(rc))
269 //{
270 //}
271 //int rc2 = vmmR3TermCoreCode(pVM);
272 //AssertRC(rc2));
273 }
274
275 return rc;
276}
277
278
279/**
280 * Allocate & setup the VMM RC stack(s) (for EMTs).
281 *
282 * The stacks are also used for long jumps in Ring-0.
283 *
284 * @returns VBox status code.
285 * @param pVM Pointer to the VM.
286 *
287 * @remarks The optional guard page gets it protection setup up during R3 init
288 * completion because of init order issues.
289 */
290static int vmmR3InitStacks(PVM pVM)
291{
292 int rc = VINF_SUCCESS;
293#ifdef VMM_R0_SWITCH_STACK
294 uint32_t fFlags = MMHYPER_AONR_FLAGS_KERNEL_MAPPING;
295#else
296 uint32_t fFlags = 0;
297#endif
298
299 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
300 {
301 PVMCPU pVCpu = &pVM->aCpus[idCpu];
302
303#ifdef VBOX_STRICT_VMM_STACK
304 rc = MMR3HyperAllocOnceNoRelEx(pVM, PAGE_SIZE + VMM_STACK_SIZE + PAGE_SIZE,
305#else
306 rc = MMR3HyperAllocOnceNoRelEx(pVM, VMM_STACK_SIZE,
307#endif
308 PAGE_SIZE, MM_TAG_VMM, fFlags, (void **)&pVCpu->vmm.s.pbEMTStackR3);
309 if (RT_SUCCESS(rc))
310 {
311#ifdef VBOX_STRICT_VMM_STACK
312 pVCpu->vmm.s.pbEMTStackR3 += PAGE_SIZE;
313#endif
314#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
315 /* MMHyperR3ToR0 returns R3 when not doing hardware assisted virtualization. */
316 if (!VMMIsHwVirtExtForced(pVM))
317 pVCpu->vmm.s.CallRing3JmpBufR0.pvSavedStack = NIL_RTR0PTR;
318 else
319#endif
320 pVCpu->vmm.s.CallRing3JmpBufR0.pvSavedStack = MMHyperR3ToR0(pVM, pVCpu->vmm.s.pbEMTStackR3);
321 pVCpu->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVCpu->vmm.s.pbEMTStackR3);
322 pVCpu->vmm.s.pbEMTStackBottomRC = pVCpu->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
323 AssertRelease(pVCpu->vmm.s.pbEMTStackRC);
324
325 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC);
326 }
327 }
328
329 return rc;
330}
331
332
333/**
334 * Initialize the loggers.
335 *
336 * @returns VBox status code.
337 * @param pVM Pointer to the VM.
338 */
339static int vmmR3InitLoggers(PVM pVM)
340{
341 int rc;
342#define RTLogCalcSizeForR0(cGroups, fFlags) (RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[cGroups]) + PAGE_SIZE)
343
344 /*
345 * Allocate RC & R0 Logger instances (they are finalized in the relocator).
346 */
347#ifdef LOG_ENABLED
348 PRTLOGGER pLogger = RTLogDefaultInstance();
349 if (pLogger)
350 {
351 pVM->vmm.s.cbRCLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
352 rc = MMR3HyperAllocOnceNoRel(pVM, pVM->vmm.s.cbRCLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCLoggerR3);
353 if (RT_FAILURE(rc))
354 return rc;
355 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
356
357# ifdef VBOX_WITH_R0_LOGGING
358 size_t const cbLogger = RTLogCalcSizeForR0(pLogger->cGroups, 0);
359 for (VMCPUID i = 0; i < pVM->cCpus; i++)
360 {
361 PVMCPU pVCpu = &pVM->aCpus[i];
362 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbLogger, PAGE_SIZE, MM_TAG_VMM, MMHYPER_AONR_FLAGS_KERNEL_MAPPING,
363 (void **)&pVCpu->vmm.s.pR0LoggerR3);
364 if (RT_FAILURE(rc))
365 return rc;
366 pVCpu->vmm.s.pR0LoggerR3->pVM = pVM->pVMR0;
367 //pVCpu->vmm.s.pR0LoggerR3->fCreated = false;
368 pVCpu->vmm.s.pR0LoggerR3->cbLogger = (uint32_t)cbLogger;
369 pVCpu->vmm.s.pR0LoggerR0 = MMHyperR3ToR0(pVM, pVCpu->vmm.s.pR0LoggerR3);
370 }
371# endif
372 }
373#endif /* LOG_ENABLED */
374
375#ifdef VBOX_WITH_RC_RELEASE_LOGGING
376 /*
377 * Allocate RC release logger instances (finalized in the relocator).
378 */
379 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
380 if (pRelLogger)
381 {
382 pVM->vmm.s.cbRCRelLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
383 rc = MMR3HyperAllocOnceNoRel(pVM, pVM->vmm.s.cbRCRelLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCRelLoggerR3);
384 if (RT_FAILURE(rc))
385 return rc;
386 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
387 }
388#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
389 return VINF_SUCCESS;
390}
391
392
393/**
394 * VMMR3Init worker that register the statistics with STAM.
395 *
396 * @param pVM The shared VM structure.
397 */
398static void vmmR3InitRegisterStats(PVM pVM)
399{
400 /*
401 * Statistics.
402 */
403 STAM_REG(pVM, &pVM->vmm.s.StatRunRC, STAMTYPE_COUNTER, "/VMM/RunRC", STAMUNIT_OCCURENCES, "Number of context switches.");
404 STAM_REG(pVM, &pVM->vmm.s.StatRZRetNormal, STAMTYPE_COUNTER, "/VMM/RZRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
405 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterrupt, STAMTYPE_COUNTER, "/VMM/RZRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
406 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
407 STAM_REG(pVM, &pVM->vmm.s.StatRZRetGuestTrap, STAMTYPE_COUNTER, "/VMM/RZRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
408 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitch, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
409 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
410 STAM_REG(pVM, &pVM->vmm.s.StatRZRetStaleSelector, STAMTYPE_COUNTER, "/VMM/RZRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
411 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIRETTrap, STAMTYPE_COUNTER, "/VMM/RZRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
412 STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
413 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIOBlockEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/EmulateIOBlock", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_IO_BLOCK returns.");
414 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
415 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIORead, STAMTYPE_COUNTER, "/VMM/RZRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_IOPORT_READ returns.");
416 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_IOPORT_WRITE returns.");
417 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIORead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_MMIO_READ returns.");
418 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_MMIO_WRITE returns.");
419 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_R3_MMIO_READ_WRITE returns.");
420 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
421 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
422 STAM_REG(pVM, &pVM->vmm.s.StatRZRetLDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
423 STAM_REG(pVM, &pVM->vmm.s.StatRZRetGDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
424 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
425 STAM_REG(pVM, &pVM->vmm.s.StatRZRetTSSFault, STAMTYPE_COUNTER, "/VMM/RZRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
426 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPDFault, STAMTYPE_COUNTER, "/VMM/RZRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
427 STAM_REG(pVM, &pVM->vmm.s.StatRZRetCSAMTask, STAMTYPE_COUNTER, "/VMM/RZRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
428 STAM_REG(pVM, &pVM->vmm.s.StatRZRetSyncCR3, STAMTYPE_COUNTER, "/VMM/RZRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
429 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMisc, STAMTYPE_COUNTER, "/VMM/RZRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
430 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchInt3, STAMTYPE_COUNTER, "/VMM/RZRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
431 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchPF, STAMTYPE_COUNTER, "/VMM/RZRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
432 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchGP, STAMTYPE_COUNTER, "/VMM/RZRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
433 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/RZRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
434 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/RZRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
435 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
436 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3Unknown, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Unknown", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
437 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3TMVirt, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/TMVirt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
438 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3HandyPages, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Handy", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
439 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3PDMQueues, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/PDMQueue", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
440 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3Rendezvous, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Rendezvous", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
441 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3Timer, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/Timer", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
442 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3DMA, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/DMA", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
443 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3CritSect, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3/CritSect", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
444 STAM_REG(pVM, &pVM->vmm.s.StatRZRetTimerPending, STAMTYPE_COUNTER, "/VMM/RZRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
445 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptPending, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
446 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/RZRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
447 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/RZRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
448 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPGMFlushPending, STAMTYPE_COUNTER, "/VMM/RZRet/PGMFlushPending", STAMUNIT_OCCURENCES, "Number of VINF_PGM_POOL_FLUSH_PENDING returns.");
449 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPendingRequest, STAMTYPE_COUNTER, "/VMM/RZRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
450 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchTPR, STAMTYPE_COUNTER, "/VMM/RZRet/PatchTPR", STAMUNIT_OCCURENCES, "Number of VINF_EM_HM_PATCH_TPR_INSTR returns.");
451 STAM_REG(pVM, &pVM->vmm.s.StatRZRetCallRing3, STAMTYPE_COUNTER, "/VMM/RZCallR3/Misc", STAMUNIT_OCCURENCES, "Number of Other ring-3 calls.");
452 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PDM_LOCK calls.");
453 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMCritSectEnter, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMCritSectEnter", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PDM_CRITSECT_ENTER calls.");
454 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_LOCK calls.");
455 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMPoolGrow", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_POOL_GROW calls.");
456 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMMapChunk, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMMapChunk", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_MAP_CHUNK calls.");
457 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMAllocHandy, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMAllocHandy", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES calls.");
458 STAM_REG(pVM, &pVM->vmm.s.StatRZCallRemReplay, STAMTYPE_COUNTER, "/VMM/RZCallR3/REMReplay", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_REM_REPLAY_HANDLER_NOTIFICATIONS calls.");
459 STAM_REG(pVM, &pVM->vmm.s.StatRZCallLogFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMMLogFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_VMM_LOGGER_FLUSH calls.");
460 STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMSetError", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_VM_SET_ERROR calls.");
461 STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetRuntimeError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMRuntimeError", STAMUNIT_OCCURENCES, "Number of VMMCALLRING3_VM_SET_RUNTIME_ERROR calls.");
462
463#ifdef VBOX_WITH_STATISTICS
464 for (VMCPUID i = 0; i < pVM->cCpus; i++)
465 {
466 STAMR3RegisterF(pVM, &pVM->aCpus[i].vmm.s.CallRing3JmpBufR0.cbUsedMax, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Max amount of stack used.", "/VMM/Stack/CPU%u/Max", i);
467 STAMR3RegisterF(pVM, &pVM->aCpus[i].vmm.s.CallRing3JmpBufR0.cbUsedAvg, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Average stack usage.", "/VMM/Stack/CPU%u/Avg", i);
468 STAMR3RegisterF(pVM, &pVM->aCpus[i].vmm.s.CallRing3JmpBufR0.cUsedTotal, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of stack usages.", "/VMM/Stack/CPU%u/Uses", i);
469 }
470#endif
471}
472
473
474/**
475 * Initializes the R0 VMM.
476 *
477 * @returns VBox status code.
478 * @param pVM Pointer to the VM.
479 */
480VMMR3_INT_DECL(int) VMMR3InitR0(PVM pVM)
481{
482 int rc;
483 PVMCPU pVCpu = VMMGetCpu(pVM);
484 Assert(pVCpu && pVCpu->idCpu == 0);
485
486#ifdef LOG_ENABLED
487 /*
488 * Initialize the ring-0 logger if we haven't done so yet.
489 */
490 if ( pVCpu->vmm.s.pR0LoggerR3
491 && !pVCpu->vmm.s.pR0LoggerR3->fCreated)
492 {
493 rc = VMMR3UpdateLoggers(pVM);
494 if (RT_FAILURE(rc))
495 return rc;
496 }
497#endif
498
499 /*
500 * Call Ring-0 entry with init code.
501 */
502 for (;;)
503 {
504#ifdef NO_SUPCALLR0VMM
505 //rc = VERR_GENERAL_FAILURE;
506 rc = VINF_SUCCESS;
507#else
508 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
509#endif
510 /*
511 * Flush the logs.
512 */
513#ifdef LOG_ENABLED
514 if ( pVCpu->vmm.s.pR0LoggerR3
515 && pVCpu->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
516 RTLogFlushR0(NULL, &pVCpu->vmm.s.pR0LoggerR3->Logger);
517#endif
518 if (rc != VINF_VMM_CALL_HOST)
519 break;
520 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
521 if (RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
522 break;
523 /* Resume R0 */
524 }
525
526 if (RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
527 {
528 LogRel(("R0 init failed, rc=%Rra\n", rc));
529 if (RT_SUCCESS(rc))
530 rc = VERR_IPE_UNEXPECTED_INFO_STATUS;
531 }
532 return rc;
533}
534
535
536/**
537 * Initializes the RC VMM.
538 *
539 * @returns VBox status code.
540 * @param pVM Pointer to the VM.
541 */
542VMMR3_INT_DECL(int) VMMR3InitRC(PVM pVM)
543{
544 PVMCPU pVCpu = VMMGetCpu(pVM);
545 Assert(pVCpu && pVCpu->idCpu == 0);
546
547 /* In VMX mode, there's no need to init RC. */
548 if (pVM->vmm.s.fSwitcherDisabled)
549 return VINF_SUCCESS;
550
551 AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
552
553 /*
554 * Call VMMGCInit():
555 * -# resolve the address.
556 * -# setup stackframe and EIP to use the trampoline.
557 * -# do a generic hypervisor call.
558 */
559 RTRCPTR RCPtrEP;
560 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
561 if (RT_SUCCESS(rc))
562 {
563 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
564 uint64_t u64TS = RTTimeProgramStartNanoTS();
565 CPUMPushHyper(pVCpu, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
566 CPUMPushHyper(pVCpu, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
567 CPUMPushHyper(pVCpu, VMMGetSvnRev()); /* Param 2: Version argument. */
568 CPUMPushHyper(pVCpu, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
569 CPUMPushHyper(pVCpu, pVM->pVMRC); /* Param 0: pVM */
570 CPUMPushHyper(pVCpu, 5 * sizeof(RTRCPTR)); /* trampoline param: stacksize. */
571 CPUMPushHyper(pVCpu, RCPtrEP); /* Call EIP. */
572 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
573 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
574
575 for (;;)
576 {
577#ifdef NO_SUPCALLR0VMM
578 //rc = VERR_GENERAL_FAILURE;
579 rc = VINF_SUCCESS;
580#else
581 rc = SUPR3CallVMMR0(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_CALL_HYPERVISOR, NULL);
582#endif
583#ifdef LOG_ENABLED
584 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
585 if ( pLogger
586 && pLogger->offScratch > 0)
587 RTLogFlushRC(NULL, pLogger);
588#endif
589#ifdef VBOX_WITH_RC_RELEASE_LOGGING
590 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
591 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
592 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
593#endif
594 if (rc != VINF_VMM_CALL_HOST)
595 break;
596 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
597 if (RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
598 break;
599 }
600
601 if (RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
602 {
603 VMMR3FatalDump(pVM, pVCpu, rc);
604 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
605 rc = VERR_IPE_UNEXPECTED_INFO_STATUS;
606 }
607 AssertRC(rc);
608 }
609 return rc;
610}
611
612
613/**
614 * Called when an init phase completes.
615 *
616 * @returns VBox status code.
617 * @param pVM Pointer to the VM.
618 * @param enmWhat Which init phase.
619 */
620VMMR3_INT_DECL(int) VMMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
621{
622 int rc = VINF_SUCCESS;
623
624 switch (enmWhat)
625 {
626 case VMINITCOMPLETED_RING3:
627 {
628 /*
629 * CPUM's post-initialization (APIC base MSR caching).
630 */
631 rc = CPUMR3InitCompleted(pVM);
632 AssertRCReturn(rc, rc);
633
634 /*
635 * Set page attributes to r/w for stack pages.
636 */
637 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
638 {
639 rc = PGMMapSetPage(pVM, pVM->aCpus[idCpu].vmm.s.pbEMTStackRC, VMM_STACK_SIZE,
640 X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
641 AssertRCReturn(rc, rc);
642 }
643
644 /*
645 * Create the EMT yield timer.
646 */
647 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
648 AssertRCReturn(rc, rc);
649
650 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
651 AssertRCReturn(rc, rc);
652
653#ifdef VBOX_WITH_NMI
654 /*
655 * Map the host APIC into GC - This is AMD/Intel + Host OS specific!
656 */
657 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
658 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
659 AssertRCReturn(rc, rc);
660#endif
661
662#ifdef VBOX_STRICT_VMM_STACK
663 /*
664 * Setup the stack guard pages: Two inaccessible pages at each sides of the
665 * stack to catch over/under-flows.
666 */
667 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
668 {
669 uint8_t *pbEMTStackR3 = pVM->aCpus[idCpu].vmm.s.pbEMTStackR3;
670
671 memset(pbEMTStackR3 - PAGE_SIZE, 0xcc, PAGE_SIZE);
672 MMR3HyperSetGuard(pVM, pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, true /*fSet*/);
673
674 memset(pbEMTStackR3 + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
675 MMR3HyperSetGuard(pVM, pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, true /*fSet*/);
676 }
677 pVM->vmm.s.fStackGuardsStationed = true;
678#endif
679 break;
680 }
681
682 case VMINITCOMPLETED_RING0:
683 {
684 /*
685 * Disable the periodic preemption timers if we can use the
686 * VMX-preemption timer instead.
687 */
688 if ( pVM->vmm.s.fUsePeriodicPreemptionTimers
689 && HMR3IsVmxPreemptionTimerUsed(pVM))
690 pVM->vmm.s.fUsePeriodicPreemptionTimers = false;
691 LogRel(("VMM: fUsePeriodicPreemptionTimers=%RTbool\n", pVM->vmm.s.fUsePeriodicPreemptionTimers));
692 break;
693 }
694
695 default: /* shuts up gcc */
696 break;
697 }
698
699 return rc;
700}
701
702
703/**
704 * Terminate the VMM bits.
705 *
706 * @returns VINF_SUCCESS.
707 * @param pVM Pointer to the VM.
708 */
709VMMR3_INT_DECL(int) VMMR3Term(PVM pVM)
710{
711 PVMCPU pVCpu = VMMGetCpu(pVM);
712 Assert(pVCpu && pVCpu->idCpu == 0);
713
714 /*
715 * Call Ring-0 entry with termination code.
716 */
717 int rc;
718 for (;;)
719 {
720#ifdef NO_SUPCALLR0VMM
721 //rc = VERR_GENERAL_FAILURE;
722 rc = VINF_SUCCESS;
723#else
724 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_VMMR0_TERM, 0, NULL);
725#endif
726 /*
727 * Flush the logs.
728 */
729#ifdef LOG_ENABLED
730 if ( pVCpu->vmm.s.pR0LoggerR3
731 && pVCpu->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
732 RTLogFlushR0(NULL, &pVCpu->vmm.s.pR0LoggerR3->Logger);
733#endif
734 if (rc != VINF_VMM_CALL_HOST)
735 break;
736 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
737 if (RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
738 break;
739 /* Resume R0 */
740 }
741 if (RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
742 {
743 LogRel(("VMMR3Term: R0 term failed, rc=%Rra. (warning)\n", rc));
744 if (RT_SUCCESS(rc))
745 rc = VERR_IPE_UNEXPECTED_INFO_STATUS;
746 }
747
748 for (VMCPUID i = 0; i < pVM->cCpus; i++)
749 {
750 RTSemEventDestroy(pVM->vmm.s.pahEvtRendezvousEnterOrdered[i]);
751 pVM->vmm.s.pahEvtRendezvousEnterOrdered[i] = NIL_RTSEMEVENT;
752 }
753 RTSemEventDestroy(pVM->vmm.s.hEvtRendezvousEnterOneByOne);
754 pVM->vmm.s.hEvtRendezvousEnterOneByOne = NIL_RTSEMEVENT;
755 RTSemEventMultiDestroy(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce);
756 pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce = NIL_RTSEMEVENTMULTI;
757 RTSemEventMultiDestroy(pVM->vmm.s.hEvtMulRendezvousDone);
758 pVM->vmm.s.hEvtMulRendezvousDone = NIL_RTSEMEVENTMULTI;
759 RTSemEventDestroy(pVM->vmm.s.hEvtRendezvousDoneCaller);
760 pVM->vmm.s.hEvtRendezvousDoneCaller = NIL_RTSEMEVENT;
761
762#ifdef VBOX_STRICT_VMM_STACK
763 /*
764 * Make the two stack guard pages present again.
765 */
766 if (pVM->vmm.s.fStackGuardsStationed)
767 {
768 for (VMCPUID i = 0; i < pVM->cCpus; i++)
769 {
770 uint8_t *pbEMTStackR3 = pVM->aCpus[i].vmm.s.pbEMTStackR3;
771 MMR3HyperSetGuard(pVM, pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, false /*fSet*/);
772 MMR3HyperSetGuard(pVM, pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, false /*fSet*/);
773 }
774 pVM->vmm.s.fStackGuardsStationed = false;
775 }
776#endif
777
778 vmmTermFormatTypes();
779 return rc;
780}
781
782
783/**
784 * Applies relocations to data and code managed by this
785 * component. This function will be called at init and
786 * whenever the VMM need to relocate it self inside the GC.
787 *
788 * The VMM will need to apply relocations to the core code.
789 *
790 * @param pVM Pointer to the VM.
791 * @param offDelta The relocation delta.
792 */
793VMMR3_INT_DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
794{
795 LogFlow(("VMMR3Relocate: offDelta=%RGv\n", offDelta));
796
797 /*
798 * Recalc the RC address.
799 */
800#ifdef VBOX_WITH_RAW_MODE
801 pVM->vmm.s.pvCoreCodeRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pvCoreCodeR3);
802#endif
803
804 /*
805 * The stack.
806 */
807 for (VMCPUID i = 0; i < pVM->cCpus; i++)
808 {
809 PVMCPU pVCpu = &pVM->aCpus[i];
810
811 CPUMSetHyperESP(pVCpu, CPUMGetHyperESP(pVCpu) + offDelta);
812
813 pVCpu->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVCpu->vmm.s.pbEMTStackR3);
814 pVCpu->vmm.s.pbEMTStackBottomRC = pVCpu->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
815 }
816
817 /*
818 * All the switchers.
819 */
820 vmmR3SwitcherRelocate(pVM, offDelta);
821
822 /*
823 * Get other RC entry points.
824 */
825 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMRCResumeGuest);
826 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Rra\n", rc));
827
828 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMRCResumeGuestV86);
829 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Rra\n", rc));
830
831 /*
832 * Update the logger.
833 */
834 VMMR3UpdateLoggers(pVM);
835}
836
837
838/**
839 * Updates the settings for the RC and R0 loggers.
840 *
841 * @returns VBox status code.
842 * @param pVM Pointer to the VM.
843 */
844VMMR3_INT_DECL(int) VMMR3UpdateLoggers(PVM pVM)
845{
846 /*
847 * Simply clone the logger instance (for RC).
848 */
849 int rc = VINF_SUCCESS;
850 RTRCPTR RCPtrLoggerFlush = 0;
851
852 if (pVM->vmm.s.pRCLoggerR3
853#ifdef VBOX_WITH_RC_RELEASE_LOGGING
854 || pVM->vmm.s.pRCRelLoggerR3
855#endif
856 )
857 {
858 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &RCPtrLoggerFlush);
859 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Rra\n", rc));
860 }
861
862 if (pVM->vmm.s.pRCLoggerR3)
863 {
864 RTRCPTR RCPtrLoggerWrapper = 0;
865 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &RCPtrLoggerWrapper);
866 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Rra\n", rc));
867
868 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
869 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pRCLoggerR3, pVM->vmm.s.cbRCLogger,
870 RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
871 AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Rra\n", rc));
872 }
873
874#ifdef VBOX_WITH_RC_RELEASE_LOGGING
875 if (pVM->vmm.s.pRCRelLoggerR3)
876 {
877 RTRCPTR RCPtrLoggerWrapper = 0;
878 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &RCPtrLoggerWrapper);
879 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Rra\n", rc));
880
881 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
882 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRCRelLoggerR3, pVM->vmm.s.cbRCRelLogger,
883 RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
884 AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Rra\n", rc));
885 }
886#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
887
888#ifdef LOG_ENABLED
889 /*
890 * For the ring-0 EMT logger, we use a per-thread logger instance
891 * in ring-0. Only initialize it once.
892 */
893 PRTLOGGER const pDefault = RTLogDefaultInstance();
894 for (VMCPUID i = 0; i < pVM->cCpus; i++)
895 {
896 PVMCPU pVCpu = &pVM->aCpus[i];
897 PVMMR0LOGGER pR0LoggerR3 = pVCpu->vmm.s.pR0LoggerR3;
898 if (pR0LoggerR3)
899 {
900 if (!pR0LoggerR3->fCreated)
901 {
902 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
903 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
904 AssertReleaseMsgRCReturn(rc, ("vmmR0LoggerWrapper not found! rc=%Rra\n", rc), rc);
905
906 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
907 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
908 AssertReleaseMsgRCReturn(rc, ("vmmR0LoggerFlush not found! rc=%Rra\n", rc), rc);
909
910 rc = RTLogCreateForR0(&pR0LoggerR3->Logger, pR0LoggerR3->cbLogger, pVCpu->vmm.s.pR0LoggerR0 + RT_OFFSETOF(VMMR0LOGGER, Logger),
911 pfnLoggerWrapper, pfnLoggerFlush,
912 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
913 AssertReleaseMsgRCReturn(rc, ("RTLogCreateForR0 failed! rc=%Rra\n", rc), rc);
914
915 RTR0PTR pfnLoggerPrefix = NIL_RTR0PTR;
916 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerPrefix", &pfnLoggerPrefix);
917 AssertReleaseMsgRCReturn(rc, ("vmmR0LoggerPrefix not found! rc=%Rra\n", rc), rc);
918 rc = RTLogSetCustomPrefixCallbackForR0(&pR0LoggerR3->Logger, pVCpu->vmm.s.pR0LoggerR0 + RT_OFFSETOF(VMMR0LOGGER, Logger), pfnLoggerPrefix, NIL_RTR0PTR);
919 AssertReleaseMsgRCReturn(rc, ("RTLogSetCustomPrefixCallback failed! rc=%Rra\n", rc), rc);
920
921 pR0LoggerR3->idCpu = i;
922 pR0LoggerR3->fCreated = true;
923 pR0LoggerR3->fFlushingDisabled = false;
924
925 }
926
927 rc = RTLogCopyGroupsAndFlagsForR0(&pR0LoggerR3->Logger, pVCpu->vmm.s.pR0LoggerR0 + RT_OFFSETOF(VMMR0LOGGER, Logger), pDefault,
928 RTLOGFLAGS_BUFFERED, UINT32_MAX);
929 AssertRC(rc);
930 }
931 }
932#endif
933 return rc;
934}
935
936
937/**
938 * Gets the pointer to a buffer containing the R0/RC RTAssertMsg1Weak output.
939 *
940 * @returns Pointer to the buffer.
941 * @param pVM Pointer to the VM.
942 */
943VMMR3DECL(const char *) VMMR3GetRZAssertMsg1(PVM pVM)
944{
945 if (HMIsEnabled(pVM))
946 return pVM->vmm.s.szRing0AssertMsg1;
947
948 RTRCPTR RCPtr;
949 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg1", &RCPtr);
950 if (RT_SUCCESS(rc))
951 return (const char *)MMHyperRCToR3(pVM, RCPtr);
952
953 return NULL;
954}
955
956
957/**
958 * Gets the pointer to a buffer containing the R0/RC RTAssertMsg2Weak output.
959 *
960 * @returns Pointer to the buffer.
961 * @param pVM Pointer to the VM.
962 */
963VMMR3DECL(const char *) VMMR3GetRZAssertMsg2(PVM pVM)
964{
965 if (HMIsEnabled(pVM))
966 return pVM->vmm.s.szRing0AssertMsg2;
967
968 RTRCPTR RCPtr;
969 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg2", &RCPtr);
970 if (RT_SUCCESS(rc))
971 return (const char *)MMHyperRCToR3(pVM, RCPtr);
972
973 return NULL;
974}
975
976
977/**
978 * Execute state save operation.
979 *
980 * @returns VBox status code.
981 * @param pVM Pointer to the VM.
982 * @param pSSM SSM operation handle.
983 */
984static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
985{
986 LogFlow(("vmmR3Save:\n"));
987
988 /*
989 * Save the started/stopped state of all CPUs except 0 as it will always
990 * be running. This avoids breaking the saved state version. :-)
991 */
992 for (VMCPUID i = 1; i < pVM->cCpus; i++)
993 SSMR3PutBool(pSSM, VMCPUSTATE_IS_STARTED(VMCPU_GET_STATE(&pVM->aCpus[i])));
994
995 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
996}
997
998
999/**
1000 * Execute state load operation.
1001 *
1002 * @returns VBox status code.
1003 * @param pVM Pointer to the VM.
1004 * @param pSSM SSM operation handle.
1005 * @param uVersion Data layout version.
1006 * @param uPass The data pass.
1007 */
1008static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1009{
1010 LogFlow(("vmmR3Load:\n"));
1011 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1012
1013 /*
1014 * Validate version.
1015 */
1016 if ( uVersion != VMM_SAVED_STATE_VERSION
1017 && uVersion != VMM_SAVED_STATE_VERSION_3_0)
1018 {
1019 AssertMsgFailed(("vmmR3Load: Invalid version uVersion=%u!\n", uVersion));
1020 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1021 }
1022
1023 if (uVersion <= VMM_SAVED_STATE_VERSION_3_0)
1024 {
1025 /* Ignore the stack bottom, stack pointer and stack bits. */
1026 RTRCPTR RCPtrIgnored;
1027 SSMR3GetRCPtr(pSSM, &RCPtrIgnored);
1028 SSMR3GetRCPtr(pSSM, &RCPtrIgnored);
1029#ifdef RT_OS_DARWIN
1030 if ( SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(3,0,0)
1031 && SSMR3HandleVersion(pSSM) < VBOX_FULL_VERSION_MAKE(3,1,0)
1032 && SSMR3HandleRevision(pSSM) >= 48858
1033 && ( !strcmp(SSMR3HandleHostOSAndArch(pSSM), "darwin.x86")
1034 || !strcmp(SSMR3HandleHostOSAndArch(pSSM), "") )
1035 )
1036 SSMR3Skip(pSSM, 16384);
1037 else
1038 SSMR3Skip(pSSM, 8192);
1039#else
1040 SSMR3Skip(pSSM, 8192);
1041#endif
1042 }
1043
1044 /*
1045 * Restore the VMCPU states. VCPU 0 is always started.
1046 */
1047 VMCPU_SET_STATE(&pVM->aCpus[0], VMCPUSTATE_STARTED);
1048 for (VMCPUID i = 1; i < pVM->cCpus; i++)
1049 {
1050 bool fStarted;
1051 int rc = SSMR3GetBool(pSSM, &fStarted);
1052 if (RT_FAILURE(rc))
1053 return rc;
1054 VMCPU_SET_STATE(&pVM->aCpus[i], fStarted ? VMCPUSTATE_STARTED : VMCPUSTATE_STOPPED);
1055 }
1056
1057 /* terminator */
1058 uint32_t u32;
1059 int rc = SSMR3GetU32(pSSM, &u32);
1060 if (RT_FAILURE(rc))
1061 return rc;
1062 if (u32 != UINT32_MAX)
1063 {
1064 AssertMsgFailed(("u32=%#x\n", u32));
1065 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1066 }
1067 return VINF_SUCCESS;
1068}
1069
1070
1071/**
1072 * Resolve a builtin RC symbol.
1073 *
1074 * Called by PDM when loading or relocating RC modules.
1075 *
1076 * @returns VBox status
1077 * @param pVM Pointer to the VM.
1078 * @param pszSymbol Symbol to resolv
1079 * @param pRCPtrValue Where to store the symbol value.
1080 *
1081 * @remark This has to work before VMMR3Relocate() is called.
1082 */
1083VMMR3_INT_DECL(int) VMMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
1084{
1085 if (!strcmp(pszSymbol, "g_Logger"))
1086 {
1087 if (pVM->vmm.s.pRCLoggerR3)
1088 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
1089 *pRCPtrValue = pVM->vmm.s.pRCLoggerRC;
1090 }
1091 else if (!strcmp(pszSymbol, "g_RelLogger"))
1092 {
1093#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1094 if (pVM->vmm.s.pRCRelLoggerR3)
1095 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
1096 *pRCPtrValue = pVM->vmm.s.pRCRelLoggerRC;
1097#else
1098 *pRCPtrValue = NIL_RTRCPTR;
1099#endif
1100 }
1101 else
1102 return VERR_SYMBOL_NOT_FOUND;
1103 return VINF_SUCCESS;
1104}
1105
1106
1107/**
1108 * Suspends the CPU yielder.
1109 *
1110 * @param pVM Pointer to the VM.
1111 */
1112VMMR3_INT_DECL(void) VMMR3YieldSuspend(PVM pVM)
1113{
1114 VMCPU_ASSERT_EMT(&pVM->aCpus[0]);
1115 if (!pVM->vmm.s.cYieldResumeMillies)
1116 {
1117 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1118 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1119 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1120 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1121 else
1122 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1123 TMTimerStop(pVM->vmm.s.pYieldTimer);
1124 }
1125 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1126}
1127
1128
1129/**
1130 * Stops the CPU yielder.
1131 *
1132 * @param pVM Pointer to the VM.
1133 */
1134VMMR3_INT_DECL(void) VMMR3YieldStop(PVM pVM)
1135{
1136 if (!pVM->vmm.s.cYieldResumeMillies)
1137 TMTimerStop(pVM->vmm.s.pYieldTimer);
1138 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1139 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1140}
1141
1142
1143/**
1144 * Resumes the CPU yielder when it has been a suspended or stopped.
1145 *
1146 * @param pVM Pointer to the VM.
1147 */
1148VMMR3_INT_DECL(void) VMMR3YieldResume(PVM pVM)
1149{
1150 if (pVM->vmm.s.cYieldResumeMillies)
1151 {
1152 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1153 pVM->vmm.s.cYieldResumeMillies = 0;
1154 }
1155}
1156
1157
1158/**
1159 * Internal timer callback function.
1160 *
1161 * @param pVM The VM.
1162 * @param pTimer The timer handle.
1163 * @param pvUser User argument specified upon timer creation.
1164 */
1165static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1166{
1167 NOREF(pvUser);
1168
1169 /*
1170 * This really needs some careful tuning. While we shouldn't be too greedy since
1171 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1172 * because that'll cause us to stop up.
1173 *
1174 * The current logic is to use the default interval when there is no lag worth
1175 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1176 *
1177 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1178 * so the lag is up to date.)
1179 */
1180 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1181 if ( u64Lag < 50000000 /* 50ms */
1182 || ( u64Lag < 1000000000 /* 1s */
1183 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1184 )
1185 {
1186 uint64_t u64Elapsed = RTTimeNanoTS();
1187 pVM->vmm.s.u64LastYield = u64Elapsed;
1188
1189 RTThreadYield();
1190
1191#ifdef LOG_ENABLED
1192 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1193 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1194#endif
1195 }
1196 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1197}
1198
1199
1200/**
1201 * Executes guest code in the raw-mode context.
1202 *
1203 * @param pVM Pointer to the VM.
1204 * @param pVCpu Pointer to the VMCPU.
1205 */
1206VMMR3_INT_DECL(int) VMMR3RawRunGC(PVM pVM, PVMCPU pVCpu)
1207{
1208 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1209
1210 AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
1211
1212 /*
1213 * Set the hypervisor to resume executing a CPUM resume function
1214 * in CPUMRCA.asm.
1215 */
1216 CPUMSetHyperState(pVCpu,
1217 CPUMGetGuestEFlags(pVCpu) & X86_EFL_VM
1218 ? pVM->vmm.s.pfnCPUMRCResumeGuestV86
1219 : pVM->vmm.s.pfnCPUMRCResumeGuest, /* eip */
1220 pVCpu->vmm.s.pbEMTStackBottomRC, /* esp */
1221 0, /* eax */
1222 VM_RC_ADDR(pVM, &pVCpu->cpum) /* edx */);
1223
1224 /*
1225 * We hide log flushes (outer) and hypervisor interrupts (inner).
1226 */
1227 for (;;)
1228 {
1229#ifdef VBOX_STRICT
1230 if (RT_UNLIKELY(!CPUMGetHyperCR3(pVCpu) || CPUMGetHyperCR3(pVCpu) != PGMGetHyperCR3(pVCpu)))
1231 EMR3FatalError(pVCpu, VERR_VMM_HYPER_CR3_MISMATCH);
1232 PGMMapCheck(pVM);
1233#endif
1234 int rc;
1235 do
1236 {
1237#ifdef NO_SUPCALLR0VMM
1238 rc = VERR_GENERAL_FAILURE;
1239#else
1240 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
1241 if (RT_LIKELY(rc == VINF_SUCCESS))
1242 rc = pVCpu->vmm.s.iLastGZRc;
1243#endif
1244 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1245
1246 /*
1247 * Flush the logs.
1248 */
1249#ifdef LOG_ENABLED
1250 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
1251 if ( pLogger
1252 && pLogger->offScratch > 0)
1253 RTLogFlushRC(NULL, pLogger);
1254#endif
1255#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1256 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
1257 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1258 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
1259#endif
1260 if (rc != VINF_VMM_CALL_HOST)
1261 {
1262 Log2(("VMMR3RawRunGC: returns %Rrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1263 return rc;
1264 }
1265 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
1266 if (RT_FAILURE(rc))
1267 return rc;
1268 /* Resume GC */
1269 }
1270}
1271
1272
1273/**
1274 * Executes guest code (Intel VT-x and AMD-V).
1275 *
1276 * @param pVM Pointer to the VM.
1277 * @param pVCpu Pointer to the VMCPU.
1278 */
1279VMMR3_INT_DECL(int) VMMR3HmRunGC(PVM pVM, PVMCPU pVCpu)
1280{
1281 Log2(("VMMR3HmRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1282
1283 for (;;)
1284 {
1285 int rc;
1286 do
1287 {
1288#ifdef NO_SUPCALLR0VMM
1289 rc = VERR_GENERAL_FAILURE;
1290#else
1291 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HM_RUN, pVCpu->idCpu);
1292 if (RT_LIKELY(rc == VINF_SUCCESS))
1293 rc = pVCpu->vmm.s.iLastGZRc;
1294#endif
1295 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1296
1297#if 0 /* todo triggers too often */
1298 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TO_R3));
1299#endif
1300
1301#ifdef LOG_ENABLED
1302 /*
1303 * Flush the log
1304 */
1305 PVMMR0LOGGER pR0LoggerR3 = pVCpu->vmm.s.pR0LoggerR3;
1306 if ( pR0LoggerR3
1307 && pR0LoggerR3->Logger.offScratch > 0)
1308 RTLogFlushR0(NULL, &pR0LoggerR3->Logger);
1309#endif /* !LOG_ENABLED */
1310 if (rc != VINF_VMM_CALL_HOST)
1311 {
1312 Log2(("VMMR3HmRunGC: returns %Rrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1313 return rc;
1314 }
1315 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
1316 if (RT_FAILURE(rc))
1317 return rc;
1318 /* Resume R0 */
1319 }
1320}
1321
1322/**
1323 * VCPU worker for VMMSendSipi.
1324 *
1325 * @param pVM Pointer to the VM.
1326 * @param idCpu Virtual CPU to perform SIPI on
1327 * @param uVector SIPI vector
1328 */
1329DECLCALLBACK(int) vmmR3SendSipi(PVM pVM, VMCPUID idCpu, uint32_t uVector)
1330{
1331 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1332 VMCPU_ASSERT_EMT(pVCpu);
1333
1334 /** @todo what are we supposed to do if the processor is already running? */
1335 if (EMGetState(pVCpu) != EMSTATE_WAIT_SIPI)
1336 return VERR_ACCESS_DENIED;
1337
1338
1339 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1340
1341 pCtx->cs.Sel = uVector << 8;
1342 pCtx->cs.ValidSel = uVector << 8;
1343 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1344 pCtx->cs.u64Base = uVector << 12;
1345 pCtx->cs.u32Limit = UINT32_C(0x0000ffff);
1346 pCtx->rip = 0;
1347
1348 Log(("vmmR3SendSipi for VCPU %d with vector %x\n", uVector));
1349
1350# if 1 /* If we keep the EMSTATE_WAIT_SIPI method, then move this to EM.cpp. */
1351 EMSetState(pVCpu, EMSTATE_HALTED);
1352 return VINF_EM_RESCHEDULE;
1353# else /* And if we go the VMCPU::enmState way it can stay here. */
1354 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STOPPED);
1355 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1356 return VINF_SUCCESS;
1357# endif
1358}
1359
1360DECLCALLBACK(int) vmmR3SendInitIpi(PVM pVM, VMCPUID idCpu)
1361{
1362 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1363 VMCPU_ASSERT_EMT(pVCpu);
1364
1365 Log(("vmmR3SendInitIpi for VCPU %d\n", idCpu));
1366 CPUMR3ResetCpu(pVCpu);
1367 return VINF_EM_WAIT_SIPI;
1368}
1369
1370/**
1371 * Sends SIPI to the virtual CPU by setting CS:EIP into vector-dependent state
1372 * and unhalting processor
1373 *
1374 * @param pVM Pointer to the VM.
1375 * @param idCpu Virtual CPU to perform SIPI on
1376 * @param uVector SIPI vector
1377 */
1378VMMR3_INT_DECL(void) VMMR3SendSipi(PVM pVM, VMCPUID idCpu, uint32_t uVector)
1379{
1380 AssertReturnVoid(idCpu < pVM->cCpus);
1381
1382 int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendSipi, 3, pVM, idCpu, uVector);
1383 AssertRC(rc);
1384}
1385
1386/**
1387 * Sends init IPI to the virtual CPU.
1388 *
1389 * @param pVM Pointer to the VM.
1390 * @param idCpu Virtual CPU to perform int IPI on
1391 */
1392VMMR3_INT_DECL(void) VMMR3SendInitIpi(PVM pVM, VMCPUID idCpu)
1393{
1394 AssertReturnVoid(idCpu < pVM->cCpus);
1395
1396 int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendInitIpi, 2, pVM, idCpu);
1397 AssertRC(rc);
1398}
1399
1400/**
1401 * Registers the guest memory range that can be used for patching
1402 *
1403 * @returns VBox status code.
1404 * @param pVM Pointer to the VM.
1405 * @param pPatchMem Patch memory range
1406 * @param cbPatchMem Size of the memory range
1407 */
1408VMMR3DECL(int) VMMR3RegisterPatchMemory(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1409{
1410 VM_ASSERT_EMT(pVM);
1411 if (HMIsEnabled(pVM))
1412 return HMR3EnablePatching(pVM, pPatchMem, cbPatchMem);
1413
1414 return VERR_NOT_SUPPORTED;
1415}
1416
1417/**
1418 * Deregisters the guest memory range that can be used for patching
1419 *
1420 * @returns VBox status code.
1421 * @param pVM Pointer to the VM.
1422 * @param pPatchMem Patch memory range
1423 * @param cbPatchMem Size of the memory range
1424 */
1425VMMR3DECL(int) VMMR3DeregisterPatchMemory(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1426{
1427 if (HMIsEnabled(pVM))
1428 return HMR3DisablePatching(pVM, pPatchMem, cbPatchMem);
1429
1430 return VINF_SUCCESS;
1431}
1432
1433
1434/**
1435 * Count returns and have the last non-caller EMT wake up the caller.
1436 *
1437 * @returns VBox strict informational status code for EM scheduling. No failures
1438 * will be returned here, those are for the caller only.
1439 *
1440 * @param pVM Pointer to the VM.
1441 */
1442DECL_FORCE_INLINE(int) vmmR3EmtRendezvousNonCallerReturn(PVM pVM)
1443{
1444 int rcRet = ASMAtomicReadS32(&pVM->vmm.s.i32RendezvousStatus);
1445 uint32_t cReturned = ASMAtomicIncU32(&pVM->vmm.s.cRendezvousEmtsReturned);
1446 if (cReturned == pVM->cCpus - 1U)
1447 {
1448 int rc = RTSemEventSignal(pVM->vmm.s.hEvtRendezvousDoneCaller);
1449 AssertLogRelRC(rc);
1450 }
1451
1452 AssertLogRelMsgReturn( rcRet <= VINF_SUCCESS
1453 || (rcRet >= VINF_EM_FIRST && rcRet <= VINF_EM_LAST),
1454 ("%Rrc\n", rcRet),
1455 VERR_IPE_UNEXPECTED_INFO_STATUS);
1456 return RT_SUCCESS(rcRet) ? rcRet : VINF_SUCCESS;
1457}
1458
1459
1460/**
1461 * Common worker for VMMR3EmtRendezvous and VMMR3EmtRendezvousFF.
1462 *
1463 * @returns VBox strict informational status code for EM scheduling. No failures
1464 * will be returned here, those are for the caller only. When
1465 * fIsCaller is set, VINF_SUCCESS is always returned.
1466 *
1467 * @param pVM Pointer to the VM.
1468 * @param pVCpu The VMCPU structure for the calling EMT.
1469 * @param fIsCaller Whether we're the VMMR3EmtRendezvous caller or
1470 * not.
1471 * @param fFlags The flags.
1472 * @param pfnRendezvous The callback.
1473 * @param pvUser The user argument for the callback.
1474 */
1475static int vmmR3EmtRendezvousCommon(PVM pVM, PVMCPU pVCpu, bool fIsCaller,
1476 uint32_t fFlags, PFNVMMEMTRENDEZVOUS pfnRendezvous, void *pvUser)
1477{
1478 int rc;
1479
1480 /*
1481 * Enter, the last EMT triggers the next callback phase.
1482 */
1483 uint32_t cEntered = ASMAtomicIncU32(&pVM->vmm.s.cRendezvousEmtsEntered);
1484 if (cEntered != pVM->cCpus)
1485 {
1486 if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE)
1487 {
1488 /* Wait for our turn. */
1489 rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousEnterOneByOne, RT_INDEFINITE_WAIT);
1490 AssertLogRelRC(rc);
1491 }
1492 else if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE)
1493 {
1494 /* Wait for the last EMT to arrive and wake everyone up. */
1495 rc = RTSemEventMultiWait(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce, RT_INDEFINITE_WAIT);
1496 AssertLogRelRC(rc);
1497 }
1498 else if ( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING
1499 || (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING)
1500 {
1501 /* Wait for our turn. */
1502 rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu], RT_INDEFINITE_WAIT);
1503 AssertLogRelRC(rc);
1504 }
1505 else
1506 {
1507 Assert((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE);
1508
1509 /*
1510 * The execute once is handled specially to optimize the code flow.
1511 *
1512 * The last EMT to arrive will perform the callback and the other
1513 * EMTs will wait on the Done/DoneCaller semaphores (instead of
1514 * the EnterOneByOne/AllAtOnce) in the meanwhile. When the callback
1515 * returns, that EMT will initiate the normal return sequence.
1516 */
1517 if (!fIsCaller)
1518 {
1519 rc = RTSemEventMultiWait(pVM->vmm.s.hEvtMulRendezvousDone, RT_INDEFINITE_WAIT);
1520 AssertLogRelRC(rc);
1521
1522 return vmmR3EmtRendezvousNonCallerReturn(pVM);
1523 }
1524 return VINF_SUCCESS;
1525 }
1526 }
1527 else
1528 {
1529 /*
1530 * All EMTs are waiting, clear the FF and take action according to the
1531 * execution method.
1532 */
1533 VM_FF_CLEAR(pVM, VM_FF_EMT_RENDEZVOUS);
1534
1535 if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE)
1536 {
1537 /* Wake up everyone. */
1538 rc = RTSemEventMultiSignal(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce);
1539 AssertLogRelRC(rc);
1540 }
1541 else if ( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING
1542 || (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING)
1543 {
1544 /* Figure out who to wake up and wake it up. If it's ourself, then
1545 it's easy otherwise wait for our turn. */
1546 VMCPUID iFirst = (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING
1547 ? 0
1548 : pVM->cCpus - 1U;
1549 if (pVCpu->idCpu != iFirst)
1550 {
1551 rc = RTSemEventSignal(pVM->vmm.s.pahEvtRendezvousEnterOrdered[iFirst]);
1552 AssertLogRelRC(rc);
1553 rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu], RT_INDEFINITE_WAIT);
1554 AssertLogRelRC(rc);
1555 }
1556 }
1557 /* else: execute the handler on the current EMT and wake up one or more threads afterwards. */
1558 }
1559
1560
1561 /*
1562 * Do the callback and update the status if necessary.
1563 */
1564 if ( !(fFlags & VMMEMTRENDEZVOUS_FLAGS_STOP_ON_ERROR)
1565 || RT_SUCCESS(ASMAtomicUoReadS32(&pVM->vmm.s.i32RendezvousStatus)) )
1566 {
1567 VBOXSTRICTRC rcStrict = pfnRendezvous(pVM, pVCpu, pvUser);
1568 if (rcStrict != VINF_SUCCESS)
1569 {
1570 AssertLogRelMsg( rcStrict <= VINF_SUCCESS
1571 || (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST),
1572 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1573 int32_t i32RendezvousStatus;
1574 do
1575 {
1576 i32RendezvousStatus = ASMAtomicUoReadS32(&pVM->vmm.s.i32RendezvousStatus);
1577 if ( rcStrict == i32RendezvousStatus
1578 || RT_FAILURE(i32RendezvousStatus)
1579 || ( i32RendezvousStatus != VINF_SUCCESS
1580 && rcStrict > i32RendezvousStatus))
1581 break;
1582 } while (!ASMAtomicCmpXchgS32(&pVM->vmm.s.i32RendezvousStatus, VBOXSTRICTRC_VAL(rcStrict), i32RendezvousStatus));
1583 }
1584 }
1585
1586 /*
1587 * Increment the done counter and take action depending on whether we're
1588 * the last to finish callback execution.
1589 */
1590 uint32_t cDone = ASMAtomicIncU32(&pVM->vmm.s.cRendezvousEmtsDone);
1591 if ( cDone != pVM->cCpus
1592 && (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE)
1593 {
1594 /* Signal the next EMT? */
1595 if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE)
1596 {
1597 rc = RTSemEventSignal(pVM->vmm.s.hEvtRendezvousEnterOneByOne);
1598 AssertLogRelRC(rc);
1599 }
1600 else if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_ASCENDING)
1601 {
1602 Assert(cDone == pVCpu->idCpu + 1U);
1603 rc = RTSemEventSignal(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu + 1U]);
1604 AssertLogRelRC(rc);
1605 }
1606 else if ((fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) == VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING)
1607 {
1608 Assert(pVM->cCpus - cDone == pVCpu->idCpu);
1609 rc = RTSemEventSignal(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVM->cCpus - cDone - 1U]);
1610 AssertLogRelRC(rc);
1611 }
1612
1613 /* Wait for the rest to finish (the caller waits on hEvtRendezvousDoneCaller). */
1614 if (!fIsCaller)
1615 {
1616 rc = RTSemEventMultiWait(pVM->vmm.s.hEvtMulRendezvousDone, RT_INDEFINITE_WAIT);
1617 AssertLogRelRC(rc);
1618 }
1619 }
1620 else
1621 {
1622 /* Callback execution is all done, tell the rest to return. */
1623 rc = RTSemEventMultiSignal(pVM->vmm.s.hEvtMulRendezvousDone);
1624 AssertLogRelRC(rc);
1625 }
1626
1627 if (!fIsCaller)
1628 return vmmR3EmtRendezvousNonCallerReturn(pVM);
1629 return VINF_SUCCESS;
1630}
1631
1632
1633/**
1634 * Called in response to VM_FF_EMT_RENDEZVOUS.
1635 *
1636 * @returns VBox strict status code - EM scheduling. No errors will be returned
1637 * here, nor will any non-EM scheduling status codes be returned.
1638 *
1639 * @param pVM Pointer to the VM.
1640 * @param pVCpu The handle of the calling EMT.
1641 *
1642 * @thread EMT
1643 */
1644VMMR3_INT_DECL(int) VMMR3EmtRendezvousFF(PVM pVM, PVMCPU pVCpu)
1645{
1646 Assert(!pVCpu->vmm.s.fInRendezvous);
1647 pVCpu->vmm.s.fInRendezvous = true;
1648 int rc = vmmR3EmtRendezvousCommon(pVM, pVCpu, false /* fIsCaller */, pVM->vmm.s.fRendezvousFlags,
1649 pVM->vmm.s.pfnRendezvous, pVM->vmm.s.pvRendezvousUser);
1650 pVCpu->vmm.s.fInRendezvous = false;
1651 return rc;
1652}
1653
1654
1655/**
1656 * EMT rendezvous.
1657 *
1658 * Gathers all the EMTs and execute some code on each of them, either in a one
1659 * by one fashion or all at once.
1660 *
1661 * @returns VBox strict status code. This will be the first error,
1662 * VINF_SUCCESS, or an EM scheduling status code.
1663 *
1664 * @param pVM Pointer to the VM.
1665 * @param fFlags Flags indicating execution methods. See
1666 * grp_VMMR3EmtRendezvous_fFlags.
1667 * @param pfnRendezvous The callback.
1668 * @param pvUser User argument for the callback.
1669 *
1670 * @thread Any.
1671 */
1672VMMR3DECL(int) VMMR3EmtRendezvous(PVM pVM, uint32_t fFlags, PFNVMMEMTRENDEZVOUS pfnRendezvous, void *pvUser)
1673{
1674 /*
1675 * Validate input.
1676 */
1677 AssertMsg( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_INVALID
1678 && (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) <= VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING
1679 && !(fFlags & ~VMMEMTRENDEZVOUS_FLAGS_VALID_MASK), ("%#x\n", fFlags));
1680 AssertMsg( !(fFlags & VMMEMTRENDEZVOUS_FLAGS_STOP_ON_ERROR)
1681 || ( (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE
1682 && (fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK) != VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE),
1683 ("type %u\n", fFlags & VMMEMTRENDEZVOUS_FLAGS_TYPE_MASK));
1684
1685 VBOXSTRICTRC rcStrict;
1686 PVMCPU pVCpu = VMMGetCpu(pVM);
1687 if (!pVCpu)
1688 /*
1689 * Forward the request to an EMT thread.
1690 */
1691 rcStrict = VMR3ReqCallWait(pVM, VMCPUID_ANY,
1692 (PFNRT)VMMR3EmtRendezvous, 4, pVM, fFlags, pfnRendezvous, pvUser);
1693 else if (pVM->cCpus == 1)
1694 {
1695 /*
1696 * Shortcut for the single EMT case.
1697 */
1698 AssertLogRelReturn(!pVCpu->vmm.s.fInRendezvous, VERR_DEADLOCK);
1699 pVCpu->vmm.s.fInRendezvous = true;
1700 rcStrict = pfnRendezvous(pVM, pVCpu, pvUser);
1701 pVCpu->vmm.s.fInRendezvous = false;
1702 }
1703 else
1704 {
1705 /*
1706 * Spin lock. If busy, wait for the other EMT to finish while keeping a
1707 * lookout of the RENDEZVOUS FF.
1708 */
1709 int rc;
1710 rcStrict = VINF_SUCCESS;
1711 if (RT_UNLIKELY(!ASMAtomicCmpXchgU32(&pVM->vmm.s.u32RendezvousLock, 0x77778888, 0)))
1712 {
1713 AssertLogRelReturn(!pVCpu->vmm.s.fInRendezvous, VERR_DEADLOCK);
1714
1715 while (!ASMAtomicCmpXchgU32(&pVM->vmm.s.u32RendezvousLock, 0x77778888, 0))
1716 {
1717 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1718 {
1719 rc = VMMR3EmtRendezvousFF(pVM, pVCpu);
1720 if ( rc != VINF_SUCCESS
1721 && ( rcStrict == VINF_SUCCESS
1722 || rcStrict > rc))
1723 rcStrict = rc;
1724 /** @todo Perhaps deal with termination here? */
1725 }
1726 ASMNopPause();
1727 }
1728 }
1729 Assert(!VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS));
1730 Assert(!pVCpu->vmm.s.fInRendezvous);
1731 pVCpu->vmm.s.fInRendezvous = true;
1732
1733 /*
1734 * Clear the slate. This is a semaphore ping-pong orgy. :-)
1735 */
1736 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1737 {
1738 rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[i], 0);
1739 AssertLogRelMsg(rc == VERR_TIMEOUT || rc == VINF_SUCCESS, ("%Rrc\n", rc));
1740 }
1741 rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousEnterOneByOne, 0); AssertLogRelMsg(rc == VERR_TIMEOUT || rc == VINF_SUCCESS, ("%Rrc\n", rc));
1742 rc = RTSemEventMultiReset(pVM->vmm.s.hEvtMulRendezvousEnterAllAtOnce); AssertLogRelRC(rc);
1743 rc = RTSemEventMultiReset(pVM->vmm.s.hEvtMulRendezvousDone); AssertLogRelRC(rc);
1744 rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousDoneCaller, 0); AssertLogRelMsg(rc == VERR_TIMEOUT || rc == VINF_SUCCESS, ("%Rrc\n", rc));
1745 ASMAtomicWriteU32(&pVM->vmm.s.cRendezvousEmtsEntered, 0);
1746 ASMAtomicWriteU32(&pVM->vmm.s.cRendezvousEmtsDone, 0);
1747 ASMAtomicWriteU32(&pVM->vmm.s.cRendezvousEmtsReturned, 0);
1748 ASMAtomicWriteS32(&pVM->vmm.s.i32RendezvousStatus, VINF_SUCCESS);
1749 ASMAtomicWritePtr((void * volatile *)&pVM->vmm.s.pfnRendezvous, (void *)(uintptr_t)pfnRendezvous);
1750 ASMAtomicWritePtr(&pVM->vmm.s.pvRendezvousUser, pvUser);
1751 ASMAtomicWriteU32(&pVM->vmm.s.fRendezvousFlags, fFlags);
1752
1753 /*
1754 * Set the FF and poke the other EMTs.
1755 */
1756 VM_FF_SET(pVM, VM_FF_EMT_RENDEZVOUS);
1757 VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_POKE);
1758
1759 /*
1760 * Do the same ourselves.
1761 */
1762 vmmR3EmtRendezvousCommon(pVM, pVCpu, true /* fIsCaller */, fFlags, pfnRendezvous, pvUser);
1763
1764 /*
1765 * The caller waits for the other EMTs to be done and return before doing
1766 * the cleanup. This makes away with wakeup / reset races we would otherwise
1767 * risk in the multiple release event semaphore code (hEvtRendezvousDoneCaller).
1768 */
1769 rc = RTSemEventWait(pVM->vmm.s.hEvtRendezvousDoneCaller, RT_INDEFINITE_WAIT);
1770 AssertLogRelRC(rc);
1771
1772 /*
1773 * Get the return code and clean up a little bit.
1774 */
1775 int rcMy = pVM->vmm.s.i32RendezvousStatus;
1776 ASMAtomicWriteNullPtr((void * volatile *)&pVM->vmm.s.pfnRendezvous);
1777
1778 ASMAtomicWriteU32(&pVM->vmm.s.u32RendezvousLock, 0);
1779 pVCpu->vmm.s.fInRendezvous = false;
1780
1781 /*
1782 * Merge rcStrict and rcMy.
1783 */
1784 AssertRC(VBOXSTRICTRC_VAL(rcStrict));
1785 if ( rcMy != VINF_SUCCESS
1786 && ( rcStrict == VINF_SUCCESS
1787 || rcStrict > rcMy))
1788 rcStrict = rcMy;
1789 }
1790
1791 AssertLogRelMsgReturn( rcStrict <= VINF_SUCCESS
1792 || (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST),
1793 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
1794 VERR_IPE_UNEXPECTED_INFO_STATUS);
1795 return VBOXSTRICTRC_VAL(rcStrict);
1796}
1797
1798
1799/**
1800 * Disables/enables EMT rendezvous.
1801 *
1802 * This is used to make sure EMT rendezvous does not take place while
1803 * processing a priority request.
1804 *
1805 * @returns Old rendezvous-disabled state.
1806 * @param pVCpu The handle of the calling EMT.
1807 * @param fDisabled True if disabled, false if enabled.
1808 */
1809VMMR3_INT_DECL(bool) VMMR3EmtRendezvousSetDisabled(PVMCPU pVCpu, bool fDisabled)
1810{
1811 VMCPU_ASSERT_EMT(pVCpu);
1812 bool fOld = pVCpu->vmm.s.fInRendezvous;
1813 pVCpu->vmm.s.fInRendezvous = fDisabled;
1814 return fOld;
1815}
1816
1817
1818/**
1819 * Read from the ring 0 jump buffer stack
1820 *
1821 * @returns VBox status code.
1822 *
1823 * @param pVM Pointer to the VM.
1824 * @param idCpu The ID of the source CPU context (for the address).
1825 * @param R0Addr Where to start reading.
1826 * @param pvBuf Where to store the data we've read.
1827 * @param cbRead The number of bytes to read.
1828 */
1829VMMR3_INT_DECL(int) VMMR3ReadR0Stack(PVM pVM, VMCPUID idCpu, RTHCUINTPTR R0Addr, void *pvBuf, size_t cbRead)
1830{
1831 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1832 AssertReturn(pVCpu, VERR_INVALID_PARAMETER);
1833
1834#ifdef VMM_R0_SWITCH_STACK
1835 RTHCUINTPTR off = R0Addr - MMHyperCCToR0(pVM, pVCpu->vmm.s.pbEMTStackR3);
1836#else
1837 RTHCUINTPTR off = pVCpu->vmm.s.CallRing3JmpBufR0.cbSavedStack - (pVCpu->vmm.s.CallRing3JmpBufR0.SpCheck - R0Addr);
1838#endif
1839 if ( off > VMM_STACK_SIZE
1840 || off + cbRead >= VMM_STACK_SIZE)
1841 return VERR_INVALID_POINTER;
1842
1843 memcpy(pvBuf, &pVCpu->vmm.s.pbEMTStackR3[off], cbRead);
1844 return VINF_SUCCESS;
1845}
1846
1847
1848/**
1849 * Calls a RC function.
1850 *
1851 * @param pVM Pointer to the VM.
1852 * @param RCPtrEntry The address of the RC function.
1853 * @param cArgs The number of arguments in the ....
1854 * @param ... Arguments to the function.
1855 */
1856VMMR3DECL(int) VMMR3CallRC(PVM pVM, RTRCPTR RCPtrEntry, unsigned cArgs, ...)
1857{
1858 va_list args;
1859 va_start(args, cArgs);
1860 int rc = VMMR3CallRCV(pVM, RCPtrEntry, cArgs, args);
1861 va_end(args);
1862 return rc;
1863}
1864
1865
1866/**
1867 * Calls a RC function.
1868 *
1869 * @param pVM Pointer to the VM.
1870 * @param RCPtrEntry The address of the RC function.
1871 * @param cArgs The number of arguments in the ....
1872 * @param args Arguments to the function.
1873 */
1874VMMR3DECL(int) VMMR3CallRCV(PVM pVM, RTRCPTR RCPtrEntry, unsigned cArgs, va_list args)
1875{
1876 /* Raw mode implies 1 VCPU. */
1877 AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
1878 PVMCPU pVCpu = &pVM->aCpus[0];
1879
1880 Log2(("VMMR3CallGCV: RCPtrEntry=%RRv cArgs=%d\n", RCPtrEntry, cArgs));
1881
1882 /*
1883 * Setup the call frame using the trampoline.
1884 */
1885 CPUMSetHyperState(pVCpu,
1886 pVM->vmm.s.pfnCallTrampolineRC, /* eip */
1887 pVCpu->vmm.s.pbEMTStackBottomRC - cArgs * sizeof(RTGCUINTPTR32), /* esp */
1888 RCPtrEntry, /* eax */
1889 cArgs /* edx */
1890 );
1891
1892 memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
1893 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVCpu->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE) - cArgs;
1894 int i = cArgs;
1895 while (i-- > 0)
1896 *pFrame++ = va_arg(args, RTGCUINTPTR32);
1897
1898 CPUMPushHyper(pVCpu, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
1899 CPUMPushHyper(pVCpu, RCPtrEntry); /* what to call */
1900
1901 /*
1902 * We hide log flushes (outer) and hypervisor interrupts (inner).
1903 */
1904 for (;;)
1905 {
1906 int rc;
1907 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
1908 do
1909 {
1910#ifdef NO_SUPCALLR0VMM
1911 rc = VERR_GENERAL_FAILURE;
1912#else
1913 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
1914 if (RT_LIKELY(rc == VINF_SUCCESS))
1915 rc = pVCpu->vmm.s.iLastGZRc;
1916#endif
1917 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1918
1919 /*
1920 * Flush the loggers.
1921 */
1922#ifdef LOG_ENABLED
1923 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
1924 if ( pLogger
1925 && pLogger->offScratch > 0)
1926 RTLogFlushRC(NULL, pLogger);
1927#endif
1928#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1929 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
1930 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1931 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
1932#endif
1933 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
1934 VMMR3FatalDump(pVM, pVCpu, rc);
1935 if (rc != VINF_VMM_CALL_HOST)
1936 {
1937 Log2(("VMMR3CallGCV: returns %Rrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1938 return rc;
1939 }
1940 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
1941 if (RT_FAILURE(rc))
1942 return rc;
1943 }
1944}
1945
1946
1947/**
1948 * Wrapper for SUPR3CallVMMR0Ex which will deal with VINF_VMM_CALL_HOST returns.
1949 *
1950 * @returns VBox status code.
1951 * @param pVM Pointer to the VM.
1952 * @param uOperation Operation to execute.
1953 * @param u64Arg Constant argument.
1954 * @param pReqHdr Pointer to a request header. See SUPR3CallVMMR0Ex for
1955 * details.
1956 */
1957VMMR3DECL(int) VMMR3CallR0(PVM pVM, uint32_t uOperation, uint64_t u64Arg, PSUPVMMR0REQHDR pReqHdr)
1958{
1959 PVMCPU pVCpu = VMMGetCpu(pVM);
1960 AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
1961
1962 /*
1963 * Call Ring-0 entry with init code.
1964 */
1965 int rc;
1966 for (;;)
1967 {
1968#ifdef NO_SUPCALLR0VMM
1969 rc = VERR_GENERAL_FAILURE;
1970#else
1971 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, uOperation, u64Arg, pReqHdr);
1972#endif
1973 /*
1974 * Flush the logs.
1975 */
1976#ifdef LOG_ENABLED
1977 if ( pVCpu->vmm.s.pR0LoggerR3
1978 && pVCpu->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
1979 RTLogFlushR0(NULL, &pVCpu->vmm.s.pR0LoggerR3->Logger);
1980#endif
1981 if (rc != VINF_VMM_CALL_HOST)
1982 break;
1983 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
1984 if (RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1985 break;
1986 /* Resume R0 */
1987 }
1988
1989 AssertLogRelMsgReturn(rc == VINF_SUCCESS || RT_FAILURE(rc),
1990 ("uOperation=%u rc=%Rrc\n", uOperation, rc),
1991 VERR_IPE_UNEXPECTED_INFO_STATUS);
1992 return rc;
1993}
1994
1995
1996/**
1997 * Resumes executing hypervisor code when interrupted by a queue flush or a
1998 * debug event.
1999 *
2000 * @returns VBox status code.
2001 * @param pVM Pointer to the VM.
2002 * @param pVCpu Pointer to the VMCPU.
2003 */
2004VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM, PVMCPU pVCpu)
2005{
2006 Log(("VMMR3ResumeHyper: eip=%RRv esp=%RRv\n", CPUMGetHyperEIP(pVCpu), CPUMGetHyperESP(pVCpu)));
2007 AssertReturn(pVM->cCpus == 1, VERR_RAW_MODE_INVALID_SMP);
2008
2009 /*
2010 * We hide log flushes (outer) and hypervisor interrupts (inner).
2011 */
2012 for (;;)
2013 {
2014 int rc;
2015 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
2016 do
2017 {
2018#ifdef NO_SUPCALLR0VMM
2019 rc = VERR_GENERAL_FAILURE;
2020#else
2021 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
2022 if (RT_LIKELY(rc == VINF_SUCCESS))
2023 rc = pVCpu->vmm.s.iLastGZRc;
2024#endif
2025 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2026
2027 /*
2028 * Flush the loggers.
2029 */
2030#ifdef LOG_ENABLED
2031 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2032 if ( pLogger
2033 && pLogger->offScratch > 0)
2034 RTLogFlushRC(NULL, pLogger);
2035#endif
2036#ifdef VBOX_WITH_RC_RELEASE_LOGGING
2037 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2038 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2039 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2040#endif
2041 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2042 VMMR3FatalDump(pVM, pVCpu, rc);
2043 if (rc != VINF_VMM_CALL_HOST)
2044 {
2045 Log(("VMMR3ResumeHyper: returns %Rrc\n", rc));
2046 return rc;
2047 }
2048 rc = vmmR3ServiceCallRing3Request(pVM, pVCpu);
2049 if (RT_FAILURE(rc))
2050 return rc;
2051 }
2052}
2053
2054
2055/**
2056 * Service a call to the ring-3 host code.
2057 *
2058 * @returns VBox status code.
2059 * @param pVM Pointer to the VM.
2060 * @param pVCpu Pointer to the VMCPU.
2061 * @remark Careful with critsects.
2062 */
2063static int vmmR3ServiceCallRing3Request(PVM pVM, PVMCPU pVCpu)
2064{
2065 /*
2066 * We must also check for pending critsect exits or else we can deadlock
2067 * when entering other critsects here.
2068 */
2069 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
2070 PDMCritSectFF(pVCpu);
2071
2072 switch (pVCpu->vmm.s.enmCallRing3Operation)
2073 {
2074 /*
2075 * Acquire a critical section.
2076 */
2077 case VMMCALLRING3_PDM_CRIT_SECT_ENTER:
2078 {
2079 pVCpu->vmm.s.rcCallRing3 = PDMR3CritSectEnterEx((PPDMCRITSECT)(uintptr_t)pVCpu->vmm.s.u64CallRing3Arg,
2080 true /*fCallRing3*/);
2081 break;
2082 }
2083
2084 /*
2085 * Acquire the PDM lock.
2086 */
2087 case VMMCALLRING3_PDM_LOCK:
2088 {
2089 pVCpu->vmm.s.rcCallRing3 = PDMR3LockCall(pVM);
2090 break;
2091 }
2092
2093 /*
2094 * Grow the PGM pool.
2095 */
2096 case VMMCALLRING3_PGM_POOL_GROW:
2097 {
2098 pVCpu->vmm.s.rcCallRing3 = PGMR3PoolGrow(pVM);
2099 break;
2100 }
2101
2102 /*
2103 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2104 */
2105 case VMMCALLRING3_PGM_MAP_CHUNK:
2106 {
2107 pVCpu->vmm.s.rcCallRing3 = PGMR3PhysChunkMap(pVM, pVCpu->vmm.s.u64CallRing3Arg);
2108 break;
2109 }
2110
2111 /*
2112 * Allocates more handy pages.
2113 */
2114 case VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES:
2115 {
2116 pVCpu->vmm.s.rcCallRing3 = PGMR3PhysAllocateHandyPages(pVM);
2117 break;
2118 }
2119
2120 /*
2121 * Allocates a large page.
2122 */
2123 case VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE:
2124 {
2125 pVCpu->vmm.s.rcCallRing3 = PGMR3PhysAllocateLargeHandyPage(pVM, pVCpu->vmm.s.u64CallRing3Arg);
2126 break;
2127 }
2128
2129 /*
2130 * Acquire the PGM lock.
2131 */
2132 case VMMCALLRING3_PGM_LOCK:
2133 {
2134 pVCpu->vmm.s.rcCallRing3 = PGMR3LockCall(pVM);
2135 break;
2136 }
2137
2138 /*
2139 * Acquire the MM hypervisor heap lock.
2140 */
2141 case VMMCALLRING3_MMHYPER_LOCK:
2142 {
2143 pVCpu->vmm.s.rcCallRing3 = MMR3LockCall(pVM);
2144 break;
2145 }
2146
2147#ifdef VBOX_WITH_REM
2148 /*
2149 * Flush REM handler notifications.
2150 */
2151 case VMMCALLRING3_REM_REPLAY_HANDLER_NOTIFICATIONS:
2152 {
2153 REMR3ReplayHandlerNotifications(pVM);
2154 pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2155 break;
2156 }
2157#endif
2158
2159 /*
2160 * This is a noop. We just take this route to avoid unnecessary
2161 * tests in the loops.
2162 */
2163 case VMMCALLRING3_VMM_LOGGER_FLUSH:
2164 pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2165 LogAlways(("*FLUSH*\n"));
2166 break;
2167
2168 /*
2169 * Set the VM error message.
2170 */
2171 case VMMCALLRING3_VM_SET_ERROR:
2172 VMR3SetErrorWorker(pVM);
2173 pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2174 break;
2175
2176 /*
2177 * Set the VM runtime error message.
2178 */
2179 case VMMCALLRING3_VM_SET_RUNTIME_ERROR:
2180 pVCpu->vmm.s.rcCallRing3 = VMR3SetRuntimeErrorWorker(pVM);
2181 break;
2182
2183 /*
2184 * Signal a ring 0 hypervisor assertion.
2185 * Cancel the longjmp operation that's in progress.
2186 */
2187 case VMMCALLRING3_VM_R0_ASSERTION:
2188 pVCpu->vmm.s.enmCallRing3Operation = VMMCALLRING3_INVALID;
2189 pVCpu->vmm.s.CallRing3JmpBufR0.fInRing3Call = false;
2190#ifdef RT_ARCH_X86
2191 pVCpu->vmm.s.CallRing3JmpBufR0.eip = 0;
2192#else
2193 pVCpu->vmm.s.CallRing3JmpBufR0.rip = 0;
2194#endif
2195#ifdef VMM_R0_SWITCH_STACK
2196 *(uint64_t *)pVCpu->vmm.s.pbEMTStackR3 = 0; /* clear marker */
2197#endif
2198 LogRel(("%s", pVM->vmm.s.szRing0AssertMsg1));
2199 LogRel(("%s", pVM->vmm.s.szRing0AssertMsg2));
2200 return VERR_VMM_RING0_ASSERTION;
2201
2202 /*
2203 * A forced switch to ring 0 for preemption purposes.
2204 */
2205 case VMMCALLRING3_VM_R0_PREEMPT:
2206 pVCpu->vmm.s.rcCallRing3 = VINF_SUCCESS;
2207 break;
2208
2209 case VMMCALLRING3_FTM_SET_CHECKPOINT:
2210 pVCpu->vmm.s.rcCallRing3 = FTMR3SetCheckpoint(pVM, (FTMCHECKPOINTTYPE)pVCpu->vmm.s.u64CallRing3Arg);
2211 break;
2212
2213 default:
2214 AssertMsgFailed(("enmCallRing3Operation=%d\n", pVCpu->vmm.s.enmCallRing3Operation));
2215 return VERR_VMM_UNKNOWN_RING3_CALL;
2216 }
2217
2218 pVCpu->vmm.s.enmCallRing3Operation = VMMCALLRING3_INVALID;
2219 return VINF_SUCCESS;
2220}
2221
2222
2223/**
2224 * Displays the Force action Flags.
2225 *
2226 * @param pVM Pointer to the VM.
2227 * @param pHlp The output helpers.
2228 * @param pszArgs The additional arguments (ignored).
2229 */
2230static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2231{
2232 int c;
2233 uint32_t f;
2234 NOREF(pszArgs);
2235
2236#define PRINT_FLAG(prf,flag) do { \
2237 if (f & (prf##flag)) \
2238 { \
2239 static const char *s_psz = #flag; \
2240 if (!(c % 6)) \
2241 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz); \
2242 else \
2243 pHlp->pfnPrintf(pHlp, ", %s", s_psz); \
2244 c++; \
2245 f &= ~(prf##flag); \
2246 } \
2247 } while (0)
2248
2249#define PRINT_GROUP(prf,grp,sfx) do { \
2250 if (f & (prf##grp##sfx)) \
2251 { \
2252 static const char *s_psz = #grp; \
2253 if (!(c % 5)) \
2254 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : " Groups:\n", s_psz); \
2255 else \
2256 pHlp->pfnPrintf(pHlp, ", %s", s_psz); \
2257 c++; \
2258 } \
2259 } while (0)
2260
2261 /*
2262 * The global flags.
2263 */
2264 const uint32_t fGlobalForcedActions = pVM->fGlobalForcedActions;
2265 pHlp->pfnPrintf(pHlp, "Global FFs: %#RX32", fGlobalForcedActions);
2266
2267 /* show the flag mnemonics */
2268 c = 0;
2269 f = fGlobalForcedActions;
2270 PRINT_FLAG(VM_FF_,TM_VIRTUAL_SYNC);
2271 PRINT_FLAG(VM_FF_,PDM_QUEUES);
2272 PRINT_FLAG(VM_FF_,PDM_DMA);
2273 PRINT_FLAG(VM_FF_,DBGF);
2274 PRINT_FLAG(VM_FF_,REQUEST);
2275 PRINT_FLAG(VM_FF_,CHECK_VM_STATE);
2276 PRINT_FLAG(VM_FF_,RESET);
2277 PRINT_FLAG(VM_FF_,EMT_RENDEZVOUS);
2278 PRINT_FLAG(VM_FF_,PGM_NEED_HANDY_PAGES);
2279 PRINT_FLAG(VM_FF_,PGM_NO_MEMORY);
2280 PRINT_FLAG(VM_FF_,PGM_POOL_FLUSH_PENDING);
2281 PRINT_FLAG(VM_FF_,REM_HANDLER_NOTIFY);
2282 PRINT_FLAG(VM_FF_,DEBUG_SUSPEND);
2283 if (f)
2284 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2285 else
2286 pHlp->pfnPrintf(pHlp, "\n");
2287
2288 /* the groups */
2289 c = 0;
2290 f = fGlobalForcedActions;
2291 PRINT_GROUP(VM_FF_,EXTERNAL_SUSPENDED,_MASK);
2292 PRINT_GROUP(VM_FF_,EXTERNAL_HALTED,_MASK);
2293 PRINT_GROUP(VM_FF_,HIGH_PRIORITY_PRE,_MASK);
2294 PRINT_GROUP(VM_FF_,HIGH_PRIORITY_PRE_RAW,_MASK);
2295 PRINT_GROUP(VM_FF_,HIGH_PRIORITY_POST,_MASK);
2296 PRINT_GROUP(VM_FF_,NORMAL_PRIORITY_POST,_MASK);
2297 PRINT_GROUP(VM_FF_,NORMAL_PRIORITY,_MASK);
2298 PRINT_GROUP(VM_FF_,ALL_REM,_MASK);
2299 if (c)
2300 pHlp->pfnPrintf(pHlp, "\n");
2301
2302 /*
2303 * Per CPU flags.
2304 */
2305 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2306 {
2307 const uint32_t fLocalForcedActions = pVM->aCpus[i].fLocalForcedActions;
2308 pHlp->pfnPrintf(pHlp, "CPU %u FFs: %#RX32", i, fLocalForcedActions);
2309
2310 /* show the flag mnemonics */
2311 c = 0;
2312 f = fLocalForcedActions;
2313 PRINT_FLAG(VMCPU_FF_,INTERRUPT_APIC);
2314 PRINT_FLAG(VMCPU_FF_,INTERRUPT_PIC);
2315 PRINT_FLAG(VMCPU_FF_,TIMER);
2316 PRINT_FLAG(VMCPU_FF_,PDM_CRITSECT);
2317 PRINT_FLAG(VMCPU_FF_,PGM_SYNC_CR3);
2318 PRINT_FLAG(VMCPU_FF_,PGM_SYNC_CR3_NON_GLOBAL);
2319 PRINT_FLAG(VMCPU_FF_,TLB_FLUSH);
2320 PRINT_FLAG(VMCPU_FF_,TRPM_SYNC_IDT);
2321 PRINT_FLAG(VMCPU_FF_,SELM_SYNC_TSS);
2322 PRINT_FLAG(VMCPU_FF_,SELM_SYNC_GDT);
2323 PRINT_FLAG(VMCPU_FF_,SELM_SYNC_LDT);
2324 PRINT_FLAG(VMCPU_FF_,INHIBIT_INTERRUPTS);
2325 PRINT_FLAG(VMCPU_FF_,CSAM_SCAN_PAGE);
2326 PRINT_FLAG(VMCPU_FF_,CSAM_PENDING_ACTION);
2327 PRINT_FLAG(VMCPU_FF_,TO_R3);
2328 if (f)
2329 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2330 else
2331 pHlp->pfnPrintf(pHlp, "\n");
2332
2333 if (fLocalForcedActions & VMCPU_FF_INHIBIT_INTERRUPTS)
2334 pHlp->pfnPrintf(pHlp, " intr inhibit RIP: %RGp\n", EMGetInhibitInterruptsPC(&pVM->aCpus[i]));
2335
2336 /* the groups */
2337 c = 0;
2338 f = fLocalForcedActions;
2339 PRINT_GROUP(VMCPU_FF_,EXTERNAL_SUSPENDED,_MASK);
2340 PRINT_GROUP(VMCPU_FF_,EXTERNAL_HALTED,_MASK);
2341 PRINT_GROUP(VMCPU_FF_,HIGH_PRIORITY_PRE,_MASK);
2342 PRINT_GROUP(VMCPU_FF_,HIGH_PRIORITY_PRE_RAW,_MASK);
2343 PRINT_GROUP(VMCPU_FF_,HIGH_PRIORITY_POST,_MASK);
2344 PRINT_GROUP(VMCPU_FF_,NORMAL_PRIORITY_POST,_MASK);
2345 PRINT_GROUP(VMCPU_FF_,NORMAL_PRIORITY,_MASK);
2346 PRINT_GROUP(VMCPU_FF_,RESUME_GUEST,_MASK);
2347 PRINT_GROUP(VMCPU_FF_,HM_TO_R3,_MASK);
2348 PRINT_GROUP(VMCPU_FF_,ALL_REM,_MASK);
2349 if (c)
2350 pHlp->pfnPrintf(pHlp, "\n");
2351 }
2352
2353#undef PRINT_FLAG
2354#undef PRINT_GROUP
2355}
2356
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