TRPM.cpp@ 39405

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Line
1	/* $Id: TRPM.cpp 39078 2011-10-21 14:18:22Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72	/*******************************************************************************
73	* Header Files *
74	*******************************************************************************/
75	#define LOG_GROUP LOG_GROUP_TRPM
76	#include <VBox/vmm/trpm.h>
77	#include <VBox/vmm/cpum.h>
78	#include <VBox/vmm/selm.h>
79	#include <VBox/vmm/ssm.h>
80	#include <VBox/vmm/pdmapi.h>
81	#include <VBox/vmm/em.h>
82	#include <VBox/vmm/pgm.h>
83	#include "internal/pgm.h"
84	#include <VBox/vmm/dbgf.h>
85	#include <VBox/vmm/mm.h>
86	#include <VBox/vmm/stam.h>
87	#include <VBox/vmm/csam.h>
88	#include <VBox/vmm/patm.h>
89	#include "TRPMInternal.h"
90	#include <VBox/vmm/vm.h>
91	#include <VBox/vmm/em.h>
92	#include <VBox/vmm/rem.h>
93	#include <VBox/vmm/hwaccm.h>
94
95	#include <VBox/err.h>
96	#include <VBox/param.h>
97	#include <VBox/log.h>
98	#include <iprt/assert.h>
99	#include <iprt/asm.h>
100	#include <iprt/string.h>
101	#include <iprt/alloc.h>
102
103
104	/*******************************************************************************
105	* Structures and Typedefs *
106	*******************************************************************************/
107	/**
108	* Trap handler function.
109	* @todo need to specialize this as we go along.
110	*/
111	typedef enum TRPMHANDLER
112	{
113	/** Generic Interrupt handler. */
114	TRPM_HANDLER_INT = 0,
115	/** Generic Trap handler. */
116	TRPM_HANDLER_TRAP,
117	/** Trap 8 (\#DF) handler. */
118	TRPM_HANDLER_TRAP_08,
119	/** Trap 12 (\#MC) handler. */
120	TRPM_HANDLER_TRAP_12,
121	/** Max. */
122	TRPM_HANDLER_MAX
123	} TRPMHANDLER, *PTRPMHANDLER;
124
125
126	/*******************************************************************************
127	* Global Variables *
128	*******************************************************************************/
129	/** Preinitialized IDT.
130	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
131	* will use to pick the right address. The u16SegSel is always VMM CS.
132	*/
133	static VBOXIDTE_GENERIC g_aIdt[256] =
134	{
135	/* special trap handler - still, this is an interrupt gate not a trap gate... */
136	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
137	/* generic trap handler. */
138	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
139	/* special interrupt handler. */
140	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
141	/* generic interrupt handler. */
142	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
143	/* special task gate IDT entry (for critical exceptions like #DF). */
144	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
145	/* draft, fixme later when the handler is written. */
146	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
147
148	/* N - M M - T - C - D i */
149	/* o - n o - y - o - e p */
150	/* - e n - p - d - s t */
151	/* - i - e - e - c . */
152	/* - c - - - r */
153	/* ============================================================= */
154	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
155	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
156	#ifdef VBOX_WITH_NMI
157	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
158	#else
159	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160	#endif
161	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
162	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
163	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
164	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
165	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
166	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
167	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
168	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
169	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
170	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
171	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
172	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
173	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
174	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
175	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
176	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
177	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
178	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
179	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
180	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
190	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
191	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
192	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
414	#undef IDTE_TRAP
415	#undef IDTE_TRAP_GEN
416	#undef IDTE_INT
417	#undef IDTE_INT_GEN
418	#undef IDTE_TASK
419	#undef IDTE_UNUSED
420	#undef IDTE_RESERVED
421	};
422
423
424	/** Enable or disable tracking of Guest's IDT. */
425	#define TRPM_TRACK_GUEST_IDT_CHANGES
426
427	/** Enable or disable tracking of Shadow IDT. */
428	#define TRPM_TRACK_SHADOW_IDT_CHANGES
429
430	/** TRPM saved state version. */
431	#define TRPM_SAVED_STATE_VERSION 9
432	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
433
434
435	/*******************************************************************************
436	* Internal Functions *
437	*******************************************************************************/
438	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
439	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
440	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
441
442
443	/**
444	* Initializes the Trap Manager
445	*
446	* @returns VBox status code.
447	* @param pVM The VM to operate on.
448	*/
449	VMMR3DECL(int) TRPMR3Init(PVM pVM)
450	{
451	LogFlow(("TRPMR3Init\n"));
452
453	/*
454	* Assert sizes and alignments.
455	*/
456	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
457	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
458	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
459	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
460
461	/*
462	* Initialize members.
463	*/
464	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
465	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
466
467	for (VMCPUID i = 0; i < pVM->cCpus; i++)
468	{
469	PVMCPU pVCpu = &pVM->aCpus[i];
470
471	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
472	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
473	pVCpu->trpm.s.uActiveVector = ~0;
474	}
475
476	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
477	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
478	pVM->trpm.s.fDisableMonitoring = false;
479	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
480
481	/*
482	* Read the configuration (if any).
483	*/
484	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
485	if (pTRPMNode)
486	{
487	bool f;
488	int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
489	if (RT_SUCCESS(rc))
490	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
491	}
492
493	/* write config summary to log */
494	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
495	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
496
497	/*
498	* Initialize the IDT.
499	* The handler addresses will be set in the TRPMR3Relocate() function.
500	*/
501	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
502	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
503
504	/*
505	* Register the saved state data unit.
506	*/
507	int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
508	NULL, NULL, NULL,
509	NULL, trpmR3Save, NULL,
510	NULL, trpmR3Load, NULL);
511	if (RT_FAILURE(rc))
512	return rc;
513
514	/*
515	* Statistics.
516	*/
517	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
518	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
519	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
520
521	/* traps */
522	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
523	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
524	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
525	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
526	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
527	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
528	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
529	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
530	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
531	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
532	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
533	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
534	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
535	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
536	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
537	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
538	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
539	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
540	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
541	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
542
543	#ifdef VBOX_WITH_STATISTICS
544	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
545	AssertRCReturn(rc, rc);
546	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
547	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
548	for (unsigned i = 0; i < 256; i++)
549	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
550	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
551
552	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
553	AssertRCReturn(rc, rc);
554	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
555	pVM->trpm.s.paStatHostIrqR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatHostIrqR3);
556	for (unsigned i = 0; i < 256; i++)
557	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
558	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
559	#endif
560
561	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
562	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
563	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
564	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
565	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
566	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
567
568	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
569	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
570
571	/*
572	* Default action when entering raw mode for the first time
573	*/
574	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
575	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
576	return 0;
577	}
578
579
580	/**
581	* Applies relocations to data and code managed by this component.
582	*
583	* This function will be called at init and whenever the VMM need
584	* to relocate itself inside the GC.
585	*
586	* @param pVM The VM handle.
587	* @param offDelta Relocation delta relative to old location.
588	*/
589	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
590	{
591	/* Only applies to raw mode which supports only 1 VCPU. */
592	PVMCPU pVCpu = &pVM->aCpus[0];
593
594	LogFlow(("TRPMR3Relocate\n"));
595	/*
596	* Get the trap handler addresses.
597	*
598	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
599	* would make init order impossible if we should assert the presence of these
600	* exports in TRPMR3Init().
601	*/
602	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
603	RT_ZERO(aRCPtrs);
604	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
605	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
606
607	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
608	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
609
610	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
611	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
612
613	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
614	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
615
616	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
617
618	/*
619	* Iterate the idt and set the addresses.
620	*/
621	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
622	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
623	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
624	{
625	if ( pIdte->Gen.u1Present
626	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
627	)
628	{
629	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
630	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
631	switch (pIdteTemplate->u16OffsetLow)
632	{
633	/*
634	* Generic handlers have different entrypoints for each possible
635	* vector number. These entrypoints makes a sort of an array with
636	* 8 byte entries where the vector number is the index.
637	* See TRPMGCHandlersA.asm for details.
638	*/
639	case TRPM_HANDLER_INT:
640	case TRPM_HANDLER_TRAP:
641	Offset += i * 8;
642	break;
643	case TRPM_HANDLER_TRAP_12:
644	break;
645	case TRPM_HANDLER_TRAP_08:
646	/* Handle #DF Task Gate in special way. */
647	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
648	pIdte->Gen.u16OffsetLow = 0;
649	pIdte->Gen.u16OffsetHigh = 0;
650	SELMSetTrap8EIP(pVM, Offset);
651	continue;
652	}
653	/* (non-task gates only ) */
654	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
655	pIdte->Gen.u16OffsetHigh = Offset >> 16;
656	pIdte->Gen.u16SegSel = SelCS;
657	}
658	}
659
660	/*
661	* Update IDTR (limit is including!).
662	*/
663	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
664
665	if ( !pVM->trpm.s.fDisableMonitoring
666	&& !VMMIsHwVirtExtForced(pVM))
667	{
668	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
669	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
670	{
671	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
672	AssertRC(rc);
673	}
674	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
675	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
676	0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
677	AssertRC(rc);
678	#endif
679	}
680
681	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
682	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
683	{
684	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
685	{
686	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
687	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
688	}
689
690	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
691	{
692	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
693	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
694
695	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
696	pHandler += offDelta;
697
698	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
699	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
700	}
701	}
702
703	#ifdef VBOX_WITH_STATISTICS
704	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
705	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
706	pVM->trpm.s.paStatHostIrqRC += offDelta;
707	pVM->trpm.s.paStatHostIrqR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatHostIrqR3);
708	#endif
709	}
710
711
712	/**
713	* Terminates the Trap Manager
714	*
715	* @returns VBox status code.
716	* @param pVM The VM to operate on.
717	*/
718	VMMR3DECL(int) TRPMR3Term(PVM pVM)
719	{
720	NOREF(pVM);
721	return 0;
722	}
723
724
725	/**
726	* Resets a virtual CPU.
727	*
728	* Used by TRPMR3Reset and CPU hot plugging.
729	*
730	* @param pVCpu The virtual CPU handle.
731	*/
732	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
733	{
734	pVCpu->trpm.s.uActiveVector = ~0;
735	}
736
737
738	/**
739	* The VM is being reset.
740	*
741	* For the TRPM component this means that any IDT write monitors
742	* needs to be removed, any pending trap cleared, and the IDT reset.
743	*
744	* @param pVM VM handle.
745	*/
746	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
747	{
748	/*
749	* Deregister any virtual handlers.
750	*/
751	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
752	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
753	{
754	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
755	{
756	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
757	AssertRC(rc);
758	}
759	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
760	}
761	pVM->trpm.s.GuestIdtr.cbIdt = 0;
762	#endif
763
764	/*
765	* Reinitialize other members calling the relocator to get things right.
766	*/
767	for (VMCPUID i = 0; i < pVM->cCpus; i++)
768	TRPMR3ResetCpu(&pVM->aCpus[i]);
769	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
770	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
771	TRPMR3Relocate(pVM, 0);
772
773	/*
774	* Default action when entering raw mode for the first time
775	*/
776	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
777	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
778	}
779
780
781	/**
782	* Execute state save operation.
783	*
784	* @returns VBox status code.
785	* @param pVM VM Handle.
786	* @param pSSM SSM operation handle.
787	*/
788	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
789	{
790	PTRPM pTrpm = &pVM->trpm.s;
791	LogFlow(("trpmR3Save:\n"));
792
793	/*
794	* Active and saved traps.
795	*/
796	for (VMCPUID i = 0; i < pVM->cCpus; i++)
797	{
798	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
799	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
800	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
801	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
802	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
803	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
804	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
805	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
806	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
807	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
808	}
809	SSMR3PutBool(pSSM, pTrpm->fDisableMonitoring);
810	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
811	SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT));
812	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
813	SSMR3PutU32(pSSM, ~0); /* separator. */
814
815	/*
816	* Save any trampoline gates.
817	*/
818	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
819	{
820	if (pTrpm->aGuestTrapHandler[iTrap])
821	{
822	SSMR3PutU32(pSSM, iTrap);
823	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
824	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
825	}
826	}
827
828	return SSMR3PutU32(pSSM, ~0); /* terminator */
829	}
830
831
832	/**
833	* Execute state load operation.
834	*
835	* @returns VBox status code.
836	* @param pVM VM Handle.
837	* @param pSSM SSM operation handle.
838	* @param uVersion Data layout version.
839	* @param uPass The data pass.
840	*/
841	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
842	{
843	LogFlow(("trpmR3Load:\n"));
844	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
845
846	/*
847	* Validate version.
848	*/
849	if ( uVersion != TRPM_SAVED_STATE_VERSION
850	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
851	{
852	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
853	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
854	}
855
856	/*
857	* Call the reset function to kick out any handled gates and other potential trouble.
858	*/
859	TRPMR3Reset(pVM);
860
861	/*
862	* Active and saved traps.
863	*/
864	PTRPM pTrpm = &pVM->trpm.s;
865
866	if (uVersion == TRPM_SAVED_STATE_VERSION)
867	{
868	for (VMCPUID i = 0; i < pVM->cCpus; i++)
869	{
870	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
871	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
872	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
873	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
874	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
875	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
876	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
877	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
878	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
879	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
880	}
881
882	SSMR3GetBool(pSSM, &pVM->trpm.s.fDisableMonitoring);
883	}
884	else
885	{
886	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
887	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
888	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
889	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
890	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
891	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
892	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
893	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
894	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
895	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
896
897	RTGCUINT fDisableMonitoring;
898	SSMR3GetGCUInt(pSSM, &fDisableMonitoring);
899	pTrpm->fDisableMonitoring = !!fDisableMonitoring;
900	}
901
902	RTUINT fSyncIDT;
903	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
904	if (RT_FAILURE(rc))
905	return rc;
906	if (fSyncIDT & ~1)
907	{
908	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
909	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
910	}
911	if (fSyncIDT)
912	{
913	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
914	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
915	}
916	/* else: cleared by reset call above. */
917
918	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
919
920	/* check the separator */
921	uint32_t u32Sep;
922	rc = SSMR3GetU32(pSSM, &u32Sep);
923	if (RT_FAILURE(rc))
924	return rc;
925	if (u32Sep != (uint32_t)~0)
926	{
927	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
928	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
929	}
930
931	/*
932	* Restore any trampoline gates.
933	*/
934	for (;;)
935	{
936	/* gate number / terminator */
937	uint32_t iTrap;
938	rc = SSMR3GetU32(pSSM, &iTrap);
939	if (RT_FAILURE(rc))
940	return rc;
941	if (iTrap == (uint32_t)~0)
942	break;
943	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
944	\|\| pTrpm->aGuestTrapHandler[iTrap])
945	{
946	AssertMsgFailed(("iTrap=%#x\n", iTrap));
947	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
948	}
949
950	/* restore the IDT entry. */
951	RTGCPTR GCPtrHandler;
952	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
953	VBOXIDTE Idte;
954	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
955	if (RT_FAILURE(rc))
956	return rc;
957	Assert(GCPtrHandler);
958	pTrpm->aIdt[iTrap] = Idte;
959	}
960
961	return VINF_SUCCESS;
962	}
963
964
965	/**
966	* Check if gate handlers were updated
967	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
968	*
969	* @returns VBox status code.
970	* @param pVM The VM handle.
971	* @param pVCpu The VMCPU handle.
972	*/
973	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
974	{
975	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
976	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
977	int rc;
978
979	if (pVM->trpm.s.fDisableMonitoring)
980	{
981	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
982	return VINF_SUCCESS; /* Nothing to do */
983	}
984
985	if (fRawRing0 && CSAMIsEnabled(pVM))
986	{
987	/* Clear all handlers */
988	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
989	/** @todo inefficient, but simple */
990	for (unsigned iGate = 0; iGate < 256; iGate++)
991	trpmClearGuestTrapHandler(pVM, iGate);
992
993	/* Scan them all (only the first time) */
994	CSAMR3CheckGates(pVM, 0, 256);
995	}
996
997	/*
998	* Get the IDTR.
999	*/
1000	VBOXIDTR IDTR;
1001	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1002	if (!IDTR.cbIdt)
1003	{
1004	Log(("No IDT entries...\n"));
1005	return DBGFSTOP(pVM);
1006	}
1007
1008	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1009	/*
1010	* Check if Guest's IDTR has changed.
1011	*/
1012	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1013	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1014	{
1015	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1016	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1017	{
1018	/*
1019	* [Re]Register write virtual handler for guest's IDT.
1020	*/
1021	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1022	{
1023	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1024	AssertRCReturn(rc, rc);
1025	}
1026	/* limit is including */
1027	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1028	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1029
1030	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1031	{
1032	/* Could be a conflict with CSAM */
1033	CSAMR3RemovePage(pVM, IDTR.pIdt);
1034	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1035	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1036
1037	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1038	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1039	}
1040
1041	AssertRCReturn(rc, rc);
1042	}
1043
1044	/* Update saved Guest IDTR. */
1045	pVM->trpm.s.GuestIdtr = IDTR;
1046	}
1047	#endif
1048
1049	/*
1050	* Sync the interrupt gate.
1051	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1052	*/
1053	X86DESC Idte3;
1054	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1055	if (RT_FAILURE(rc))
1056	{
1057	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1058	return DBGFSTOP(pVM);
1059	}
1060	AssertRCReturn(rc, rc);
1061	if (fRawRing0)
1062	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1063	else
1064	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1065
1066	/*
1067	* Clear the FF and we're done.
1068	*/
1069	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1070	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1071	return VINF_SUCCESS;
1072	}
1073
1074
1075	/**
1076	* Disable IDT monitoring and syncing
1077	*
1078	* @param pVM The VM to operate on.
1079	*/
1080	VMMR3DECL(void) TRPMR3DisableMonitoring(PVM pVM)
1081	{
1082	/*
1083	* Deregister any virtual handlers.
1084	*/
1085	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1086	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1087	{
1088	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1089	{
1090	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1091	AssertRC(rc);
1092	}
1093	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
1094	}
1095	pVM->trpm.s.GuestIdtr.cbIdt = 0;
1096	#endif
1097
1098	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
1099	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
1100	{
1101	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
1102	AssertRC(rc);
1103	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
1104	}
1105	#endif
1106
1107	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
1108	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1109
1110	pVM->trpm.s.fDisableMonitoring = true;
1111	}
1112
1113
1114	/**
1115	* \#PF Handler callback for virtual access handler ranges.
1116	*
1117	* Important to realize that a physical page in a range can have aliases, and
1118	* for ALL and WRITE handlers these will also trigger.
1119	*
1120	* @returns VINF_SUCCESS if the handler have carried out the operation.
1121	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1122	* @param pVM VM Handle.
1123	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1124	* @param pvPtr The HC mapping of that address.
1125	* @param pvBuf What the guest is reading/writing.
1126	* @param cbBuf How much it's reading/writing.
1127	* @param enmAccessType The access type.
1128	* @param pvUser User argument.
1129	*/
1130	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1131	PGMACCESSTYPE enmAccessType, void *pvUser)
1132	{
1133	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1134	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1135	NOREF(pvPtr); NOREF(pvUser); NOREF(pvBuf);
1136
1137	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1138	return VINF_PGM_HANDLER_DO_DEFAULT;
1139	}
1140
1141
1142	/**
1143	* Clear passthrough interrupt gate handler (reset to default handler)
1144	*
1145	* @returns VBox status code.
1146	* @param pVM The VM to operate on.
1147	* @param iTrap Trap/interrupt gate number.
1148	*/
1149	VMMR3DECL(int) trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1150	{
1151	/* Only applies to raw mode which supports only 1 VCPU. */
1152	PVMCPU pVCpu = &pVM->aCpus[0];
1153
1154	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1155	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1156	int rc;
1157
1158	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1159
1160	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1161	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1162
1163	if ( iTrap < TRPM_HANDLER_INT_BASE
1164	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1165	{
1166	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1167	return VERR_INVALID_PARAMETER;
1168	}
1169	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1170
1171	/* Unmark it for relocation purposes. */
1172	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1173
1174	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1175	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1176	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1177	if (pIdte->Gen.u1Present)
1178	{
1179	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1180	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1181	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1182
1183	/*
1184	* Generic handlers have different entrypoints for each possible
1185	* vector number. These entrypoints make a sort of an array with
1186	* 8 byte entries where the vector number is the index.
1187	* See TRPMGCHandlersA.asm for details.
1188	*/
1189	Offset += iTrap * 8;
1190
1191	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1192	{
1193	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1194	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1195	pIdte->Gen.u16SegSel = SelCS;
1196	}
1197	}
1198
1199	return VINF_SUCCESS;
1200	}
1201
1202
1203	/**
1204	* Check if address is a gate handler (interrupt or trap).
1205	*
1206	* @returns gate nr or ~0 is not found
1207	*
1208	* @param pVM VM handle.
1209	* @param GCPtr GC address to check.
1210	*/
1211	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1212	{
1213	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1214	{
1215	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1216	return iTrap;
1217
1218	/* redundant */
1219	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1220	{
1221	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1222	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1223
1224	if (pHandler == GCPtr)
1225	return iTrap;
1226	}
1227	}
1228	return ~0;
1229	}
1230
1231
1232	/**
1233	* Get guest trap/interrupt gate handler
1234	*
1235	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1236	* @param pVM The VM to operate on.
1237	* @param iTrap Interrupt/trap number.
1238	*/
1239	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1240	{
1241	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1242
1243	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1244	}
1245
1246
1247	/**
1248	* Set guest trap/interrupt gate handler
1249	* Used for setting up trap gates used for kernel calls.
1250	*
1251	* @returns VBox status code.
1252	* @param pVM The VM to operate on.
1253	* @param iTrap Interrupt/trap number.
1254	* @param pHandler GC handler pointer
1255	*/
1256	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1257	{
1258	/* Only valid in raw mode which implies 1 VCPU */
1259	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1260	PVMCPU pVCpu = &pVM->aCpus[0];
1261
1262	/*
1263	* Validate.
1264	*/
1265	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1266	{
1267	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1268	return VERR_INVALID_PARAMETER;
1269	}
1270
1271	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1272
1273	uint16_t cbIDT;
1274	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1275	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1276	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1277
1278	if (pHandler == TRPM_INVALID_HANDLER)
1279	{
1280	/* clear trap handler */
1281	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1282	return trpmClearGuestTrapHandler(pVM, iTrap);
1283	}
1284
1285	/*
1286	* Read the guest IDT entry.
1287	*/
1288	VBOXIDTE GuestIdte;
1289	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1290	if (RT_FAILURE(rc))
1291	{
1292	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1293	return rc;
1294	}
1295
1296	if (EMIsRawRing0Enabled(pVM))
1297	{
1298	/*
1299	* Only replace handlers for which we are 100% certain there won't be
1300	* any host interrupts.
1301	*
1302	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1303	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1304	*
1305	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1306	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1307	* and will therefor never assign hardware interrupts to 0x80.
1308	*
1309	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1310	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1311	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1312	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1313	* defect #3604.
1314	*
1315	* PORTME - Check if your host keeps any of these gates free from hw ints.
1316	*
1317	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1318	*/
1319	/** @todo handle those dependencies better! */
1320	/** @todo Solve this in a proper manner. see defect #1186 */
1321	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1322	if (iTrap == 0x2E)
1323	#elif defined(RT_OS_LINUX)
1324	if (iTrap == 0x80)
1325	#else
1326	if (0)
1327	#endif
1328	{
1329	if ( GuestIdte.Gen.u1Present
1330	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1331	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1332	&& GuestIdte.Gen.u2DPL == 3)
1333	{
1334	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1335
1336	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1337	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1338	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1339	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1340	*pIdte = GuestIdte;
1341
1342	/* Mark it for relocation purposes. */
1343	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1344
1345	/* Also store it in our guest trap array. */
1346	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1347
1348	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1349	return VINF_SUCCESS;
1350	}
1351	/* ok, let's try to install a trampoline handler then. */
1352	}
1353	}
1354
1355	if ( GuestIdte.Gen.u1Present
1356	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1357	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1358	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1359	{
1360	/*
1361	* Save handler which can be used for a trampoline call inside the GC
1362	*/
1363	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1364	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1365	return VINF_SUCCESS;
1366	}
1367	return VERR_INVALID_PARAMETER;
1368	}
1369
1370
1371	/**
1372	* Check if address is a gate handler (interrupt/trap/task/anything).
1373	*
1374	* @returns True is gate handler, false if not.
1375	*
1376	* @param pVM VM handle.
1377	* @param GCPtr GC address to check.
1378	*/
1379	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1380	{
1381	/* Only valid in raw mode which implies 1 VCPU */
1382	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1383	PVMCPU pVCpu = &pVM->aCpus[0];
1384
1385	/*
1386	* Read IDTR and calc last entry.
1387	*/
1388	uint16_t cbIDT;
1389	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1390	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1391	if (!cEntries)
1392	return false;
1393	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1394
1395	/*
1396	* Outer loop: iterate pages.
1397	*/
1398	while (GCPtrIDTE <= GCPtrIDTELast)
1399	{
1400	/*
1401	* Convert this page to a HC address.
1402	* (This function checks for not-present pages.)
1403	*/
1404	PCVBOXIDTE pIDTE;
1405	PGMPAGEMAPLOCK Lock;
1406	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1407	if (RT_SUCCESS(rc))
1408	{
1409	/*
1410	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1411	* N.B. Member of the Flat Earth Society...
1412	*/
1413	while (GCPtrIDTE <= GCPtrIDTELast)
1414	{
1415	if (pIDTE->Gen.u1Present)
1416	{
1417	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1418	if (GCPtr == GCPtrHandler)
1419	{
1420	PGMPhysReleasePageMappingLock(pVM, &Lock);
1421	return true;
1422	}
1423	}
1424
1425	/* next entry */
1426	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1427	{
1428	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1429	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1430	GCPtrIDTE += sizeof(VBOXIDTE);
1431	break;
1432	}
1433	GCPtrIDTE += sizeof(VBOXIDTE);
1434	pIDTE++;
1435	}
1436	PGMPhysReleasePageMappingLock(pVM, &Lock);
1437	}
1438	else
1439	{
1440	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1441	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1442	return false;
1443	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1444	}
1445	}
1446	return false;
1447	}
1448
1449
1450	/**
1451	* Inject event (such as external irq or trap)
1452	*
1453	* @returns VBox status code.
1454	* @param pVM The VM to operate on.
1455	* @param pVCpu The VMCPU to operate on.
1456	* @param enmEvent Trpm event type
1457	*/
1458	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1459	{
1460	PCPUMCTX pCtx;
1461	int rc;
1462
1463	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1464	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1465	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1466
1467	/* Currently only useful for external hardware interrupts. */
1468	Assert(enmEvent == TRPM_HARDWARE_INT);
1469
1470	if ( REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1471	&& !EMIsSupervisorCodeRecompiled(pVM))
1472	{
1473	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1474
1475	# ifdef LOG_ENABLED
1476	DBGFR3InfoLog(pVM, "cpumguest", "TRPMInject");
1477	DBGFR3DisasInstrCurrentLog(pVCpu, "TRPMInject");
1478	# endif
1479
1480	uint8_t u8Interrupt;
1481	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1482	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1483	if (RT_SUCCESS(rc))
1484	{
1485	# ifndef IEM_VERIFICATION_MODE
1486	if (HWACCMIsEnabled(pVM))
1487	# endif
1488	{
1489	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1490	AssertRC(rc);
1491	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1492	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM;
1493	}
1494	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1495	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1496	{
1497	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1498	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1499	}
1500
1501	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1502	{
1503	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1504	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1505	if (rc == VINF_SUCCESS)
1506	{
1507	/* There's a handler -> let's execute it in raw mode */
1508	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1509	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1510	{
1511	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1512
1513	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1514	return VINF_EM_RESCHEDULE_RAW;
1515	}
1516	}
1517	}
1518	else
1519	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1520	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1521	}
1522	else
1523	{
1524	AssertRC(rc);
1525	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1526	}
1527	#else
1528	if (HWACCMR3IsActive(pVM))
1529	{
1530	uint8_t u8Interrupt;
1531	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1532	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1533	if (RT_SUCCESS(rc))
1534	{
1535	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
1536	AssertRC(rc);
1537	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1538	return VINF_EM_RESCHEDULE_HWACC;
1539	}
1540	}
1541	else
1542	AssertRC(rc);
1543	#endif
1544	}
1545	/** @todo check if it's safe to translate the patch address to the original guest address.
1546	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1547	*/
1548	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1549
1550	/* Fall back to the recompiler */
1551	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1552	}
1553

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 39405

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