TRPM.cpp@ 37950

Last change on this file since 37950 was 36823, checked in by vboxsync, 14 years ago
IEM: fixed interrupt delivery in verification mode.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 76.1 KB

Line
1	/* $Id: TRPM.cpp 36823 2011-04-23 22:32:27Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72	/*******************************************************************************
73	* Header Files *
74	*******************************************************************************/
75	#define LOG_GROUP LOG_GROUP_TRPM
76	#include <VBox/vmm/trpm.h>
77	#include <VBox/vmm/cpum.h>
78	#include <VBox/vmm/selm.h>
79	#include <VBox/vmm/ssm.h>
80	#include <VBox/vmm/pdmapi.h>
81	#include <VBox/vmm/pgm.h>
82	#include "internal/pgm.h"
83	#include <VBox/vmm/dbgf.h>
84	#include <VBox/vmm/mm.h>
85	#include <VBox/vmm/stam.h>
86	#include <VBox/vmm/csam.h>
87	#include <VBox/vmm/patm.h>
88	#include "TRPMInternal.h"
89	#include <VBox/vmm/vm.h>
90	#include <VBox/vmm/em.h>
91	#include <VBox/vmm/rem.h>
92	#include <VBox/vmm/hwaccm.h>
93
94	#include <VBox/err.h>
95	#include <VBox/param.h>
96	#include <VBox/log.h>
97	#include <iprt/assert.h>
98	#include <iprt/asm.h>
99	#include <iprt/string.h>
100	#include <iprt/alloc.h>
101
102
103	/*******************************************************************************
104	* Structures and Typedefs *
105	*******************************************************************************/
106	/**
107	* Trap handler function.
108	* @todo need to specialize this as we go along.
109	*/
110	typedef enum TRPMHANDLER
111	{
112	/** Generic Interrupt handler. */
113	TRPM_HANDLER_INT = 0,
114	/** Generic Trap handler. */
115	TRPM_HANDLER_TRAP,
116	/** Trap 8 (\#DF) handler. */
117	TRPM_HANDLER_TRAP_08,
118	/** Trap 12 (\#MC) handler. */
119	TRPM_HANDLER_TRAP_12,
120	/** Max. */
121	TRPM_HANDLER_MAX
122	} TRPMHANDLER, *PTRPMHANDLER;
123
124
125	/*******************************************************************************
126	* Global Variables *
127	*******************************************************************************/
128	/** Preinitialized IDT.
129	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
130	* will use to pick the right address. The u16SegSel is always VMM CS.
131	*/
132	static VBOXIDTE_GENERIC g_aIdt[256] =
133	{
134	/* special trap handler - still, this is an interrupt gate not a trap gate... */
135	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
136	/* generic trap handler. */
137	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
138	/* special interrupt handler. */
139	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
140	/* generic interrupt handler. */
141	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
142	/* special task gate IDT entry (for critical exceptions like #DF). */
143	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
144	/* draft, fixme later when the handler is written. */
145	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
146
147	/* N - M M - T - C - D i */
148	/* o - n o - y - o - e p */
149	/* - e n - p - d - s t */
150	/* - i - e - e - c . */
151	/* - c - - - r */
152	/* ============================================================= */
153	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
154	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
155	#ifdef VBOX_WITH_NMI
156	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
157	#else
158	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
159	#endif
160	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
161	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
162	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
163	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
164	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
165	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
166	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
167	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
168	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
169	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
170	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
171	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
172	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
173	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
174	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
175	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
176	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
177	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
178	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
179	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
180	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
189	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
190	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
191	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
192	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
413	#undef IDTE_TRAP
414	#undef IDTE_TRAP_GEN
415	#undef IDTE_INT
416	#undef IDTE_INT_GEN
417	#undef IDTE_TASK
418	#undef IDTE_UNUSED
419	#undef IDTE_RESERVED
420	};
421
422
423	/** Enable or disable tracking of Guest's IDT. */
424	#define TRPM_TRACK_GUEST_IDT_CHANGES
425
426	/** Enable or disable tracking of Shadow IDT. */
427	#define TRPM_TRACK_SHADOW_IDT_CHANGES
428
429	/** TRPM saved state version. */
430	#define TRPM_SAVED_STATE_VERSION 9
431	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
432
433
434	/*******************************************************************************
435	* Internal Functions *
436	*******************************************************************************/
437	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
438	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
439	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
440
441
442	/**
443	* Initializes the Trap Manager
444	*
445	* @returns VBox status code.
446	* @param pVM The VM to operate on.
447	*/
448	VMMR3DECL(int) TRPMR3Init(PVM pVM)
449	{
450	LogFlow(("TRPMR3Init\n"));
451
452	/*
453	* Assert sizes and alignments.
454	*/
455	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
456	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
457	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
458	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
459
460	/*
461	* Initialize members.
462	*/
463	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
464	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
465
466	for (VMCPUID i = 0; i < pVM->cCpus; i++)
467	{
468	PVMCPU pVCpu = &pVM->aCpus[i];
469
470	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
471	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
472	pVCpu->trpm.s.uActiveVector = ~0;
473	}
474
475	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
476	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
477	pVM->trpm.s.fDisableMonitoring = false;
478	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
479
480	/*
481	* Read the configuration (if any).
482	*/
483	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
484	if (pTRPMNode)
485	{
486	bool f;
487	int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
488	if (RT_SUCCESS(rc))
489	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
490	}
491
492	/* write config summary to log */
493	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
494	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
495
496	/*
497	* Initialize the IDT.
498	* The handler addresses will be set in the TRPMR3Relocate() function.
499	*/
500	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
501	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
502
503	/*
504	* Register the saved state data unit.
505	*/
506	int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
507	NULL, NULL, NULL,
508	NULL, trpmR3Save, NULL,
509	NULL, trpmR3Load, NULL);
510	if (RT_FAILURE(rc))
511	return rc;
512
513	/*
514	* Statistics.
515	*/
516	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
517	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
518	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
519
520	/* traps */
521	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
522	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
523	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
524	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
525	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
526	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
527	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
528	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
529	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
530	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
531	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
532	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
533	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
534	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
535	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
536	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
537	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
538	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
539	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
540	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
541
542	#ifdef VBOX_WITH_STATISTICS
543	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 255, 8, MM_TAG_STAM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
544	AssertRCReturn(rc, rc);
545	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
546	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
547	for (unsigned i = 0; i < 255; i++)
548	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
549	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
550	#endif
551
552	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
553	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
554	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
555	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
556	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
557	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
558
559	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
560	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
561
562	/*
563	* Default action when entering raw mode for the first time
564	*/
565	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
566	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
567	return 0;
568	}
569
570
571	/**
572	* Applies relocations to data and code managed by this component.
573	*
574	* This function will be called at init and whenever the VMM need
575	* to relocate itself inside the GC.
576	*
577	* @param pVM The VM handle.
578	* @param offDelta Relocation delta relative to old location.
579	*/
580	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
581	{
582	/* Only applies to raw mode which supports only 1 VCPU. */
583	PVMCPU pVCpu = &pVM->aCpus[0];
584
585	LogFlow(("TRPMR3Relocate\n"));
586	/*
587	* Get the trap handler addresses.
588	*
589	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
590	* would make init order impossible if we should assert the presence of these
591	* exports in TRPMR3Init().
592	*/
593	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
594	RT_ZERO(aRCPtrs);
595	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
596	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
597
598	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
599	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
600
601	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
602	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
603
604	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
605	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
606
607	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
608
609	/*
610	* Iterate the idt and set the addresses.
611	*/
612	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
613	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
614	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
615	{
616	if ( pIdte->Gen.u1Present
617	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
618	)
619	{
620	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
621	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
622	switch (pIdteTemplate->u16OffsetLow)
623	{
624	/*
625	* Generic handlers have different entrypoints for each possible
626	* vector number. These entrypoints makes a sort of an array with
627	* 8 byte entries where the vector number is the index.
628	* See TRPMGCHandlersA.asm for details.
629	*/
630	case TRPM_HANDLER_INT:
631	case TRPM_HANDLER_TRAP:
632	Offset += i * 8;
633	break;
634	case TRPM_HANDLER_TRAP_12:
635	break;
636	case TRPM_HANDLER_TRAP_08:
637	/* Handle #DF Task Gate in special way. */
638	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
639	pIdte->Gen.u16OffsetLow = 0;
640	pIdte->Gen.u16OffsetHigh = 0;
641	SELMSetTrap8EIP(pVM, Offset);
642	continue;
643	}
644	/* (non-task gates only ) */
645	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
646	pIdte->Gen.u16OffsetHigh = Offset >> 16;
647	pIdte->Gen.u16SegSel = SelCS;
648	}
649	}
650
651	/*
652	* Update IDTR (limit is including!).
653	*/
654	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
655
656	if ( !pVM->trpm.s.fDisableMonitoring
657	&& !VMMIsHwVirtExtForced(pVM))
658	{
659	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
660	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
661	{
662	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
663	AssertRC(rc);
664	}
665	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
666	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
667	0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
668	AssertRC(rc);
669	#endif
670	}
671
672	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
673	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
674	{
675	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
676	{
677	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
678	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
679	}
680
681	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
682	{
683	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
684	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
685
686	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
687	pHandler += offDelta;
688
689	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
690	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
691	}
692	}
693
694	#ifdef VBOX_WITH_STATISTICS
695	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
696	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
697	#endif
698	}
699
700
701	/**
702	* Terminates the Trap Manager
703	*
704	* @returns VBox status code.
705	* @param pVM The VM to operate on.
706	*/
707	VMMR3DECL(int) TRPMR3Term(PVM pVM)
708	{
709	NOREF(pVM);
710	return 0;
711	}
712
713
714	/**
715	* Resets a virtual CPU.
716	*
717	* Used by TRPMR3Reset and CPU hot plugging.
718	*
719	* @param pVCpu The virtual CPU handle.
720	*/
721	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
722	{
723	pVCpu->trpm.s.uActiveVector = ~0;
724	}
725
726
727	/**
728	* The VM is being reset.
729	*
730	* For the TRPM component this means that any IDT write monitors
731	* needs to be removed, any pending trap cleared, and the IDT reset.
732	*
733	* @param pVM VM handle.
734	*/
735	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
736	{
737	/*
738	* Deregister any virtual handlers.
739	*/
740	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
741	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
742	{
743	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
744	{
745	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
746	AssertRC(rc);
747	}
748	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
749	}
750	pVM->trpm.s.GuestIdtr.cbIdt = 0;
751	#endif
752
753	/*
754	* Reinitialize other members calling the relocator to get things right.
755	*/
756	for (VMCPUID i = 0; i < pVM->cCpus; i++)
757	TRPMR3ResetCpu(&pVM->aCpus[i]);
758	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
759	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
760	TRPMR3Relocate(pVM, 0);
761
762	/*
763	* Default action when entering raw mode for the first time
764	*/
765	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
766	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
767	}
768
769
770	/**
771	* Execute state save operation.
772	*
773	* @returns VBox status code.
774	* @param pVM VM Handle.
775	* @param pSSM SSM operation handle.
776	*/
777	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
778	{
779	PTRPM pTrpm = &pVM->trpm.s;
780	LogFlow(("trpmR3Save:\n"));
781
782	/*
783	* Active and saved traps.
784	*/
785	for (VMCPUID i = 0; i < pVM->cCpus; i++)
786	{
787	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
788	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
789	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
790	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
791	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
792	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
793	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
794	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
795	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
796	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
797	}
798	SSMR3PutBool(pSSM, pTrpm->fDisableMonitoring);
799	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
800	SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT));
801	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
802	SSMR3PutU32(pSSM, ~0); /* separator. */
803
804	/*
805	* Save any trampoline gates.
806	*/
807	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
808	{
809	if (pTrpm->aGuestTrapHandler[iTrap])
810	{
811	SSMR3PutU32(pSSM, iTrap);
812	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
813	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
814	}
815	}
816
817	return SSMR3PutU32(pSSM, ~0); /* terminator */
818	}
819
820
821	/**
822	* Execute state load operation.
823	*
824	* @returns VBox status code.
825	* @param pVM VM Handle.
826	* @param pSSM SSM operation handle.
827	* @param uVersion Data layout version.
828	* @param uPass The data pass.
829	*/
830	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
831	{
832	LogFlow(("trpmR3Load:\n"));
833	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
834
835	/*
836	* Validate version.
837	*/
838	if ( uVersion != TRPM_SAVED_STATE_VERSION
839	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
840	{
841	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
842	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
843	}
844
845	/*
846	* Call the reset function to kick out any handled gates and other potential trouble.
847	*/
848	TRPMR3Reset(pVM);
849
850	/*
851	* Active and saved traps.
852	*/
853	PTRPM pTrpm = &pVM->trpm.s;
854
855	if (uVersion == TRPM_SAVED_STATE_VERSION)
856	{
857	for (VMCPUID i = 0; i < pVM->cCpus; i++)
858	{
859	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
860	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
861	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
862	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
863	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
864	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
865	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
866	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
867	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
868	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
869	}
870
871	SSMR3GetBool(pSSM, &pVM->trpm.s.fDisableMonitoring);
872	}
873	else
874	{
875	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
876	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
877	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
878	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
879	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
880	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
881	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
882	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
883	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
884	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
885
886	RTGCUINT fDisableMonitoring;
887	SSMR3GetGCUInt(pSSM, &fDisableMonitoring);
888	pTrpm->fDisableMonitoring = !!fDisableMonitoring;
889	}
890
891	RTUINT fSyncIDT;
892	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
893	if (RT_FAILURE(rc))
894	return rc;
895	if (fSyncIDT & ~1)
896	{
897	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
898	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
899	}
900	if (fSyncIDT)
901	{
902	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
903	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
904	}
905	/* else: cleared by reset call above. */
906
907	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
908
909	/* check the separator */
910	uint32_t u32Sep;
911	rc = SSMR3GetU32(pSSM, &u32Sep);
912	if (RT_FAILURE(rc))
913	return rc;
914	if (u32Sep != (uint32_t)~0)
915	{
916	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
917	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
918	}
919
920	/*
921	* Restore any trampoline gates.
922	*/
923	for (;;)
924	{
925	/* gate number / terminator */
926	uint32_t iTrap;
927	rc = SSMR3GetU32(pSSM, &iTrap);
928	if (RT_FAILURE(rc))
929	return rc;
930	if (iTrap == (uint32_t)~0)
931	break;
932	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
933	\|\| pTrpm->aGuestTrapHandler[iTrap])
934	{
935	AssertMsgFailed(("iTrap=%#x\n", iTrap));
936	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
937	}
938
939	/* restore the IDT entry. */
940	RTGCPTR GCPtrHandler;
941	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
942	VBOXIDTE Idte;
943	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
944	if (RT_FAILURE(rc))
945	return rc;
946	Assert(GCPtrHandler);
947	pTrpm->aIdt[iTrap] = Idte;
948	}
949
950	return VINF_SUCCESS;
951	}
952
953
954	/**
955	* Check if gate handlers were updated
956	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
957	*
958	* @returns VBox status code.
959	* @param pVM The VM handle.
960	* @param pVCpu The VMCPU handle.
961	*/
962	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
963	{
964	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
965	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
966	int rc;
967
968	if (pVM->trpm.s.fDisableMonitoring)
969	{
970	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
971	return VINF_SUCCESS; /* Nothing to do */
972	}
973
974	if (fRawRing0 && CSAMIsEnabled(pVM))
975	{
976	/* Clear all handlers */
977	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
978	/** @todo inefficient, but simple */
979	for (unsigned iGate = 0; iGate < 256; iGate++)
980	trpmClearGuestTrapHandler(pVM, iGate);
981
982	/* Scan them all (only the first time) */
983	CSAMR3CheckGates(pVM, 0, 256);
984	}
985
986	/*
987	* Get the IDTR.
988	*/
989	VBOXIDTR IDTR;
990	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
991	if (!IDTR.cbIdt)
992	{
993	Log(("No IDT entries...\n"));
994	return DBGFSTOP(pVM);
995	}
996
997	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
998	/*
999	* Check if Guest's IDTR has changed.
1000	*/
1001	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1002	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1003	{
1004	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1005	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1006	{
1007	/*
1008	* [Re]Register write virtual handler for guest's IDT.
1009	*/
1010	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1011	{
1012	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1013	AssertRCReturn(rc, rc);
1014	}
1015	/* limit is including */
1016	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1017	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1018
1019	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1020	{
1021	/* Could be a conflict with CSAM */
1022	CSAMR3RemovePage(pVM, IDTR.pIdt);
1023	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1024	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1025
1026	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1027	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1028	}
1029
1030	AssertRCReturn(rc, rc);
1031	}
1032
1033	/* Update saved Guest IDTR. */
1034	pVM->trpm.s.GuestIdtr = IDTR;
1035	}
1036	#endif
1037
1038	/*
1039	* Sync the interrupt gate.
1040	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1041	*/
1042	X86DESC Idte3;
1043	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1044	if (RT_FAILURE(rc))
1045	{
1046	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1047	return DBGFSTOP(pVM);
1048	}
1049	AssertRCReturn(rc, rc);
1050	if (fRawRing0)
1051	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1052	else
1053	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1054
1055	/*
1056	* Clear the FF and we're done.
1057	*/
1058	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1059	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1060	return VINF_SUCCESS;
1061	}
1062
1063
1064	/**
1065	* Disable IDT monitoring and syncing
1066	*
1067	* @param pVM The VM to operate on.
1068	*/
1069	VMMR3DECL(void) TRPMR3DisableMonitoring(PVM pVM)
1070	{
1071	/*
1072	* Deregister any virtual handlers.
1073	*/
1074	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1075	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1076	{
1077	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1078	{
1079	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1080	AssertRC(rc);
1081	}
1082	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
1083	}
1084	pVM->trpm.s.GuestIdtr.cbIdt = 0;
1085	#endif
1086
1087	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
1088	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
1089	{
1090	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
1091	AssertRC(rc);
1092	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
1093	}
1094	#endif
1095
1096	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
1097	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1098
1099	pVM->trpm.s.fDisableMonitoring = true;
1100	}
1101
1102
1103	/**
1104	* \#PF Handler callback for virtual access handler ranges.
1105	*
1106	* Important to realize that a physical page in a range can have aliases, and
1107	* for ALL and WRITE handlers these will also trigger.
1108	*
1109	* @returns VINF_SUCCESS if the handler have carried out the operation.
1110	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1111	* @param pVM VM Handle.
1112	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1113	* @param pvPtr The HC mapping of that address.
1114	* @param pvBuf What the guest is reading/writing.
1115	* @param cbBuf How much it's reading/writing.
1116	* @param enmAccessType The access type.
1117	* @param pvUser User argument.
1118	*/
1119	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1120	{
1121	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1122	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1123	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1124	return VINF_PGM_HANDLER_DO_DEFAULT;
1125	}
1126
1127
1128	/**
1129	* Clear passthrough interrupt gate handler (reset to default handler)
1130	*
1131	* @returns VBox status code.
1132	* @param pVM The VM to operate on.
1133	* @param iTrap Trap/interrupt gate number.
1134	*/
1135	VMMR3DECL(int) trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1136	{
1137	/* Only applies to raw mode which supports only 1 VCPU. */
1138	PVMCPU pVCpu = &pVM->aCpus[0];
1139
1140	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1141	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1142	int rc;
1143
1144	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1145
1146	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1147	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1148
1149	if ( iTrap < TRPM_HANDLER_INT_BASE
1150	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1151	{
1152	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1153	return VERR_INVALID_PARAMETER;
1154	}
1155	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1156
1157	/* Unmark it for relocation purposes. */
1158	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1159
1160	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1161	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1162	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1163	if (pIdte->Gen.u1Present)
1164	{
1165	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1166	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1167	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1168
1169	/*
1170	* Generic handlers have different entrypoints for each possible
1171	* vector number. These entrypoints make a sort of an array with
1172	* 8 byte entries where the vector number is the index.
1173	* See TRPMGCHandlersA.asm for details.
1174	*/
1175	Offset += iTrap * 8;
1176
1177	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1178	{
1179	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1180	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1181	pIdte->Gen.u16SegSel = SelCS;
1182	}
1183	}
1184
1185	return VINF_SUCCESS;
1186	}
1187
1188
1189	/**
1190	* Check if address is a gate handler (interrupt or trap).
1191	*
1192	* @returns gate nr or ~0 is not found
1193	*
1194	* @param pVM VM handle.
1195	* @param GCPtr GC address to check.
1196	*/
1197	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1198	{
1199	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1200	{
1201	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1202	return iTrap;
1203
1204	/* redundant */
1205	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1206	{
1207	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1208	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1209
1210	if (pHandler == GCPtr)
1211	return iTrap;
1212	}
1213	}
1214	return ~0;
1215	}
1216
1217
1218	/**
1219	* Get guest trap/interrupt gate handler
1220	*
1221	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1222	* @param pVM The VM to operate on.
1223	* @param iTrap Interrupt/trap number.
1224	*/
1225	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1226	{
1227	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1228
1229	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1230	}
1231
1232
1233	/**
1234	* Set guest trap/interrupt gate handler
1235	* Used for setting up trap gates used for kernel calls.
1236	*
1237	* @returns VBox status code.
1238	* @param pVM The VM to operate on.
1239	* @param iTrap Interrupt/trap number.
1240	* @param pHandler GC handler pointer
1241	*/
1242	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1243	{
1244	/* Only valid in raw mode which implies 1 VCPU */
1245	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1246	PVMCPU pVCpu = &pVM->aCpus[0];
1247
1248	/*
1249	* Validate.
1250	*/
1251	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1252	{
1253	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1254	return VERR_INVALID_PARAMETER;
1255	}
1256
1257	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1258
1259	uint16_t cbIDT;
1260	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1261	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1262	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1263
1264	if (pHandler == TRPM_INVALID_HANDLER)
1265	{
1266	/* clear trap handler */
1267	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1268	return trpmClearGuestTrapHandler(pVM, iTrap);
1269	}
1270
1271	/*
1272	* Read the guest IDT entry.
1273	*/
1274	VBOXIDTE GuestIdte;
1275	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1276	if (RT_FAILURE(rc))
1277	{
1278	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1279	return rc;
1280	}
1281
1282	if (EMIsRawRing0Enabled(pVM))
1283	{
1284	/*
1285	* Only replace handlers for which we are 100% certain there won't be
1286	* any host interrupts.
1287	*
1288	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1289	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1290	*
1291	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1292	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1293	* and will therefor never assign hardware interrupts to 0x80.
1294	*
1295	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1296	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1297	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1298	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1299	* defect #3604.
1300	*
1301	* PORTME - Check if your host keeps any of these gates free from hw ints.
1302	*
1303	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1304	*/
1305	/** @todo handle those dependencies better! */
1306	/** @todo Solve this in a proper manner. see defect #1186 */
1307	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1308	if (iTrap == 0x2E)
1309	#elif defined(RT_OS_LINUX)
1310	if (iTrap == 0x80)
1311	#else
1312	if (0)
1313	#endif
1314	{
1315	if ( GuestIdte.Gen.u1Present
1316	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1317	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1318	&& GuestIdte.Gen.u2DPL == 3)
1319	{
1320	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1321
1322	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1323	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1324	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1325	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1326	*pIdte = GuestIdte;
1327
1328	/* Mark it for relocation purposes. */
1329	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1330
1331	/* Also store it in our guest trap array. */
1332	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1333
1334	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1335	return VINF_SUCCESS;
1336	}
1337	/* ok, let's try to install a trampoline handler then. */
1338	}
1339	}
1340
1341	if ( GuestIdte.Gen.u1Present
1342	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1343	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1344	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1345	{
1346	/*
1347	* Save handler which can be used for a trampoline call inside the GC
1348	*/
1349	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1350	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1351	return VINF_SUCCESS;
1352	}
1353	return VERR_INVALID_PARAMETER;
1354	}
1355
1356
1357	/**
1358	* Check if address is a gate handler (interrupt/trap/task/anything).
1359	*
1360	* @returns True is gate handler, false if not.
1361	*
1362	* @param pVM VM handle.
1363	* @param GCPtr GC address to check.
1364	*/
1365	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1366	{
1367	/* Only valid in raw mode which implies 1 VCPU */
1368	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1369	PVMCPU pVCpu = &pVM->aCpus[0];
1370
1371	/*
1372	* Read IDTR and calc last entry.
1373	*/
1374	uint16_t cbIDT;
1375	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1376	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1377	if (!cEntries)
1378	return false;
1379	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1380
1381	/*
1382	* Outer loop: iterate pages.
1383	*/
1384	while (GCPtrIDTE <= GCPtrIDTELast)
1385	{
1386	/*
1387	* Convert this page to a HC address.
1388	* (This function checks for not-present pages.)
1389	*/
1390	PCVBOXIDTE pIDTE;
1391	PGMPAGEMAPLOCK Lock;
1392	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1393	if (RT_SUCCESS(rc))
1394	{
1395	/*
1396	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1397	* N.B. Member of the Flat Earth Society...
1398	*/
1399	while (GCPtrIDTE <= GCPtrIDTELast)
1400	{
1401	if (pIDTE->Gen.u1Present)
1402	{
1403	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1404	if (GCPtr == GCPtrHandler)
1405	{
1406	PGMPhysReleasePageMappingLock(pVM, &Lock);
1407	return true;
1408	}
1409	}
1410
1411	/* next entry */
1412	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1413	{
1414	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1415	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1416	GCPtrIDTE += sizeof(VBOXIDTE);
1417	break;
1418	}
1419	GCPtrIDTE += sizeof(VBOXIDTE);
1420	pIDTE++;
1421	}
1422	PGMPhysReleasePageMappingLock(pVM, &Lock);
1423	}
1424	else
1425	{
1426	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1427	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1428	return false;
1429	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1430	}
1431	}
1432	return false;
1433	}
1434
1435
1436	/**
1437	* Inject event (such as external irq or trap)
1438	*
1439	* @returns VBox status code.
1440	* @param pVM The VM to operate on.
1441	* @param pVCpu The VMCPU to operate on.
1442	* @param enmEvent Trpm event type
1443	*/
1444	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1445	{
1446	PCPUMCTX pCtx;
1447	int rc;
1448
1449	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1450	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1451	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1452
1453	/* Currently only useful for external hardware interrupts. */
1454	Assert(enmEvent == TRPM_HARDWARE_INT);
1455
1456	if (REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ)
1457	{
1458	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1459
1460	# ifdef LOG_ENABLED
1461	DBGFR3InfoLog(pVM, "cpumguest", "TRPMInject");
1462	DBGFR3DisasInstrCurrentLog(pVCpu, "TRPMInject");
1463	# endif
1464
1465	uint8_t u8Interrupt;
1466	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1467	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1468	if (RT_SUCCESS(rc))
1469	{
1470	# ifndef IEM_VERIFICATION_MODE
1471	if (HWACCMIsEnabled(pVM))
1472	# endif
1473	{
1474	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1475	AssertRC(rc);
1476	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1477	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM;
1478	}
1479	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1480	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1481	{
1482	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1483	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1484	}
1485
1486	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1487	{
1488	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1489	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1490	if (rc == VINF_SUCCESS)
1491	{
1492	/* There's a handler -> let's execute it in raw mode */
1493	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1494	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1495	{
1496	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1497
1498	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1499	return VINF_EM_RESCHEDULE_RAW;
1500	}
1501	}
1502	}
1503	else
1504	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1505	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1506	}
1507	else
1508	{
1509	AssertRC(rc);
1510	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1511	}
1512	#else
1513	if (HWACCMR3IsActive(pVM))
1514	{
1515	uint8_t u8Interrupt;
1516	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1517	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1518	if (RT_SUCCESS(rc))
1519	{
1520	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
1521	AssertRC(rc);
1522	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1523	return VINF_EM_RESCHEDULE_HWACC;
1524	}
1525	}
1526	else
1527	AssertRC(rc);
1528	#endif
1529	}
1530	/** @todo check if it's safe to translate the patch address to the original guest address.
1531	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1532	*/
1533	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1534
1535	/* Fall back to the recompiler */
1536	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1537	}
1538

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 37950

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