SELM.cpp@ 45530

Last change on this file since 45530 was 45485, checked in by vboxsync, 12 years ago
*: Where possible, drop the #ifdef VBOX_WITH_RAW_RING1 when EMIsRawRing1Enabled is used. SELM: Don't shadow TSS.esp1/ss1 unless ring-1 compression is enabled (also fixed a log statement there). SELM: selmGuestToShadowDesc should not push ring-1 selectors into ring-2 unless EMIsRawRing1Enabled() holds true. REM: Don't set CPU_INTERRUPT_EXTERNAL_EXIT in helper_ltr() for now.
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1	/* $Id: SELM.cpp 45485 2013-04-11 14:46:04Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/em.h>
66	#include <VBox/vmm/mm.h>
67	#include <VBox/vmm/ssm.h>
68	#include <VBox/vmm/pgm.h>
69	#include <VBox/vmm/trpm.h>
70	#include <VBox/vmm/dbgf.h>
71	#include "SELMInternal.h"
72	#include <VBox/vmm/vm.h>
73	#include <VBox/err.h>
74	#include <VBox/param.h>
75
76	#include <iprt/assert.h>
77	#include <VBox/log.h>
78	#include <iprt/asm.h>
79	#include <iprt/string.h>
80	#include <iprt/thread.h>
81	#include <iprt/string.h>
82
83	#include "SELMInline.h"
84
85
86	/** SELM saved state version. */
87	#define SELM_SAVED_STATE_VERSION 5
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
95	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
96	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
97	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
98	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
99	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105
106
107	/*******************************************************************************
108	* Global Variables *
109	*******************************************************************************/
110	#ifdef LOG_ENABLED
111	/** Segment register names. */
112	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
113	#endif
114
115
116	/**
117	* Initializes the SELM.
118	*
119	* @returns VBox status code.
120	* @param pVM Pointer to the VM.
121	*/
122	VMMR3DECL(int) SELMR3Init(PVM pVM)
123	{
124	LogFlow(("SELMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	* (The TSS block requires contiguous back.)
129	*/
130	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
131	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
132	#if 0 /* doesn't work */
133	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
134	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
135	#endif
136	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
137	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
138	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
139
140	/*
141	* Init the structure.
142	*/
143	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
144	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
145	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
147	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
148	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
149
150	/*
151	* Allocate GDT table.
152	*/
153	int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
154	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
155	AssertRCReturn(rc, rc);
156
157	/*
158	* Allocate LDT area.
159	*/
160	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
161	AssertRCReturn(rc, rc);
162
163	/*
164	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
165	*/
166	pVM->selm.s.cbEffGuestGdtLimit = 0;
167	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
168	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
169	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
170
171	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
172	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
173	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
174	pVM->selm.s.GCSelTss = RTSEL_MAX;
175
176	pVM->selm.s.fDisableMonitoring = false;
177	pVM->selm.s.fSyncTSSRing0Stack = false;
178
179	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
180	* for I/O operations. */
181	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
182	/* bit set to 1 means no redirection */
183	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
184
185	/*
186	* Register the saved state data unit.
187	*/
188	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
189	NULL, NULL, NULL,
190	NULL, selmR3Save, NULL,
191	NULL, selmR3Load, selmR3LoadDone);
192	if (RT_FAILURE(rc))
193	return rc;
194
195	/*
196	* Statistics.
197	*/
198	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
199	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
200	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
201	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
202	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
203	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
204	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
205	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
206	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
207
208	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
209	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
210
211	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
212	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
213	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
214	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
215	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
216	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
217
218	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
219	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
220	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
221	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
222	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
223	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
224
225	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
226
227	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
228	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
229	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
230	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
231	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
232	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
233
234	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
235	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
236	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
237	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
238
239	/*
240	* Default action when entering raw mode for the first time
241	*/
242	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
243	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
244	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
245	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
246
247	/*
248	* Register info handlers.
249	*/
250	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
251	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
252	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
253	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
254	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
255	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
256
257	return rc;
258	}
259
260
261	/**
262	* Finalizes HMA page attributes.
263	*
264	* @returns VBox status code.
265	* @param pVM Pointer to the VM.
266	*/
267	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
268	{
269	/** @cfgm{/DoubleFault,bool,false}
270	* Enables catching of double faults in the raw-mode context VMM code. This can
271	* be used when the triple faults or hangs occur and one suspect an unhandled
272	* double fault. This is not enabled by default because it means making the
273	* hyper selectors writeable for all supervisor code, including the guest's.
274	* The double fault is a task switch and thus requires write access to the GDT
275	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
276	* 8 TSS for the back link.
277	*/
278	bool f;
279	#if defined(DEBUG_bird)
280	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
281	#else
282	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
283	#endif
284	AssertLogRelRCReturn(rc, rc);
285	if (f)
286	{
287	PX86DESC paGdt = pVM->selm.s.paGdtR3;
288	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
289	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
290	AssertRC(rc);
291	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
292	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
293	AssertRC(rc);
294	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
295	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
296	AssertRC(rc);
297	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
298	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
299	AssertRC(rc);
300	}
301	return VINF_SUCCESS;
302	}
303
304
305	/**
306	* Setup the hypervisor GDT selectors in our shadow table
307	*
308	* @param pVM Pointer to the VM.
309	*/
310	static void selmR3SetupHyperGDTSelectors(PVM pVM)
311	{
312	PX86DESC paGdt = pVM->selm.s.paGdtR3;
313
314	/*
315	* Set up global code and data descriptors for use in the guest context.
316	* Both are wide open (base 0, limit 4GB)
317	*/
318	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
319	pDesc->Gen.u16LimitLow = 0xffff;
320	pDesc->Gen.u4LimitHigh = 0xf;
321	pDesc->Gen.u16BaseLow = 0;
322	pDesc->Gen.u8BaseHigh1 = 0;
323	pDesc->Gen.u8BaseHigh2 = 0;
324	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
325	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
326	pDesc->Gen.u2Dpl = 0; /* supervisor */
327	pDesc->Gen.u1Present = 1;
328	pDesc->Gen.u1Available = 0;
329	pDesc->Gen.u1Long = 0;
330	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
331	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
332
333	/* data */
334	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
335	pDesc->Gen.u16LimitLow = 0xffff;
336	pDesc->Gen.u4LimitHigh = 0xf;
337	pDesc->Gen.u16BaseLow = 0;
338	pDesc->Gen.u8BaseHigh1 = 0;
339	pDesc->Gen.u8BaseHigh2 = 0;
340	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
341	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
342	pDesc->Gen.u2Dpl = 0; /* supervisor */
343	pDesc->Gen.u1Present = 1;
344	pDesc->Gen.u1Available = 0;
345	pDesc->Gen.u1Long = 0;
346	pDesc->Gen.u1DefBig = 1; /* big */
347	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
348
349	/* 64-bit mode code (& data?) */
350	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
351	pDesc->Gen.u16LimitLow = 0xffff;
352	pDesc->Gen.u4LimitHigh = 0xf;
353	pDesc->Gen.u16BaseLow = 0;
354	pDesc->Gen.u8BaseHigh1 = 0;
355	pDesc->Gen.u8BaseHigh2 = 0;
356	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
357	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
358	pDesc->Gen.u2Dpl = 0; /* supervisor */
359	pDesc->Gen.u1Present = 1;
360	pDesc->Gen.u1Available = 0;
361	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
362	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
363	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
364
365	/*
366	* TSS descriptor
367	*/
368	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
369	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
370	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
371	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
372	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
373	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
374	pDesc->Gen.u4LimitHigh = 0;
375	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
376	pDesc->Gen.u1DescType = 0; /* system */
377	pDesc->Gen.u2Dpl = 0; /* supervisor */
378	pDesc->Gen.u1Present = 1;
379	pDesc->Gen.u1Available = 0;
380	pDesc->Gen.u1Long = 0;
381	pDesc->Gen.u1DefBig = 0;
382	pDesc->Gen.u1Granularity = 0; /* byte limit */
383
384	/*
385	* TSS descriptor for trap 08
386	*/
387	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
388	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
389	pDesc->Gen.u4LimitHigh = 0;
390	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
391	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
392	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
393	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
394	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
395	pDesc->Gen.u1DescType = 0; /* system */
396	pDesc->Gen.u2Dpl = 0; /* supervisor */
397	pDesc->Gen.u1Present = 1;
398	pDesc->Gen.u1Available = 0;
399	pDesc->Gen.u1Long = 0;
400	pDesc->Gen.u1DefBig = 0;
401	pDesc->Gen.u1Granularity = 0; /* byte limit */
402	}
403
404	/**
405	* Applies relocations to data and code managed by this
406	* component. This function will be called at init and
407	* whenever the VMM need to relocate it self inside the GC.
408	*
409	* @param pVM The VM.
410	*/
411	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
412	{
413	PX86DESC paGdt = pVM->selm.s.paGdtR3;
414	LogFlow(("SELMR3Relocate\n"));
415
416	for (VMCPUID i = 0; i < pVM->cCpus; i++)
417	{
418	PVMCPU pVCpu = &pVM->aCpus[i];
419
420	/*
421	* Update GDTR and selector.
422	*/
423	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
424
425	/** @todo selector relocations should be a separate operation? */
426	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
427	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
428	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
429	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
430	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
431	}
432
433	selmR3SetupHyperGDTSelectors(pVM);
434
435	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
436	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
437	/*
438	* Update the TSSes.
439	*/
440	/* Only applies to raw mode which supports only 1 VCPU */
441	PVMCPU pVCpu = &pVM->aCpus[0];
442
443	/* Current TSS */
444	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
445	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
446	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
447	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
448	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
449	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
450	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
451
452	/* trap 08 */
453	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
454	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
455	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
456	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
457	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
458	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
459	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
460	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
461	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
462	pVM->selm.s.TssTrap08.fs = 0;
463	pVM->selm.s.TssTrap08.gs = 0;
464	pVM->selm.s.TssTrap08.selLdt = 0;
465	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
466	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
467	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
468	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
469	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
470	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
471	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
472	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
473	/* TRPM will be updating the eip */
474
475	if ( !pVM->selm.s.fDisableMonitoring
476	&& !VMMIsHwVirtExtForced(pVM))
477	{
478	/*
479	* Update shadow GDT/LDT/TSS write access handlers.
480	*/
481	int rc;
482	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
483	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
484	{
485	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
486	AssertRC(rc);
487	}
488	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
489	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
490	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
491	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
492	AssertRC(rc);
493	#endif
494	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
495	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
496	{
497	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
498	AssertRC(rc);
499	}
500	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
501	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
502	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
503	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
504	AssertRC(rc);
505	#endif
506
507	/*
508	* Update the GC LDT region handler and address.
509	*/
510	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
511	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
512	{
513	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
514	AssertRC(rc);
515	}
516	#endif
517	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
518	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
519	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
520	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
521	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
522	AssertRC(rc);
523	#endif
524	}
525	}
526
527
528	/**
529	* Terminates the SELM.
530	*
531	* Termination means cleaning up and freeing all resources,
532	* the VM it self is at this point powered off or suspended.
533	*
534	* @returns VBox status code.
535	* @param pVM Pointer to the VM.
536	*/
537	VMMR3DECL(int) SELMR3Term(PVM pVM)
538	{
539	NOREF(pVM);
540	return 0;
541	}
542
543
544	/**
545	* The VM is being reset.
546	*
547	* For the SELM component this means that any GDT/LDT/TSS monitors
548	* needs to be removed.
549	*
550	* @param pVM Pointer to the VM.
551	*/
552	VMMR3DECL(void) SELMR3Reset(PVM pVM)
553	{
554	LogFlow(("SELMR3Reset:\n"));
555	VM_ASSERT_EMT(pVM);
556
557	/*
558	* Uninstall guest GDT/LDT/TSS write access handlers.
559	*/
560	int rc = VINF_SUCCESS;
561	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
562	{
563	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
564	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
565	AssertRC(rc);
566	#endif
567	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
568	pVM->selm.s.GuestGdtr.cbGdt = 0;
569	}
570	pVM->selm.s.fGDTRangeRegistered = false;
571	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
572	{
573	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
574	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
575	AssertRC(rc);
576	#endif
577	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
578	}
579	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
580	{
581	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
582	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
583	AssertRC(rc);
584	#endif
585	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
586	pVM->selm.s.GCSelTss = RTSEL_MAX;
587	}
588
589	/*
590	* Re-initialize other members.
591	*/
592	pVM->selm.s.cbLdtLimit = 0;
593	pVM->selm.s.offLdtHyper = 0;
594	pVM->selm.s.cbMonitoredGuestTss = 0;
595
596	pVM->selm.s.fSyncTSSRing0Stack = false;
597
598	/*
599	* Default action when entering raw mode for the first time
600	*/
601	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
602	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
603	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
605	}
606
607	/**
608	* Disable GDT/LDT/TSS monitoring and syncing
609	*
610	* @param pVM Pointer to the VM.
611	*/
612	VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
613	{
614	/*
615	* Uninstall guest GDT/LDT/TSS write access handlers.
616	*/
617	int rc;
618	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
619	{
620	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
621	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
622	AssertRC(rc);
623	#endif
624	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
625	pVM->selm.s.GuestGdtr.cbGdt = 0;
626	}
627	pVM->selm.s.fGDTRangeRegistered = false;
628	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
629	{
630	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
631	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
632	AssertRC(rc);
633	#endif
634	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
635	}
636	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
637	{
638	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
639	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
640	AssertRC(rc);
641	#endif
642	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
643	pVM->selm.s.GCSelTss = RTSEL_MAX;
644	}
645
646	/*
647	* Unregister shadow GDT/LDT/TSS write access handlers.
648	*/
649	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
650	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
651	{
652	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
653	AssertRC(rc);
654	pVM->selm.s.paGdtRC = NIL_RTRCPTR;
655	}
656	#endif
657	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
658	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
659	{
660	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
661	AssertRC(rc);
662	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
663	}
664	#endif
665	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
666	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
667	{
668	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
669	AssertRC(rc);
670	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
671	}
672	#endif
673
674	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
675	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
676	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
677	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
678
679	pVM->selm.s.fDisableMonitoring = true;
680	}
681
682
683	/**
684	* Execute state save operation.
685	*
686	* @returns VBox status code.
687	* @param pVM Pointer to the VM.
688	* @param pSSM SSM operation handle.
689	*/
690	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
691	{
692	LogFlow(("selmR3Save:\n"));
693
694	/*
695	* Save the basic bits - fortunately all the other things can be resynced on load.
696	*/
697	PSELM pSelm = &pVM->selm.s;
698
699	SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
700	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
701	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
702	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
703	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
704	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
705	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
706	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
707	}
708
709
710	/**
711	* Execute state load operation.
712	*
713	* @returns VBox status code.
714	* @param pVM Pointer to the VM.
715	* @param pSSM SSM operation handle.
716	* @param uVersion Data layout version.
717	* @param uPass The data pass.
718	*/
719	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
720	{
721	LogFlow(("selmR3Load:\n"));
722	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
723
724	/*
725	* Validate version.
726	*/
727	if (uVersion != SELM_SAVED_STATE_VERSION)
728	{
729	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
730	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
731	}
732
733	/*
734	* Do a reset.
735	*/
736	SELMR3Reset(pVM);
737
738	/* Get the monitoring flag. */
739	SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
740
741	/* Get the TSS state flag. */
742	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
743
744	/*
745	* Get the selectors.
746	*/
747	RTSEL SelCS;
748	SSMR3GetSel(pSSM, &SelCS);
749	RTSEL SelDS;
750	SSMR3GetSel(pSSM, &SelDS);
751	RTSEL SelCS64;
752	SSMR3GetSel(pSSM, &SelCS64);
753	RTSEL SelDS64;
754	SSMR3GetSel(pSSM, &SelDS64);
755	RTSEL SelTSS;
756	SSMR3GetSel(pSSM, &SelTSS);
757	RTSEL SelTSSTrap08;
758	SSMR3GetSel(pSSM, &SelTSSTrap08);
759
760	/* Copy the selectors; they will be checked during relocation. */
761	PSELM pSelm = &pVM->selm.s;
762	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
763	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
764	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
765	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
766	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
767
768	return VINF_SUCCESS;
769	}
770
771
772	/**
773	* Sync the GDT, LDT and TSS after loading the state.
774	*
775	* Just to play save, we set the FFs to force syncing before
776	* executing GC code.
777	*
778	* @returns VBox status code.
779	* @param pVM Pointer to the VM.
780	* @param pSSM SSM operation handle.
781	*/
782	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
783	{
784	PVMCPU pVCpu = VMMGetCpu(pVM);
785
786	LogFlow(("selmR3LoadDone:\n"));
787
788	/*
789	* Don't do anything if it's a load failure.
790	*/
791	int rc = SSMR3HandleGetStatus(pSSM);
792	if (RT_FAILURE(rc))
793	return VINF_SUCCESS;
794
795	/*
796	* Do the syncing if we're in protected mode.
797	*/
798	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
799	{
800	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
801	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
802	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
803	SELMR3UpdateFromCPUM(pVM, pVCpu);
804	}
805
806	/*
807	* Flag everything for resync on next raw mode entry.
808	*/
809	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
810	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
811	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
812
813	return VINF_SUCCESS;
814	}
815
816	#ifdef VBOX_WITH_RAW_MODE
817
818	/**
819	* Updates (syncs) the shadow GDT.
820	*
821	* @returns VBox status code.
822	* @param pVM The VM handle.
823	* @param pVCpu The current virtual CPU.
824	*/
825	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
826	{
827	/*
828	* Always assume the best...
829	*/
830	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
831
832	/* If the GDT was changed, then make sure the LDT is checked too */
833	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
834	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
835	/* Same goes for the TSS selector */
836	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
837
838	/*
839	* Get the GDTR and check if there is anything to do (there usually is).
840	*/
841	VBOXGDTR GDTR;
842	CPUMGetGuestGDTR(pVCpu, &GDTR);
843	if (GDTR.cbGdt < sizeof(X86DESC))
844	{
845	Log(("No GDT entries...\n"));
846	return VINF_SUCCESS;
847	}
848
849	/*
850	* Read the Guest GDT.
851	* ASSUMES that the entire GDT is in memory.
852	*/
853	RTUINT cbEffLimit = GDTR.cbGdt;
854	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
855	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
856	if (RT_FAILURE(rc))
857	{
858	/*
859	* Read it page by page.
860	*
861	* Keep track of the last valid page and delay memsets and
862	* adjust cbEffLimit to reflect the effective size. The latter
863	* is something we do in the belief that the guest will probably
864	* never actually commit the last page, thus allowing us to keep
865	* our selectors in the high end of the GDT.
866	*/
867	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
868	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
869	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
870	uint8_t *pu8DstInvalid = pu8Dst;
871
872	while (cbLeft)
873	{
874	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
875	cb = RT_MIN(cb, cbLeft);
876	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
877	if (RT_SUCCESS(rc))
878	{
879	if (pu8DstInvalid != pu8Dst)
880	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
881	GCPtrSrc += cb;
882	pu8Dst += cb;
883	pu8DstInvalid = pu8Dst;
884	}
885	else if ( rc == VERR_PAGE_NOT_PRESENT
886	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
887	{
888	GCPtrSrc += cb;
889	pu8Dst += cb;
890	}
891	else
892	{
893	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
894	return VERR_SELM_GDT_READ_ERROR;
895	}
896	cbLeft -= cb;
897	}
898
899	/* any invalid pages at the end? */
900	if (pu8DstInvalid != pu8Dst)
901	{
902	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
903	/* If any GDTEs was invalidated, zero them. */
904	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
905	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
906	}
907
908	/* keep track of the effective limit. */
909	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
910	{
911	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
912	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
913	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
914	}
915	}
916
917	/*
918	* Check if the Guest GDT intrudes on our GDT entries.
919	*/
920	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
921	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
922	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
923	{
924	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
925	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
926	int iGDT = 0;
927
928	Log(("Internal SELM GDT conflict: use non-present entries\n"));
929	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
930	while (pGDTECur > pGDTEStart)
931	{
932	/* We can reuse non-present entries */
933	if (!pGDTECur->Gen.u1Present)
934	{
935	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
936	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
937	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
938	iGDT++;
939	if (iGDT >= SELM_HYPER_SEL_MAX)
940	break;
941	}
942
943	pGDTECur--;
944	}
945	if (iGDT != SELM_HYPER_SEL_MAX)
946	{
947	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
948	return VERR_SELM_GDT_TOO_FULL;
949	}
950	}
951	else
952	{
953	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
954	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
955	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
956	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
957	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
958	}
959
960	#ifdef VBOX_WITH_SAFE_STR
961	/* Use the guest's TR selector to plug the str virtualization hole. */
962	if (CPUMGetGuestTR(pVCpu, NULL) != 0)
963	{
964	Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
965	aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
966	}
967	#endif
968
969	/*
970	* Work thru the copied GDT entries adjusting them for correct virtualization.
971	*/
972	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
973	while (pGDTE < pGDTEEnd)
974	{
975	if (pGDTE->Gen.u1Present)
976	selmGuestToShadowDesc(pVM, pGDTE);
977
978	/* Next GDT entry. */
979	pGDTE++;
980	}
981
982	/*
983	* Check if our hypervisor selectors were changed.
984	*/
985	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
986	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
987	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
988	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
989	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
990	{
991	/* Reinitialize our hypervisor GDTs */
992	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
993	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
994	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
995	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
996	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
997
998	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
999
1000	/*
1001	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
1002	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1003	*/
1004	VMR3Relocate(pVM, 0);
1005	}
1006	else
1007	#ifdef VBOX_WITH_SAFE_STR
1008	if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
1009	\|\| CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
1010	#else
1011	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1012	#endif
1013	/* We overwrote all entries above, so we have to save them again. */
1014	selmR3SetupHyperGDTSelectors(pVM);
1015
1016	/*
1017	* Adjust the cached GDT limit.
1018	* Any GDT entries which have been removed must be cleared.
1019	*/
1020	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1021	{
1022	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1023	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1024	}
1025
1026	/*
1027	* Check if Guest's GDTR is changed.
1028	*/
1029	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1030	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1031	{
1032	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1033
1034	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1035	/*
1036	* [Re]Register write virtual handler for guest's GDT.
1037	*/
1038	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1039	{
1040	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1041	AssertRC(rc);
1042	}
1043
1044	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1045	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1046	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1047	"Guest GDT write access handler");
1048	# ifdef VBOX_WITH_RAW_RING1
1049	/** @todo !HACK ALERT!
1050	* Some guest OSes (QNX) share code and the GDT on the same page;
1051	* PGMR3HandlerVirtualRegister doesn't support more than one handler,
1052	* so we kick out the PATM handler as this one is more important.
1053	* Fix this properly in PGMR3HandlerVirtualRegister?
1054	*/
1055	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1056	{
1057	LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1058	rc = PGMHandlerVirtualDeregister(pVM, GDTR.pGdt & PAGE_BASE_GC_MASK);
1059	AssertRC(rc);
1060
1061	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1062	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1063	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1064	"Guest GDT write access handler");
1065	}
1066	# endif
1067	if (RT_FAILURE(rc))
1068	return rc;
1069	#endif /* SELM_TRACK_GUEST_GDT_CHANGES */
1070
1071	/* Update saved Guest GDTR. */
1072	pVM->selm.s.GuestGdtr = GDTR;
1073	pVM->selm.s.fGDTRangeRegistered = true;
1074	}
1075
1076	return VINF_SUCCESS;
1077	}
1078
1079
1080	/**
1081	* Updates (syncs) the shadow LDT.
1082	*
1083	* @returns VBox status code.
1084	* @param pVM The VM handle.
1085	* @param pVCpu The current virtual CPU.
1086	*/
1087	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1088	{
1089	int rc = VINF_SUCCESS;
1090
1091	/*
1092	* Always assume the best...
1093	*/
1094	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1095
1096	/*
1097	* LDT handling is done similarly to the GDT handling with a shadow
1098	* array. However, since the LDT is expected to be swappable (at least
1099	* some ancient OSes makes it swappable) it must be floating and
1100	* synced on a per-page basis.
1101	*
1102	* Eventually we will change this to be fully on demand. Meaning that
1103	* we will only sync pages containing LDT selectors actually used and
1104	* let the #PF handler lazily sync pages as they are used.
1105	* (This applies to GDT too, when we start making OS/2 fast.)
1106	*/
1107
1108	/*
1109	* First, determine the current LDT selector.
1110	*/
1111	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1112	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1113	{
1114	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1115	CPUMSetHyperLDTR(pVCpu, 0);
1116	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1117	{
1118	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1119	AssertRC(rc);
1120	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1121	}
1122	pVM->selm.s.cbLdtLimit = 0;
1123	return VINF_SUCCESS;
1124	}
1125
1126	/*
1127	* Get the LDT selector.
1128	*/
1129	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1130	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1131	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1132	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1133
1134	/*
1135	* Validate it.
1136	*/
1137	if ( !cbLdt
1138	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1139	\|\| pDesc->Gen.u1DescType
1140	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1141	{
1142	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1143
1144	/* cbLdt > 0:
1145	* This is quite impossible, so we do as most people do when faced with
1146	* the impossible, we simply ignore it.
1147	*/
1148	CPUMSetHyperLDTR(pVCpu, 0);
1149	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1150	{
1151	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1152	AssertRC(rc);
1153	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1154	}
1155	return VINF_SUCCESS;
1156	}
1157	/** @todo check what intel does about odd limits. */
1158	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1159
1160	/*
1161	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1162	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1163	*/
1164	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1165	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1166
1167
1168	/** @todo Handle only present LDT segments. */
1169	// if (pDesc->Gen.u1Present)
1170	{
1171	/*
1172	* Check if Guest's LDT address/limit is changed.
1173	*/
1174	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1175	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1176	{
1177	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1178	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1179
1180	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1181	/*
1182	* [Re]Register write virtual handler for guest's GDT.
1183	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1184	*/
1185	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1186	{
1187	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1188	AssertRC(rc);
1189	}
1190	# ifdef DEBUG
1191	if (pDesc->Gen.u1Present)
1192	Log(("LDT selector marked not present!!\n"));
1193	# endif
1194	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1195	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1196	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1197	{
1198	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1199	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1200	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1201	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1202	}
1203	else if (RT_SUCCESS(rc))
1204	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1205	else
1206	{
1207	CPUMSetHyperLDTR(pVCpu, 0);
1208	return rc;
1209	}
1210	#else
1211	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1212	#endif
1213	pVM->selm.s.cbLdtLimit = cbLdt;
1214	}
1215	}
1216
1217	/*
1218	* Calc Shadow LDT base.
1219	*/
1220	unsigned off;
1221	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1222	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1223	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1224
1225	/*
1226	* Enable the LDT selector in the shadow GDT.
1227	*/
1228	pDesc->Gen.u1Present = 1;
1229	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1230	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1231	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1232	pDesc->Gen.u1Available = 0;
1233	pDesc->Gen.u1Long = 0;
1234	if (cbLdt > 0xffff)
1235	{
1236	cbLdt = 0xffff;
1237	pDesc->Gen.u4LimitHigh = 0;
1238	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1239	}
1240
1241	/*
1242	* Set Hyper LDTR and notify TRPM.
1243	*/
1244	CPUMSetHyperLDTR(pVCpu, SelLdt);
1245
1246	/*
1247	* Loop synchronising the LDT page by page.
1248	*/
1249	/** @todo investigate how intel handle various operations on half present cross page entries. */
1250	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1251	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1252
1253	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1254	unsigned cbLeft = cbLdt + 1;
1255	PX86DESC pLDTE = pShadowLDT;
1256	while (cbLeft)
1257	{
1258	/*
1259	* Read a chunk.
1260	*/
1261	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1262	if (cbChunk > cbLeft)
1263	cbChunk = cbLeft;
1264	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1265	if (RT_SUCCESS(rc))
1266	{
1267	/*
1268	* Mark page
1269	*/
1270	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1271	AssertRC(rc);
1272
1273	/*
1274	* Loop thru the available LDT entries.
1275	* Figure out where to start and end and the potential cross pageness of
1276	* things adds a little complexity. pLDTE is updated there and not in the
1277	* 'next' part of the loop. The pLDTEEnd is inclusive.
1278	*/
1279	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1280	if (pLDTE + 1 < pShadowLDT)
1281	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1282	while (pLDTE <= pLDTEEnd)
1283	{
1284	if (pLDTE->Gen.u1Present)
1285	selmGuestToShadowDesc(pVM, pLDTE);
1286
1287	/* Next LDT entry. */
1288	pLDTE++;
1289	}
1290	}
1291	else
1292	{
1293	RT_BZERO(pShadowLDT, cbChunk);
1294	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1295	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1296	AssertRC(rc);
1297	}
1298
1299	/*
1300	* Advance to the next page.
1301	*/
1302	cbLeft -= cbChunk;
1303	GCPtrShadowLDT += cbChunk;
1304	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1305	GCPtrLdt += cbChunk;
1306	}
1307
1308	return VINF_SUCCESS;
1309	}
1310
1311
1312	/**
1313	* Checks and updates segment selector registers.
1314	*
1315	* @returns VBox strict status code.
1316	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1317	*
1318	* @param pVM The VM handle.
1319	* @param pVCpu The current virtual CPU.
1320	*/
1321	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1322	{
1323	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1324
1325	/*
1326	* No stale selectors in V8086 mode.
1327	*/
1328	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1329	if (pCtx->eflags.Bits.u1VM)
1330	return VINF_SUCCESS;
1331
1332	/*
1333	* Check for stale selectors and load hidden register bits where they
1334	* are missing.
1335	*/
1336	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1337	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1338	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1339	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1340	{
1341	RTSEL const Sel = paSReg[iSReg].Sel;
1342	if (Sel & X86_SEL_MASK_OFF_RPL)
1343	{
1344	/* Get the shadow descriptor entry corresponding to this. */
1345	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1346	PCX86DESC pDesc;
1347	if (!(Sel & X86_SEL_LDT))
1348	{
1349	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1350	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1351	else
1352	pDesc = &s_NotPresentDesc;
1353	}
1354	else
1355	{
1356	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1357	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1358	else
1359	pDesc = &s_NotPresentDesc;
1360	}
1361
1362	/* Check the segment register. */
1363	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1364	{
1365	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1366	{
1367	/* Did it go stale? */
1368	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1369	{
1370	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1371	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1372	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1373	rcStrict = VINF_EM_RESCHEDULE_REM;
1374	}
1375	}
1376	else
1377	{
1378	/* Did it stop being stale? I.e. did the guest change it things
1379	back to the way they were? */
1380	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1381	{
1382	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1383	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1384	}
1385	else
1386	{
1387	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1388	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1389	rcStrict = VINF_EM_RESCHEDULE_REM;
1390	}
1391	}
1392	}
1393	/* Load the hidden registers if it's a valid descriptor for the
1394	current segment register. */
1395	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1396	{
1397	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1398	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1399	}
1400	/* It's stale. */
1401	else
1402	{
1403	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1404	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1405	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1406	rcStrict = VINF_EM_RESCHEDULE_REM;
1407	}
1408	}
1409	/* else: 0 selector, ignore. */
1410	}
1411
1412	return rcStrict;
1413	}
1414
1415	#endif /VBOX_WITH_RAW_MODE/
1416
1417
1418	/**
1419	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1420	*
1421	* @returns VBox status code.
1422	* @param pVM Pointer to the VM.
1423	* @param pVCpu Pointer to the VMCPU.
1424	*/
1425	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1426	{
1427	#ifdef VBOX_WITH_RAW_MODE
1428	if (pVM->selm.s.fDisableMonitoring)
1429	#endif
1430	{
1431	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1432	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1433	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1434	return VINF_SUCCESS;
1435	}
1436
1437	#ifdef VBOX_WITH_RAW_MODE
1438	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1439
1440	/*
1441	* GDT sync
1442	*/
1443	int rc;
1444	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1445	{
1446	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1447	if (RT_FAILURE(rc))
1448	return rc; /* We're toast, so forget the profiling. */
1449	AssertRCSuccess(rc);
1450	}
1451
1452	/*
1453	* TSS sync
1454	*/
1455	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1456	{
1457	rc = SELMR3SyncTSS(pVM, pVCpu);
1458	if (RT_FAILURE(rc))
1459	return rc;
1460	AssertRCSuccess(rc);
1461	}
1462
1463	/*
1464	* LDT sync
1465	*/
1466	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1467	{
1468	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1469	if (RT_FAILURE(rc))
1470	return rc;
1471	AssertRCSuccess(rc);
1472	}
1473
1474	/*
1475	* Check selector registers.
1476	*/
1477	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1478
1479	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1480	return rcStrict;
1481	#endif /* VBOX_WITH_RAW_MODE */
1482	}
1483
1484
1485	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1486	/**
1487	* \#PF Handler callback for virtual access handler ranges.
1488	*
1489	* Important to realize that a physical page in a range can have aliases, and
1490	* for ALL and WRITE handlers these will also trigger.
1491	*
1492	* @returns VINF_SUCCESS if the handler have carried out the operation.
1493	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1494	* @param pVM Pointer to the VM.
1495	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1496	* @param pvPtr The HC mapping of that address.
1497	* @param pvBuf What the guest is reading/writing.
1498	* @param cbBuf How much it's reading/writing.
1499	* @param enmAccessType The access type.
1500	* @param pvUser User argument.
1501	*/
1502	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1503	PGMACCESSTYPE enmAccessType, void *pvUser)
1504	{
1505	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1506	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1507	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1508
1509	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1510	return VINF_PGM_HANDLER_DO_DEFAULT;
1511	}
1512	#endif
1513
1514	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1515	/**
1516	* \#PF Handler callback for virtual access handler ranges.
1517	*
1518	* Important to realize that a physical page in a range can have aliases, and
1519	* for ALL and WRITE handlers these will also trigger.
1520	*
1521	* @returns VINF_SUCCESS if the handler have carried out the operation.
1522	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1523	* @param pVM Pointer to the VM.
1524	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1525	* @param pvPtr The HC mapping of that address.
1526	* @param pvBuf What the guest is reading/writing.
1527	* @param cbBuf How much it's reading/writing.
1528	* @param enmAccessType The access type.
1529	* @param pvUser User argument.
1530	*/
1531	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1532	PGMACCESSTYPE enmAccessType, void *pvUser)
1533	{
1534	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1535	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1536	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1537
1538	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1539	return VINF_PGM_HANDLER_DO_DEFAULT;
1540	}
1541	#endif
1542
1543
1544	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1545	/**
1546	* \#PF Handler callback for virtual access handler ranges.
1547	*
1548	* Important to realize that a physical page in a range can have aliases, and
1549	* for ALL and WRITE handlers these will also trigger.
1550	*
1551	* @returns VINF_SUCCESS if the handler have carried out the operation.
1552	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1553	* @param pVM Pointer to the VM.
1554	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1555	* @param pvPtr The HC mapping of that address.
1556	* @param pvBuf What the guest is reading/writing.
1557	* @param cbBuf How much it's reading/writing.
1558	* @param enmAccessType The access type.
1559	* @param pvUser User argument.
1560	*/
1561	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1562	PGMACCESSTYPE enmAccessType, void *pvUser)
1563	{
1564	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1565	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1566	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1567
1568	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1569	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1570	* should probably also deregister the virtual handler if TR.base/size
1571	* changes while we're in REM. */
1572
1573	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1574	return VINF_PGM_HANDLER_DO_DEFAULT;
1575	}
1576	#endif
1577
1578
1579	/**
1580	* Synchronize the shadowed fields in the TSS.
1581	*
1582	* At present we're shadowing the ring-0 stack selector & pointer, and the
1583	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1584	* REM and this function is called both if REM made any changes to the TSS or
1585	* loaded TR.
1586	*
1587	* @returns VBox status code.
1588	* @param pVM Pointer to the VM.
1589	* @param pVCpu Pointer to the VMCPU.
1590	*/
1591	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1592	{
1593	int rc;
1594
1595	#ifdef VBOX_WITH_RAW_MODE
1596	if (pVM->selm.s.fDisableMonitoring)
1597	#endif
1598	{
1599	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1600	return VINF_SUCCESS;
1601	}
1602
1603	#ifdef VBOX_WITH_RAW_MODE
1604	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1605	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1606
1607	/*
1608	* Get TR and extract and store the basic info.
1609	*
1610	* Note! The TSS limit is not checked by the LTR code, so we
1611	* have to be a bit careful with it. We make sure cbTss
1612	* won't be zero if TR is valid and if it's NULL we'll
1613	* make sure cbTss is 0.
1614	*/
1615	/** @todo use the hidden bits, not shadow GDT. */
1616	CPUMSELREGHID trHid;
1617	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1618	RTGCPTR GCPtrTss = trHid.u64Base;
1619	uint32_t cbTss = trHid.u32Limit;
1620	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1621	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1622	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1623	if (SelTss & X86_SEL_MASK_OFF_RPL)
1624	{
1625	Assert(!(SelTss & X86_SEL_LDT));
1626	Assert(trHid.Attr.n.u1DescType == 0);
1627	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1628	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1629	if (!++cbTss)
1630	cbTss = UINT32_MAX;
1631	}
1632	else
1633	{
1634	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1635	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1636	cbTss = 0; /* the reset case. */
1637	}
1638	pVM->selm.s.cbGuestTss = cbTss;
1639	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1640	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1641
1642	/*
1643	* Figure out the size of what need to monitor.
1644	*/
1645	/* We're not interested in any 16-bit TSSes. */
1646	uint32_t cbMonitoredTss = cbTss;
1647	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1648	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1649	cbMonitoredTss = 0;
1650
1651	pVM->selm.s.offGuestIoBitmap = 0;
1652	bool fNoRing1Stack = true;
1653	if (cbMonitoredTss)
1654	{
1655	/*
1656	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1657	* If VME is enabled we also want to keep an eye on the interrupt
1658	* redirection bitmap.
1659	*/
1660	VBOXTSS Tss;
1661	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1662	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1663	if ( !(cr4 & X86_CR4_VME)
1664	\|\| ( RT_SUCCESS(rc)
1665	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1666	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1667	)
1668	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1669	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1670	else if (RT_SUCCESS(rc))
1671	{
1672	/*
1673	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1674	* this can be quite a large chunk. We use to skip it earlier and just hope it
1675	* was kind of static...
1676	*
1677	* Update the virtual interrupt redirection bitmap while we're here.
1678	* (It is located in the 32 bytes before TR:offIoBitmap.)
1679	*/
1680	cbMonitoredTss = Tss.offIoBitmap;
1681	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1682
1683	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1684	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1685	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1686	AssertRC(rc);
1687	/** @todo memset the bitmap on failure? */
1688	Log2(("Redirection bitmap:\n"));
1689	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1690	}
1691	else
1692	{
1693	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1694	pVM->selm.s.offGuestIoBitmap = 0;
1695	/** @todo memset the bitmap? */
1696	}
1697
1698	/*
1699	* Update the ring 0 stack selector and base address.
1700	*/
1701	if (RT_SUCCESS(rc))
1702	{
1703	#ifdef LOG_ENABLED
1704	if (LogIsEnabled())
1705	{
1706	uint32_t ssr0, espr0;
1707	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1708	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1709	{
1710	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1711	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1712	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1713	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1714	AssertMsg(ssr0 != Tss.ss0,
1715	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1716	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1717	}
1718	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1719	}
1720	#endif /* LOG_ENABLED */
1721	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1722
1723	/* Update our TSS structure for the guest's ring 1 stack */
1724	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1725	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1726
1727	#ifdef VBOX_WITH_RAW_RING1
1728	/* Update our TSS structure for the guest's ring 2 stack */
1729	if (EMIsRawRing1Enabled(pVM))
1730	{
1731	if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) \| 1))
1732	\|\| pVM->selm.s.Tss.esp2 != Tss.esp1)
1733	Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) \| 1, pVM->selm.s.Tss.esp2));
1734	selmSetRing2Stack(pVM, (Tss.ss1 & ~1) \| 2, Tss.esp1);
1735	}
1736	#endif
1737	}
1738	}
1739
1740	/*
1741	* Flush the ring-1 stack and the direct syscall dispatching if we
1742	* cannot obtain SS0:ESP0.
1743	*/
1744	if (fNoRing1Stack)
1745	{
1746	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1747	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1748
1749	/** @todo handle these dependencies better! */
1750	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1751	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1752	}
1753
1754	/*
1755	* Check for monitor changes and apply them.
1756	*/
1757	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1758	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1759	{
1760	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1761	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1762
1763	/* Release the old range first. */
1764	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1765	{
1766	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1767	AssertRC(rc);
1768	}
1769
1770	/* Register the write handler if TS != 0. */
1771	if (cbMonitoredTss != 0)
1772	{
1773	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1774	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1775	0, selmR3GuestTSSWriteHandler,
1776	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1777	if (RT_FAILURE(rc))
1778	{
1779	# ifdef VBOX_WITH_RAW_RING1
1780	/** @todo !HACK ALERT!
1781	* Some guest OSes (QNX) share code and the TSS on the same page;
1782	* PGMR3HandlerVirtualRegister doesn't support more than one
1783	* handler, so we kick out the PATM handler as this one is more
1784	* important. Fix this properly in PGMR3HandlerVirtualRegister?
1785	*/
1786	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1787	{
1788	LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1789	rc = PGMHandlerVirtualDeregister(pVM, GCPtrTss & PAGE_BASE_GC_MASK);
1790	AssertRC(rc);
1791
1792	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1793	0, selmR3GuestTSSWriteHandler,
1794	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1795	if (RT_FAILURE(rc))
1796	{
1797	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1798	return rc;
1799	}
1800	}
1801	# else
1802	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1803	return rc;
1804	# endif
1805	}
1806	#endif /* SELM_TRACK_GUEST_TSS_CHANGES */
1807
1808	/* Update saved Guest TSS info. */
1809	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1810	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1811	pVM->selm.s.GCSelTss = SelTss;
1812	}
1813	else
1814	{
1815	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1816	pVM->selm.s.cbMonitoredGuestTss = 0;
1817	pVM->selm.s.GCSelTss = 0;
1818	}
1819	}
1820
1821	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1822
1823	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1824	return VINF_SUCCESS;
1825	#endif /VBOX_WITH_RAW_MODE/
1826	}
1827
1828	#ifdef VBOX_WITH_RAW_MODE
1829
1830	/**
1831	* Compares the Guest GDT and LDT with the shadow tables.
1832	* This is a VBOX_STRICT only function.
1833	*
1834	* @returns VBox status code.
1835	* @param pVM Pointer to the VM.
1836	*/
1837	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1838	{
1839	#ifdef VBOX_STRICT
1840	PVMCPU pVCpu = VMMGetCpu(pVM);
1841
1842	/*
1843	* Get GDTR and check for conflict.
1844	*/
1845	VBOXGDTR GDTR;
1846	CPUMGetGuestGDTR(pVCpu, &GDTR);
1847	if (GDTR.cbGdt == 0)
1848	return VINF_SUCCESS;
1849
1850	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1851	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1852
1853	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1854	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1855
1856	/*
1857	* Loop thru the GDT checking each entry.
1858	*/
1859	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1860	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1861	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1862	while (pGDTE < pGDTEEnd)
1863	{
1864	X86DESC GDTEGuest;
1865	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1866	if (RT_SUCCESS(rc))
1867	{
1868	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1869	{
1870	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1871	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1872	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1873	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1874	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1875	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1876	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1877	{
1878	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1879	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1880	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1881	}
1882	}
1883	}
1884
1885	/* Advance to the next descriptor. */
1886	GCPtrGDTEGuest += sizeof(X86DESC);
1887	pGDTE++;
1888	}
1889
1890
1891	/*
1892	* LDT?
1893	*/
1894	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1895	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1896	return VINF_SUCCESS;
1897	Assert(!(SelLdt & X86_SEL_LDT));
1898	if (SelLdt > GDTR.cbGdt)
1899	{
1900	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1901	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1902	}
1903	X86DESC LDTDesc;
1904	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1905	if (RT_FAILURE(rc))
1906	{
1907	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1908	return rc;
1909	}
1910	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1911	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1912
1913	/*
1914	* Validate it.
1915	*/
1916	if (!cbLdt)
1917	return VINF_SUCCESS;
1918	/** @todo check what intel does about odd limits. */
1919	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1920	if ( LDTDesc.Gen.u1DescType
1921	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1922	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1923	{
1924	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1925	return VERR_SELM_INVALID_LDT;
1926	}
1927
1928	/*
1929	* Loop thru the LDT checking each entry.
1930	*/
1931	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1932	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1933	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1934	while (pLDTE < pLDTEEnd)
1935	{
1936	X86DESC LDTEGuest;
1937	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1938	if (RT_SUCCESS(rc))
1939	{
1940	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1941	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1942	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1943	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1944	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1945	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1946	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1947	{
1948	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1949	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1950	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1951	}
1952	}
1953
1954	/* Advance to the next descriptor. */
1955	GCPtrLDTEGuest += sizeof(X86DESC);
1956	pLDTE++;
1957	}
1958
1959	#else /* !VBOX_STRICT */
1960	NOREF(pVM);
1961	#endif /* !VBOX_STRICT */
1962
1963	return VINF_SUCCESS;
1964	}
1965
1966
1967	/**
1968	* Validates the RawR0 TSS values against the one in the Guest TSS.
1969	*
1970	* @returns true if it matches.
1971	* @returns false and assertions on mismatch..
1972	* @param pVM Pointer to the VM.
1973	*/
1974	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1975	{
1976	#if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1977	PVMCPU pVCpu = VMMGetCpu(pVM);
1978
1979	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1980	return true;
1981
1982	/*
1983	* Get TR and extract the basic info.
1984	*/
1985	CPUMSELREGHID trHid;
1986	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1987	RTGCPTR GCPtrTss = trHid.u64Base;
1988	uint32_t cbTss = trHid.u32Limit;
1989	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1990	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1991	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1992	if (SelTss & X86_SEL_MASK_OFF_RPL)
1993	{
1994	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1995	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1996	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1997	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1998	false);
1999	if (!++cbTss)
2000	cbTss = UINT32_MAX;
2001	}
2002	else
2003	{
2004	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
2005	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
2006	false);
2007	cbTss = 0; /* the reset case. */
2008	}
2009	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
2010	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2011	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
2012	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
2013	false);
2014	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
2015	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
2016	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
2017	false);
2018	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
2019	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
2020	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
2021	false);
2022
2023
2024	/*
2025	* Figure out the size of what need to monitor.
2026	*/
2027	/* We're not interested in any 16-bit TSSes. */
2028	uint32_t cbMonitoredTss = cbTss;
2029	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
2030	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2031	cbMonitoredTss = 0;
2032	if (cbMonitoredTss)
2033	{
2034	VBOXTSS Tss;
2035	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
2036	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
2037	AssertReturn( rc == VINF_SUCCESS
2038	/* Happens early in XP boot during page table switching. */
2039	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
2040	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
2041	false);
2042	if ( !(cr4 & X86_CR4_VME)
2043	\|\| ( RT_SUCCESS(rc)
2044	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
2045	&& Tss.offIoBitmap > cbTss)
2046	)
2047	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
2048	else if (RT_SUCCESS(rc))
2049	{
2050	cbMonitoredTss = Tss.offIoBitmap;
2051	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
2052	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
2053	false);
2054
2055	/* check the bitmap */
2056	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
2057	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
2058	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
2059	AssertRCReturn(rc, false);
2060	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
2061	("offIoBitmap=%#x cbTss=%#x\n"
2062	" Guest: %.32Rhxs\n"
2063	"Shadow: %.32Rhxs\n",
2064	Tss.offIoBitmap, cbTss,
2065	&Tss.IntRedirBitmap[0],
2066	&pVM->selm.s.Tss.IntRedirBitmap[0]),
2067	false);
2068	}
2069	else
2070	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
2071
2072	/*
2073	* Check SS0 and ESP0.
2074	*/
2075	if ( !pVM->selm.s.fSyncTSSRing0Stack
2076	&& RT_SUCCESS(rc))
2077	{
2078	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
2079	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
2080	{
2081	RTGCPHYS GCPhys;
2082	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
2083	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
2084	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
2085	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
2086	return false;
2087	}
2088	}
2089	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2090	}
2091	else
2092	{
2093	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
2094	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
2095	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2096	}
2097
2098
2099
2100	return true;
2101
2102	#else /* !VBOX_STRICT */
2103	NOREF(pVM);
2104	return true;
2105	#endif /* !VBOX_STRICT */
2106	}
2107
2108
2109	# ifdef VBOX_WITH_SAFE_STR
2110	/**
2111	* Validates the RawR0 TR shadow GDT entry.
2112	*
2113	* @returns true if it matches.
2114	* @returns false and assertions on mismatch..
2115	* @param pVM Pointer to the VM.
2116	*/
2117	VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2118	{
2119	# ifdef VBOX_STRICT
2120	PX86DESC paGdt = pVM->selm.s.paGdtR3;
2121
2122	/*
2123	* TSS descriptor
2124	*/
2125	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2126	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2127
2128	if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2129	\|\| pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2130	\|\| pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2131	\|\| pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2132	\|\| pDesc->Gen.u4LimitHigh != 0
2133	\|\| (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2134	\|\| pDesc->Gen.u1DescType != 0 /* system */
2135	\|\| pDesc->Gen.u2Dpl != 0 /* supervisor */
2136	\|\| pDesc->Gen.u1Present != 1
2137	\|\| pDesc->Gen.u1Available != 0
2138	\|\| pDesc->Gen.u1Long != 0
2139	\|\| pDesc->Gen.u1DefBig != 0
2140	\|\| pDesc->Gen.u1Granularity != 0 /* byte limit */
2141	)
2142	{
2143	AssertFailed();
2144	return false;
2145	}
2146	# endif
2147	return true;
2148	}
2149	# endif /* VBOX_WITH_SAFE_STR */
2150
2151	#endif /* VBOX_WITH_RAW_MODE */
2152
2153	/**
2154	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2155	*
2156	* See SELMR3GetSelectorInfo for details.
2157	*
2158	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2159	*
2160	* @param pVCpu Pointer to the VMCPU.
2161	* @param Sel The selector to get info about.
2162	* @param pSelInfo Where to store the information.
2163	*/
2164	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2165	{
2166	/*
2167	* Read it from the guest descriptor table.
2168	*/
2169	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2170	X86DESC64 Desc;
2171	RTGCPTR GCPtrDesc;
2172	if (!(Sel & X86_SEL_LDT))
2173	{
2174	/* GDT */
2175	VBOXGDTR Gdtr;
2176	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2177	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2178	return VERR_INVALID_SELECTOR;
2179	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2180	}
2181	else
2182	{
2183	/* LDT */
2184	uint64_t GCPtrBase;
2185	uint32_t cbLimit;
2186	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2187	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2188	return VERR_INVALID_SELECTOR;
2189
2190	/* calc the descriptor location. */
2191	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2192	}
2193
2194	/* read the descriptor. */
2195	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2196	if (RT_FAILURE(rc))
2197	{
2198	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2199	if (RT_FAILURE(rc))
2200	return rc;
2201	Desc.au64[1] = 0;
2202	}
2203
2204	/*
2205	* Extract the base and limit
2206	* (We ignore the present bit here, which is probably a bit silly...)
2207	*/
2208	pSelInfo->Sel = Sel;
2209	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2210	pSelInfo->u.Raw64 = Desc;
2211	if (Desc.Gen.u1DescType)
2212	{
2213	/*
2214	* 64-bit code selectors are wide open, it's not possible to detect
2215	* 64-bit data or stack selectors without also dragging in assumptions
2216	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2217	* the selinfo user needs to deal with this in the context the info is
2218	* used unfortunately.
2219	*/
2220	if ( Desc.Gen.u1Long
2221	&& !Desc.Gen.u1DefBig
2222	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2223	{
2224	/* Note! We ignore the segment limit hacks that was added by AMD. */
2225	pSelInfo->GCPtrBase = 0;
2226	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2227	}
2228	else
2229	{
2230	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2231	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2232	}
2233	pSelInfo->SelGate = 0;
2234	}
2235	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2236	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2237	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2238	{
2239	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2240	in the AMD manual here as a simplification. */
2241	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2242	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2243	pSelInfo->SelGate = 0;
2244	}
2245	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2246	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2247	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2248	{
2249	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2250	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2251	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2252	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2253	pSelInfo->SelGate = Desc.Gate.u16Sel;
2254	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2255	}
2256	else
2257	{
2258	pSelInfo->cbLimit = 0;
2259	pSelInfo->GCPtrBase = 0;
2260	pSelInfo->SelGate = 0;
2261	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2262	}
2263	if (!Desc.Gen.u1Present)
2264	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2265
2266	return VINF_SUCCESS;
2267	}
2268
2269
2270	/**
2271	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2272	* interprets a legacy descriptor table entry and fills in the selector info
2273	* structure from it.
2274	*
2275	* @param pSelInfo Where to store the selector info. Only the fFlags and
2276	* Sel members have been initialized.
2277	* @param pDesc The legacy descriptor to parse.
2278	*/
2279	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2280	{
2281	pSelInfo->u.Raw64.au64[1] = 0;
2282	pSelInfo->u.Raw = *pDesc;
2283	if ( pDesc->Gen.u1DescType
2284	\|\| !(pDesc->Gen.u4Type & 4))
2285	{
2286	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2287	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2288	pSelInfo->SelGate = 0;
2289	}
2290	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2291	{
2292	pSelInfo->cbLimit = 0;
2293	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2294	pSelInfo->GCPtrBase = 0;
2295	else
2296	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2297	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2298	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2299	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2300	}
2301	else
2302	{
2303	pSelInfo->cbLimit = 0;
2304	pSelInfo->GCPtrBase = 0;
2305	pSelInfo->SelGate = 0;
2306	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2307	}
2308	if (!pDesc->Gen.u1Present)
2309	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2310	}
2311
2312
2313	/**
2314	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2315	*
2316	* See SELMR3GetSelectorInfo for details.
2317	*
2318	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2319	*
2320	* @param pVM Pointer to the VM.
2321	* @param pVCpu Pointer to the VMCPU.
2322	* @param Sel The selector to get info about.
2323	* @param pSelInfo Where to store the information.
2324	*/
2325	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2326	{
2327	/*
2328	* Read the descriptor entry
2329	*/
2330	pSelInfo->fFlags = 0;
2331	X86DESC Desc;
2332	if ( !(Sel & X86_SEL_LDT)
2333	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2334	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2335	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2336	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2337	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2338	)
2339	{
2340	/*
2341	* Hypervisor descriptor.
2342	*/
2343	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2344	if (CPUMIsGuestInProtectedMode(pVCpu))
2345	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2346	else
2347	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2348
2349	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2350	}
2351	else if (CPUMIsGuestInProtectedMode(pVCpu))
2352	{
2353	/*
2354	* Read it from the guest descriptor table.
2355	*/
2356	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2357
2358	RTGCPTR GCPtrDesc;
2359	if (!(Sel & X86_SEL_LDT))
2360	{
2361	/* GDT */
2362	VBOXGDTR Gdtr;
2363	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2364	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2365	return VERR_INVALID_SELECTOR;
2366	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2367	}
2368	else
2369	{
2370	/* LDT */
2371	uint64_t GCPtrBase;
2372	uint32_t cbLimit;
2373	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2374	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2375	return VERR_INVALID_SELECTOR;
2376
2377	/* calc the descriptor location. */
2378	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2379	}
2380
2381	/* read the descriptor. */
2382	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2383	if (RT_FAILURE(rc))
2384	return rc;
2385	}
2386	else
2387	{
2388	/*
2389	* We're in real mode.
2390	*/
2391	pSelInfo->Sel = Sel;
2392	pSelInfo->GCPtrBase = Sel << 4;
2393	pSelInfo->cbLimit = 0xffff;
2394	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2395	pSelInfo->u.Raw64.au64[0] = 0;
2396	pSelInfo->u.Raw64.au64[1] = 0;
2397	pSelInfo->SelGate = 0;
2398	return VINF_SUCCESS;
2399	}
2400
2401	/*
2402	* Extract the base and limit or sel:offset for gates.
2403	*/
2404	pSelInfo->Sel = Sel;
2405	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2406
2407	return VINF_SUCCESS;
2408	}
2409
2410
2411	/**
2412	* Gets information about a selector.
2413	*
2414	* Intended for the debugger mostly and will prefer the guest descriptor tables
2415	* over the shadow ones.
2416	*
2417	* @retval VINF_SUCCESS on success.
2418	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2419	* descriptor table.
2420	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2421	* is not returned if the selector itself isn't present, you have to
2422	* check that for yourself (see DBGFSELINFO::fFlags).
2423	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2424	* pagetable or page backing the selector table wasn't present.
2425	* @returns Other VBox status code on other errors.
2426	*
2427	* @param pVM Pointer to the VM.
2428	* @param pVCpu Pointer to the VMCPU.
2429	* @param Sel The selector to get info about.
2430	* @param pSelInfo Where to store the information.
2431	*/
2432	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2433	{
2434	AssertPtr(pSelInfo);
2435	if (CPUMIsGuestInLongMode(pVCpu))
2436	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2437	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2438	}
2439
2440
2441	/**
2442	* Gets information about a selector from the shadow tables.
2443	*
2444	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2445	* requires that the caller ensures that the shadow tables are up to date.
2446	*
2447	* @retval VINF_SUCCESS on success.
2448	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2449	* descriptor table.
2450	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2451	* is not returned if the selector itself isn't present, you have to
2452	* check that for yourself (see DBGFSELINFO::fFlags).
2453	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2454	* pagetable or page backing the selector table wasn't present.
2455	* @returns Other VBox status code on other errors.
2456	*
2457	* @param pVM Pointer to the VM.
2458	* @param Sel The selector to get info about.
2459	* @param pSelInfo Where to store the information.
2460	*
2461	* @remarks Don't use this when in hardware assisted virtualization mode.
2462	*/
2463	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2464	{
2465	Assert(pSelInfo);
2466
2467	/*
2468	* Read the descriptor entry
2469	*/
2470	X86DESC Desc;
2471	if (!(Sel & X86_SEL_LDT))
2472	{
2473	/*
2474	* Global descriptor.
2475	*/
2476	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2477	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2478	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2479	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2480	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2481	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2482	? DBGFSELINFO_FLAGS_HYPER
2483	: 0;
2484	/** @todo check that the GDT offset is valid. */
2485	}
2486	else
2487	{
2488	/*
2489	* Local Descriptor.
2490	*/
2491	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2492	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2493	/** @todo check if the LDT page is actually available. */
2494	/** @todo check that the LDT offset is valid. */
2495	pSelInfo->fFlags = 0;
2496	}
2497	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2498	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2499	else
2500	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2501
2502	/*
2503	* Extract the base and limit or sel:offset for gates.
2504	*/
2505	pSelInfo->Sel = Sel;
2506	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2507
2508	return VINF_SUCCESS;
2509	}
2510
2511
2512	/**
2513	* Formats a descriptor.
2514	*
2515	* @param Desc Descriptor to format.
2516	* @param Sel Selector number.
2517	* @param pszOutput Output buffer.
2518	* @param cchOutput Size of output buffer.
2519	*/
2520	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2521	{
2522	/*
2523	* Make variable description string.
2524	*/
2525	static struct
2526	{
2527	unsigned cch;
2528	const char *psz;
2529	} const aTypes[32] =
2530	{
2531	#define STRENTRY(str) { sizeof(str) - 1, str }
2532	/* system */
2533	STRENTRY("Reserved0 "), /* 0x00 */
2534	STRENTRY("TSS16Avail "), /* 0x01 */
2535	STRENTRY("LDT "), /* 0x02 */
2536	STRENTRY("TSS16Busy "), /* 0x03 */
2537	STRENTRY("Call16 "), /* 0x04 */
2538	STRENTRY("Task "), /* 0x05 */
2539	STRENTRY("Int16 "), /* 0x06 */
2540	STRENTRY("Trap16 "), /* 0x07 */
2541	STRENTRY("Reserved8 "), /* 0x08 */
2542	STRENTRY("TSS32Avail "), /* 0x09 */
2543	STRENTRY("ReservedA "), /* 0x0a */
2544	STRENTRY("TSS32Busy "), /* 0x0b */
2545	STRENTRY("Call32 "), /* 0x0c */
2546	STRENTRY("ReservedD "), /* 0x0d */
2547	STRENTRY("Int32 "), /* 0x0e */
2548	STRENTRY("Trap32 "), /* 0x0f */
2549	/* non system */
2550	STRENTRY("DataRO "), /* 0x10 */
2551	STRENTRY("DataRO Accessed "), /* 0x11 */
2552	STRENTRY("DataRW "), /* 0x12 */
2553	STRENTRY("DataRW Accessed "), /* 0x13 */
2554	STRENTRY("DataDownRO "), /* 0x14 */
2555	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2556	STRENTRY("DataDownRW "), /* 0x16 */
2557	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2558	STRENTRY("CodeEO "), /* 0x18 */
2559	STRENTRY("CodeEO Accessed "), /* 0x19 */
2560	STRENTRY("CodeER "), /* 0x1a */
2561	STRENTRY("CodeER Accessed "), /* 0x1b */
2562	STRENTRY("CodeConfEO "), /* 0x1c */
2563	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2564	STRENTRY("CodeConfER "), /* 0x1e */
2565	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2566	#undef SYSENTRY
2567	};
2568	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2569	char szMsg[128];
2570	char *psz = &szMsg[0];
2571	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2572	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2573	psz += aTypes[i].cch;
2574
2575	if (Desc.Gen.u1Present)
2576	ADD_STR(psz, "Present ");
2577	else
2578	ADD_STR(psz, "Not-Present ");
2579	if (Desc.Gen.u1Granularity)
2580	ADD_STR(psz, "Page ");
2581	if (Desc.Gen.u1DefBig)
2582	ADD_STR(psz, "32-bit ");
2583	else
2584	ADD_STR(psz, "16-bit ");
2585	#undef ADD_STR
2586	*psz = '\0';
2587
2588	/*
2589	* Limit and Base and format the output.
2590	*/
2591	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2592	uint32_t u32Base = X86DESC_BASE(&Desc);
2593
2594	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2595	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2596	}
2597
2598
2599	/**
2600	* Dumps a descriptor.
2601	*
2602	* @param Desc Descriptor to dump.
2603	* @param Sel Selector number.
2604	* @param pszMsg Message to prepend the log entry with.
2605	*/
2606	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2607	{
2608	char szOutput[128];
2609	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2610	Log(("%s: %s\n", pszMsg, szOutput));
2611	NOREF(szOutput[0]);
2612	}
2613
2614
2615	/**
2616	* Display the shadow gdt.
2617	*
2618	* @param pVM Pointer to the VM.
2619	* @param pHlp The info helpers.
2620	* @param pszArgs Arguments, ignored.
2621	*/
2622	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2623	{
2624	NOREF(pszArgs);
2625	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2626	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2627	{
2628	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2629	{
2630	char szOutput[128];
2631	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2632	const char *psz = "";
2633	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2634	psz = " HyperCS";
2635	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2636	psz = " HyperDS";
2637	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2638	psz = " HyperCS64";
2639	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2640	psz = " HyperTSS";
2641	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2642	psz = " HyperTSSTrap08";
2643	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2644	}
2645	}
2646	}
2647
2648
2649	/**
2650	* Display the guest gdt.
2651	*
2652	* @param pVM Pointer to the VM.
2653	* @param pHlp The info helpers.
2654	* @param pszArgs Arguments, ignored.
2655	*/
2656	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2657	{
2658	/** @todo SMP support! */
2659	PVMCPU pVCpu = &pVM->aCpus[0];
2660
2661	VBOXGDTR GDTR;
2662	CPUMGetGuestGDTR(pVCpu, &GDTR);
2663	RTGCPTR GCPtrGDT = GDTR.pGdt;
2664	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2665
2666	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2667	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2668	{
2669	X86DESC GDTE;
2670	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2671	if (RT_SUCCESS(rc))
2672	{
2673	if (GDTE.Gen.u1Present)
2674	{
2675	char szOutput[128];
2676	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2677	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2678	}
2679	}
2680	else if (rc == VERR_PAGE_NOT_PRESENT)
2681	{
2682	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2683	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2684	}
2685	else
2686	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2687	}
2688	NOREF(pszArgs);
2689	}
2690
2691
2692	/**
2693	* Display the shadow ldt.
2694	*
2695	* @param pVM Pointer to the VM.
2696	* @param pHlp The info helpers.
2697	* @param pszArgs Arguments, ignored.
2698	*/
2699	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2700	{
2701	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2702	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2703	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2704	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2705	{
2706	if (paLDT[iLDT].Gen.u1Present)
2707	{
2708	char szOutput[128];
2709	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2710	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2711	}
2712	}
2713	NOREF(pszArgs);
2714	}
2715
2716
2717	/**
2718	* Display the guest ldt.
2719	*
2720	* @param pVM Pointer to the VM.
2721	* @param pHlp The info helpers.
2722	* @param pszArgs Arguments, ignored.
2723	*/
2724	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2725	{
2726	/** @todo SMP support! */
2727	PVMCPU pVCpu = &pVM->aCpus[0];
2728
2729	uint64_t GCPtrLdt;
2730	uint32_t cbLdt;
2731	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2732	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2733	{
2734	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2735	return;
2736	}
2737
2738	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2739	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2740	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2741	{
2742	X86DESC LdtE;
2743	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2744	if (RT_SUCCESS(rc))
2745	{
2746	if (LdtE.Gen.u1Present)
2747	{
2748	char szOutput[128];
2749	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2750	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2751	}
2752	}
2753	else if (rc == VERR_PAGE_NOT_PRESENT)
2754	{
2755	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2756	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2757	}
2758	else
2759	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2760	}
2761	NOREF(pszArgs);
2762	}
2763
2764
2765	/**
2766	* Dumps the hypervisor GDT
2767	*
2768	* @param pVM Pointer to the VM.
2769	*/
2770	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2771	{
2772	DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2773	}
2774
2775
2776	/**
2777	* Dumps the hypervisor LDT
2778	*
2779	* @param pVM Pointer to the VM.
2780	*/
2781	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2782	{
2783	DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2784	}
2785
2786
2787	/**
2788	* Dumps the guest GDT
2789	*
2790	* @param pVM Pointer to the VM.
2791	*/
2792	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2793	{
2794	DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2795	}
2796
2797
2798	/**
2799	* Dumps the guest LDT
2800	*
2801	* @param pVM Pointer to the VM.
2802	*/
2803	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2804	{
2805	DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2806	}
2807

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 45530

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