SELM.cpp@ 42418

Last change on this file since 42418 was 42418, checked in by vboxsync, 12 years ago
try to fix the burns
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1	/* $Id: SELM.cpp 42418 2012-07-26 16:24:26Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/mm.h>
66	#include <VBox/vmm/ssm.h>
67	#include <VBox/vmm/pgm.h>
68	#include <VBox/vmm/trpm.h>
69	#include <VBox/vmm/dbgf.h>
70	#include "SELMInternal.h"
71	#include <VBox/vmm/vm.h>
72	#include <VBox/err.h>
73	#include <VBox/param.h>
74
75	#include <iprt/assert.h>
76	#include <VBox/log.h>
77	#include <iprt/asm.h>
78	#include <iprt/string.h>
79	#include <iprt/thread.h>
80	#include <iprt/string.h>
81
82
83	/**
84	* Enable or disable tracking of Shadow GDT/LDT/TSS.
85	* @{
86	*/
87	#define SELM_TRACK_SHADOW_GDT_CHANGES
88	#define SELM_TRACK_SHADOW_LDT_CHANGES
89	#define SELM_TRACK_SHADOW_TSS_CHANGES
90	/** @} */
91
92
93	/** SELM saved state version. */
94	#define SELM_SAVED_STATE_VERSION 5
95
96
97	/*******************************************************************************
98	* Internal Functions *
99	*******************************************************************************/
100	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
101	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
104	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
105	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
106	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112
113
114	/*******************************************************************************
115	* Global Variables *
116	*******************************************************************************/
117	#ifdef LOG_ENABLED
118	/** Segment register names. */
119	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
120	#endif
121
122
123	/**
124	* Initializes the SELM.
125	*
126	* @returns VBox status code.
127	* @param pVM Pointer to the VM.
128	*/
129	VMMR3DECL(int) SELMR3Init(PVM pVM)
130	{
131	LogFlow(("SELMR3Init\n"));
132
133	/*
134	* Assert alignment and sizes.
135	* (The TSS block requires contiguous back.)
136	*/
137	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
138	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
139	#if 0 /* doesn't work */
140	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
141	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
142	#endif
143	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
144	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
145	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
146
147	/*
148	* Init the structure.
149	*/
150	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
151	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
152	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
153	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
154	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
155	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
156
157	/*
158	* Allocate GDT table.
159	*/
160	int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
161	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
162	AssertRCReturn(rc, rc);
163
164	/*
165	* Allocate LDT area.
166	*/
167	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
168	AssertRCReturn(rc, rc);
169
170	/*
171	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
172	*/
173	pVM->selm.s.cbEffGuestGdtLimit = 0;
174	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
175	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
176	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
177
178	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
179	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
180	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
181	pVM->selm.s.GCSelTss = RTSEL_MAX;
182
183	pVM->selm.s.fDisableMonitoring = false;
184	pVM->selm.s.fSyncTSSRing0Stack = false;
185
186	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
187	* for I/O operations. */
188	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
189	/* bit set to 1 means no redirection */
190	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
191
192	/*
193	* Register the saved state data unit.
194	*/
195	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
196	NULL, NULL, NULL,
197	NULL, selmR3Save, NULL,
198	NULL, selmR3Load, selmR3LoadDone);
199	if (RT_FAILURE(rc))
200	return rc;
201
202	/*
203	* Statistics.
204	*/
205	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
206	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
207	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
208	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
209	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
210	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
211	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
212	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
213	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
214
215	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
216	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
217
218	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
219	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
220	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
221	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
222	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
223	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
224
225	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
226	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
227	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
228	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
229	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
230	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
231
232	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
233
234	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
235	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
236	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
237	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
238	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
239	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
240
241	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
242	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
243	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
244	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
245
246	/*
247	* Default action when entering raw mode for the first time
248	*/
249	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
250	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
251	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
252	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
253
254	/*
255	* Register info handlers.
256	*/
257	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
258	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
259	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
260	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
261	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
262	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
263
264	return rc;
265	}
266
267
268	/**
269	* Finalizes HMA page attributes.
270	*
271	* @returns VBox status code.
272	* @param pVM Pointer to the VM.
273	*/
274	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
275	{
276	/** @cfgm{/DoubleFault,bool,false}
277	* Enables catching of double faults in the raw-mode context VMM code. This can
278	* be used when the triple faults or hangs occur and one suspect an unhandled
279	* double fault. This is not enabled by default because it means making the
280	* hyper selectors writeable for all supervisor code, including the guest's.
281	* The double fault is a task switch and thus requires write access to the GDT
282	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
283	* 8 TSS for the back link.
284	*/
285	bool f;
286	#if defined(DEBUG_bird)
287	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
288	#else
289	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
290	#endif
291	AssertLogRelRCReturn(rc, rc);
292	if (f)
293	{
294	PX86DESC paGdt = pVM->selm.s.paGdtR3;
295	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
296	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
297	AssertRC(rc);
298	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
299	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
300	AssertRC(rc);
301	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
302	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
303	AssertRC(rc);
304	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
305	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
306	AssertRC(rc);
307	}
308	return VINF_SUCCESS;
309	}
310
311
312	/**
313	* Setup the hypervisor GDT selectors in our shadow table
314	*
315	* @param pVM Pointer to the VM.
316	*/
317	static void selmR3SetupHyperGDTSelectors(PVM pVM)
318	{
319	PX86DESC paGdt = pVM->selm.s.paGdtR3;
320
321	/*
322	* Set up global code and data descriptors for use in the guest context.
323	* Both are wide open (base 0, limit 4GB)
324	*/
325	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
326	pDesc->Gen.u16LimitLow = 0xffff;
327	pDesc->Gen.u4LimitHigh = 0xf;
328	pDesc->Gen.u16BaseLow = 0;
329	pDesc->Gen.u8BaseHigh1 = 0;
330	pDesc->Gen.u8BaseHigh2 = 0;
331	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
332	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
333	pDesc->Gen.u2Dpl = 0; /* supervisor */
334	pDesc->Gen.u1Present = 1;
335	pDesc->Gen.u1Available = 0;
336	pDesc->Gen.u1Long = 0;
337	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
338	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
339
340	/* data */
341	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
342	pDesc->Gen.u16LimitLow = 0xffff;
343	pDesc->Gen.u4LimitHigh = 0xf;
344	pDesc->Gen.u16BaseLow = 0;
345	pDesc->Gen.u8BaseHigh1 = 0;
346	pDesc->Gen.u8BaseHigh2 = 0;
347	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
348	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
349	pDesc->Gen.u2Dpl = 0; /* supervisor */
350	pDesc->Gen.u1Present = 1;
351	pDesc->Gen.u1Available = 0;
352	pDesc->Gen.u1Long = 0;
353	pDesc->Gen.u1DefBig = 1; /* big */
354	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
355
356	/* 64-bit mode code (& data?) */
357	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
358	pDesc->Gen.u16LimitLow = 0xffff;
359	pDesc->Gen.u4LimitHigh = 0xf;
360	pDesc->Gen.u16BaseLow = 0;
361	pDesc->Gen.u8BaseHigh1 = 0;
362	pDesc->Gen.u8BaseHigh2 = 0;
363	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
364	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
365	pDesc->Gen.u2Dpl = 0; /* supervisor */
366	pDesc->Gen.u1Present = 1;
367	pDesc->Gen.u1Available = 0;
368	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
369	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
370	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
371
372	/*
373	* TSS descriptor
374	*/
375	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
376	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
377	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
378	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
379	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
380	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
381	pDesc->Gen.u4LimitHigh = 0;
382	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
383	pDesc->Gen.u1DescType = 0; /* system */
384	pDesc->Gen.u2Dpl = 0; /* supervisor */
385	pDesc->Gen.u1Present = 1;
386	pDesc->Gen.u1Available = 0;
387	pDesc->Gen.u1Long = 0;
388	pDesc->Gen.u1DefBig = 0;
389	pDesc->Gen.u1Granularity = 0; /* byte limit */
390
391	/*
392	* TSS descriptor for trap 08
393	*/
394	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
395	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
396	pDesc->Gen.u4LimitHigh = 0;
397	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
398	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
399	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
400	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
401	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
402	pDesc->Gen.u1DescType = 0; /* system */
403	pDesc->Gen.u2Dpl = 0; /* supervisor */
404	pDesc->Gen.u1Present = 1;
405	pDesc->Gen.u1Available = 0;
406	pDesc->Gen.u1Long = 0;
407	pDesc->Gen.u1DefBig = 0;
408	pDesc->Gen.u1Granularity = 0; /* byte limit */
409	}
410
411	/**
412	* Applies relocations to data and code managed by this
413	* component. This function will be called at init and
414	* whenever the VMM need to relocate it self inside the GC.
415	*
416	* @param pVM The VM.
417	*/
418	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
419	{
420	PX86DESC paGdt = pVM->selm.s.paGdtR3;
421	LogFlow(("SELMR3Relocate\n"));
422
423	for (VMCPUID i = 0; i < pVM->cCpus; i++)
424	{
425	PVMCPU pVCpu = &pVM->aCpus[i];
426
427	/*
428	* Update GDTR and selector.
429	*/
430	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
431
432	/** @todo selector relocations should be a separate operation? */
433	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
434	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
435	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
436	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
437	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
438	}
439
440	selmR3SetupHyperGDTSelectors(pVM);
441
442	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
443	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
444	/*
445	* Update the TSSes.
446	*/
447	/* Only applies to raw mode which supports only 1 VCPU */
448	PVMCPU pVCpu = &pVM->aCpus[0];
449
450	/* Current TSS */
451	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
452	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
453	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
454	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
455	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
456	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
457	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
458
459	/* trap 08 */
460	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
461	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
462	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
463	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
464	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
465	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
466	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
467	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
468	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
469	pVM->selm.s.TssTrap08.fs = 0;
470	pVM->selm.s.TssTrap08.gs = 0;
471	pVM->selm.s.TssTrap08.selLdt = 0;
472	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
473	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
474	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
475	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
476	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
477	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
478	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
479	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
480	/* TRPM will be updating the eip */
481
482	if ( !pVM->selm.s.fDisableMonitoring
483	&& !VMMIsHwVirtExtForced(pVM))
484	{
485	/*
486	* Update shadow GDT/LDT/TSS write access handlers.
487	*/
488	int rc;
489	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
490	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
491	{
492	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
493	AssertRC(rc);
494	}
495	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
496	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
497	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
498	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
499	AssertRC(rc);
500	#endif
501	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
502	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
503	{
504	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
505	AssertRC(rc);
506	}
507	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
508	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
509	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
510	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
511	AssertRC(rc);
512	#endif
513
514	/*
515	* Update the GC LDT region handler and address.
516	*/
517	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
518	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
519	{
520	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
521	AssertRC(rc);
522	}
523	#endif
524	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
525	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
526	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
527	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
528	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
529	AssertRC(rc);
530	#endif
531	}
532	}
533
534
535	/**
536	* Terminates the SELM.
537	*
538	* Termination means cleaning up and freeing all resources,
539	* the VM it self is at this point powered off or suspended.
540	*
541	* @returns VBox status code.
542	* @param pVM Pointer to the VM.
543	*/
544	VMMR3DECL(int) SELMR3Term(PVM pVM)
545	{
546	NOREF(pVM);
547	return 0;
548	}
549
550
551	/**
552	* The VM is being reset.
553	*
554	* For the SELM component this means that any GDT/LDT/TSS monitors
555	* needs to be removed.
556	*
557	* @param pVM Pointer to the VM.
558	*/
559	VMMR3DECL(void) SELMR3Reset(PVM pVM)
560	{
561	LogFlow(("SELMR3Reset:\n"));
562	VM_ASSERT_EMT(pVM);
563
564	/*
565	* Uninstall guest GDT/LDT/TSS write access handlers.
566	*/
567	int rc;
568	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
569	{
570	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
571	AssertRC(rc);
572	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
573	pVM->selm.s.GuestGdtr.cbGdt = 0;
574	}
575	pVM->selm.s.fGDTRangeRegistered = false;
576	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
577	{
578	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
579	AssertRC(rc);
580	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
581	}
582	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
583	{
584	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
585	AssertRC(rc);
586	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
587	pVM->selm.s.GCSelTss = RTSEL_MAX;
588	}
589
590	/*
591	* Re-initialize other members.
592	*/
593	pVM->selm.s.cbLdtLimit = 0;
594	pVM->selm.s.offLdtHyper = 0;
595	pVM->selm.s.cbMonitoredGuestTss = 0;
596
597	pVM->selm.s.fSyncTSSRing0Stack = false;
598
599	/*
600	* Default action when entering raw mode for the first time
601	*/
602	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
603	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
605	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
606	}
607
608	/**
609	* Disable GDT/LDT/TSS monitoring and syncing
610	*
611	* @param pVM Pointer to the VM.
612	*/
613	VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
614	{
615	/*
616	* Uninstall guest GDT/LDT/TSS write access handlers.
617	*/
618	int rc;
619	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
620	{
621	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
622	AssertRC(rc);
623	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
624	pVM->selm.s.GuestGdtr.cbGdt = 0;
625	}
626	pVM->selm.s.fGDTRangeRegistered = false;
627	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
628	{
629	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
630	AssertRC(rc);
631	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
632	}
633	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
634	{
635	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
636	AssertRC(rc);
637	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
638	pVM->selm.s.GCSelTss = RTSEL_MAX;
639	}
640
641	/*
642	* Unregister shadow GDT/LDT/TSS write access handlers.
643	*/
644	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
645	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
646	{
647	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
648	AssertRC(rc);
649	pVM->selm.s.paGdtRC = NIL_RTRCPTR;
650	}
651	#endif
652	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
653	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
654	{
655	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
656	AssertRC(rc);
657	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
658	}
659	#endif
660	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
661	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
662	{
663	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
664	AssertRC(rc);
665	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
666	}
667	#endif
668
669	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
670	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
671	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
672	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
673
674	pVM->selm.s.fDisableMonitoring = true;
675	}
676
677
678	/**
679	* Execute state save operation.
680	*
681	* @returns VBox status code.
682	* @param pVM Pointer to the VM.
683	* @param pSSM SSM operation handle.
684	*/
685	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
686	{
687	LogFlow(("selmR3Save:\n"));
688
689	/*
690	* Save the basic bits - fortunately all the other things can be resynced on load.
691	*/
692	PSELM pSelm = &pVM->selm.s;
693
694	SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
695	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
696	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
697	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
698	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
699	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
700	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
701	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
702	}
703
704
705	/**
706	* Execute state load operation.
707	*
708	* @returns VBox status code.
709	* @param pVM Pointer to the VM.
710	* @param pSSM SSM operation handle.
711	* @param uVersion Data layout version.
712	* @param uPass The data pass.
713	*/
714	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
715	{
716	LogFlow(("selmR3Load:\n"));
717	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
718
719	/*
720	* Validate version.
721	*/
722	if (uVersion != SELM_SAVED_STATE_VERSION)
723	{
724	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
725	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
726	}
727
728	/*
729	* Do a reset.
730	*/
731	SELMR3Reset(pVM);
732
733	/* Get the monitoring flag. */
734	SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
735
736	/* Get the TSS state flag. */
737	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
738
739	/*
740	* Get the selectors.
741	*/
742	RTSEL SelCS;
743	SSMR3GetSel(pSSM, &SelCS);
744	RTSEL SelDS;
745	SSMR3GetSel(pSSM, &SelDS);
746	RTSEL SelCS64;
747	SSMR3GetSel(pSSM, &SelCS64);
748	RTSEL SelDS64;
749	SSMR3GetSel(pSSM, &SelDS64);
750	RTSEL SelTSS;
751	SSMR3GetSel(pSSM, &SelTSS);
752	RTSEL SelTSSTrap08;
753	SSMR3GetSel(pSSM, &SelTSSTrap08);
754
755	/* Copy the selectors; they will be checked during relocation. */
756	PSELM pSelm = &pVM->selm.s;
757	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
758	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
759	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
760	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
761	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
762
763	return VINF_SUCCESS;
764	}
765
766
767	/**
768	* Sync the GDT, LDT and TSS after loading the state.
769	*
770	* Just to play save, we set the FFs to force syncing before
771	* executing GC code.
772	*
773	* @returns VBox status code.
774	* @param pVM Pointer to the VM.
775	* @param pSSM SSM operation handle.
776	*/
777	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
778	{
779	PVMCPU pVCpu = VMMGetCpu(pVM);
780
781	LogFlow(("selmR3LoadDone:\n"));
782
783	/*
784	* Don't do anything if it's a load failure.
785	*/
786	int rc = SSMR3HandleGetStatus(pSSM);
787	if (RT_FAILURE(rc))
788	return VINF_SUCCESS;
789
790	/*
791	* Do the syncing if we're in protected mode.
792	*/
793	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
794	{
795	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
796	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
797	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
798	SELMR3UpdateFromCPUM(pVM, pVCpu);
799	}
800
801	/*
802	* Flag everything for resync on next raw mode entry.
803	*/
804	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
805	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
806	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
807
808	return VINF_SUCCESS;
809	}
810
811
812	/**
813	* Updates (syncs) the shadow GDT.
814	*
815	* @returns VBox status code.
816	* @param pVM The VM handle.
817	* @param pVCpu The current virtual CPU.
818	*/
819	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
820	{
821	/*
822	* Always assume the best...
823	*/
824	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
825
826	/* If the GDT was changed, then make sure the LDT is checked too */
827	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
828	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
829	/* Same goes for the TSS selector */
830	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
831
832	/*
833	* Get the GDTR and check if there is anything to do (there usually is).
834	*/
835	VBOXGDTR GDTR;
836	CPUMGetGuestGDTR(pVCpu, &GDTR);
837	if (GDTR.cbGdt < sizeof(X86DESC))
838	{
839	Log(("No GDT entries...\n"));
840	return VINF_SUCCESS;
841	}
842
843	/*
844	* Read the Guest GDT.
845	* ASSUMES that the entire GDT is in memory.
846	*/
847	RTUINT cbEffLimit = GDTR.cbGdt;
848	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
849	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
850	if (RT_FAILURE(rc))
851	{
852	/*
853	* Read it page by page.
854	*
855	* Keep track of the last valid page and delay memsets and
856	* adjust cbEffLimit to reflect the effective size. The latter
857	* is something we do in the belief that the guest will probably
858	* never actually commit the last page, thus allowing us to keep
859	* our selectors in the high end of the GDT.
860	*/
861	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
862	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
863	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
864	uint8_t *pu8DstInvalid = pu8Dst;
865
866	while (cbLeft)
867	{
868	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
869	cb = RT_MIN(cb, cbLeft);
870	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
871	if (RT_SUCCESS(rc))
872	{
873	if (pu8DstInvalid != pu8Dst)
874	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
875	GCPtrSrc += cb;
876	pu8Dst += cb;
877	pu8DstInvalid = pu8Dst;
878	}
879	else if ( rc == VERR_PAGE_NOT_PRESENT
880	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
881	{
882	GCPtrSrc += cb;
883	pu8Dst += cb;
884	}
885	else
886	{
887	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
888	return VERR_SELM_GDT_READ_ERROR;
889	}
890	cbLeft -= cb;
891	}
892
893	/* any invalid pages at the end? */
894	if (pu8DstInvalid != pu8Dst)
895	{
896	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
897	/* If any GDTEs was invalidated, zero them. */
898	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
899	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
900	}
901
902	/* keep track of the effective limit. */
903	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
904	{
905	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
906	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
907	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
908	}
909	}
910
911	/*
912	* Check if the Guest GDT intrudes on our GDT entries.
913	*/
914	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
915	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
916	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
917	{
918	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
919	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
920	int iGDT = 0;
921
922	Log(("Internal SELM GDT conflict: use non-present entries\n"));
923	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
924	while (pGDTECur > pGDTEStart)
925	{
926	/* We can reuse non-present entries */
927	if (!pGDTECur->Gen.u1Present)
928	{
929	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
930	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
931	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
932	iGDT++;
933	if (iGDT >= SELM_HYPER_SEL_MAX)
934	break;
935	}
936
937	pGDTECur--;
938	}
939	if (iGDT != SELM_HYPER_SEL_MAX)
940	{
941	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
942	return VERR_SELM_GDT_TOO_FULL;
943	}
944	}
945	else
946	{
947	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
948	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
949	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
950	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
951	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
952	}
953
954	/*
955	* Work thru the copied GDT entries adjusting them for correct virtualization.
956	*/
957	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
958	while (pGDTE < pGDTEEnd)
959	{
960	if (pGDTE->Gen.u1Present)
961	selmGuestToShadowDesc(pGDTE);
962
963	/* Next GDT entry. */
964	pGDTE++;
965	}
966
967	/*
968	* Check if our hypervisor selectors were changed.
969	*/
970	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
971	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
972	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
973	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
974	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
975	{
976	/* Reinitialize our hypervisor GDTs */
977	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
978	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
979	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
980	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
981	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
982
983	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
984
985	/*
986	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
987	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
988	*/
989	VMR3Relocate(pVM, 0);
990	}
991	else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
992	/* We overwrote all entries above, so we have to save them again. */
993	selmR3SetupHyperGDTSelectors(pVM);
994
995	/*
996	* Adjust the cached GDT limit.
997	* Any GDT entries which have been removed must be cleared.
998	*/
999	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1000	{
1001	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1002	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1003	}
1004
1005	/*
1006	* Check if Guest's GDTR is changed.
1007	*/
1008	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1009	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1010	{
1011	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1012
1013	/*
1014	* [Re]Register write virtual handler for guest's GDT.
1015	*/
1016	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1017	{
1018	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1019	AssertRC(rc);
1020	}
1021
1022	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1023	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1024	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1025	"Guest GDT write access handler");
1026	if (RT_FAILURE(rc))
1027	return rc;
1028
1029	/* Update saved Guest GDTR. */
1030	pVM->selm.s.GuestGdtr = GDTR;
1031	pVM->selm.s.fGDTRangeRegistered = true;
1032	}
1033
1034	return VINF_SUCCESS;
1035	}
1036
1037
1038	/**
1039	* Updates (syncs) the shadow LDT.
1040	*
1041	* @returns VBox status code.
1042	* @param pVM The VM handle.
1043	* @param pVCpu The current virtual CPU.
1044	*/
1045	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1046	{
1047	int rc = VINF_SUCCESS;
1048
1049	/*
1050	* Always assume the best...
1051	*/
1052	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1053
1054	/*
1055	* LDT handling is done similarly to the GDT handling with a shadow
1056	* array. However, since the LDT is expected to be swappable (at least
1057	* some ancient OSes makes it swappable) it must be floating and
1058	* synced on a per-page basis.
1059	*
1060	* Eventually we will change this to be fully on demand. Meaning that
1061	* we will only sync pages containing LDT selectors actually used and
1062	* let the #PF handler lazily sync pages as they are used.
1063	* (This applies to GDT too, when we start making OS/2 fast.)
1064	*/
1065
1066	/*
1067	* First, determine the current LDT selector.
1068	*/
1069	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1070	if ((SelLdt & X86_SEL_MASK) == 0)
1071	{
1072	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1073	CPUMSetHyperLDTR(pVCpu, 0);
1074	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1075	{
1076	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1077	AssertRC(rc);
1078	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1079	}
1080	pVM->selm.s.cbLdtLimit = 0;
1081	return VINF_SUCCESS;
1082	}
1083
1084	/*
1085	* Get the LDT selector.
1086	*/
1087	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1088	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1089	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1090
1091	/*
1092	* Validate it.
1093	*/
1094	if ( !cbLdt
1095	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1096	\|\| pDesc->Gen.u1DescType
1097	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1098	{
1099	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1100
1101	/* cbLdt > 0:
1102	* This is quite impossible, so we do as most people do when faced with
1103	* the impossible, we simply ignore it.
1104	*/
1105	CPUMSetHyperLDTR(pVCpu, 0);
1106	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1107	{
1108	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1109	AssertRC(rc);
1110	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1111	}
1112	return VINF_SUCCESS;
1113	}
1114	/** @todo check what intel does about odd limits. */
1115	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1116
1117	/*
1118	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1119	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1120	*/
1121	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1122	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1123
1124
1125	/** @todo Handle only present LDT segments. */
1126	// if (pDesc->Gen.u1Present)
1127	{
1128	/*
1129	* Check if Guest's LDT address/limit is changed.
1130	*/
1131	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1132	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1133	{
1134	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1135	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1136
1137	/*
1138	* [Re]Register write virtual handler for guest's GDT.
1139	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1140	*/
1141	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1142	{
1143	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1144	AssertRC(rc);
1145	}
1146	#ifdef DEBUG
1147	if (pDesc->Gen.u1Present)
1148	Log(("LDT selector marked not present!!\n"));
1149	#endif
1150	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1151	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1152	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1153	{
1154	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1155	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1156	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1157	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1158	}
1159	else if (RT_SUCCESS(rc))
1160	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1161	else
1162	{
1163	CPUMSetHyperLDTR(pVCpu, 0);
1164	return rc;
1165	}
1166
1167	pVM->selm.s.cbLdtLimit = cbLdt;
1168	}
1169	}
1170
1171	/*
1172	* Calc Shadow LDT base.
1173	*/
1174	unsigned off;
1175	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1176	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1177	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1178
1179	/*
1180	* Enable the LDT selector in the shadow GDT.
1181	*/
1182	pDesc->Gen.u1Present = 1;
1183	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1184	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1185	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1186	pDesc->Gen.u1Available = 0;
1187	pDesc->Gen.u1Long = 0;
1188	if (cbLdt > 0xffff)
1189	{
1190	cbLdt = 0xffff;
1191	pDesc->Gen.u4LimitHigh = 0;
1192	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1193	}
1194
1195	/*
1196	* Set Hyper LDTR and notify TRPM.
1197	*/
1198	CPUMSetHyperLDTR(pVCpu, SelLdt);
1199
1200	/*
1201	* Loop synchronising the LDT page by page.
1202	*/
1203	/** @todo investigate how intel handle various operations on half present cross page entries. */
1204	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1205	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1206
1207	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1208	unsigned cbLeft = cbLdt + 1;
1209	PX86DESC pLDTE = pShadowLDT;
1210	while (cbLeft)
1211	{
1212	/*
1213	* Read a chunk.
1214	*/
1215	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1216	if (cbChunk > cbLeft)
1217	cbChunk = cbLeft;
1218	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1219	if (RT_SUCCESS(rc))
1220	{
1221	/*
1222	* Mark page
1223	*/
1224	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1225	AssertRC(rc);
1226
1227	/*
1228	* Loop thru the available LDT entries.
1229	* Figure out where to start and end and the potential cross pageness of
1230	* things adds a little complexity. pLDTE is updated there and not in the
1231	* 'next' part of the loop. The pLDTEEnd is inclusive.
1232	*/
1233	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1234	if (pLDTE + 1 < pShadowLDT)
1235	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1236	while (pLDTE <= pLDTEEnd)
1237	{
1238	if (pLDTE->Gen.u1Present)
1239	selmGuestToShadowDesc(pLDTE);
1240
1241	/* Next LDT entry. */
1242	pLDTE++;
1243	}
1244	}
1245	else
1246	{
1247	RT_BZERO(pShadowLDT, cbChunk);
1248	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1249	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1250	AssertRC(rc);
1251	}
1252
1253	/*
1254	* Advance to the next page.
1255	*/
1256	cbLeft -= cbChunk;
1257	GCPtrShadowLDT += cbChunk;
1258	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1259	GCPtrLdt += cbChunk;
1260	}
1261
1262	return VINF_SUCCESS;
1263	}
1264
1265
1266	/**
1267	* Checks and updates segment selector registers.
1268	*
1269	* @returns VBox strict status code.
1270	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1271	*
1272	* @param pVM The VM handle.
1273	* @param pVCpu The current virtual CPU.
1274	*/
1275	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1276	{
1277	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1278
1279	/*
1280	* No stale selectors in V8086 mode.
1281	*/
1282	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1283	if (pCtx->eflags.Bits.u1VM)
1284	return VINF_SUCCESS;
1285
1286	/*
1287	* Check for stale selectors and load hidden register bits where they
1288	* are missing.
1289	*/
1290	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1291	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1292	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1293	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1294	{
1295	RTSEL const Sel = paSReg[iSReg].Sel & (X86_SEL_MASK \| X86_SEL_LDT);
1296	if (Sel & (X86_SEL_MASK \| X86_SEL_LDT))
1297	{
1298	/* Get the shadow descriptor entry corresponding to this. */
1299	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1300	PCX86DESC pDesc;
1301	if (!(Sel & X86_SEL_LDT))
1302	{
1303	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1304	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1305	else
1306	pDesc = &s_NotPresentDesc;
1307	}
1308	else
1309	{
1310	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1311	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1312	else
1313	pDesc = &s_NotPresentDesc;
1314	}
1315
1316	/* Check the segment register. */
1317	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1318	{
1319	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1320	{
1321	/* Did it go stale? */
1322	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1323	{
1324	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1325	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1326	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1327	rcStrict = VINF_EM_RESCHEDULE_REM;
1328	}
1329	}
1330	else
1331	{
1332	/* Did it stop being stale? I.e. did the guest change it things
1333	back to the way they were? */
1334	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1335	{
1336	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1337	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1338	}
1339	else
1340	{
1341	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1342	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1343	rcStrict = VINF_EM_RESCHEDULE_REM;
1344	}
1345	}
1346	}
1347	/* Load the hidden registers if it's a valid descriptor for the
1348	current segment register. */
1349	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1350	{
1351	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1352	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1353	}
1354	/* It's stale. */
1355	else
1356	{
1357	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1358	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1359	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1360	rcStrict = VINF_EM_RESCHEDULE_REM;
1361	}
1362	}
1363	/* else: 0 selector, ignore. */
1364	}
1365
1366	return rcStrict;
1367	}
1368
1369
1370	/**
1371	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1372	*
1373	* @returns VBox status code.
1374	* @param pVM Pointer to the VM.
1375	* @param pVCpu Pointer to the VMCPU.
1376	*/
1377	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1378	{
1379	if (pVM->selm.s.fDisableMonitoring)
1380	{
1381	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1382	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1383	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1384	return VINF_SUCCESS;
1385	}
1386
1387	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1388
1389	/*
1390	* GDT sync
1391	*/
1392	int rc;
1393	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1394	{
1395	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1396	if (RT_FAILURE(rc))
1397	return rc; /* We're toast, so forget the profiling. */
1398	AssertRCSuccess(rc);
1399	}
1400
1401	/*
1402	* TSS sync
1403	*/
1404	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1405	{
1406	rc = SELMR3SyncTSS(pVM, pVCpu);
1407	if (RT_FAILURE(rc))
1408	return rc;
1409	AssertRCSuccess(rc);
1410	}
1411
1412	/*
1413	* LDT sync
1414	*/
1415	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1416	{
1417	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1418	if (RT_FAILURE(rc))
1419	return rc;
1420	AssertRCSuccess(rc);
1421	}
1422
1423	/*
1424	* Check selector registers.
1425	*/
1426	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1427
1428	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1429	return rcStrict;
1430	}
1431
1432
1433	/**
1434	* \#PF Handler callback for virtual access handler ranges.
1435	*
1436	* Important to realize that a physical page in a range can have aliases, and
1437	* for ALL and WRITE handlers these will also trigger.
1438	*
1439	* @returns VINF_SUCCESS if the handler have carried out the operation.
1440	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1441	* @param pVM Pointer to the VM.
1442	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1443	* @param pvPtr The HC mapping of that address.
1444	* @param pvBuf What the guest is reading/writing.
1445	* @param cbBuf How much it's reading/writing.
1446	* @param enmAccessType The access type.
1447	* @param pvUser User argument.
1448	*/
1449	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1450	PGMACCESSTYPE enmAccessType, void *pvUser)
1451	{
1452	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1453	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1454	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1455
1456	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1457	return VINF_PGM_HANDLER_DO_DEFAULT;
1458	}
1459
1460
1461	/**
1462	* \#PF Handler callback for virtual access handler ranges.
1463	*
1464	* Important to realize that a physical page in a range can have aliases, and
1465	* for ALL and WRITE handlers these will also trigger.
1466	*
1467	* @returns VINF_SUCCESS if the handler have carried out the operation.
1468	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1469	* @param pVM Pointer to the VM.
1470	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1471	* @param pvPtr The HC mapping of that address.
1472	* @param pvBuf What the guest is reading/writing.
1473	* @param cbBuf How much it's reading/writing.
1474	* @param enmAccessType The access type.
1475	* @param pvUser User argument.
1476	*/
1477	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1478	PGMACCESSTYPE enmAccessType, void *pvUser)
1479	{
1480	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1481	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1482	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1483
1484	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1485	return VINF_PGM_HANDLER_DO_DEFAULT;
1486	}
1487
1488
1489	/**
1490	* \#PF Handler callback for virtual access handler ranges.
1491	*
1492	* Important to realize that a physical page in a range can have aliases, and
1493	* for ALL and WRITE handlers these will also trigger.
1494	*
1495	* @returns VINF_SUCCESS if the handler have carried out the operation.
1496	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1497	* @param pVM Pointer to the VM.
1498	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1499	* @param pvPtr The HC mapping of that address.
1500	* @param pvBuf What the guest is reading/writing.
1501	* @param cbBuf How much it's reading/writing.
1502	* @param enmAccessType The access type.
1503	* @param pvUser User argument.
1504	*/
1505	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1506	PGMACCESSTYPE enmAccessType, void *pvUser)
1507	{
1508	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1509	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1510	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1511
1512	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1513	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1514	* should probably also deregister the virtual handler if TR.base/size
1515	* changes while we're in REM. */
1516
1517	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1518	return VINF_PGM_HANDLER_DO_DEFAULT;
1519	}
1520
1521
1522	/**
1523	* Synchronize the shadowed fields in the TSS.
1524	*
1525	* At present we're shadowing the ring-0 stack selector & pointer, and the
1526	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1527	* REM and this function is called both if REM made any changes to the TSS or
1528	* loaded TR.
1529	*
1530	* @returns VBox status code.
1531	* @param pVM Pointer to the VM.
1532	* @param pVCpu Pointer to the VMCPU.
1533	*/
1534	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1535	{
1536	int rc;
1537
1538	if (pVM->selm.s.fDisableMonitoring)
1539	{
1540	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1541	return VINF_SUCCESS;
1542	}
1543
1544	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1545	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1546
1547	/*
1548	* Get TR and extract and store the basic info.
1549	*
1550	* Note! The TSS limit is not checked by the LTR code, so we
1551	* have to be a bit careful with it. We make sure cbTss
1552	* won't be zero if TR is valid and if it's NULL we'll
1553	* make sure cbTss is 0.
1554	*/
1555	CPUMSELREGHID trHid;
1556	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1557	RTGCPTR GCPtrTss = trHid.u64Base;
1558	uint32_t cbTss = trHid.u32Limit;
1559	Assert( (SelTss & X86_SEL_MASK)
1560	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1561	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1562	if (SelTss & X86_SEL_MASK)
1563	{
1564	Assert(!(SelTss & X86_SEL_LDT));
1565	Assert(trHid.Attr.n.u1DescType == 0);
1566	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1567	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1568	if (!++cbTss)
1569	cbTss = UINT32_MAX;
1570	}
1571	else
1572	{
1573	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1574	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1575	cbTss = 0; /* the reset case. */
1576	}
1577	pVM->selm.s.cbGuestTss = cbTss;
1578	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1579	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1580
1581	/*
1582	* Figure out the size of what need to monitor.
1583	*/
1584	/* We're not interested in any 16-bit TSSes. */
1585	uint32_t cbMonitoredTss = cbTss;
1586	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1587	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1588	cbMonitoredTss = 0;
1589
1590	pVM->selm.s.offGuestIoBitmap = 0;
1591	bool fNoRing1Stack = true;
1592	if (cbMonitoredTss)
1593	{
1594	/*
1595	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1596	* If VME is enabled we also want to keep an eye on the interrupt
1597	* redirection bitmap.
1598	*/
1599	VBOXTSS Tss;
1600	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1601	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1602	if ( !(cr4 & X86_CR4_VME)
1603	\|\| ( RT_SUCCESS(rc)
1604	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1605	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1606	)
1607	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1608	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1609	else if (RT_SUCCESS(rc))
1610	{
1611	/*
1612	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1613	* this can be quite a large chunk. We use to skip it earlier and just hope it
1614	* was kind of static...
1615	*
1616	* Update the virtual interrupt redirection bitmap while we're here.
1617	* (It is located in the 32 bytes before TR:offIoBitmap.)
1618	*/
1619	cbMonitoredTss = Tss.offIoBitmap;
1620	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1621
1622	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1623	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1624	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1625	AssertRC(rc);
1626	/** @todo memset the bitmap on failure? */
1627	Log2(("Redirection bitmap:\n"));
1628	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1629	}
1630	else
1631	{
1632	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1633	pVM->selm.s.offGuestIoBitmap = 0;
1634	/** @todo memset the bitmap? */
1635	}
1636
1637	/*
1638	* Update the ring 0 stack selector and base address.
1639	*/
1640	if (RT_SUCCESS(rc))
1641	{
1642	#ifdef LOG_ENABLED
1643	if (LogIsEnabled())
1644	{
1645	uint32_t ssr0, espr0;
1646	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1647	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1648	{
1649	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1650	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1651	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1652	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1653	AssertMsg(ssr0 != Tss.ss0,
1654	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1655	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1656	}
1657	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1658	}
1659	#endif /* LOG_ENABLED */
1660	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1661
1662	/* Update our TSS structure for the guest's ring 1 stack */
1663	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1664	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1665	}
1666	}
1667
1668	/*
1669	* Flush the ring-1 stack and the direct syscall dispatching if we
1670	* cannot obtain SS0:ESP0.
1671	*/
1672	if (fNoRing1Stack)
1673	{
1674	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1675	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1676
1677	/** @todo handle these dependencies better! */
1678	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1679	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1680	}
1681
1682	/*
1683	* Check for monitor changes and apply them.
1684	*/
1685	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1686	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1687	{
1688	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1689	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1690
1691	/* Release the old range first. */
1692	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1693	{
1694	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1695	AssertRC(rc);
1696	}
1697
1698	/* Register the write handler if TS != 0. */
1699	if (cbMonitoredTss != 0)
1700	{
1701	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1702	0, selmR3GuestTSSWriteHandler,
1703	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1704	if (RT_FAILURE(rc))
1705	{
1706	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1707	return rc;
1708	}
1709
1710	/* Update saved Guest TSS info. */
1711	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1712	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1713	pVM->selm.s.GCSelTss = SelTss;
1714	}
1715	else
1716	{
1717	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1718	pVM->selm.s.cbMonitoredGuestTss = 0;
1719	pVM->selm.s.GCSelTss = 0;
1720	}
1721	}
1722
1723	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1724
1725	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1726	return VINF_SUCCESS;
1727	}
1728
1729
1730	/**
1731	* Compares the Guest GDT and LDT with the shadow tables.
1732	* This is a VBOX_STRICT only function.
1733	*
1734	* @returns VBox status code.
1735	* @param pVM Pointer to the VM.
1736	*/
1737	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1738	{
1739	#ifdef VBOX_STRICT
1740	PVMCPU pVCpu = VMMGetCpu(pVM);
1741
1742	/*
1743	* Get GDTR and check for conflict.
1744	*/
1745	VBOXGDTR GDTR;
1746	CPUMGetGuestGDTR(pVCpu, &GDTR);
1747	if (GDTR.cbGdt == 0)
1748	return VINF_SUCCESS;
1749
1750	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1751	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1752
1753	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1754	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1755
1756	/*
1757	* Loop thru the GDT checking each entry.
1758	*/
1759	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1760	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1761	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1762	while (pGDTE < pGDTEEnd)
1763	{
1764	X86DESC GDTEGuest;
1765	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1766	if (RT_SUCCESS(rc))
1767	{
1768	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1769	{
1770	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1771	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1772	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1773	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1774	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1775	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1776	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1777	{
1778	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1779	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1780	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1781	}
1782	}
1783	}
1784
1785	/* Advance to the next descriptor. */
1786	GCPtrGDTEGuest += sizeof(X86DESC);
1787	pGDTE++;
1788	}
1789
1790
1791	/*
1792	* LDT?
1793	*/
1794	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1795	if ((SelLdt & X86_SEL_MASK) == 0)
1796	return VINF_SUCCESS;
1797	if (SelLdt > GDTR.cbGdt)
1798	{
1799	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1800	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1801	}
1802	X86DESC LDTDesc;
1803	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1804	if (RT_FAILURE(rc))
1805	{
1806	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1807	return rc;
1808	}
1809	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1810	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1811
1812	/*
1813	* Validate it.
1814	*/
1815	if (!cbLdt)
1816	return VINF_SUCCESS;
1817	/** @todo check what intel does about odd limits. */
1818	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1819	if ( LDTDesc.Gen.u1DescType
1820	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1821	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1822	{
1823	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1824	return VERR_SELM_INVALID_LDT;
1825	}
1826
1827	/*
1828	* Loop thru the LDT checking each entry.
1829	*/
1830	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1831	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1832	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1833	while (pLDTE < pLDTEEnd)
1834	{
1835	X86DESC LDTEGuest;
1836	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1837	if (RT_SUCCESS(rc))
1838	{
1839	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1840	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1841	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1842	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1843	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1844	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1845	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1846	{
1847	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1848	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1849	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1850	}
1851	}
1852
1853	/* Advance to the next descriptor. */
1854	GCPtrLDTEGuest += sizeof(X86DESC);
1855	pLDTE++;
1856	}
1857
1858	#else /* !VBOX_STRICT */
1859	NOREF(pVM);
1860	#endif /* !VBOX_STRICT */
1861
1862	return VINF_SUCCESS;
1863	}
1864
1865
1866	/**
1867	* Validates the RawR0 TSS values against the one in the Guest TSS.
1868	*
1869	* @returns true if it matches.
1870	* @returns false and assertions on mismatch..
1871	* @param pVM Pointer to the VM.
1872	*/
1873	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1874	{
1875	#ifdef VBOX_STRICT
1876	PVMCPU pVCpu = VMMGetCpu(pVM);
1877
1878	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1879	return true;
1880
1881	/*
1882	* Get TR and extract the basic info.
1883	*/
1884	CPUMSELREGHID trHid;
1885	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1886	RTGCPTR GCPtrTss = trHid.u64Base;
1887	uint32_t cbTss = trHid.u32Limit;
1888	Assert( (SelTss & X86_SEL_MASK)
1889	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1890	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1891	if (SelTss & X86_SEL_MASK)
1892	{
1893	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1894	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1895	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1896	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1897	false);
1898	if (!++cbTss)
1899	cbTss = UINT32_MAX;
1900	}
1901	else
1902	{
1903	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1904	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1905	false);
1906	cbTss = 0; /* the reset case. */
1907	}
1908	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1909	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1910	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1911	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1912	false);
1913	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1914	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1915	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1916	false);
1917	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1918	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1919	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1920	false);
1921
1922
1923	/*
1924	* Figure out the size of what need to monitor.
1925	*/
1926	/* We're not interested in any 16-bit TSSes. */
1927	uint32_t cbMonitoredTss = cbTss;
1928	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1929	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1930	cbMonitoredTss = 0;
1931	if (cbMonitoredTss)
1932	{
1933	VBOXTSS Tss;
1934	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1935	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1936	AssertReturn( rc == VINF_SUCCESS
1937	/* Happens early in XP boot during page table switching. */
1938	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
1939	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1940	false);
1941	if ( !(cr4 & X86_CR4_VME)
1942	\|\| ( RT_SUCCESS(rc)
1943	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1944	&& Tss.offIoBitmap > cbTss)
1945	)
1946	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1947	else if (RT_SUCCESS(rc))
1948	{
1949	cbMonitoredTss = Tss.offIoBitmap;
1950	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1951	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1952	false);
1953
1954	/* check the bitmap */
1955	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1956	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1957	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1958	AssertRCReturn(rc, false);
1959	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1960	("offIoBitmap=%#x cbTss=%#x\n"
1961	" Guest: %.32Rhxs\n"
1962	"Shadow: %.32Rhxs\n",
1963	Tss.offIoBitmap, cbTss,
1964	&Tss.IntRedirBitmap[0],
1965	&pVM->selm.s.Tss.IntRedirBitmap[0]),
1966	false);
1967	}
1968	else
1969	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1970
1971	/*
1972	* Check SS0 and ESP0.
1973	*/
1974	if ( !pVM->selm.s.fSyncTSSRing0Stack
1975	&& RT_SUCCESS(rc))
1976	{
1977	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1978	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1979	{
1980	RTGCPHYS GCPhys;
1981	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1982	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1983	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1984	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1985	return false;
1986	}
1987	}
1988	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1989	}
1990	else
1991	{
1992	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1993	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1994	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1995	}
1996
1997
1998
1999	return true;
2000
2001	#else /* !VBOX_STRICT */
2002	NOREF(pVM);
2003	return true;
2004	#endif /* !VBOX_STRICT */
2005	}
2006
2007
2008	/**
2009	* Returns flat address and limit of LDT by LDT selector from guest GDTR.
2010	*
2011	* Fully validate selector.
2012	*
2013	* @returns VBox status.
2014	* @param pVM Pointer to the VM.
2015	* @param SelLdt LDT selector.
2016	* @param ppvLdt Where to store the flat address of LDT.
2017	* @param pcbLimit Where to store LDT limit.
2018	*/
2019	VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
2020	{
2021	PVMCPU pVCpu = VMMGetCpu(pVM);
2022
2023	/* Get guest GDTR. */
2024	VBOXGDTR GDTR;
2025	CPUMGetGuestGDTR(pVCpu, &GDTR);
2026
2027	/* Check selector TI and GDT limit. */
2028	if ( (SelLdt & X86_SEL_LDT)
2029	\|\| SelLdt > GDTR.cbGdt)
2030	return VERR_INVALID_SELECTOR;
2031
2032	/* Read descriptor from GC. */
2033	X86DESC Desc;
2034	int rc = PGMPhysSimpleReadGCPtr(pVCpu, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
2035	if (RT_FAILURE(rc))
2036	{
2037	/* fatal */
2038	Log(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
2039	return VERR_SELECTOR_NOT_PRESENT;
2040	}
2041
2042	/* Check if LDT descriptor is not present. */
2043	if (Desc.Gen.u1Present == 0)
2044	return VERR_SELECTOR_NOT_PRESENT;
2045
2046	/* Check LDT descriptor type. */
2047	if ( Desc.Gen.u1DescType == 1
2048	\|\| Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2049	return VERR_INVALID_SELECTOR;
2050
2051	/* LDT descriptor is ok. */
2052	if (ppvLdt)
2053	{
2054	*ppvLdt = (RTGCPTR)X86DESC_BASE(&Desc);
2055	*pcbLimit = X86DESC_LIMIT_G(&Desc);
2056	}
2057	return VINF_SUCCESS;
2058	}
2059
2060
2061	/**
2062	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2063	*
2064	* See SELMR3GetSelectorInfo for details.
2065	*
2066	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2067	*
2068	* @param pVCpu Pointer to the VMCPU.
2069	* @param Sel The selector to get info about.
2070	* @param pSelInfo Where to store the information.
2071	*/
2072	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2073	{
2074	/*
2075	* Read it from the guest descriptor table.
2076	*/
2077	X86DESC64 Desc;
2078	VBOXGDTR Gdtr;
2079	RTGCPTR GCPtrDesc;
2080	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2081	if (!(Sel & X86_SEL_LDT))
2082	{
2083	/* GDT */
2084	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2085	return VERR_INVALID_SELECTOR;
2086	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2087	}
2088	else
2089	{
2090	/*
2091	* LDT - must locate the LDT first.
2092	*/
2093	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2094	if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? / /* @todo r=bird: No, I don't think so */
2095	\|\| (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2096	return VERR_INVALID_SELECTOR;
2097	GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2098	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2099	if (RT_FAILURE(rc))
2100	return rc;
2101
2102	/* validate the LDT descriptor. */
2103	if (Desc.Gen.u1Present == 0)
2104	return VERR_SELECTOR_NOT_PRESENT;
2105	if ( Desc.Gen.u1DescType == 1
2106	\|\| Desc.Gen.u4Type != AMD64_SEL_TYPE_SYS_LDT)
2107	return VERR_INVALID_SELECTOR;
2108
2109	uint32_t cbLimit = X86DESC_LIMIT_G(&Desc);
2110	if ((uint32_t)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2111	return VERR_INVALID_SELECTOR;
2112
2113	/* calc the descriptor location. */
2114	GCPtrDesc = X86DESC64_BASE(&Desc);
2115	GCPtrDesc += (Sel & X86_SEL_MASK);
2116	}
2117
2118	/* read the descriptor. */
2119	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2120	if (RT_FAILURE(rc))
2121	{
2122	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2123	if (RT_FAILURE(rc))
2124	return rc;
2125	Desc.au64[1] = 0;
2126	}
2127
2128	/*
2129	* Extract the base and limit
2130	* (We ignore the present bit here, which is probably a bit silly...)
2131	*/
2132	pSelInfo->Sel = Sel;
2133	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2134	pSelInfo->u.Raw64 = Desc;
2135	if (Desc.Gen.u1DescType)
2136	{
2137	/*
2138	* 64-bit code selectors are wide open, it's not possible to detect
2139	* 64-bit data or stack selectors without also dragging in assumptions
2140	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2141	* the selinfo user needs to deal with this in the context the info is
2142	* used unfortunately.
2143	*/
2144	if ( Desc.Gen.u1Long
2145	&& !Desc.Gen.u1DefBig
2146	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2147	{
2148	/* Note! We ignore the segment limit hacks that was added by AMD. */
2149	pSelInfo->GCPtrBase = 0;
2150	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2151	}
2152	else
2153	{
2154	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2155	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2156	}
2157	pSelInfo->SelGate = 0;
2158	}
2159	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2160	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2161	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2162	{
2163	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2164	in the AMD manual here as a simplification. */
2165	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2166	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2167	pSelInfo->SelGate = 0;
2168	}
2169	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2170	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2171	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2172	{
2173	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2174	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2175	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2176	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2177	pSelInfo->SelGate = Desc.Gate.u16Sel;
2178	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2179	}
2180	else
2181	{
2182	pSelInfo->cbLimit = 0;
2183	pSelInfo->GCPtrBase = 0;
2184	pSelInfo->SelGate = 0;
2185	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2186	}
2187	if (!Desc.Gen.u1Present)
2188	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2189
2190	return VINF_SUCCESS;
2191	}
2192
2193
2194	/**
2195	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2196	* interprets a legacy descriptor table entry and fills in the selector info
2197	* structure from it.
2198	*
2199	* @param pSelInfo Where to store the selector info. Only the fFlags and
2200	* Sel members have been initialized.
2201	* @param pDesc The legacy descriptor to parse.
2202	*/
2203	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2204	{
2205	pSelInfo->u.Raw64.au64[1] = 0;
2206	pSelInfo->u.Raw = *pDesc;
2207	if ( pDesc->Gen.u1DescType
2208	\|\| !(pDesc->Gen.u4Type & 4))
2209	{
2210	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2211	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2212	pSelInfo->SelGate = 0;
2213	}
2214	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2215	{
2216	pSelInfo->cbLimit = 0;
2217	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2218	pSelInfo->GCPtrBase = 0;
2219	else
2220	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2221	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2222	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2223	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2224	}
2225	else
2226	{
2227	pSelInfo->cbLimit = 0;
2228	pSelInfo->GCPtrBase = 0;
2229	pSelInfo->SelGate = 0;
2230	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2231	}
2232	if (!pDesc->Gen.u1Present)
2233	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2234	}
2235
2236
2237	/**
2238	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2239	*
2240	* See SELMR3GetSelectorInfo for details.
2241	*
2242	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2243	*
2244	* @param pVM Pointer to the VM.
2245	* @param pVCpu Pointer to the VMCPU.
2246	* @param Sel The selector to get info about.
2247	* @param pSelInfo Where to store the information.
2248	*/
2249	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2250	{
2251	/*
2252	* Read the descriptor entry
2253	*/
2254	pSelInfo->fFlags = 0;
2255	X86DESC Desc;
2256	if ( !(Sel & X86_SEL_LDT)
2257	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2258	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2259	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2260	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2261	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
2262	)
2263	{
2264	/*
2265	* Hypervisor descriptor.
2266	*/
2267	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2268	if (CPUMIsGuestInProtectedMode(pVCpu))
2269	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2270	else
2271	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2272
2273	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2274	}
2275	else if (CPUMIsGuestInProtectedMode(pVCpu))
2276	{
2277	/*
2278	* Read it from the guest descriptor table.
2279	*/
2280	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2281
2282	VBOXGDTR Gdtr;
2283	RTGCPTR GCPtrDesc;
2284	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2285	if (!(Sel & X86_SEL_LDT))
2286	{
2287	/* GDT */
2288	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2289	return VERR_INVALID_SELECTOR;
2290	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2291	}
2292	else
2293	{
2294	/*
2295	* LDT - must locate the LDT first...
2296	*/
2297	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2298	if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? / /* @todo r=bird: No, I don't think so */
2299	\|\| (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2300	return VERR_INVALID_SELECTOR;
2301	GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2302	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2303	if (RT_FAILURE(rc))
2304	return rc;
2305
2306	/* validate the LDT descriptor. */
2307	if (Desc.Gen.u1Present == 0)
2308	return VERR_SELECTOR_NOT_PRESENT;
2309	if ( Desc.Gen.u1DescType == 1
2310	\|\| Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2311	return VERR_INVALID_SELECTOR;
2312
2313	uint32_t cbLimit = X86DESC_LIMIT_G(&Desc);
2314	if ((uint32_t)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2315	return VERR_INVALID_SELECTOR;
2316
2317	/* calc the descriptor location. */
2318	GCPtrDesc = X86DESC_BASE(&Desc);
2319	GCPtrDesc += (Sel & X86_SEL_MASK);
2320	}
2321
2322	/* read the descriptor. */
2323	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2324	if (RT_FAILURE(rc))
2325	return rc;
2326	}
2327	else
2328	{
2329	/*
2330	* We're in real mode.
2331	*/
2332	pSelInfo->Sel = Sel;
2333	pSelInfo->GCPtrBase = Sel << 4;
2334	pSelInfo->cbLimit = 0xffff;
2335	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2336	pSelInfo->u.Raw64.au64[0] = 0;
2337	pSelInfo->u.Raw64.au64[1] = 0;
2338	pSelInfo->SelGate = 0;
2339	return VINF_SUCCESS;
2340	}
2341
2342	/*
2343	* Extract the base and limit or sel:offset for gates.
2344	*/
2345	pSelInfo->Sel = Sel;
2346	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2347
2348	return VINF_SUCCESS;
2349	}
2350
2351
2352	/**
2353	* Gets information about a selector.
2354	*
2355	* Intended for the debugger mostly and will prefer the guest descriptor tables
2356	* over the shadow ones.
2357	*
2358	* @retval VINF_SUCCESS on success.
2359	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2360	* descriptor table.
2361	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2362	* is not returned if the selector itself isn't present, you have to
2363	* check that for yourself (see DBGFSELINFO::fFlags).
2364	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2365	* pagetable or page backing the selector table wasn't present.
2366	* @returns Other VBox status code on other errors.
2367	*
2368	* @param pVM Pointer to the VM.
2369	* @param pVCpu Pointer to the VMCPU.
2370	* @param Sel The selector to get info about.
2371	* @param pSelInfo Where to store the information.
2372	*/
2373	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2374	{
2375	AssertPtr(pSelInfo);
2376	if (CPUMIsGuestInLongMode(pVCpu))
2377	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2378	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2379	}
2380
2381
2382	/**
2383	* Gets information about a selector from the shadow tables.
2384	*
2385	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2386	* requires that the caller ensures that the shadow tables are up to date.
2387	*
2388	* @retval VINF_SUCCESS on success.
2389	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2390	* descriptor table.
2391	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2392	* is not returned if the selector itself isn't present, you have to
2393	* check that for yourself (see DBGFSELINFO::fFlags).
2394	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2395	* pagetable or page backing the selector table wasn't present.
2396	* @returns Other VBox status code on other errors.
2397	*
2398	* @param pVM Pointer to the VM.
2399	* @param Sel The selector to get info about.
2400	* @param pSelInfo Where to store the information.
2401	*
2402	* @remarks Don't use this when in hardware assisted virtualization mode.
2403	*/
2404	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2405	{
2406	Assert(pSelInfo);
2407
2408	/*
2409	* Read the descriptor entry
2410	*/
2411	X86DESC Desc;
2412	if (!(Sel & X86_SEL_LDT))
2413	{
2414	/*
2415	* Global descriptor.
2416	*/
2417	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2418	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2419	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2420	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2421	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2422	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK)
2423	? DBGFSELINFO_FLAGS_HYPER
2424	: 0;
2425	/** @todo check that the GDT offset is valid. */
2426	}
2427	else
2428	{
2429	/*
2430	* Local Descriptor.
2431	*/
2432	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2433	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2434	/** @todo check if the LDT page is actually available. */
2435	/** @todo check that the LDT offset is valid. */
2436	pSelInfo->fFlags = 0;
2437	}
2438	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2439	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2440	else
2441	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2442
2443	/*
2444	* Extract the base and limit or sel:offset for gates.
2445	*/
2446	pSelInfo->Sel = Sel;
2447	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2448
2449	return VINF_SUCCESS;
2450	}
2451
2452
2453	/**
2454	* Formats a descriptor.
2455	*
2456	* @param Desc Descriptor to format.
2457	* @param Sel Selector number.
2458	* @param pszOutput Output buffer.
2459	* @param cchOutput Size of output buffer.
2460	*/
2461	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2462	{
2463	/*
2464	* Make variable description string.
2465	*/
2466	static struct
2467	{
2468	unsigned cch;
2469	const char *psz;
2470	} const aTypes[32] =
2471	{
2472	#define STRENTRY(str) { sizeof(str) - 1, str }
2473	/* system */
2474	STRENTRY("Reserved0 "), /* 0x00 */
2475	STRENTRY("TSS16Avail "), /* 0x01 */
2476	STRENTRY("LDT "), /* 0x02 */
2477	STRENTRY("TSS16Busy "), /* 0x03 */
2478	STRENTRY("Call16 "), /* 0x04 */
2479	STRENTRY("Task "), /* 0x05 */
2480	STRENTRY("Int16 "), /* 0x06 */
2481	STRENTRY("Trap16 "), /* 0x07 */
2482	STRENTRY("Reserved8 "), /* 0x08 */
2483	STRENTRY("TSS32Avail "), /* 0x09 */
2484	STRENTRY("ReservedA "), /* 0x0a */
2485	STRENTRY("TSS32Busy "), /* 0x0b */
2486	STRENTRY("Call32 "), /* 0x0c */
2487	STRENTRY("ReservedD "), /* 0x0d */
2488	STRENTRY("Int32 "), /* 0x0e */
2489	STRENTRY("Trap32 "), /* 0x0f */
2490	/* non system */
2491	STRENTRY("DataRO "), /* 0x10 */
2492	STRENTRY("DataRO Accessed "), /* 0x11 */
2493	STRENTRY("DataRW "), /* 0x12 */
2494	STRENTRY("DataRW Accessed "), /* 0x13 */
2495	STRENTRY("DataDownRO "), /* 0x14 */
2496	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2497	STRENTRY("DataDownRW "), /* 0x16 */
2498	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2499	STRENTRY("CodeEO "), /* 0x18 */
2500	STRENTRY("CodeEO Accessed "), /* 0x19 */
2501	STRENTRY("CodeER "), /* 0x1a */
2502	STRENTRY("CodeER Accessed "), /* 0x1b */
2503	STRENTRY("CodeConfEO "), /* 0x1c */
2504	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2505	STRENTRY("CodeConfER "), /* 0x1e */
2506	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2507	#undef SYSENTRY
2508	};
2509	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2510	char szMsg[128];
2511	char *psz = &szMsg[0];
2512	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2513	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2514	psz += aTypes[i].cch;
2515
2516	if (Desc.Gen.u1Present)
2517	ADD_STR(psz, "Present ");
2518	else
2519	ADD_STR(psz, "Not-Present ");
2520	if (Desc.Gen.u1Granularity)
2521	ADD_STR(psz, "Page ");
2522	if (Desc.Gen.u1DefBig)
2523	ADD_STR(psz, "32-bit ");
2524	else
2525	ADD_STR(psz, "16-bit ");
2526	#undef ADD_STR
2527	*psz = '\0';
2528
2529	/*
2530	* Limit and Base and format the output.
2531	*/
2532	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2533	uint32_t u32Base = X86DESC_BASE(&Desc);
2534
2535	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2536	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2537	}
2538
2539
2540	/**
2541	* Dumps a descriptor.
2542	*
2543	* @param Desc Descriptor to dump.
2544	* @param Sel Selector number.
2545	* @param pszMsg Message to prepend the log entry with.
2546	*/
2547	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2548	{
2549	char szOutput[128];
2550	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2551	Log(("%s: %s\n", pszMsg, szOutput));
2552	NOREF(szOutput[0]);
2553	}
2554
2555
2556	/**
2557	* Display the shadow gdt.
2558	*
2559	* @param pVM Pointer to the VM.
2560	* @param pHlp The info helpers.
2561	* @param pszArgs Arguments, ignored.
2562	*/
2563	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2564	{
2565	NOREF(pszArgs);
2566	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2567	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2568	{
2569	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2570	{
2571	char szOutput[128];
2572	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2573	const char *psz = "";
2574	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2575	psz = " HyperCS";
2576	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2577	psz = " HyperDS";
2578	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2579	psz = " HyperCS64";
2580	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2581	psz = " HyperTSS";
2582	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2583	psz = " HyperTSSTrap08";
2584	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2585	}
2586	}
2587	}
2588
2589
2590	/**
2591	* Display the guest gdt.
2592	*
2593	* @param pVM Pointer to the VM.
2594	* @param pHlp The info helpers.
2595	* @param pszArgs Arguments, ignored.
2596	*/
2597	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2598	{
2599	/** @todo SMP support! */
2600	PVMCPU pVCpu = &pVM->aCpus[0];
2601
2602	VBOXGDTR GDTR;
2603	CPUMGetGuestGDTR(pVCpu, &GDTR);
2604	RTGCPTR GCPtrGDT = GDTR.pGdt;
2605	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2606
2607	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2608	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2609	{
2610	X86DESC GDTE;
2611	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2612	if (RT_SUCCESS(rc))
2613	{
2614	if (GDTE.Gen.u1Present)
2615	{
2616	char szOutput[128];
2617	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2618	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2619	}
2620	}
2621	else if (rc == VERR_PAGE_NOT_PRESENT)
2622	{
2623	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2624	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2625	}
2626	else
2627	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2628	}
2629	NOREF(pszArgs);
2630	}
2631
2632
2633	/**
2634	* Display the shadow ldt.
2635	*
2636	* @param pVM Pointer to the VM.
2637	* @param pHlp The info helpers.
2638	* @param pszArgs Arguments, ignored.
2639	*/
2640	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2641	{
2642	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2643	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2644	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2645	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2646	{
2647	if (paLDT[iLDT].Gen.u1Present)
2648	{
2649	char szOutput[128];
2650	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2651	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2652	}
2653	}
2654	NOREF(pszArgs);
2655	}
2656
2657
2658	/**
2659	* Display the guest ldt.
2660	*
2661	* @param pVM Pointer to the VM.
2662	* @param pHlp The info helpers.
2663	* @param pszArgs Arguments, ignored.
2664	*/
2665	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2666	{
2667	/** @todo SMP support! */
2668	PVMCPU pVCpu = &pVM->aCpus[0];
2669
2670	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2671	if (!(SelLdt & X86_SEL_MASK))
2672	{
2673	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2674	return;
2675	}
2676
2677	RTGCPTR GCPtrLdt;
2678	unsigned cbLdt;
2679	int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
2680	if (RT_FAILURE(rc))
2681	{
2682	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
2683	return;
2684	}
2685
2686	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2687	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2688	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2689	{
2690	X86DESC LdtE;
2691	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2692	if (RT_SUCCESS(rc))
2693	{
2694	if (LdtE.Gen.u1Present)
2695	{
2696	char szOutput[128];
2697	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2698	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2699	}
2700	}
2701	else if (rc == VERR_PAGE_NOT_PRESENT)
2702	{
2703	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2704	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2705	}
2706	else
2707	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2708	}
2709	NOREF(pszArgs);
2710	}
2711
2712
2713	/**
2714	* Dumps the hypervisor GDT
2715	*
2716	* @param pVM Pointer to the VM.
2717	*/
2718	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2719	{
2720	DBGFR3Info(pVM, "gdt", NULL, NULL);
2721	}
2722
2723
2724	/**
2725	* Dumps the hypervisor LDT
2726	*
2727	* @param pVM Pointer to the VM.
2728	*/
2729	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2730	{
2731	DBGFR3Info(pVM, "ldt", NULL, NULL);
2732	}
2733
2734
2735	/**
2736	* Dumps the guest GDT
2737	*
2738	* @param pVM Pointer to the VM.
2739	*/
2740	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2741	{
2742	DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2743	}
2744
2745
2746	/**
2747	* Dumps the guest LDT
2748	*
2749	* @param pVM Pointer to the VM.
2750	*/
2751	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2752	{
2753	DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2754	}
2755

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 42418

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