SELM.cpp@ 42640

Last change on this file since 42640 was 42427, checked in by vboxsync, 12 years ago
VMM: Fixed some selector arithmetic, introducing a new constand and renaming and old one to make things clearer. Also added CPUMGetGuestLdtrEx and make some (but not all) of SELM use this instead of shadow GDT.
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File size: 102.6 KB

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1	/* $Id: SELM.cpp 42427 2012-07-26 23:48:01Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/mm.h>
66	#include <VBox/vmm/ssm.h>
67	#include <VBox/vmm/pgm.h>
68	#include <VBox/vmm/trpm.h>
69	#include <VBox/vmm/dbgf.h>
70	#include "SELMInternal.h"
71	#include <VBox/vmm/vm.h>
72	#include <VBox/err.h>
73	#include <VBox/param.h>
74
75	#include <iprt/assert.h>
76	#include <VBox/log.h>
77	#include <iprt/asm.h>
78	#include <iprt/string.h>
79	#include <iprt/thread.h>
80	#include <iprt/string.h>
81
82
83	/**
84	* Enable or disable tracking of Shadow GDT/LDT/TSS.
85	* @{
86	*/
87	#define SELM_TRACK_SHADOW_GDT_CHANGES
88	#define SELM_TRACK_SHADOW_LDT_CHANGES
89	#define SELM_TRACK_SHADOW_TSS_CHANGES
90	/** @} */
91
92
93	/** SELM saved state version. */
94	#define SELM_SAVED_STATE_VERSION 5
95
96
97	/*******************************************************************************
98	* Internal Functions *
99	*******************************************************************************/
100	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
101	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
104	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
105	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
106	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112
113
114	/*******************************************************************************
115	* Global Variables *
116	*******************************************************************************/
117	#ifdef LOG_ENABLED
118	/** Segment register names. */
119	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
120	#endif
121
122
123	/**
124	* Initializes the SELM.
125	*
126	* @returns VBox status code.
127	* @param pVM Pointer to the VM.
128	*/
129	VMMR3DECL(int) SELMR3Init(PVM pVM)
130	{
131	LogFlow(("SELMR3Init\n"));
132
133	/*
134	* Assert alignment and sizes.
135	* (The TSS block requires contiguous back.)
136	*/
137	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
138	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
139	#if 0 /* doesn't work */
140	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
141	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
142	#endif
143	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
144	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
145	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
146
147	/*
148	* Init the structure.
149	*/
150	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
151	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
152	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
153	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
154	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
155	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
156
157	/*
158	* Allocate GDT table.
159	*/
160	int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
161	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
162	AssertRCReturn(rc, rc);
163
164	/*
165	* Allocate LDT area.
166	*/
167	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
168	AssertRCReturn(rc, rc);
169
170	/*
171	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
172	*/
173	pVM->selm.s.cbEffGuestGdtLimit = 0;
174	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
175	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
176	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
177
178	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
179	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
180	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
181	pVM->selm.s.GCSelTss = RTSEL_MAX;
182
183	pVM->selm.s.fDisableMonitoring = false;
184	pVM->selm.s.fSyncTSSRing0Stack = false;
185
186	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
187	* for I/O operations. */
188	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
189	/* bit set to 1 means no redirection */
190	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
191
192	/*
193	* Register the saved state data unit.
194	*/
195	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
196	NULL, NULL, NULL,
197	NULL, selmR3Save, NULL,
198	NULL, selmR3Load, selmR3LoadDone);
199	if (RT_FAILURE(rc))
200	return rc;
201
202	/*
203	* Statistics.
204	*/
205	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
206	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
207	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
208	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
209	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
210	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
211	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
212	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
213	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
214
215	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
216	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
217
218	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
219	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
220	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
221	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
222	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
223	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
224
225	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
226	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
227	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
228	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
229	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
230	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
231
232	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
233
234	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
235	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
236	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
237	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
238	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
239	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
240
241	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
242	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
243	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
244	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
245
246	/*
247	* Default action when entering raw mode for the first time
248	*/
249	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
250	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
251	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
252	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
253
254	/*
255	* Register info handlers.
256	*/
257	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
258	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
259	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
260	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
261	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
262	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
263
264	return rc;
265	}
266
267
268	/**
269	* Finalizes HMA page attributes.
270	*
271	* @returns VBox status code.
272	* @param pVM Pointer to the VM.
273	*/
274	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
275	{
276	/** @cfgm{/DoubleFault,bool,false}
277	* Enables catching of double faults in the raw-mode context VMM code. This can
278	* be used when the triple faults or hangs occur and one suspect an unhandled
279	* double fault. This is not enabled by default because it means making the
280	* hyper selectors writeable for all supervisor code, including the guest's.
281	* The double fault is a task switch and thus requires write access to the GDT
282	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
283	* 8 TSS for the back link.
284	*/
285	bool f;
286	#if defined(DEBUG_bird)
287	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
288	#else
289	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
290	#endif
291	AssertLogRelRCReturn(rc, rc);
292	if (f)
293	{
294	PX86DESC paGdt = pVM->selm.s.paGdtR3;
295	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
296	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
297	AssertRC(rc);
298	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
299	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
300	AssertRC(rc);
301	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
302	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
303	AssertRC(rc);
304	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
305	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
306	AssertRC(rc);
307	}
308	return VINF_SUCCESS;
309	}
310
311
312	/**
313	* Setup the hypervisor GDT selectors in our shadow table
314	*
315	* @param pVM Pointer to the VM.
316	*/
317	static void selmR3SetupHyperGDTSelectors(PVM pVM)
318	{
319	PX86DESC paGdt = pVM->selm.s.paGdtR3;
320
321	/*
322	* Set up global code and data descriptors for use in the guest context.
323	* Both are wide open (base 0, limit 4GB)
324	*/
325	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
326	pDesc->Gen.u16LimitLow = 0xffff;
327	pDesc->Gen.u4LimitHigh = 0xf;
328	pDesc->Gen.u16BaseLow = 0;
329	pDesc->Gen.u8BaseHigh1 = 0;
330	pDesc->Gen.u8BaseHigh2 = 0;
331	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
332	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
333	pDesc->Gen.u2Dpl = 0; /* supervisor */
334	pDesc->Gen.u1Present = 1;
335	pDesc->Gen.u1Available = 0;
336	pDesc->Gen.u1Long = 0;
337	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
338	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
339
340	/* data */
341	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
342	pDesc->Gen.u16LimitLow = 0xffff;
343	pDesc->Gen.u4LimitHigh = 0xf;
344	pDesc->Gen.u16BaseLow = 0;
345	pDesc->Gen.u8BaseHigh1 = 0;
346	pDesc->Gen.u8BaseHigh2 = 0;
347	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
348	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
349	pDesc->Gen.u2Dpl = 0; /* supervisor */
350	pDesc->Gen.u1Present = 1;
351	pDesc->Gen.u1Available = 0;
352	pDesc->Gen.u1Long = 0;
353	pDesc->Gen.u1DefBig = 1; /* big */
354	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
355
356	/* 64-bit mode code (& data?) */
357	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
358	pDesc->Gen.u16LimitLow = 0xffff;
359	pDesc->Gen.u4LimitHigh = 0xf;
360	pDesc->Gen.u16BaseLow = 0;
361	pDesc->Gen.u8BaseHigh1 = 0;
362	pDesc->Gen.u8BaseHigh2 = 0;
363	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
364	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
365	pDesc->Gen.u2Dpl = 0; /* supervisor */
366	pDesc->Gen.u1Present = 1;
367	pDesc->Gen.u1Available = 0;
368	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
369	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
370	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
371
372	/*
373	* TSS descriptor
374	*/
375	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
376	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
377	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
378	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
379	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
380	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
381	pDesc->Gen.u4LimitHigh = 0;
382	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
383	pDesc->Gen.u1DescType = 0; /* system */
384	pDesc->Gen.u2Dpl = 0; /* supervisor */
385	pDesc->Gen.u1Present = 1;
386	pDesc->Gen.u1Available = 0;
387	pDesc->Gen.u1Long = 0;
388	pDesc->Gen.u1DefBig = 0;
389	pDesc->Gen.u1Granularity = 0; /* byte limit */
390
391	/*
392	* TSS descriptor for trap 08
393	*/
394	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
395	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
396	pDesc->Gen.u4LimitHigh = 0;
397	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
398	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
399	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
400	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
401	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
402	pDesc->Gen.u1DescType = 0; /* system */
403	pDesc->Gen.u2Dpl = 0; /* supervisor */
404	pDesc->Gen.u1Present = 1;
405	pDesc->Gen.u1Available = 0;
406	pDesc->Gen.u1Long = 0;
407	pDesc->Gen.u1DefBig = 0;
408	pDesc->Gen.u1Granularity = 0; /* byte limit */
409	}
410
411	/**
412	* Applies relocations to data and code managed by this
413	* component. This function will be called at init and
414	* whenever the VMM need to relocate it self inside the GC.
415	*
416	* @param pVM The VM.
417	*/
418	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
419	{
420	PX86DESC paGdt = pVM->selm.s.paGdtR3;
421	LogFlow(("SELMR3Relocate\n"));
422
423	for (VMCPUID i = 0; i < pVM->cCpus; i++)
424	{
425	PVMCPU pVCpu = &pVM->aCpus[i];
426
427	/*
428	* Update GDTR and selector.
429	*/
430	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
431
432	/** @todo selector relocations should be a separate operation? */
433	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
434	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
435	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
436	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
437	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
438	}
439
440	selmR3SetupHyperGDTSelectors(pVM);
441
442	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
443	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
444	/*
445	* Update the TSSes.
446	*/
447	/* Only applies to raw mode which supports only 1 VCPU */
448	PVMCPU pVCpu = &pVM->aCpus[0];
449
450	/* Current TSS */
451	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
452	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
453	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
454	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
455	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
456	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
457	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
458
459	/* trap 08 */
460	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
461	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
462	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
463	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
464	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
465	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
466	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
467	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
468	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
469	pVM->selm.s.TssTrap08.fs = 0;
470	pVM->selm.s.TssTrap08.gs = 0;
471	pVM->selm.s.TssTrap08.selLdt = 0;
472	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
473	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
474	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
475	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
476	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
477	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
478	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
479	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
480	/* TRPM will be updating the eip */
481
482	if ( !pVM->selm.s.fDisableMonitoring
483	&& !VMMIsHwVirtExtForced(pVM))
484	{
485	/*
486	* Update shadow GDT/LDT/TSS write access handlers.
487	*/
488	int rc;
489	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
490	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
491	{
492	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
493	AssertRC(rc);
494	}
495	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
496	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
497	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
498	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
499	AssertRC(rc);
500	#endif
501	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
502	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
503	{
504	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
505	AssertRC(rc);
506	}
507	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
508	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
509	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
510	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
511	AssertRC(rc);
512	#endif
513
514	/*
515	* Update the GC LDT region handler and address.
516	*/
517	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
518	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
519	{
520	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
521	AssertRC(rc);
522	}
523	#endif
524	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
525	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
526	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
527	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
528	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
529	AssertRC(rc);
530	#endif
531	}
532	}
533
534
535	/**
536	* Terminates the SELM.
537	*
538	* Termination means cleaning up and freeing all resources,
539	* the VM it self is at this point powered off or suspended.
540	*
541	* @returns VBox status code.
542	* @param pVM Pointer to the VM.
543	*/
544	VMMR3DECL(int) SELMR3Term(PVM pVM)
545	{
546	NOREF(pVM);
547	return 0;
548	}
549
550
551	/**
552	* The VM is being reset.
553	*
554	* For the SELM component this means that any GDT/LDT/TSS monitors
555	* needs to be removed.
556	*
557	* @param pVM Pointer to the VM.
558	*/
559	VMMR3DECL(void) SELMR3Reset(PVM pVM)
560	{
561	LogFlow(("SELMR3Reset:\n"));
562	VM_ASSERT_EMT(pVM);
563
564	/*
565	* Uninstall guest GDT/LDT/TSS write access handlers.
566	*/
567	int rc;
568	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
569	{
570	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
571	AssertRC(rc);
572	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
573	pVM->selm.s.GuestGdtr.cbGdt = 0;
574	}
575	pVM->selm.s.fGDTRangeRegistered = false;
576	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
577	{
578	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
579	AssertRC(rc);
580	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
581	}
582	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
583	{
584	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
585	AssertRC(rc);
586	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
587	pVM->selm.s.GCSelTss = RTSEL_MAX;
588	}
589
590	/*
591	* Re-initialize other members.
592	*/
593	pVM->selm.s.cbLdtLimit = 0;
594	pVM->selm.s.offLdtHyper = 0;
595	pVM->selm.s.cbMonitoredGuestTss = 0;
596
597	pVM->selm.s.fSyncTSSRing0Stack = false;
598
599	/*
600	* Default action when entering raw mode for the first time
601	*/
602	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
603	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
605	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
606	}
607
608	/**
609	* Disable GDT/LDT/TSS monitoring and syncing
610	*
611	* @param pVM Pointer to the VM.
612	*/
613	VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
614	{
615	/*
616	* Uninstall guest GDT/LDT/TSS write access handlers.
617	*/
618	int rc;
619	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
620	{
621	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
622	AssertRC(rc);
623	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
624	pVM->selm.s.GuestGdtr.cbGdt = 0;
625	}
626	pVM->selm.s.fGDTRangeRegistered = false;
627	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
628	{
629	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
630	AssertRC(rc);
631	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
632	}
633	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
634	{
635	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
636	AssertRC(rc);
637	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
638	pVM->selm.s.GCSelTss = RTSEL_MAX;
639	}
640
641	/*
642	* Unregister shadow GDT/LDT/TSS write access handlers.
643	*/
644	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
645	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
646	{
647	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
648	AssertRC(rc);
649	pVM->selm.s.paGdtRC = NIL_RTRCPTR;
650	}
651	#endif
652	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
653	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
654	{
655	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
656	AssertRC(rc);
657	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
658	}
659	#endif
660	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
661	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
662	{
663	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
664	AssertRC(rc);
665	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
666	}
667	#endif
668
669	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
670	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
671	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
672	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
673
674	pVM->selm.s.fDisableMonitoring = true;
675	}
676
677
678	/**
679	* Execute state save operation.
680	*
681	* @returns VBox status code.
682	* @param pVM Pointer to the VM.
683	* @param pSSM SSM operation handle.
684	*/
685	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
686	{
687	LogFlow(("selmR3Save:\n"));
688
689	/*
690	* Save the basic bits - fortunately all the other things can be resynced on load.
691	*/
692	PSELM pSelm = &pVM->selm.s;
693
694	SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
695	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
696	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
697	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
698	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
699	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
700	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
701	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
702	}
703
704
705	/**
706	* Execute state load operation.
707	*
708	* @returns VBox status code.
709	* @param pVM Pointer to the VM.
710	* @param pSSM SSM operation handle.
711	* @param uVersion Data layout version.
712	* @param uPass The data pass.
713	*/
714	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
715	{
716	LogFlow(("selmR3Load:\n"));
717	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
718
719	/*
720	* Validate version.
721	*/
722	if (uVersion != SELM_SAVED_STATE_VERSION)
723	{
724	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
725	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
726	}
727
728	/*
729	* Do a reset.
730	*/
731	SELMR3Reset(pVM);
732
733	/* Get the monitoring flag. */
734	SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
735
736	/* Get the TSS state flag. */
737	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
738
739	/*
740	* Get the selectors.
741	*/
742	RTSEL SelCS;
743	SSMR3GetSel(pSSM, &SelCS);
744	RTSEL SelDS;
745	SSMR3GetSel(pSSM, &SelDS);
746	RTSEL SelCS64;
747	SSMR3GetSel(pSSM, &SelCS64);
748	RTSEL SelDS64;
749	SSMR3GetSel(pSSM, &SelDS64);
750	RTSEL SelTSS;
751	SSMR3GetSel(pSSM, &SelTSS);
752	RTSEL SelTSSTrap08;
753	SSMR3GetSel(pSSM, &SelTSSTrap08);
754
755	/* Copy the selectors; they will be checked during relocation. */
756	PSELM pSelm = &pVM->selm.s;
757	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
758	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
759	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
760	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
761	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
762
763	return VINF_SUCCESS;
764	}
765
766
767	/**
768	* Sync the GDT, LDT and TSS after loading the state.
769	*
770	* Just to play save, we set the FFs to force syncing before
771	* executing GC code.
772	*
773	* @returns VBox status code.
774	* @param pVM Pointer to the VM.
775	* @param pSSM SSM operation handle.
776	*/
777	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
778	{
779	PVMCPU pVCpu = VMMGetCpu(pVM);
780
781	LogFlow(("selmR3LoadDone:\n"));
782
783	/*
784	* Don't do anything if it's a load failure.
785	*/
786	int rc = SSMR3HandleGetStatus(pSSM);
787	if (RT_FAILURE(rc))
788	return VINF_SUCCESS;
789
790	/*
791	* Do the syncing if we're in protected mode.
792	*/
793	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
794	{
795	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
796	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
797	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
798	SELMR3UpdateFromCPUM(pVM, pVCpu);
799	}
800
801	/*
802	* Flag everything for resync on next raw mode entry.
803	*/
804	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
805	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
806	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
807
808	return VINF_SUCCESS;
809	}
810
811
812	/**
813	* Updates (syncs) the shadow GDT.
814	*
815	* @returns VBox status code.
816	* @param pVM The VM handle.
817	* @param pVCpu The current virtual CPU.
818	*/
819	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
820	{
821	/*
822	* Always assume the best...
823	*/
824	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
825
826	/* If the GDT was changed, then make sure the LDT is checked too */
827	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
828	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
829	/* Same goes for the TSS selector */
830	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
831
832	/*
833	* Get the GDTR and check if there is anything to do (there usually is).
834	*/
835	VBOXGDTR GDTR;
836	CPUMGetGuestGDTR(pVCpu, &GDTR);
837	if (GDTR.cbGdt < sizeof(X86DESC))
838	{
839	Log(("No GDT entries...\n"));
840	return VINF_SUCCESS;
841	}
842
843	/*
844	* Read the Guest GDT.
845	* ASSUMES that the entire GDT is in memory.
846	*/
847	RTUINT cbEffLimit = GDTR.cbGdt;
848	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
849	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
850	if (RT_FAILURE(rc))
851	{
852	/*
853	* Read it page by page.
854	*
855	* Keep track of the last valid page and delay memsets and
856	* adjust cbEffLimit to reflect the effective size. The latter
857	* is something we do in the belief that the guest will probably
858	* never actually commit the last page, thus allowing us to keep
859	* our selectors in the high end of the GDT.
860	*/
861	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
862	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
863	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
864	uint8_t *pu8DstInvalid = pu8Dst;
865
866	while (cbLeft)
867	{
868	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
869	cb = RT_MIN(cb, cbLeft);
870	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
871	if (RT_SUCCESS(rc))
872	{
873	if (pu8DstInvalid != pu8Dst)
874	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
875	GCPtrSrc += cb;
876	pu8Dst += cb;
877	pu8DstInvalid = pu8Dst;
878	}
879	else if ( rc == VERR_PAGE_NOT_PRESENT
880	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
881	{
882	GCPtrSrc += cb;
883	pu8Dst += cb;
884	}
885	else
886	{
887	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
888	return VERR_SELM_GDT_READ_ERROR;
889	}
890	cbLeft -= cb;
891	}
892
893	/* any invalid pages at the end? */
894	if (pu8DstInvalid != pu8Dst)
895	{
896	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
897	/* If any GDTEs was invalidated, zero them. */
898	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
899	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
900	}
901
902	/* keep track of the effective limit. */
903	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
904	{
905	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
906	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
907	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
908	}
909	}
910
911	/*
912	* Check if the Guest GDT intrudes on our GDT entries.
913	*/
914	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
915	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
916	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
917	{
918	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
919	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
920	int iGDT = 0;
921
922	Log(("Internal SELM GDT conflict: use non-present entries\n"));
923	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
924	while (pGDTECur > pGDTEStart)
925	{
926	/* We can reuse non-present entries */
927	if (!pGDTECur->Gen.u1Present)
928	{
929	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
930	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
931	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
932	iGDT++;
933	if (iGDT >= SELM_HYPER_SEL_MAX)
934	break;
935	}
936
937	pGDTECur--;
938	}
939	if (iGDT != SELM_HYPER_SEL_MAX)
940	{
941	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
942	return VERR_SELM_GDT_TOO_FULL;
943	}
944	}
945	else
946	{
947	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
948	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
949	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
950	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
951	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
952	}
953
954	/*
955	* Work thru the copied GDT entries adjusting them for correct virtualization.
956	*/
957	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
958	while (pGDTE < pGDTEEnd)
959	{
960	if (pGDTE->Gen.u1Present)
961	selmGuestToShadowDesc(pGDTE);
962
963	/* Next GDT entry. */
964	pGDTE++;
965	}
966
967	/*
968	* Check if our hypervisor selectors were changed.
969	*/
970	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
971	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
972	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
973	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
974	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
975	{
976	/* Reinitialize our hypervisor GDTs */
977	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
978	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
979	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
980	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
981	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
982
983	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
984
985	/*
986	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
987	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
988	*/
989	VMR3Relocate(pVM, 0);
990	}
991	else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
992	/* We overwrote all entries above, so we have to save them again. */
993	selmR3SetupHyperGDTSelectors(pVM);
994
995	/*
996	* Adjust the cached GDT limit.
997	* Any GDT entries which have been removed must be cleared.
998	*/
999	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1000	{
1001	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1002	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1003	}
1004
1005	/*
1006	* Check if Guest's GDTR is changed.
1007	*/
1008	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1009	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1010	{
1011	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1012
1013	/*
1014	* [Re]Register write virtual handler for guest's GDT.
1015	*/
1016	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1017	{
1018	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1019	AssertRC(rc);
1020	}
1021
1022	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1023	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1024	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1025	"Guest GDT write access handler");
1026	if (RT_FAILURE(rc))
1027	return rc;
1028
1029	/* Update saved Guest GDTR. */
1030	pVM->selm.s.GuestGdtr = GDTR;
1031	pVM->selm.s.fGDTRangeRegistered = true;
1032	}
1033
1034	return VINF_SUCCESS;
1035	}
1036
1037
1038	/**
1039	* Updates (syncs) the shadow LDT.
1040	*
1041	* @returns VBox status code.
1042	* @param pVM The VM handle.
1043	* @param pVCpu The current virtual CPU.
1044	*/
1045	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1046	{
1047	int rc = VINF_SUCCESS;
1048
1049	/*
1050	* Always assume the best...
1051	*/
1052	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1053
1054	/*
1055	* LDT handling is done similarly to the GDT handling with a shadow
1056	* array. However, since the LDT is expected to be swappable (at least
1057	* some ancient OSes makes it swappable) it must be floating and
1058	* synced on a per-page basis.
1059	*
1060	* Eventually we will change this to be fully on demand. Meaning that
1061	* we will only sync pages containing LDT selectors actually used and
1062	* let the #PF handler lazily sync pages as they are used.
1063	* (This applies to GDT too, when we start making OS/2 fast.)
1064	*/
1065
1066	/*
1067	* First, determine the current LDT selector.
1068	*/
1069	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1070	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1071	{
1072	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1073	CPUMSetHyperLDTR(pVCpu, 0);
1074	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1075	{
1076	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1077	AssertRC(rc);
1078	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1079	}
1080	pVM->selm.s.cbLdtLimit = 0;
1081	return VINF_SUCCESS;
1082	}
1083
1084	/*
1085	* Get the LDT selector.
1086	*/
1087	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1088	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1089	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1090	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1091
1092	/*
1093	* Validate it.
1094	*/
1095	if ( !cbLdt
1096	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1097	\|\| pDesc->Gen.u1DescType
1098	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1099	{
1100	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1101
1102	/* cbLdt > 0:
1103	* This is quite impossible, so we do as most people do when faced with
1104	* the impossible, we simply ignore it.
1105	*/
1106	CPUMSetHyperLDTR(pVCpu, 0);
1107	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1108	{
1109	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1110	AssertRC(rc);
1111	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1112	}
1113	return VINF_SUCCESS;
1114	}
1115	/** @todo check what intel does about odd limits. */
1116	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1117
1118	/*
1119	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1120	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1121	*/
1122	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1123	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1124
1125
1126	/** @todo Handle only present LDT segments. */
1127	// if (pDesc->Gen.u1Present)
1128	{
1129	/*
1130	* Check if Guest's LDT address/limit is changed.
1131	*/
1132	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1133	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1134	{
1135	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1136	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1137
1138	/*
1139	* [Re]Register write virtual handler for guest's GDT.
1140	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1141	*/
1142	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1143	{
1144	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1145	AssertRC(rc);
1146	}
1147	#ifdef DEBUG
1148	if (pDesc->Gen.u1Present)
1149	Log(("LDT selector marked not present!!\n"));
1150	#endif
1151	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1152	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1153	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1154	{
1155	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1156	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1157	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1158	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1159	}
1160	else if (RT_SUCCESS(rc))
1161	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1162	else
1163	{
1164	CPUMSetHyperLDTR(pVCpu, 0);
1165	return rc;
1166	}
1167
1168	pVM->selm.s.cbLdtLimit = cbLdt;
1169	}
1170	}
1171
1172	/*
1173	* Calc Shadow LDT base.
1174	*/
1175	unsigned off;
1176	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1177	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1178	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1179
1180	/*
1181	* Enable the LDT selector in the shadow GDT.
1182	*/
1183	pDesc->Gen.u1Present = 1;
1184	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1185	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1186	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1187	pDesc->Gen.u1Available = 0;
1188	pDesc->Gen.u1Long = 0;
1189	if (cbLdt > 0xffff)
1190	{
1191	cbLdt = 0xffff;
1192	pDesc->Gen.u4LimitHigh = 0;
1193	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1194	}
1195
1196	/*
1197	* Set Hyper LDTR and notify TRPM.
1198	*/
1199	CPUMSetHyperLDTR(pVCpu, SelLdt);
1200
1201	/*
1202	* Loop synchronising the LDT page by page.
1203	*/
1204	/** @todo investigate how intel handle various operations on half present cross page entries. */
1205	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1206	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1207
1208	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1209	unsigned cbLeft = cbLdt + 1;
1210	PX86DESC pLDTE = pShadowLDT;
1211	while (cbLeft)
1212	{
1213	/*
1214	* Read a chunk.
1215	*/
1216	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1217	if (cbChunk > cbLeft)
1218	cbChunk = cbLeft;
1219	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1220	if (RT_SUCCESS(rc))
1221	{
1222	/*
1223	* Mark page
1224	*/
1225	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1226	AssertRC(rc);
1227
1228	/*
1229	* Loop thru the available LDT entries.
1230	* Figure out where to start and end and the potential cross pageness of
1231	* things adds a little complexity. pLDTE is updated there and not in the
1232	* 'next' part of the loop. The pLDTEEnd is inclusive.
1233	*/
1234	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1235	if (pLDTE + 1 < pShadowLDT)
1236	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1237	while (pLDTE <= pLDTEEnd)
1238	{
1239	if (pLDTE->Gen.u1Present)
1240	selmGuestToShadowDesc(pLDTE);
1241
1242	/* Next LDT entry. */
1243	pLDTE++;
1244	}
1245	}
1246	else
1247	{
1248	RT_BZERO(pShadowLDT, cbChunk);
1249	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1250	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1251	AssertRC(rc);
1252	}
1253
1254	/*
1255	* Advance to the next page.
1256	*/
1257	cbLeft -= cbChunk;
1258	GCPtrShadowLDT += cbChunk;
1259	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1260	GCPtrLdt += cbChunk;
1261	}
1262
1263	return VINF_SUCCESS;
1264	}
1265
1266
1267	/**
1268	* Checks and updates segment selector registers.
1269	*
1270	* @returns VBox strict status code.
1271	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1272	*
1273	* @param pVM The VM handle.
1274	* @param pVCpu The current virtual CPU.
1275	*/
1276	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1277	{
1278	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1279
1280	/*
1281	* No stale selectors in V8086 mode.
1282	*/
1283	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1284	if (pCtx->eflags.Bits.u1VM)
1285	return VINF_SUCCESS;
1286
1287	/*
1288	* Check for stale selectors and load hidden register bits where they
1289	* are missing.
1290	*/
1291	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1292	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1293	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1294	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1295	{
1296	RTSEL const Sel = paSReg[iSReg].Sel;
1297	if (Sel & X86_SEL_MASK_OFF_RPL)
1298	{
1299	/* Get the shadow descriptor entry corresponding to this. */
1300	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1301	PCX86DESC pDesc;
1302	if (!(Sel & X86_SEL_LDT))
1303	{
1304	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1305	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1306	else
1307	pDesc = &s_NotPresentDesc;
1308	}
1309	else
1310	{
1311	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1312	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1313	else
1314	pDesc = &s_NotPresentDesc;
1315	}
1316
1317	/* Check the segment register. */
1318	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1319	{
1320	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1321	{
1322	/* Did it go stale? */
1323	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1324	{
1325	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1326	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1327	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1328	rcStrict = VINF_EM_RESCHEDULE_REM;
1329	}
1330	}
1331	else
1332	{
1333	/* Did it stop being stale? I.e. did the guest change it things
1334	back to the way they were? */
1335	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1336	{
1337	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1338	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1339	}
1340	else
1341	{
1342	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1343	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1344	rcStrict = VINF_EM_RESCHEDULE_REM;
1345	}
1346	}
1347	}
1348	/* Load the hidden registers if it's a valid descriptor for the
1349	current segment register. */
1350	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1351	{
1352	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1353	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1354	}
1355	/* It's stale. */
1356	else
1357	{
1358	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1359	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1360	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1361	rcStrict = VINF_EM_RESCHEDULE_REM;
1362	}
1363	}
1364	/* else: 0 selector, ignore. */
1365	}
1366
1367	return rcStrict;
1368	}
1369
1370
1371	/**
1372	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1373	*
1374	* @returns VBox status code.
1375	* @param pVM Pointer to the VM.
1376	* @param pVCpu Pointer to the VMCPU.
1377	*/
1378	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1379	{
1380	if (pVM->selm.s.fDisableMonitoring)
1381	{
1382	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1383	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1384	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1385	return VINF_SUCCESS;
1386	}
1387
1388	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1389
1390	/*
1391	* GDT sync
1392	*/
1393	int rc;
1394	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1395	{
1396	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1397	if (RT_FAILURE(rc))
1398	return rc; /* We're toast, so forget the profiling. */
1399	AssertRCSuccess(rc);
1400	}
1401
1402	/*
1403	* TSS sync
1404	*/
1405	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1406	{
1407	rc = SELMR3SyncTSS(pVM, pVCpu);
1408	if (RT_FAILURE(rc))
1409	return rc;
1410	AssertRCSuccess(rc);
1411	}
1412
1413	/*
1414	* LDT sync
1415	*/
1416	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1417	{
1418	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1419	if (RT_FAILURE(rc))
1420	return rc;
1421	AssertRCSuccess(rc);
1422	}
1423
1424	/*
1425	* Check selector registers.
1426	*/
1427	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1428
1429	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1430	return rcStrict;
1431	}
1432
1433
1434	/**
1435	* \#PF Handler callback for virtual access handler ranges.
1436	*
1437	* Important to realize that a physical page in a range can have aliases, and
1438	* for ALL and WRITE handlers these will also trigger.
1439	*
1440	* @returns VINF_SUCCESS if the handler have carried out the operation.
1441	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1442	* @param pVM Pointer to the VM.
1443	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1444	* @param pvPtr The HC mapping of that address.
1445	* @param pvBuf What the guest is reading/writing.
1446	* @param cbBuf How much it's reading/writing.
1447	* @param enmAccessType The access type.
1448	* @param pvUser User argument.
1449	*/
1450	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1451	PGMACCESSTYPE enmAccessType, void *pvUser)
1452	{
1453	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1454	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1455	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1456
1457	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1458	return VINF_PGM_HANDLER_DO_DEFAULT;
1459	}
1460
1461
1462	/**
1463	* \#PF Handler callback for virtual access handler ranges.
1464	*
1465	* Important to realize that a physical page in a range can have aliases, and
1466	* for ALL and WRITE handlers these will also trigger.
1467	*
1468	* @returns VINF_SUCCESS if the handler have carried out the operation.
1469	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1470	* @param pVM Pointer to the VM.
1471	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1472	* @param pvPtr The HC mapping of that address.
1473	* @param pvBuf What the guest is reading/writing.
1474	* @param cbBuf How much it's reading/writing.
1475	* @param enmAccessType The access type.
1476	* @param pvUser User argument.
1477	*/
1478	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1479	PGMACCESSTYPE enmAccessType, void *pvUser)
1480	{
1481	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1482	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1483	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1484
1485	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1486	return VINF_PGM_HANDLER_DO_DEFAULT;
1487	}
1488
1489
1490	/**
1491	* \#PF Handler callback for virtual access handler ranges.
1492	*
1493	* Important to realize that a physical page in a range can have aliases, and
1494	* for ALL and WRITE handlers these will also trigger.
1495	*
1496	* @returns VINF_SUCCESS if the handler have carried out the operation.
1497	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1498	* @param pVM Pointer to the VM.
1499	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1500	* @param pvPtr The HC mapping of that address.
1501	* @param pvBuf What the guest is reading/writing.
1502	* @param cbBuf How much it's reading/writing.
1503	* @param enmAccessType The access type.
1504	* @param pvUser User argument.
1505	*/
1506	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1507	PGMACCESSTYPE enmAccessType, void *pvUser)
1508	{
1509	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1510	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1511	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1512
1513	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1514	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1515	* should probably also deregister the virtual handler if TR.base/size
1516	* changes while we're in REM. */
1517
1518	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1519	return VINF_PGM_HANDLER_DO_DEFAULT;
1520	}
1521
1522
1523	/**
1524	* Synchronize the shadowed fields in the TSS.
1525	*
1526	* At present we're shadowing the ring-0 stack selector & pointer, and the
1527	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1528	* REM and this function is called both if REM made any changes to the TSS or
1529	* loaded TR.
1530	*
1531	* @returns VBox status code.
1532	* @param pVM Pointer to the VM.
1533	* @param pVCpu Pointer to the VMCPU.
1534	*/
1535	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1536	{
1537	int rc;
1538
1539	if (pVM->selm.s.fDisableMonitoring)
1540	{
1541	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1542	return VINF_SUCCESS;
1543	}
1544
1545	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1546	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1547
1548	/*
1549	* Get TR and extract and store the basic info.
1550	*
1551	* Note! The TSS limit is not checked by the LTR code, so we
1552	* have to be a bit careful with it. We make sure cbTss
1553	* won't be zero if TR is valid and if it's NULL we'll
1554	* make sure cbTss is 0.
1555	*/
1556	/** @todo use the hidden bits, not shadow GDT. */
1557	CPUMSELREGHID trHid;
1558	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1559	RTGCPTR GCPtrTss = trHid.u64Base;
1560	uint32_t cbTss = trHid.u32Limit;
1561	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1562	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1563	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1564	if (SelTss & X86_SEL_MASK_OFF_RPL)
1565	{
1566	Assert(!(SelTss & X86_SEL_LDT));
1567	Assert(trHid.Attr.n.u1DescType == 0);
1568	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1569	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1570	if (!++cbTss)
1571	cbTss = UINT32_MAX;
1572	}
1573	else
1574	{
1575	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1576	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1577	cbTss = 0; /* the reset case. */
1578	}
1579	pVM->selm.s.cbGuestTss = cbTss;
1580	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1581	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1582
1583	/*
1584	* Figure out the size of what need to monitor.
1585	*/
1586	/* We're not interested in any 16-bit TSSes. */
1587	uint32_t cbMonitoredTss = cbTss;
1588	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1589	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1590	cbMonitoredTss = 0;
1591
1592	pVM->selm.s.offGuestIoBitmap = 0;
1593	bool fNoRing1Stack = true;
1594	if (cbMonitoredTss)
1595	{
1596	/*
1597	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1598	* If VME is enabled we also want to keep an eye on the interrupt
1599	* redirection bitmap.
1600	*/
1601	VBOXTSS Tss;
1602	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1603	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1604	if ( !(cr4 & X86_CR4_VME)
1605	\|\| ( RT_SUCCESS(rc)
1606	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1607	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1608	)
1609	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1610	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1611	else if (RT_SUCCESS(rc))
1612	{
1613	/*
1614	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1615	* this can be quite a large chunk. We use to skip it earlier and just hope it
1616	* was kind of static...
1617	*
1618	* Update the virtual interrupt redirection bitmap while we're here.
1619	* (It is located in the 32 bytes before TR:offIoBitmap.)
1620	*/
1621	cbMonitoredTss = Tss.offIoBitmap;
1622	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1623
1624	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1625	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1626	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1627	AssertRC(rc);
1628	/** @todo memset the bitmap on failure? */
1629	Log2(("Redirection bitmap:\n"));
1630	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1631	}
1632	else
1633	{
1634	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1635	pVM->selm.s.offGuestIoBitmap = 0;
1636	/** @todo memset the bitmap? */
1637	}
1638
1639	/*
1640	* Update the ring 0 stack selector and base address.
1641	*/
1642	if (RT_SUCCESS(rc))
1643	{
1644	#ifdef LOG_ENABLED
1645	if (LogIsEnabled())
1646	{
1647	uint32_t ssr0, espr0;
1648	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1649	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1650	{
1651	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1652	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1653	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1654	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1655	AssertMsg(ssr0 != Tss.ss0,
1656	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1657	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1658	}
1659	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1660	}
1661	#endif /* LOG_ENABLED */
1662	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1663
1664	/* Update our TSS structure for the guest's ring 1 stack */
1665	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1666	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1667	}
1668	}
1669
1670	/*
1671	* Flush the ring-1 stack and the direct syscall dispatching if we
1672	* cannot obtain SS0:ESP0.
1673	*/
1674	if (fNoRing1Stack)
1675	{
1676	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1677	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1678
1679	/** @todo handle these dependencies better! */
1680	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1681	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1682	}
1683
1684	/*
1685	* Check for monitor changes and apply them.
1686	*/
1687	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1688	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1689	{
1690	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1691	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1692
1693	/* Release the old range first. */
1694	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1695	{
1696	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1697	AssertRC(rc);
1698	}
1699
1700	/* Register the write handler if TS != 0. */
1701	if (cbMonitoredTss != 0)
1702	{
1703	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1704	0, selmR3GuestTSSWriteHandler,
1705	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1706	if (RT_FAILURE(rc))
1707	{
1708	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1709	return rc;
1710	}
1711
1712	/* Update saved Guest TSS info. */
1713	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1714	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1715	pVM->selm.s.GCSelTss = SelTss;
1716	}
1717	else
1718	{
1719	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1720	pVM->selm.s.cbMonitoredGuestTss = 0;
1721	pVM->selm.s.GCSelTss = 0;
1722	}
1723	}
1724
1725	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1726
1727	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1728	return VINF_SUCCESS;
1729	}
1730
1731
1732	/**
1733	* Compares the Guest GDT and LDT with the shadow tables.
1734	* This is a VBOX_STRICT only function.
1735	*
1736	* @returns VBox status code.
1737	* @param pVM Pointer to the VM.
1738	*/
1739	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1740	{
1741	#ifdef VBOX_STRICT
1742	PVMCPU pVCpu = VMMGetCpu(pVM);
1743
1744	/*
1745	* Get GDTR and check for conflict.
1746	*/
1747	VBOXGDTR GDTR;
1748	CPUMGetGuestGDTR(pVCpu, &GDTR);
1749	if (GDTR.cbGdt == 0)
1750	return VINF_SUCCESS;
1751
1752	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1753	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1754
1755	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1756	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1757
1758	/*
1759	* Loop thru the GDT checking each entry.
1760	*/
1761	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1762	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1763	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1764	while (pGDTE < pGDTEEnd)
1765	{
1766	X86DESC GDTEGuest;
1767	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1768	if (RT_SUCCESS(rc))
1769	{
1770	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1771	{
1772	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1773	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1774	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1775	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1776	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1777	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1778	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1779	{
1780	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1781	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1782	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1783	}
1784	}
1785	}
1786
1787	/* Advance to the next descriptor. */
1788	GCPtrGDTEGuest += sizeof(X86DESC);
1789	pGDTE++;
1790	}
1791
1792
1793	/*
1794	* LDT?
1795	*/
1796	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1797	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1798	return VINF_SUCCESS;
1799	Assert(!(SelLdt & X86_SEL_LDT));
1800	if (SelLdt > GDTR.cbGdt)
1801	{
1802	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1803	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1804	}
1805	X86DESC LDTDesc;
1806	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1807	if (RT_FAILURE(rc))
1808	{
1809	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1810	return rc;
1811	}
1812	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1813	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1814
1815	/*
1816	* Validate it.
1817	*/
1818	if (!cbLdt)
1819	return VINF_SUCCESS;
1820	/** @todo check what intel does about odd limits. */
1821	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1822	if ( LDTDesc.Gen.u1DescType
1823	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1824	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1825	{
1826	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1827	return VERR_SELM_INVALID_LDT;
1828	}
1829
1830	/*
1831	* Loop thru the LDT checking each entry.
1832	*/
1833	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1834	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1835	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1836	while (pLDTE < pLDTEEnd)
1837	{
1838	X86DESC LDTEGuest;
1839	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1840	if (RT_SUCCESS(rc))
1841	{
1842	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1843	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1844	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1845	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1846	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1847	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1848	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1849	{
1850	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1851	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1852	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1853	}
1854	}
1855
1856	/* Advance to the next descriptor. */
1857	GCPtrLDTEGuest += sizeof(X86DESC);
1858	pLDTE++;
1859	}
1860
1861	#else /* !VBOX_STRICT */
1862	NOREF(pVM);
1863	#endif /* !VBOX_STRICT */
1864
1865	return VINF_SUCCESS;
1866	}
1867
1868
1869	/**
1870	* Validates the RawR0 TSS values against the one in the Guest TSS.
1871	*
1872	* @returns true if it matches.
1873	* @returns false and assertions on mismatch..
1874	* @param pVM Pointer to the VM.
1875	*/
1876	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1877	{
1878	#ifdef VBOX_STRICT
1879	PVMCPU pVCpu = VMMGetCpu(pVM);
1880
1881	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1882	return true;
1883
1884	/*
1885	* Get TR and extract the basic info.
1886	*/
1887	CPUMSELREGHID trHid;
1888	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1889	RTGCPTR GCPtrTss = trHid.u64Base;
1890	uint32_t cbTss = trHid.u32Limit;
1891	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1892	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1893	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1894	if (SelTss & X86_SEL_MASK_OFF_RPL)
1895	{
1896	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1897	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1898	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1899	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1900	false);
1901	if (!++cbTss)
1902	cbTss = UINT32_MAX;
1903	}
1904	else
1905	{
1906	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1907	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1908	false);
1909	cbTss = 0; /* the reset case. */
1910	}
1911	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1912	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1913	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1914	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1915	false);
1916	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1917	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1918	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1919	false);
1920	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1921	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1922	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1923	false);
1924
1925
1926	/*
1927	* Figure out the size of what need to monitor.
1928	*/
1929	/* We're not interested in any 16-bit TSSes. */
1930	uint32_t cbMonitoredTss = cbTss;
1931	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1932	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1933	cbMonitoredTss = 0;
1934	if (cbMonitoredTss)
1935	{
1936	VBOXTSS Tss;
1937	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1938	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1939	AssertReturn( rc == VINF_SUCCESS
1940	/* Happens early in XP boot during page table switching. */
1941	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
1942	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1943	false);
1944	if ( !(cr4 & X86_CR4_VME)
1945	\|\| ( RT_SUCCESS(rc)
1946	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1947	&& Tss.offIoBitmap > cbTss)
1948	)
1949	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1950	else if (RT_SUCCESS(rc))
1951	{
1952	cbMonitoredTss = Tss.offIoBitmap;
1953	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1954	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1955	false);
1956
1957	/* check the bitmap */
1958	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1959	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1960	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1961	AssertRCReturn(rc, false);
1962	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1963	("offIoBitmap=%#x cbTss=%#x\n"
1964	" Guest: %.32Rhxs\n"
1965	"Shadow: %.32Rhxs\n",
1966	Tss.offIoBitmap, cbTss,
1967	&Tss.IntRedirBitmap[0],
1968	&pVM->selm.s.Tss.IntRedirBitmap[0]),
1969	false);
1970	}
1971	else
1972	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1973
1974	/*
1975	* Check SS0 and ESP0.
1976	*/
1977	if ( !pVM->selm.s.fSyncTSSRing0Stack
1978	&& RT_SUCCESS(rc))
1979	{
1980	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1981	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1982	{
1983	RTGCPHYS GCPhys;
1984	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1985	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1986	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1987	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1988	return false;
1989	}
1990	}
1991	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1992	}
1993	else
1994	{
1995	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1996	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1997	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1998	}
1999
2000
2001
2002	return true;
2003
2004	#else /* !VBOX_STRICT */
2005	NOREF(pVM);
2006	return true;
2007	#endif /* !VBOX_STRICT */
2008	}
2009
2010
2011	/**
2012	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2013	*
2014	* See SELMR3GetSelectorInfo for details.
2015	*
2016	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2017	*
2018	* @param pVCpu Pointer to the VMCPU.
2019	* @param Sel The selector to get info about.
2020	* @param pSelInfo Where to store the information.
2021	*/
2022	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2023	{
2024	/*
2025	* Read it from the guest descriptor table.
2026	*/
2027	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2028	X86DESC64 Desc;
2029	RTGCPTR GCPtrDesc;
2030	if (!(Sel & X86_SEL_LDT))
2031	{
2032	/* GDT */
2033	VBOXGDTR Gdtr;
2034	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2035	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2036	return VERR_INVALID_SELECTOR;
2037	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2038	}
2039	else
2040	{
2041	/* LDT */
2042	uint64_t GCPtrBase;
2043	uint32_t cbLimit;
2044	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2045	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2046	return VERR_INVALID_SELECTOR;
2047
2048	/* calc the descriptor location. */
2049	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2050	}
2051
2052	/* read the descriptor. */
2053	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2054	if (RT_FAILURE(rc))
2055	{
2056	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2057	if (RT_FAILURE(rc))
2058	return rc;
2059	Desc.au64[1] = 0;
2060	}
2061
2062	/*
2063	* Extract the base and limit
2064	* (We ignore the present bit here, which is probably a bit silly...)
2065	*/
2066	pSelInfo->Sel = Sel;
2067	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2068	pSelInfo->u.Raw64 = Desc;
2069	if (Desc.Gen.u1DescType)
2070	{
2071	/*
2072	* 64-bit code selectors are wide open, it's not possible to detect
2073	* 64-bit data or stack selectors without also dragging in assumptions
2074	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2075	* the selinfo user needs to deal with this in the context the info is
2076	* used unfortunately.
2077	*/
2078	if ( Desc.Gen.u1Long
2079	&& !Desc.Gen.u1DefBig
2080	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2081	{
2082	/* Note! We ignore the segment limit hacks that was added by AMD. */
2083	pSelInfo->GCPtrBase = 0;
2084	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2085	}
2086	else
2087	{
2088	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2089	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2090	}
2091	pSelInfo->SelGate = 0;
2092	}
2093	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2094	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2095	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2096	{
2097	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2098	in the AMD manual here as a simplification. */
2099	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2100	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2101	pSelInfo->SelGate = 0;
2102	}
2103	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2104	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2105	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2106	{
2107	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2108	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2109	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2110	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2111	pSelInfo->SelGate = Desc.Gate.u16Sel;
2112	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2113	}
2114	else
2115	{
2116	pSelInfo->cbLimit = 0;
2117	pSelInfo->GCPtrBase = 0;
2118	pSelInfo->SelGate = 0;
2119	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2120	}
2121	if (!Desc.Gen.u1Present)
2122	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2123
2124	return VINF_SUCCESS;
2125	}
2126
2127
2128	/**
2129	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2130	* interprets a legacy descriptor table entry and fills in the selector info
2131	* structure from it.
2132	*
2133	* @param pSelInfo Where to store the selector info. Only the fFlags and
2134	* Sel members have been initialized.
2135	* @param pDesc The legacy descriptor to parse.
2136	*/
2137	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2138	{
2139	pSelInfo->u.Raw64.au64[1] = 0;
2140	pSelInfo->u.Raw = *pDesc;
2141	if ( pDesc->Gen.u1DescType
2142	\|\| !(pDesc->Gen.u4Type & 4))
2143	{
2144	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2145	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2146	pSelInfo->SelGate = 0;
2147	}
2148	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2149	{
2150	pSelInfo->cbLimit = 0;
2151	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2152	pSelInfo->GCPtrBase = 0;
2153	else
2154	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2155	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2156	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2157	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2158	}
2159	else
2160	{
2161	pSelInfo->cbLimit = 0;
2162	pSelInfo->GCPtrBase = 0;
2163	pSelInfo->SelGate = 0;
2164	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2165	}
2166	if (!pDesc->Gen.u1Present)
2167	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2168	}
2169
2170
2171	/**
2172	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2173	*
2174	* See SELMR3GetSelectorInfo for details.
2175	*
2176	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2177	*
2178	* @param pVM Pointer to the VM.
2179	* @param pVCpu Pointer to the VMCPU.
2180	* @param Sel The selector to get info about.
2181	* @param pSelInfo Where to store the information.
2182	*/
2183	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2184	{
2185	/*
2186	* Read the descriptor entry
2187	*/
2188	pSelInfo->fFlags = 0;
2189	X86DESC Desc;
2190	if ( !(Sel & X86_SEL_LDT)
2191	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2192	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2193	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2194	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2195	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2196	)
2197	{
2198	/*
2199	* Hypervisor descriptor.
2200	*/
2201	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2202	if (CPUMIsGuestInProtectedMode(pVCpu))
2203	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2204	else
2205	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2206
2207	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2208	}
2209	else if (CPUMIsGuestInProtectedMode(pVCpu))
2210	{
2211	/*
2212	* Read it from the guest descriptor table.
2213	*/
2214	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2215
2216	RTGCPTR GCPtrDesc;
2217	if (!(Sel & X86_SEL_LDT))
2218	{
2219	/* GDT */
2220	VBOXGDTR Gdtr;
2221	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2222	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2223	return VERR_INVALID_SELECTOR;
2224	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2225	}
2226	else
2227	{
2228	/* LDT */
2229	uint64_t GCPtrBase;
2230	uint32_t cbLimit;
2231	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2232	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2233	return VERR_INVALID_SELECTOR;
2234
2235	/* calc the descriptor location. */
2236	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2237	}
2238
2239	/* read the descriptor. */
2240	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2241	if (RT_FAILURE(rc))
2242	return rc;
2243	}
2244	else
2245	{
2246	/*
2247	* We're in real mode.
2248	*/
2249	pSelInfo->Sel = Sel;
2250	pSelInfo->GCPtrBase = Sel << 4;
2251	pSelInfo->cbLimit = 0xffff;
2252	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2253	pSelInfo->u.Raw64.au64[0] = 0;
2254	pSelInfo->u.Raw64.au64[1] = 0;
2255	pSelInfo->SelGate = 0;
2256	return VINF_SUCCESS;
2257	}
2258
2259	/*
2260	* Extract the base and limit or sel:offset for gates.
2261	*/
2262	pSelInfo->Sel = Sel;
2263	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2264
2265	return VINF_SUCCESS;
2266	}
2267
2268
2269	/**
2270	* Gets information about a selector.
2271	*
2272	* Intended for the debugger mostly and will prefer the guest descriptor tables
2273	* over the shadow ones.
2274	*
2275	* @retval VINF_SUCCESS on success.
2276	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2277	* descriptor table.
2278	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2279	* is not returned if the selector itself isn't present, you have to
2280	* check that for yourself (see DBGFSELINFO::fFlags).
2281	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2282	* pagetable or page backing the selector table wasn't present.
2283	* @returns Other VBox status code on other errors.
2284	*
2285	* @param pVM Pointer to the VM.
2286	* @param pVCpu Pointer to the VMCPU.
2287	* @param Sel The selector to get info about.
2288	* @param pSelInfo Where to store the information.
2289	*/
2290	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2291	{
2292	AssertPtr(pSelInfo);
2293	if (CPUMIsGuestInLongMode(pVCpu))
2294	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2295	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2296	}
2297
2298
2299	/**
2300	* Gets information about a selector from the shadow tables.
2301	*
2302	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2303	* requires that the caller ensures that the shadow tables are up to date.
2304	*
2305	* @retval VINF_SUCCESS on success.
2306	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2307	* descriptor table.
2308	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2309	* is not returned if the selector itself isn't present, you have to
2310	* check that for yourself (see DBGFSELINFO::fFlags).
2311	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2312	* pagetable or page backing the selector table wasn't present.
2313	* @returns Other VBox status code on other errors.
2314	*
2315	* @param pVM Pointer to the VM.
2316	* @param Sel The selector to get info about.
2317	* @param pSelInfo Where to store the information.
2318	*
2319	* @remarks Don't use this when in hardware assisted virtualization mode.
2320	*/
2321	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2322	{
2323	Assert(pSelInfo);
2324
2325	/*
2326	* Read the descriptor entry
2327	*/
2328	X86DESC Desc;
2329	if (!(Sel & X86_SEL_LDT))
2330	{
2331	/*
2332	* Global descriptor.
2333	*/
2334	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2335	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2336	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2337	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2338	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2339	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2340	? DBGFSELINFO_FLAGS_HYPER
2341	: 0;
2342	/** @todo check that the GDT offset is valid. */
2343	}
2344	else
2345	{
2346	/*
2347	* Local Descriptor.
2348	*/
2349	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2350	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2351	/** @todo check if the LDT page is actually available. */
2352	/** @todo check that the LDT offset is valid. */
2353	pSelInfo->fFlags = 0;
2354	}
2355	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2356	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2357	else
2358	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2359
2360	/*
2361	* Extract the base and limit or sel:offset for gates.
2362	*/
2363	pSelInfo->Sel = Sel;
2364	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2365
2366	return VINF_SUCCESS;
2367	}
2368
2369
2370	/**
2371	* Formats a descriptor.
2372	*
2373	* @param Desc Descriptor to format.
2374	* @param Sel Selector number.
2375	* @param pszOutput Output buffer.
2376	* @param cchOutput Size of output buffer.
2377	*/
2378	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2379	{
2380	/*
2381	* Make variable description string.
2382	*/
2383	static struct
2384	{
2385	unsigned cch;
2386	const char *psz;
2387	} const aTypes[32] =
2388	{
2389	#define STRENTRY(str) { sizeof(str) - 1, str }
2390	/* system */
2391	STRENTRY("Reserved0 "), /* 0x00 */
2392	STRENTRY("TSS16Avail "), /* 0x01 */
2393	STRENTRY("LDT "), /* 0x02 */
2394	STRENTRY("TSS16Busy "), /* 0x03 */
2395	STRENTRY("Call16 "), /* 0x04 */
2396	STRENTRY("Task "), /* 0x05 */
2397	STRENTRY("Int16 "), /* 0x06 */
2398	STRENTRY("Trap16 "), /* 0x07 */
2399	STRENTRY("Reserved8 "), /* 0x08 */
2400	STRENTRY("TSS32Avail "), /* 0x09 */
2401	STRENTRY("ReservedA "), /* 0x0a */
2402	STRENTRY("TSS32Busy "), /* 0x0b */
2403	STRENTRY("Call32 "), /* 0x0c */
2404	STRENTRY("ReservedD "), /* 0x0d */
2405	STRENTRY("Int32 "), /* 0x0e */
2406	STRENTRY("Trap32 "), /* 0x0f */
2407	/* non system */
2408	STRENTRY("DataRO "), /* 0x10 */
2409	STRENTRY("DataRO Accessed "), /* 0x11 */
2410	STRENTRY("DataRW "), /* 0x12 */
2411	STRENTRY("DataRW Accessed "), /* 0x13 */
2412	STRENTRY("DataDownRO "), /* 0x14 */
2413	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2414	STRENTRY("DataDownRW "), /* 0x16 */
2415	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2416	STRENTRY("CodeEO "), /* 0x18 */
2417	STRENTRY("CodeEO Accessed "), /* 0x19 */
2418	STRENTRY("CodeER "), /* 0x1a */
2419	STRENTRY("CodeER Accessed "), /* 0x1b */
2420	STRENTRY("CodeConfEO "), /* 0x1c */
2421	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2422	STRENTRY("CodeConfER "), /* 0x1e */
2423	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2424	#undef SYSENTRY
2425	};
2426	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2427	char szMsg[128];
2428	char *psz = &szMsg[0];
2429	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2430	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2431	psz += aTypes[i].cch;
2432
2433	if (Desc.Gen.u1Present)
2434	ADD_STR(psz, "Present ");
2435	else
2436	ADD_STR(psz, "Not-Present ");
2437	if (Desc.Gen.u1Granularity)
2438	ADD_STR(psz, "Page ");
2439	if (Desc.Gen.u1DefBig)
2440	ADD_STR(psz, "32-bit ");
2441	else
2442	ADD_STR(psz, "16-bit ");
2443	#undef ADD_STR
2444	*psz = '\0';
2445
2446	/*
2447	* Limit and Base and format the output.
2448	*/
2449	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2450	uint32_t u32Base = X86DESC_BASE(&Desc);
2451
2452	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2453	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2454	}
2455
2456
2457	/**
2458	* Dumps a descriptor.
2459	*
2460	* @param Desc Descriptor to dump.
2461	* @param Sel Selector number.
2462	* @param pszMsg Message to prepend the log entry with.
2463	*/
2464	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2465	{
2466	char szOutput[128];
2467	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2468	Log(("%s: %s\n", pszMsg, szOutput));
2469	NOREF(szOutput[0]);
2470	}
2471
2472
2473	/**
2474	* Display the shadow gdt.
2475	*
2476	* @param pVM Pointer to the VM.
2477	* @param pHlp The info helpers.
2478	* @param pszArgs Arguments, ignored.
2479	*/
2480	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2481	{
2482	NOREF(pszArgs);
2483	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2484	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2485	{
2486	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2487	{
2488	char szOutput[128];
2489	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2490	const char *psz = "";
2491	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2492	psz = " HyperCS";
2493	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2494	psz = " HyperDS";
2495	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2496	psz = " HyperCS64";
2497	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2498	psz = " HyperTSS";
2499	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2500	psz = " HyperTSSTrap08";
2501	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2502	}
2503	}
2504	}
2505
2506
2507	/**
2508	* Display the guest gdt.
2509	*
2510	* @param pVM Pointer to the VM.
2511	* @param pHlp The info helpers.
2512	* @param pszArgs Arguments, ignored.
2513	*/
2514	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2515	{
2516	/** @todo SMP support! */
2517	PVMCPU pVCpu = &pVM->aCpus[0];
2518
2519	VBOXGDTR GDTR;
2520	CPUMGetGuestGDTR(pVCpu, &GDTR);
2521	RTGCPTR GCPtrGDT = GDTR.pGdt;
2522	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2523
2524	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2525	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2526	{
2527	X86DESC GDTE;
2528	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2529	if (RT_SUCCESS(rc))
2530	{
2531	if (GDTE.Gen.u1Present)
2532	{
2533	char szOutput[128];
2534	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2535	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2536	}
2537	}
2538	else if (rc == VERR_PAGE_NOT_PRESENT)
2539	{
2540	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2541	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2542	}
2543	else
2544	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2545	}
2546	NOREF(pszArgs);
2547	}
2548
2549
2550	/**
2551	* Display the shadow ldt.
2552	*
2553	* @param pVM Pointer to the VM.
2554	* @param pHlp The info helpers.
2555	* @param pszArgs Arguments, ignored.
2556	*/
2557	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2558	{
2559	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2560	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2561	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2562	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2563	{
2564	if (paLDT[iLDT].Gen.u1Present)
2565	{
2566	char szOutput[128];
2567	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2568	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2569	}
2570	}
2571	NOREF(pszArgs);
2572	}
2573
2574
2575	/**
2576	* Display the guest ldt.
2577	*
2578	* @param pVM Pointer to the VM.
2579	* @param pHlp The info helpers.
2580	* @param pszArgs Arguments, ignored.
2581	*/
2582	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2583	{
2584	/** @todo SMP support! */
2585	PVMCPU pVCpu = &pVM->aCpus[0];
2586
2587	uint64_t GCPtrLdt;
2588	uint32_t cbLdt;
2589	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2590	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2591	{
2592	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2593	return;
2594	}
2595
2596	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2597	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2598	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2599	{
2600	X86DESC LdtE;
2601	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2602	if (RT_SUCCESS(rc))
2603	{
2604	if (LdtE.Gen.u1Present)
2605	{
2606	char szOutput[128];
2607	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2608	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2609	}
2610	}
2611	else if (rc == VERR_PAGE_NOT_PRESENT)
2612	{
2613	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2614	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2615	}
2616	else
2617	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2618	}
2619	NOREF(pszArgs);
2620	}
2621
2622
2623	/**
2624	* Dumps the hypervisor GDT
2625	*
2626	* @param pVM Pointer to the VM.
2627	*/
2628	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2629	{
2630	DBGFR3Info(pVM, "gdt", NULL, NULL);
2631	}
2632
2633
2634	/**
2635	* Dumps the hypervisor LDT
2636	*
2637	* @param pVM Pointer to the VM.
2638	*/
2639	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2640	{
2641	DBGFR3Info(pVM, "ldt", NULL, NULL);
2642	}
2643
2644
2645	/**
2646	* Dumps the guest GDT
2647	*
2648	* @param pVM Pointer to the VM.
2649	*/
2650	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2651	{
2652	DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2653	}
2654
2655
2656	/**
2657	* Dumps the guest LDT
2658	*
2659	* @param pVM Pointer to the VM.
2660	*/
2661	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2662	{
2663	DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2664	}
2665

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 42640

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