PGMSavedState.cpp@ 104557

Last change on this file since 104557 was 104557, checked in by vboxsync, 5 months ago
VMM/PGMSavedState.cpp: Check status code for errors and return on error before continuing, bugref:3409
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1	/* $Id: PGMSavedState.cpp 104557 2024-05-08 14:15:39Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_PGM
33	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
34	#include <VBox/vmm/pgm.h>
35	#include <VBox/vmm/stam.h>
36	#include <VBox/vmm/ssm.h>
37	#include <VBox/vmm/pdmdrv.h>
38	#include <VBox/vmm/pdmdev.h>
39	#include "PGMInternal.h"
40	#include <VBox/vmm/vmcc.h>
41	#include "PGMInline.h"
42
43	#include <VBox/param.h>
44	#include <VBox/err.h>
45
46	#include <iprt/asm.h>
47	#include <iprt/assert.h>
48	#include <iprt/crc.h>
49	#include <iprt/mem.h>
50	#include <iprt/sha.h>
51	#include <iprt/string.h>
52	#include <iprt/thread.h>
53
54
55	/*********************************************************************************************************************************
56	* Defined Constants And Macros *
57	*********************************************************************************************************************************/
58	/** Saved state data unit version. */
59	#define PGM_SAVED_STATE_VERSION 14
60	/** Saved state data unit version before the PAE PDPE registers. */
61	#define PGM_SAVED_STATE_VERSION_PRE_PAE 13
62	/** Saved state data unit version after this includes ballooned page flags in
63	* the state (see @bugref{5515}). */
64	#define PGM_SAVED_STATE_VERSION_BALLOON_BROKEN 12
65	/** Saved state before the balloon change. */
66	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
67	/** Saved state data unit version used during 3.1 development, misses the RAM
68	* config. */
69	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
70	/** Saved state data unit version for 3.0 (pre teleportation). */
71	#define PGM_SAVED_STATE_VERSION_3_0_0 9
72	/** Saved state data unit version for 2.2.2 and later. */
73	#define PGM_SAVED_STATE_VERSION_2_2_2 8
74	/** Saved state data unit version for 2.2.0. */
75	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
76	/** Saved state data unit version. */
77	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
78
79
80	/** @name Sparse state record types
81	* @{ */
82	/** Zero page. No data. */
83	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
84	/** Raw page. */
85	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
86	/** Raw MMIO2 page. */
87	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
88	/** Zero MMIO2 page. */
89	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
90	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
91	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
92	/** Raw shadowed ROM page. The protection (8-bit) precedes the raw bits. */
93	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
94	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
95	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
96	/** ROM protection (8-bit). */
97	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
98	/** Ballooned page. No data. */
99	#define PGM_STATE_REC_RAM_BALLOONED UINT8_C(0x08)
100	/** The last record type. */
101	#define PGM_STATE_REC_LAST PGM_STATE_REC_RAM_BALLOONED
102	/** End marker. */
103	#define PGM_STATE_REC_END UINT8_C(0xff)
104	/** Flag indicating that the data is preceded by the page address.
105	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
106	* range ID and a 32-bit page index.
107	*/
108	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
109	/** @} */
110
111	/** The CRC-32 for a zero page. */
112	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
113	/** The CRC-32 for a zero half page. */
114	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
115
116
117
118	/** @name Old Page types used in older saved states.
119	* @{ */
120	/** Old saved state: The usual invalid zero entry. */
121	#define PGMPAGETYPE_OLD_INVALID 0
122	/** Old saved state: RAM page. (RWX) */
123	#define PGMPAGETYPE_OLD_RAM 1
124	/** Old saved state: MMIO2 page. (RWX) */
125	#define PGMPAGETYPE_OLD_MMIO2 1
126	/** Old saved state: MMIO2 page aliased over an MMIO page. (RWX)
127	* See PGMHandlerPhysicalPageAlias(). */
128	#define PGMPAGETYPE_OLD_MMIO2_ALIAS_MMIO 2
129	/** Old saved state: Shadowed ROM. (RWX) */
130	#define PGMPAGETYPE_OLD_ROM_SHADOW 3
131	/** Old saved state: ROM page. (R-X) */
132	#define PGMPAGETYPE_OLD_ROM 4
133	/** Old saved state: MMIO page. (---) */
134	#define PGMPAGETYPE_OLD_MMIO 5
135	/** @} */
136
137
138	/*********************************************************************************************************************************
139	* Structures and Typedefs *
140	*********************************************************************************************************************************/
141	/** For loading old saved states. (pre-smp) */
142	typedef struct
143	{
144	/** If set no conflict checks are required. (boolean) */
145	bool fMappingsFixed;
146	/** Size of fixed mapping */
147	uint32_t cbMappingFixed;
148	/** Base address (GC) of fixed mapping */
149	RTGCPTR GCPtrMappingFixed;
150	/** A20 gate mask.
151	* Our current approach to A20 emulation is to let REM do it and don't bother
152	* anywhere else. The interesting guests will be operating with it enabled anyway.
153	* But should the need arise, we'll subject physical addresses to this mask. */
154	RTGCPHYS GCPhysA20Mask;
155	/** A20 gate state - boolean! */
156	bool fA20Enabled;
157	/** The guest paging mode. */
158	PGMMODE enmGuestMode;
159	} PGMOLD;
160
161
162	/*********************************************************************************************************************************
163	* Global Variables *
164	*********************************************************************************************************************************/
165	/** PGM fields to save/load. */
166
167	static const SSMFIELD s_aPGMFields[] =
168	{
169	SSMFIELD_ENTRY_OLD( fMappingsFixed, sizeof(bool)),
170	SSMFIELD_ENTRY_OLD_GCPTR( GCPtrMappingFixed),
171	SSMFIELD_ENTRY_OLD( cbMappingFixed, sizeof(uint32_t)),
172	SSMFIELD_ENTRY( PGM, cBalloonedPages),
173	SSMFIELD_ENTRY_TERM()
174	};
175
176	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
177	{
178	SSMFIELD_ENTRY_OLD( fMappingsFixed, sizeof(bool)),
179	SSMFIELD_ENTRY_OLD_GCPTR( GCPtrMappingFixed),
180	SSMFIELD_ENTRY_OLD( cbMappingFixed, sizeof(uint32_t)),
181	SSMFIELD_ENTRY_TERM()
182	};
183
184	static const SSMFIELD s_aPGMCpuFields[] =
185	{
186	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
187	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
188	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
189	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[0]),
190	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[1]),
191	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[2]),
192	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[3]),
193	SSMFIELD_ENTRY_TERM()
194	};
195
196	static const SSMFIELD s_aPGMCpuFieldsPrePae[] =
197	{
198	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
199	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
200	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
201	SSMFIELD_ENTRY_TERM()
202	};
203
204	static const SSMFIELD s_aPGMFields_Old[] =
205	{
206	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
207	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
208	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
209	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
210	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
211	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
212	SSMFIELD_ENTRY_TERM()
213	};
214
215
216	/**
217	* Find the ROM tracking structure for the given page.
218	*
219	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
220	* that it's a ROM page.
221	* @param pVM The cross context VM structure.
222	* @param GCPhys The address of the ROM page.
223	*/
224	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
225	{
226	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
227	pRomRange;
228	pRomRange = pRomRange->CTX_SUFF(pNext))
229	{
230	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
231	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
232	return &pRomRange->aPages[off >> GUEST_PAGE_SHIFT];
233	}
234	return NULL;
235	}
236
237
238	/**
239	* Prepares the ROM pages for a live save.
240	*
241	* @returns VBox status code.
242	* @param pVM The cross context VM structure.
243	*/
244	static int pgmR3PrepRomPages(PVM pVM)
245	{
246	/*
247	* Initialize the live save tracking in the ROM page descriptors.
248	*/
249	PGM_LOCK_VOID(pVM);
250	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
251	{
252	PPGMRAMRANGE pRamHint = NULL;;
253	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
254
255	for (uint32_t iPage = 0; iPage < cPages; iPage++)
256	{
257	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
258	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
259	pRom->aPages[iPage].LiveSave.fDirty = true;
260	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
261	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
262	{
263	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
264	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
265	else
266	{
267	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
268	PPGMPAGE pPage;
269	int rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
270	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
271	if (RT_SUCCESS(rc))
272	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
273	else
274	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
275	}
276	}
277	}
278
279	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
280	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
281	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
282	}
283	PGM_UNLOCK(pVM);
284
285	return VINF_SUCCESS;
286	}
287
288
289	/**
290	* Assigns IDs to the ROM ranges and saves them.
291	*
292	* @returns VBox status code.
293	* @param pVM The cross context VM structure.
294	* @param pSSM Saved state handle.
295	*/
296	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
297	{
298	PGM_LOCK_VOID(pVM);
299	uint8_t id = 1;
300	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
301	{
302	pRom->idSavedState = id;
303	SSMR3PutU8(pSSM, id);
304	SSMR3PutStrZ(pSSM, ""); /* device name */
305	SSMR3PutU32(pSSM, 0); /* device instance */
306	SSMR3PutU8(pSSM, 0); /* region */
307	SSMR3PutStrZ(pSSM, pRom->pszDesc);
308	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
309	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
310	if (RT_FAILURE(rc))
311	break;
312	}
313	PGM_UNLOCK(pVM);
314	return SSMR3PutU8(pSSM, UINT8_MAX);
315	}
316
317
318	/**
319	* Loads the ROM range ID assignments.
320	*
321	* @returns VBox status code.
322	*
323	* @param pVM The cross context VM structure.
324	* @param pSSM The saved state handle.
325	*/
326	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
327	{
328	PGM_LOCK_ASSERT_OWNER(pVM);
329
330	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
331	pRom->idSavedState = UINT8_MAX;
332
333	for (;;)
334	{
335	/*
336	* Read the data.
337	*/
338	uint8_t id;
339	int rc = SSMR3GetU8(pSSM, &id);
340	if (RT_FAILURE(rc))
341	return rc;
342	if (id == UINT8_MAX)
343	{
344	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
345	if (pRom->idSavedState != UINT8_MAX)
346	{ /* likely */ }
347	else if (pRom->fFlags & PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE)
348	LogRel(("PGM: The '%s' ROM was not found in the saved state, but it is marked as maybe-missing, so that's probably okay.\n",
349	pRom->pszDesc));
350	else
351	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
352	("The '%s' ROM was not found in the saved state. Probably due to some misconfiguration\n",
353	pRom->pszDesc));
354	return VINF_SUCCESS; /* the end */
355	}
356	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
357
358	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
359	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
360	AssertLogRelRCReturn(rc, rc);
361
362	uint32_t uInstance;
363	SSMR3GetU32(pSSM, &uInstance);
364	uint8_t iRegion;
365	SSMR3GetU8(pSSM, &iRegion);
366
367	char szDesc[64];
368	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
369	AssertLogRelRCReturn(rc, rc);
370
371	RTGCPHYS GCPhys;
372	SSMR3GetGCPhys(pSSM, &GCPhys);
373	RTGCPHYS cb;
374	rc = SSMR3GetGCPhys(pSSM, &cb);
375	if (RT_FAILURE(rc))
376	return rc;
377	AssertLogRelMsgReturn(!(GCPhys & GUEST_PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
378	AssertLogRelMsgReturn(!(cb & GUEST_PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
379
380	/*
381	* Locate a matching ROM range.
382	*/
383	AssertLogRelMsgReturn( uInstance == 0
384	&& iRegion == 0
385	&& szDevName[0] == '\0',
386	("GCPhys=%RGp %s\n", GCPhys, szDesc),
387	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
388	PPGMROMRANGE pRom;
389	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
390	{
391	if ( pRom->idSavedState == UINT8_MAX
392	&& !strcmp(pRom->pszDesc, szDesc))
393	{
394	pRom->idSavedState = id;
395	break;
396	}
397	}
398	if (!pRom)
399	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
400	} /* forever */
401	}
402
403
404	/**
405	* Scan ROM pages.
406	*
407	* @param pVM The cross context VM structure.
408	*/
409	static void pgmR3ScanRomPages(PVM pVM)
410	{
411	/*
412	* The shadow ROMs.
413	*/
414	PGM_LOCK_VOID(pVM);
415	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
416	{
417	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
418	{
419	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
420	for (uint32_t iPage = 0; iPage < cPages; iPage++)
421	{
422	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
423	if (pRomPage->LiveSave.fWrittenTo)
424	{
425	pRomPage->LiveSave.fWrittenTo = false;
426	if (!pRomPage->LiveSave.fDirty)
427	{
428	pRomPage->LiveSave.fDirty = true;
429	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
430	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
431	}
432	pRomPage->LiveSave.fDirtiedRecently = true;
433	}
434	else
435	pRomPage->LiveSave.fDirtiedRecently = false;
436	}
437	}
438	}
439	PGM_UNLOCK(pVM);
440	}
441
442
443	/**
444	* Takes care of the virgin ROM pages in the first pass.
445	*
446	* This is an attempt at simplifying the handling of ROM pages a little bit.
447	* This ASSUMES that no new ROM ranges will be added and that they won't be
448	* relinked in any way.
449	*
450	* @param pVM The cross context VM structure.
451	* @param pSSM The SSM handle.
452	* @param fLiveSave Whether we're in a live save or not.
453	*/
454	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
455	{
456	PGM_LOCK_VOID(pVM);
457	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
458	{
459	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
460	for (uint32_t iPage = 0; iPage < cPages; iPage++)
461	{
462	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
463	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
464
465	/* Get the virgin page descriptor. */
466	PPGMPAGE pPage;
467	if (PGMROMPROT_IS_ROM(enmProt))
468	pPage = pgmPhysGetPage(pVM, GCPhys);
469	else
470	pPage = &pRom->aPages[iPage].Virgin;
471
472	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
473	int rc = VINF_SUCCESS;
474	char abPage[GUEST_PAGE_SIZE];
475	if ( !PGM_PAGE_IS_ZERO(pPage)
476	&& !PGM_PAGE_IS_BALLOONED(pPage))
477	{
478	void const *pvPage;
479	#ifdef VBOX_WITH_PGM_NEM_MODE
480	if (!PGMROMPROT_IS_ROM(enmProt) && pVM->pgm.s.fNemMode)
481	pvPage = &pRom->pbR3Alternate[iPage << GUEST_PAGE_SHIFT];
482	else
483	#endif
484	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
485	if (RT_SUCCESS(rc))
486	memcpy(abPage, pvPage, GUEST_PAGE_SIZE);
487	}
488	else
489	RT_ZERO(abPage);
490	PGM_UNLOCK(pVM);
491	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
492
493	/* Save it. */
494	if (iPage > 0)
495	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
496	else
497	{
498	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
499	SSMR3PutU8(pSSM, pRom->idSavedState);
500	SSMR3PutU32(pSSM, iPage);
501	}
502	SSMR3PutU8(pSSM, (uint8_t)enmProt);
503	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
504	if (RT_FAILURE(rc))
505	return rc;
506
507	/* Update state. */
508	PGM_LOCK_VOID(pVM);
509	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
510	if (fLiveSave)
511	{
512	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
513	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
514	pVM->pgm.s.LiveSave.cSavedPages++;
515	}
516	}
517	}
518	PGM_UNLOCK(pVM);
519	return VINF_SUCCESS;
520	}
521
522
523	/**
524	* Saves dirty pages in the shadowed ROM ranges.
525	*
526	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
527	*
528	* @returns VBox status code.
529	* @param pVM The cross context VM structure.
530	* @param pSSM The SSM handle.
531	* @param fLiveSave Whether it's a live save or not.
532	* @param fFinalPass Whether this is the final pass or not.
533	*/
534	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
535	{
536	/*
537	* The Shadowed ROMs.
538	*
539	* ASSUMES that the ROM ranges are fixed.
540	* ASSUMES that all the ROM ranges are mapped.
541	*/
542	PGM_LOCK_VOID(pVM);
543	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
544	{
545	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
546	{
547	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
548	uint32_t iPrevPage = cPages;
549	for (uint32_t iPage = 0; iPage < cPages; iPage++)
550	{
551	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
552	if ( !fLiveSave
553	\|\| ( pRomPage->LiveSave.fDirty
554	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
555	&& !pRomPage->LiveSave.fWrittenTo)
556	\|\| fFinalPass
557	)
558	)
559	)
560	{
561	uint8_t abPage[GUEST_PAGE_SIZE];
562	PGMROMPROT enmProt = pRomPage->enmProt;
563	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
564	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(pVM, GCPhys);
565	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage); Assert(!PGM_PAGE_IS_BALLOONED(pPage)); /* Shouldn't be ballooned. */
566	int rc = VINF_SUCCESS;
567	if (!fZero)
568	{
569	void const *pvPage;
570	#ifdef VBOX_WITH_PGM_NEM_MODE
571	if (PGMROMPROT_IS_ROM(enmProt) && pVM->pgm.s.fNemMode)
572	pvPage = &pRom->pbR3Alternate[iPage << GUEST_PAGE_SHIFT];
573	else
574	#endif
575	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
576	if (RT_SUCCESS(rc))
577	memcpy(abPage, pvPage, GUEST_PAGE_SIZE);
578	}
579	if (fLiveSave && RT_SUCCESS(rc))
580	{
581	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
582	pRomPage->LiveSave.fDirty = false;
583	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
584	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
585	pVM->pgm.s.LiveSave.cSavedPages++;
586	}
587	PGM_UNLOCK(pVM);
588	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
589
590	if (iPage - 1U == iPrevPage && iPage > 0)
591	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
592	else
593	{
594	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
595	SSMR3PutU8(pSSM, pRom->idSavedState);
596	SSMR3PutU32(pSSM, iPage);
597	}
598	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
599	if (!fZero)
600	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
601	if (RT_FAILURE(rc))
602	return rc;
603
604	PGM_LOCK_VOID(pVM);
605	iPrevPage = iPage;
606	}
607	/*
608	* In the final pass, make sure the protection is in sync.
609	*/
610	else if ( fFinalPass
611	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
612	{
613	PGMROMPROT enmProt = pRomPage->enmProt;
614	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
615	PGM_UNLOCK(pVM);
616
617	if (iPage - 1U == iPrevPage && iPage > 0)
618	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
619	else
620	{
621	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
622	SSMR3PutU8(pSSM, pRom->idSavedState);
623	SSMR3PutU32(pSSM, iPage);
624	}
625	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
626	if (RT_FAILURE(rc))
627	return rc;
628
629	PGM_LOCK_VOID(pVM);
630	iPrevPage = iPage;
631	}
632	}
633	}
634	}
635	PGM_UNLOCK(pVM);
636	return VINF_SUCCESS;
637	}
638
639
640	/**
641	* Cleans up ROM pages after a live save.
642	*
643	* @param pVM The cross context VM structure.
644	*/
645	static void pgmR3DoneRomPages(PVM pVM)
646	{
647	NOREF(pVM);
648	}
649
650
651	/**
652	* Prepares the MMIO2 pages for a live save.
653	*
654	* @returns VBox status code.
655	* @param pVM The cross context VM structure.
656	*/
657	static int pgmR3PrepMmio2Pages(PVM pVM)
658	{
659	/*
660	* Initialize the live save tracking in the MMIO2 ranges.
661	* ASSUME nothing changes here.
662	*/
663	PGM_LOCK_VOID(pVM);
664	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
665	{
666	uint32_t const cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
667	PGM_UNLOCK(pVM);
668
669	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM,
670	sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
671	if (!paLSPages)
672	return VERR_NO_MEMORY;
673	for (uint32_t iPage = 0; iPage < cPages; iPage++)
674	{
675	/* Initialize it as a dirty zero page. */
676	paLSPages[iPage].fDirty = true;
677	paLSPages[iPage].cUnchangedScans = 0;
678	paLSPages[iPage].fZero = true;
679	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
680	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
681	}
682
683	PGM_LOCK_VOID(pVM);
684	pRegMmio->paLSPages = paLSPages;
685	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
686	}
687	PGM_UNLOCK(pVM);
688	return VINF_SUCCESS;
689	}
690
691
692	/**
693	* Assigns IDs to the MMIO2 ranges and saves them.
694	*
695	* @returns VBox status code.
696	* @param pVM The cross context VM structure.
697	* @param pSSM Saved state handle.
698	*/
699	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
700	{
701	PGM_LOCK_VOID(pVM);
702	uint8_t id = 1;
703	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
704	{
705	pRegMmio->idSavedState = id;
706	SSMR3PutU8(pSSM, id);
707	SSMR3PutStrZ(pSSM, pRegMmio->pDevInsR3->pReg->szName);
708	SSMR3PutU32(pSSM, pRegMmio->pDevInsR3->iInstance);
709	SSMR3PutU8(pSSM, pRegMmio->iRegion);
710	SSMR3PutStrZ(pSSM, pRegMmio->RamRange.pszDesc);
711	int rc = SSMR3PutGCPhys(pSSM, pRegMmio->RamRange.cb);
712	if (RT_FAILURE(rc))
713	break;
714	id++;
715	}
716	PGM_UNLOCK(pVM);
717	return SSMR3PutU8(pSSM, UINT8_MAX);
718	}
719
720
721	/**
722	* Loads the MMIO2 range ID assignments.
723	*
724	* @returns VBox status code.
725	*
726	* @param pVM The cross context VM structure.
727	* @param pSSM The saved state handle.
728	*/
729	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
730	{
731	PGM_LOCK_ASSERT_OWNER(pVM);
732
733	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
734	pRegMmio->idSavedState = UINT8_MAX;
735
736	for (;;)
737	{
738	/*
739	* Read the data.
740	*/
741	uint8_t id;
742	int rc = SSMR3GetU8(pSSM, &id);
743	if (RT_FAILURE(rc))
744	return rc;
745	if (id == UINT8_MAX)
746	{
747	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
748	AssertLogRelMsg(pRegMmio->idSavedState != UINT8_MAX, ("%s\n", pRegMmio->RamRange.pszDesc));
749	return VINF_SUCCESS; /* the end */
750	}
751	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
752
753	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
754	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
755	AssertLogRelRCReturn(rc, rc);
756
757	uint32_t uInstance;
758	SSMR3GetU32(pSSM, &uInstance);
759	uint8_t iRegion;
760	SSMR3GetU8(pSSM, &iRegion);
761
762	char szDesc[64];
763	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
764	AssertLogRelRCReturn(rc, rc);
765
766	RTGCPHYS cb;
767	rc = SSMR3GetGCPhys(pSSM, &cb);
768	AssertLogRelRCReturn(rc, rc);
769	AssertLogRelMsgReturn(!(cb & GUEST_PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
770
771	/*
772	* Locate a matching MMIO2 range.
773	*/
774	PPGMREGMMIO2RANGE pRegMmio;
775	for (pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
776	{
777	if ( pRegMmio->idSavedState == UINT8_MAX
778	&& pRegMmio->iRegion == iRegion
779	&& pRegMmio->pDevInsR3->iInstance == uInstance
780	&& !strcmp(pRegMmio->pDevInsR3->pReg->szName, szDevName))
781	{
782	pRegMmio->idSavedState = id;
783	break;
784	}
785	}
786	if (!pRegMmio)
787	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
788	szDesc, szDevName, uInstance, iRegion);
789
790	/*
791	* Validate the configuration, the size of the MMIO2 region should be
792	* the same.
793	*/
794	if (cb != pRegMmio->RamRange.cb)
795	{
796	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
797	pRegMmio->RamRange.pszDesc, cb, pRegMmio->RamRange.cb));
798	if (cb > pRegMmio->RamRange.cb) /* bad idea? */
799	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
800	pRegMmio->RamRange.pszDesc, cb, pRegMmio->RamRange.cb);
801	}
802	} /* forever */
803	}
804
805
806	/**
807	* Scans one MMIO2 page.
808	*
809	* @returns True if changed, false if unchanged.
810	*
811	* @param pVM The cross context VM structure.
812	* @param pbPage The page bits.
813	* @param pLSPage The live save tracking structure for the page.
814	*
815	*/
816	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
817	{
818	/*
819	* Special handling of zero pages.
820	*/
821	bool const fZero = pLSPage->fZero;
822	if (fZero)
823	{
824	if (ASMMemIsZero(pbPage, GUEST_PAGE_SIZE))
825	{
826	/* Not modified. */
827	if (pLSPage->fDirty)
828	pLSPage->cUnchangedScans++;
829	return false;
830	}
831
832	pLSPage->fZero = false;
833	pLSPage->u32CrcH1 = RTCrc32(pbPage, GUEST_PAGE_SIZE / 2);
834	}
835	else
836	{
837	/*
838	* CRC the first half, if it doesn't match the page is dirty and
839	* we won't check the 2nd half (we'll do that next time).
840	*/
841	uint32_t u32CrcH1 = RTCrc32(pbPage, GUEST_PAGE_SIZE / 2);
842	if (u32CrcH1 == pLSPage->u32CrcH1)
843	{
844	uint32_t u32CrcH2 = RTCrc32(pbPage + GUEST_PAGE_SIZE / 2, GUEST_PAGE_SIZE / 2);
845	if (u32CrcH2 == pLSPage->u32CrcH2)
846	{
847	/* Probably not modified. */
848	if (pLSPage->fDirty)
849	pLSPage->cUnchangedScans++;
850	return false;
851	}
852
853	pLSPage->u32CrcH2 = u32CrcH2;
854	}
855	else
856	{
857	pLSPage->u32CrcH1 = u32CrcH1;
858	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
859	&& ASMMemIsZero(pbPage, GUEST_PAGE_SIZE))
860	{
861	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
862	pLSPage->fZero = true;
863	}
864	}
865	}
866
867	/* dirty page path */
868	pLSPage->cUnchangedScans = 0;
869	if (!pLSPage->fDirty)
870	{
871	pLSPage->fDirty = true;
872	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
873	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
874	if (fZero)
875	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
876	}
877	return true;
878	}
879
880
881	/**
882	* Scan for MMIO2 page modifications.
883	*
884	* @param pVM The cross context VM structure.
885	* @param uPass The pass number.
886	*/
887	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
888	{
889	/*
890	* Since this is a bit expensive we lower the scan rate after a little while.
891	*/
892	if ( ( (uPass & 3) != 0
893	&& uPass > 10)
894	\|\| uPass == SSM_PASS_FINAL)
895	return;
896
897	PGM_LOCK_VOID(pVM); /* paranoia */
898	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
899	{
900	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
901	uint32_t cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
902	PGM_UNLOCK(pVM);
903
904	for (uint32_t iPage = 0; iPage < cPages; iPage++)
905	{
906	uint8_t const pbPage = (uint8_t const )pRegMmio->pvR3 + iPage * GUEST_PAGE_SIZE;
907	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
908	}
909
910	PGM_LOCK_VOID(pVM);
911	}
912	PGM_UNLOCK(pVM);
913
914	}
915
916
917	/**
918	* Save quiescent MMIO2 pages.
919	*
920	* @returns VBox status code.
921	* @param pVM The cross context VM structure.
922	* @param pSSM The SSM handle.
923	* @param fLiveSave Whether it's a live save or not.
924	* @param uPass The pass number.
925	*/
926	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
927	{
928	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
929	* device that we wish to know about changes.) */
930
931	int rc = VINF_SUCCESS;
932	if (uPass == SSM_PASS_FINAL)
933	{
934	/*
935	* The mop up round.
936	*/
937	PGM_LOCK_VOID(pVM);
938	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3;
939	pRegMmio && RT_SUCCESS(rc);
940	pRegMmio = pRegMmio->pNextR3)
941	{
942	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
943	uint8_t const pbPage = (uint8_t const )pRegMmio->RamRange.pvR3;
944	uint32_t cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
945	uint32_t iPageLast = cPages;
946	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += GUEST_PAGE_SIZE)
947	{
948	uint8_t u8Type;
949	if (!fLiveSave)
950	u8Type = ASMMemIsZero(pbPage, GUEST_PAGE_SIZE) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
951	else
952	{
953	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
954	if ( !paLSPages[iPage].fDirty
955	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
956	{
957	if (paLSPages[iPage].fZero)
958	continue;
959
960	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
961	RTSha1(pbPage, GUEST_PAGE_SIZE, abSha1Hash);
962	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
963	continue;
964	}
965	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
966	pVM->pgm.s.LiveSave.cSavedPages++;
967	}
968
969	if (iPage != 0 && iPage == iPageLast + 1)
970	rc = SSMR3PutU8(pSSM, u8Type);
971	else
972	{
973	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
974	SSMR3PutU8(pSSM, pRegMmio->idSavedState);
975	rc = SSMR3PutU32(pSSM, iPage);
976	}
977	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
978	rc = SSMR3PutMem(pSSM, pbPage, GUEST_PAGE_SIZE);
979	if (RT_FAILURE(rc))
980	break;
981	iPageLast = iPage;
982	}
983	}
984	PGM_UNLOCK(pVM);
985	}
986	/*
987	* Reduce the rate after a little while since the current MMIO2 approach is
988	* a bit expensive.
989	* We position it two passes after the scan pass to avoid saving busy pages.
990	*/
991	else if ( uPass <= 10
992	\|\| (uPass & 3) == 2)
993	{
994	PGM_LOCK_VOID(pVM);
995	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3;
996	pRegMmio && RT_SUCCESS(rc);
997	pRegMmio = pRegMmio->pNextR3)
998	{
999	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
1000	uint8_t const pbPage = (uint8_t const )pRegMmio->RamRange.pvR3;
1001	uint32_t cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
1002	uint32_t iPageLast = cPages;
1003	PGM_UNLOCK(pVM);
1004
1005	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += GUEST_PAGE_SIZE)
1006	{
1007	/* Skip clean pages and pages which hasn't quiesced. */
1008	if (!paLSPages[iPage].fDirty)
1009	continue;
1010	if (paLSPages[iPage].cUnchangedScans < 3)
1011	continue;
1012	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
1013	continue;
1014
1015	/* Save it. */
1016	bool const fZero = paLSPages[iPage].fZero;
1017	uint8_t abPage[GUEST_PAGE_SIZE];
1018	if (!fZero)
1019	{
1020	memcpy(abPage, pbPage, GUEST_PAGE_SIZE);
1021	RTSha1(abPage, GUEST_PAGE_SIZE, paLSPages[iPage].abSha1Saved);
1022	}
1023
1024	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
1025	if (iPage != 0 && iPage == iPageLast + 1)
1026	rc = SSMR3PutU8(pSSM, u8Type);
1027	else
1028	{
1029	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
1030	SSMR3PutU8(pSSM, pRegMmio->idSavedState);
1031	rc = SSMR3PutU32(pSSM, iPage);
1032	}
1033	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
1034	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
1035	if (RT_FAILURE(rc))
1036	break;
1037
1038	/* Housekeeping. */
1039	paLSPages[iPage].fDirty = false;
1040	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
1041	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
1042	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
1043	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
1044	pVM->pgm.s.LiveSave.cSavedPages++;
1045	iPageLast = iPage;
1046	}
1047
1048	PGM_LOCK_VOID(pVM);
1049	}
1050	PGM_UNLOCK(pVM);
1051	}
1052
1053	return rc;
1054	}
1055
1056
1057	/**
1058	* Cleans up MMIO2 pages after a live save.
1059	*
1060	* @param pVM The cross context VM structure.
1061	*/
1062	static void pgmR3DoneMmio2Pages(PVM pVM)
1063	{
1064	/*
1065	* Free the tracking structures for the MMIO2 pages.
1066	* We do the freeing outside the lock in case the VM is running.
1067	*/
1068	PGM_LOCK_VOID(pVM);
1069	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
1070	{
1071	void *pvMmio2ToFree = pRegMmio->paLSPages;
1072	if (pvMmio2ToFree)
1073	{
1074	pRegMmio->paLSPages = NULL;
1075	PGM_UNLOCK(pVM);
1076	MMR3HeapFree(pvMmio2ToFree);
1077	PGM_LOCK_VOID(pVM);
1078	}
1079	}
1080	PGM_UNLOCK(pVM);
1081	}
1082
1083
1084	/**
1085	* Prepares the RAM pages for a live save.
1086	*
1087	* @returns VBox status code.
1088	* @param pVM The cross context VM structure.
1089	*/
1090	static int pgmR3PrepRamPages(PVM pVM)
1091	{
1092
1093	/*
1094	* Try allocating tracking structures for the ram ranges.
1095	*
1096	* To avoid lock contention, we leave the lock every time we're allocating
1097	* a new array. This means we'll have to ditch the allocation and start
1098	* all over again if the RAM range list changes in-between.
1099	*
1100	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1101	* for cleaning up.
1102	*/
1103	PPGMRAMRANGE pCur;
1104	PGM_LOCK_VOID(pVM);
1105	do
1106	{
1107	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1108	{
1109	if ( !pCur->paLSPages
1110	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1111	{
1112	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1113	uint32_t const cPages = pCur->cb >> GUEST_PAGE_SHIFT;
1114	PGM_UNLOCK(pVM);
1115	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1116	if (!paLSPages)
1117	return VERR_NO_MEMORY;
1118	PGM_LOCK_VOID(pVM);
1119	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1120	{
1121	PGM_UNLOCK(pVM);
1122	MMR3HeapFree(paLSPages);
1123	PGM_LOCK_VOID(pVM);
1124	break; /* try again */
1125	}
1126	pCur->paLSPages = paLSPages;
1127
1128	/*
1129	* Initialize the array.
1130	*/
1131	uint32_t iPage = cPages;
1132	while (iPage-- > 0)
1133	{
1134	/** @todo yield critsect! (after moving this away from EMT0) */
1135	PCPGMPAGE pPage = &pCur->aPages[iPage];
1136	paLSPages[iPage].cDirtied = 0;
1137	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1138	paLSPages[iPage].fWriteMonitored = 0;
1139	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1140	paLSPages[iPage].u2Reserved = 0;
1141	switch (PGM_PAGE_GET_TYPE(pPage))
1142	{
1143	case PGMPAGETYPE_RAM:
1144	if ( PGM_PAGE_IS_ZERO(pPage)
1145	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1146	{
1147	paLSPages[iPage].fZero = 1;
1148	paLSPages[iPage].fShared = 0;
1149	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1150	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1151	#endif
1152	}
1153	else if (PGM_PAGE_IS_SHARED(pPage))
1154	{
1155	paLSPages[iPage].fZero = 0;
1156	paLSPages[iPage].fShared = 1;
1157	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1158	paLSPages[iPage].u32Crc = UINT32_MAX;
1159	#endif
1160	}
1161	else
1162	{
1163	paLSPages[iPage].fZero = 0;
1164	paLSPages[iPage].fShared = 0;
1165	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1166	paLSPages[iPage].u32Crc = UINT32_MAX;
1167	#endif
1168	}
1169	paLSPages[iPage].fIgnore = 0;
1170	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1171	break;
1172
1173	case PGMPAGETYPE_ROM_SHADOW:
1174	case PGMPAGETYPE_ROM:
1175	{
1176	paLSPages[iPage].fZero = 0;
1177	paLSPages[iPage].fShared = 0;
1178	paLSPages[iPage].fDirty = 0;
1179	paLSPages[iPage].fIgnore = 1;
1180	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1181	paLSPages[iPage].u32Crc = UINT32_MAX;
1182	#endif
1183	pVM->pgm.s.LiveSave.cIgnoredPages++;
1184	break;
1185	}
1186
1187	default:
1188	AssertMsgFailed(("%R[pgmpage]", pPage));
1189	RT_FALL_THRU();
1190	case PGMPAGETYPE_MMIO2:
1191	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1192	paLSPages[iPage].fZero = 0;
1193	paLSPages[iPage].fShared = 0;
1194	paLSPages[iPage].fDirty = 0;
1195	paLSPages[iPage].fIgnore = 1;
1196	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1197	paLSPages[iPage].u32Crc = UINT32_MAX;
1198	#endif
1199	pVM->pgm.s.LiveSave.cIgnoredPages++;
1200	break;
1201
1202	case PGMPAGETYPE_MMIO:
1203	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
1204	paLSPages[iPage].fZero = 0;
1205	paLSPages[iPage].fShared = 0;
1206	paLSPages[iPage].fDirty = 0;
1207	paLSPages[iPage].fIgnore = 1;
1208	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1209	paLSPages[iPage].u32Crc = UINT32_MAX;
1210	#endif
1211	pVM->pgm.s.LiveSave.cIgnoredPages++;
1212	break;
1213	}
1214	}
1215	}
1216	}
1217	} while (pCur);
1218	PGM_UNLOCK(pVM);
1219
1220	return VINF_SUCCESS;
1221	}
1222
1223
1224	/**
1225	* Saves the RAM configuration.
1226	*
1227	* @returns VBox status code.
1228	* @param pVM The cross context VM structure.
1229	* @param pSSM The saved state handle.
1230	*/
1231	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1232	{
1233	uint32_t cbRamHole = 0;
1234	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1235	AssertRCReturn(rc, rc);
1236
1237	uint64_t cbRam = 0;
1238	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1239	AssertRCReturn(rc, rc);
1240
1241	SSMR3PutU32(pSSM, cbRamHole);
1242	return SSMR3PutU64(pSSM, cbRam);
1243	}
1244
1245
1246	/**
1247	* Loads and verifies the RAM configuration.
1248	*
1249	* @returns VBox status code.
1250	* @param pVM The cross context VM structure.
1251	* @param pSSM The saved state handle.
1252	*/
1253	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1254	{
1255	uint32_t cbRamHoleCfg = 0;
1256	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1257	AssertRCReturn(rc, rc);
1258
1259	uint64_t cbRamCfg = 0;
1260	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1261	AssertRCReturn(rc, rc);
1262
1263	uint32_t cbRamHoleSaved;
1264	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1265
1266	uint64_t cbRamSaved;
1267	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1268	AssertRCReturn(rc, rc);
1269
1270	if ( cbRamHoleCfg != cbRamHoleSaved
1271	\|\| cbRamCfg != cbRamSaved)
1272	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1273	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1274	return VINF_SUCCESS;
1275	}
1276
1277	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1278
1279	/**
1280	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1281	* info with it.
1282	*
1283	* @param pVM The cross context VM structure.
1284	* @param pCur The current RAM range.
1285	* @param paLSPages The current array of live save page tracking
1286	* structures.
1287	* @param iPage The page index.
1288	*/
1289	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1290	{
1291	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1292	PGMPAGEMAPLOCK PgMpLck;
1293	void const *pvPage;
1294	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1295	if (RT_SUCCESS(rc))
1296	{
1297	paLSPages[iPage].u32Crc = RTCrc32(pvPage, GUEST_PAGE_SIZE);
1298	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1299	}
1300	else
1301	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1302	}
1303
1304
1305	/**
1306	* Verifies the CRC-32 for a page given it's raw bits.
1307	*
1308	* @param pvPage The page bits.
1309	* @param pCur The current RAM range.
1310	* @param paLSPages The current array of live save page tracking
1311	* structures.
1312	* @param iPage The page index.
1313	*/
1314	static void pgmR3StateVerifyCrc32ForPage(void const pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char pszWhere)
1315	{
1316	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1317	{
1318	uint32_t u32Crc = RTCrc32(pvPage, GUEST_PAGE_SIZE);
1319	Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1320	&& !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1321	\|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1322	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1323	("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1324	pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1325	}
1326	}
1327
1328
1329	/**
1330	* Verifies the CRC-32 for a RAM page.
1331	*
1332	* @param pVM The cross context VM structure.
1333	* @param pCur The current RAM range.
1334	* @param paLSPages The current array of live save page tracking
1335	* structures.
1336	* @param iPage The page index.
1337	*/
1338	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1339	{
1340	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1341	{
1342	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1343	PGMPAGEMAPLOCK PgMpLck;
1344	void const *pvPage;
1345	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1346	if (RT_SUCCESS(rc))
1347	{
1348	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1349	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1350	}
1351	}
1352	}
1353
1354	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1355
1356	/**
1357	* Scan for RAM page modifications and reprotect them.
1358	*
1359	* @param pVM The cross context VM structure.
1360	* @param fFinalPass Whether this is the final pass or not.
1361	*/
1362	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1363	{
1364	/*
1365	* The RAM.
1366	*/
1367	RTGCPHYS GCPhysCur = 0;
1368	PPGMRAMRANGE pCur;
1369	PGM_LOCK_VOID(pVM);
1370	do
1371	{
1372	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1373	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1374	{
1375	if ( pCur->GCPhysLast > GCPhysCur
1376	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1377	{
1378	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1379	uint32_t cPages = pCur->cb >> GUEST_PAGE_SHIFT;
1380	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> GUEST_PAGE_SHIFT;
1381	GCPhysCur = 0;
1382	for (; iPage < cPages; iPage++)
1383	{
1384	/* Do yield first. */
1385	if ( !fFinalPass
1386	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1387	&& (iPage & 0x7ff) == 0x100
1388	#endif
1389	&& PDMR3CritSectYield(pVM, &pVM->pgm.s.CritSectX)
1390	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1391	{
1392	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1393	break; /* restart */
1394	}
1395
1396	/* Skip already ignored pages. */
1397	if (paLSPages[iPage].fIgnore)
1398	continue;
1399
1400	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1401	{
1402	/*
1403	* A RAM page.
1404	*/
1405	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1406	{
1407	case PGM_PAGE_STATE_ALLOCATED:
1408	/** @todo Optimize this: Don't always re-enable write
1409	* monitoring if the page is known to be very busy. */
1410	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1411	{
1412	AssertMsg(paLSPages[iPage].fWriteMonitored,
1413	("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT), &pCur->aPages[iPage]));
1414	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1415	Assert(pVM->pgm.s.cWrittenToPages > 0);
1416	pVM->pgm.s.cWrittenToPages--;
1417	}
1418	else
1419	{
1420	AssertMsg(!paLSPages[iPage].fWriteMonitored,
1421	("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT), &pCur->aPages[iPage]));
1422	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1423	}
1424
1425	if (!paLSPages[iPage].fDirty)
1426	{
1427	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1428	if (paLSPages[iPage].fZero)
1429	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1430	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1431	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1432	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1433	}
1434
1435	pgmPhysPageWriteMonitor(pVM, &pCur->aPages[iPage],
1436	pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT));
1437	paLSPages[iPage].fWriteMonitored = 1;
1438	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1439	paLSPages[iPage].fDirty = 1;
1440	paLSPages[iPage].fZero = 0;
1441	paLSPages[iPage].fShared = 0;
1442	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1443	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1444	#endif
1445	break;
1446
1447	case PGM_PAGE_STATE_WRITE_MONITORED:
1448	Assert(paLSPages[iPage].fWriteMonitored);
1449	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1450	{
1451	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1452	if (paLSPages[iPage].fWriteMonitoredJustNow)
1453	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1454	else
1455	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1456	#endif
1457	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1458	}
1459	else
1460	{
1461	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1462	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1463	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1464	#endif
1465	if (!paLSPages[iPage].fDirty)
1466	{
1467	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1468	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1469	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1470	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1471	}
1472	}
1473	break;
1474
1475	case PGM_PAGE_STATE_ZERO:
1476	case PGM_PAGE_STATE_BALLOONED:
1477	if (!paLSPages[iPage].fZero)
1478	{
1479	if (!paLSPages[iPage].fDirty)
1480	{
1481	paLSPages[iPage].fDirty = 1;
1482	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1483	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1484	}
1485	paLSPages[iPage].fZero = 1;
1486	paLSPages[iPage].fShared = 0;
1487	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1488	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1489	#endif
1490	}
1491	break;
1492
1493	case PGM_PAGE_STATE_SHARED:
1494	if (!paLSPages[iPage].fShared)
1495	{
1496	if (!paLSPages[iPage].fDirty)
1497	{
1498	paLSPages[iPage].fDirty = 1;
1499	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1500	if (paLSPages[iPage].fZero)
1501	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1502	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1503	}
1504	paLSPages[iPage].fZero = 0;
1505	paLSPages[iPage].fShared = 1;
1506	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1507	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1508	#endif
1509	}
1510	break;
1511	}
1512	}
1513	else
1514	{
1515	/*
1516	* All other types => Ignore the page.
1517	*/
1518	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1519	paLSPages[iPage].fIgnore = 1;
1520	if (paLSPages[iPage].fWriteMonitored)
1521	{
1522	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1523	* pages! */
1524	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1525	{
1526	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1527	PGM_PAGE_SET_STATE(pVM, &pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1528	Assert(pVM->pgm.s.cMonitoredPages > 0);
1529	pVM->pgm.s.cMonitoredPages--;
1530	}
1531	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1532	{
1533	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1534	Assert(pVM->pgm.s.cWrittenToPages > 0);
1535	pVM->pgm.s.cWrittenToPages--;
1536	}
1537	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1538	}
1539
1540	/** @todo the counting doesn't quite work out here. fix later? */
1541	if (paLSPages[iPage].fDirty)
1542	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1543	else
1544	{
1545	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1546	if (paLSPages[iPage].fZero)
1547	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1548	}
1549	pVM->pgm.s.LiveSave.cIgnoredPages++;
1550	}
1551	} /* for each page in range */
1552
1553	if (GCPhysCur != 0)
1554	break; /* Yield + ramrange change */
1555	GCPhysCur = pCur->GCPhysLast;
1556	}
1557	} /* for each range */
1558	} while (pCur);
1559	PGM_UNLOCK(pVM);
1560	}
1561
1562
1563	/**
1564	* Save quiescent RAM pages.
1565	*
1566	* @returns VBox status code.
1567	* @param pVM The cross context VM structure.
1568	* @param pSSM The SSM handle.
1569	* @param fLiveSave Whether it's a live save or not.
1570	* @param uPass The pass number.
1571	*/
1572	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1573	{
1574	NOREF(fLiveSave);
1575
1576	/*
1577	* The RAM.
1578	*/
1579	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1580	RTGCPHYS GCPhysCur = 0;
1581	PPGMRAMRANGE pCur;
1582
1583	PGM_LOCK_VOID(pVM);
1584	do
1585	{
1586	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1587	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1588	{
1589	if ( pCur->GCPhysLast > GCPhysCur
1590	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1591	{
1592	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1593	uint32_t cPages = pCur->cb >> GUEST_PAGE_SHIFT;
1594	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> GUEST_PAGE_SHIFT;
1595	GCPhysCur = 0;
1596	for (; iPage < cPages; iPage++)
1597	{
1598	/* Do yield first. */
1599	if ( uPass != SSM_PASS_FINAL
1600	&& (iPage & 0x7ff) == 0x100
1601	&& PDMR3CritSectYield(pVM, &pVM->pgm.s.CritSectX)
1602	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1603	{
1604	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1605	break; /* restart */
1606	}
1607
1608	PPGMPAGE pCurPage = &pCur->aPages[iPage];
1609
1610	/*
1611	* Only save pages that haven't changed since last scan and are dirty.
1612	*/
1613	if ( uPass != SSM_PASS_FINAL
1614	&& paLSPages)
1615	{
1616	if (!paLSPages[iPage].fDirty)
1617	continue;
1618	if (paLSPages[iPage].fWriteMonitoredJustNow)
1619	continue;
1620	if (paLSPages[iPage].fIgnore)
1621	continue;
1622	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1623	continue;
1624	if ( PGM_PAGE_GET_STATE(pCurPage)
1625	!= ( paLSPages[iPage].fZero
1626	? PGM_PAGE_STATE_ZERO
1627	: paLSPages[iPage].fShared
1628	? PGM_PAGE_STATE_SHARED
1629	: PGM_PAGE_STATE_WRITE_MONITORED))
1630	continue;
1631	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1632	continue;
1633	}
1634	else
1635	{
1636	if ( paLSPages
1637	&& !paLSPages[iPage].fDirty
1638	&& !paLSPages[iPage].fIgnore)
1639	{
1640	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1641	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1642	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1643	#endif
1644	continue;
1645	}
1646	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1647	continue;
1648	}
1649
1650	/*
1651	* Do the saving outside the PGM critsect since SSM may block on I/O.
1652	*/
1653	int rc;
1654	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1655	bool fZero = PGM_PAGE_IS_ZERO(pCurPage);
1656	bool fBallooned = PGM_PAGE_IS_BALLOONED(pCurPage);
1657	bool fSkipped = false;
1658
1659	if (!fZero && !fBallooned)
1660	{
1661	/*
1662	* Copy the page and then save it outside the lock (since any
1663	* SSM call may block).
1664	*/
1665	uint8_t abPage[GUEST_PAGE_SIZE];
1666	PGMPAGEMAPLOCK PgMpLck;
1667	void const *pvPage;
1668	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pCurPage, GCPhys, &pvPage, &PgMpLck);
1669	if (RT_SUCCESS(rc))
1670	{
1671	memcpy(abPage, pvPage, GUEST_PAGE_SIZE);
1672	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1673	if (paLSPages)
1674	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1675	#endif
1676	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1677	}
1678	PGM_UNLOCK(pVM);
1679	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1680
1681	/* Try save some memory when restoring. */
1682	if (!ASMMemIsZero(pvPage, GUEST_PAGE_SIZE))
1683	{
1684	if (GCPhys == GCPhysLast + GUEST_PAGE_SIZE)
1685	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1686	else
1687	{
1688	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1689	SSMR3PutGCPhys(pSSM, GCPhys);
1690	}
1691	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
1692	}
1693	else
1694	{
1695	if (GCPhys == GCPhysLast + GUEST_PAGE_SIZE)
1696	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1697	else
1698	{
1699	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1700	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1701	}
1702	}
1703	}
1704	else
1705	{
1706	/*
1707	* Dirty zero or ballooned page.
1708	*/
1709	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1710	if (paLSPages)
1711	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1712	#endif
1713	PGM_UNLOCK(pVM);
1714
1715	uint8_t u8RecType = fBallooned ? PGM_STATE_REC_RAM_BALLOONED : PGM_STATE_REC_RAM_ZERO;
1716	if (GCPhys == GCPhysLast + GUEST_PAGE_SIZE)
1717	rc = SSMR3PutU8(pSSM, u8RecType);
1718	else
1719	{
1720	SSMR3PutU8(pSSM, u8RecType \| PGM_STATE_REC_FLAG_ADDR);
1721	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1722	}
1723	}
1724	if (RT_FAILURE(rc))
1725	return rc;
1726
1727	PGM_LOCK_VOID(pVM);
1728	if (!fSkipped)
1729	GCPhysLast = GCPhys;
1730	if (paLSPages)
1731	{
1732	paLSPages[iPage].fDirty = 0;
1733	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1734	if (fZero)
1735	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1736	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1737	pVM->pgm.s.LiveSave.cSavedPages++;
1738	}
1739	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1740	{
1741	GCPhysCur = GCPhys \| GUEST_PAGE_OFFSET_MASK;
1742	break; /* restart */
1743	}
1744
1745	} /* for each page in range */
1746
1747	if (GCPhysCur != 0)
1748	break; /* Yield + ramrange change */
1749	GCPhysCur = pCur->GCPhysLast;
1750	}
1751	} /* for each range */
1752	} while (pCur);
1753
1754	PGM_UNLOCK(pVM);
1755
1756	return VINF_SUCCESS;
1757	}
1758
1759
1760	/**
1761	* Cleans up RAM pages after a live save.
1762	*
1763	* @param pVM The cross context VM structure.
1764	*/
1765	static void pgmR3DoneRamPages(PVM pVM)
1766	{
1767	/*
1768	* Free the tracking arrays and disable write monitoring.
1769	*
1770	* Play nice with the PGM lock in case we're called while the VM is still
1771	* running. This means we have to delay the freeing since we wish to use
1772	* paLSPages as an indicator of which RAM ranges which we need to scan for
1773	* write monitored pages.
1774	*/
1775	void *pvToFree = NULL;
1776	PPGMRAMRANGE pCur;
1777	uint32_t cMonitoredPages = 0;
1778	PGM_LOCK_VOID(pVM);
1779	do
1780	{
1781	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1782	{
1783	if (pCur->paLSPages)
1784	{
1785	if (pvToFree)
1786	{
1787	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1788	PGM_UNLOCK(pVM);
1789	MMR3HeapFree(pvToFree);
1790	pvToFree = NULL;
1791	PGM_LOCK_VOID(pVM);
1792	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1793	break; /* start over again. */
1794	}
1795
1796	pvToFree = pCur->paLSPages;
1797	pCur->paLSPages = NULL;
1798
1799	uint32_t iPage = pCur->cb >> GUEST_PAGE_SHIFT;
1800	while (iPage--)
1801	{
1802	PPGMPAGE pPage = &pCur->aPages[iPage];
1803	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1804	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1805	{
1806	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
1807	cMonitoredPages++;
1808	}
1809	}
1810	}
1811	}
1812	} while (pCur);
1813
1814	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1815	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1816	pVM->pgm.s.cMonitoredPages = 0;
1817	else
1818	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1819
1820	PGM_UNLOCK(pVM);
1821
1822	MMR3HeapFree(pvToFree);
1823	pvToFree = NULL;
1824	}
1825
1826
1827	/**
1828	* @callback_method_impl{FNSSMINTLIVEEXEC}
1829	*/
1830	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1831	{
1832	int rc;
1833
1834	/*
1835	* Save the MMIO2 and ROM range IDs in pass 0.
1836	*/
1837	if (uPass == 0)
1838	{
1839	rc = pgmR3SaveRamConfig(pVM, pSSM);
1840	if (RT_FAILURE(rc))
1841	return rc;
1842	rc = pgmR3SaveRomRanges(pVM, pSSM);
1843	if (RT_FAILURE(rc))
1844	return rc;
1845	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1846	if (RT_FAILURE(rc))
1847	return rc;
1848	}
1849	/*
1850	* Reset the page-per-second estimate to avoid inflation by the initial
1851	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1852	*/
1853	else if (uPass == 7)
1854	{
1855	pVM->pgm.s.LiveSave.cSavedPages = 0;
1856	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1857	}
1858
1859	/*
1860	* Do the scanning.
1861	*/
1862	pgmR3ScanRomPages(pVM);
1863	pgmR3ScanMmio2Pages(pVM, uPass);
1864	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1865	pgmR3PoolClearAll(pVM, true /fFlushRemTlb/); /** @todo this could perhaps be optimized a bit. */
1866
1867	/*
1868	* Save the pages.
1869	*/
1870	if (uPass == 0)
1871	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1872	else
1873	rc = VINF_SUCCESS;
1874	if (RT_SUCCESS(rc))
1875	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1876	if (RT_SUCCESS(rc))
1877	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1878	if (RT_SUCCESS(rc))
1879	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1880	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1881
1882	return rc;
1883	}
1884
1885
1886	/**
1887	* @callback_method_impl{FNSSMINTLIVEVOTE}
1888	*/
1889	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1890	{
1891	/*
1892	* Update and calculate parameters used in the decision making.
1893	*/
1894	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1895
1896	/* update history. */
1897	PGM_LOCK_VOID(pVM);
1898	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1899	PGM_UNLOCK(pVM);
1900	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1901	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1902	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1903	+ cWrittenToPages;
1904	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1905	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1906	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1907
1908	/* calc shortterm average (4 passes). */
1909	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1910	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1911	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1912	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1913	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1914	uint32_t const cDirtyPagesShort = cTotal / 4;
1915	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1916
1917	/* calc longterm average. */
1918	cTotal = 0;
1919	if (uPass < cHistoryEntries)
1920	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1921	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1922	else
1923	for (i = 0; i < cHistoryEntries; i++)
1924	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1925	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1926	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1927
1928	/* estimate the speed */
1929	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1930	uint32_t cPagesPerSecond = (uint32_t)( (long double)pVM->pgm.s.LiveSave.cSavedPages
1931	/ ((long double)cNsElapsed / 1000000000.0) );
1932	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1933
1934	/*
1935	* Try make a decision.
1936	*/
1937	if ( cDirtyPagesShort <= cDirtyPagesLong
1938	&& ( cDirtyNow <= cDirtyPagesShort
1939	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1940	)
1941	)
1942	{
1943	if (uPass > 10)
1944	{
1945	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1946	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1947	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1948	if (cMsMaxDowntime < 32)
1949	cMsMaxDowntime = 32;
1950	if ( ( cMsLeftLong <= cMsMaxDowntime
1951	&& cMsLeftShort < cMsMaxDowntime)
1952	\|\| cMsLeftShort < cMsMaxDowntime / 2
1953	)
1954	{
1955	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1956	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1957	return VINF_SUCCESS;
1958	}
1959	}
1960	else
1961	{
1962	if ( ( cDirtyPagesShort <= 128
1963	&& cDirtyPagesLong <= 1024)
1964	\|\| cDirtyPagesLong <= 256
1965	)
1966	{
1967	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1968	return VINF_SUCCESS;
1969	}
1970	}
1971	}
1972
1973	/*
1974	* Come up with a completion percentage. Currently this is a simple
1975	* dirty page (long term) vs. total pages ratio + some pass trickery.
1976	*/
1977	unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1978	/ (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1979	if (uPctDirty <= 100)
1980	SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1981	else
1982	AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1983	uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1984
1985	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1986	}
1987
1988
1989	/**
1990	* @callback_method_impl{FNSSMINTLIVEPREP}
1991	*
1992	* This will attempt to allocate and initialize the tracking structures. It
1993	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1994	* pgmR3SaveDone will do the cleanups.
1995	*/
1996	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1997	{
1998	/*
1999	* Indicate that we will be using the write monitoring.
2000	*/
2001	PGM_LOCK_VOID(pVM);
2002	/** @todo find a way of mediating this when more users are added. */
2003	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
2004	{
2005	PGM_UNLOCK(pVM);
2006	AssertLogRelFailedReturn(VERR_PGM_WRITE_MONITOR_ENGAGED);
2007	}
2008	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
2009	PGM_UNLOCK(pVM);
2010
2011	/*
2012	* Initialize the statistics.
2013	*/
2014	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
2015	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
2016	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
2017	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
2018	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
2019	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
2020	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
2021	pVM->pgm.s.LiveSave.fActive = true;
2022	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
2023	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
2024	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
2025	pVM->pgm.s.LiveSave.cSavedPages = 0;
2026	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
2027	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
2028
2029	/*
2030	* Per page type.
2031	*/
2032	int rc = pgmR3PrepRomPages(pVM);
2033	if (RT_SUCCESS(rc))
2034	rc = pgmR3PrepMmio2Pages(pVM);
2035	if (RT_SUCCESS(rc))
2036	rc = pgmR3PrepRamPages(pVM);
2037
2038	NOREF(pSSM);
2039	return rc;
2040	}
2041
2042
2043	/**
2044	* @callback_method_impl{FNSSMINTSAVEEXEC}
2045	*/
2046	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2047	{
2048	PPGM pPGM = &pVM->pgm.s;
2049
2050	/*
2051	* Lock PGM and set the no-more-writes indicator.
2052	*/
2053	PGM_LOCK_VOID(pVM);
2054	pVM->pgm.s.fNoMorePhysWrites = true;
2055
2056	/*
2057	* Save basic data (required / unaffected by relocation).
2058	*/
2059	int rc = SSMR3PutStructEx(pSSM, pPGM, sizeof(pPGM), 0 /fFlags/, &s_aPGMFields[0], NULL /pvUser*/);
2060
2061	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus && RT_SUCCESS(rc); idCpu++)
2062	rc = SSMR3PutStruct(pSSM, &pVM->apCpusR3[idCpu]->pgm.s, &s_aPGMCpuFields[0]);
2063
2064	/*
2065	* Save the (remainder of the) memory.
2066	*/
2067	if (RT_SUCCESS(rc))
2068	{
2069	if (pVM->pgm.s.LiveSave.fActive)
2070	{
2071	pgmR3ScanRomPages(pVM);
2072	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2073	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2074
2075	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2076	if (RT_SUCCESS(rc))
2077	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2078	if (RT_SUCCESS(rc))
2079	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2080	}
2081	else
2082	{
2083	rc = pgmR3SaveRamConfig(pVM, pSSM);
2084	if (RT_SUCCESS(rc))
2085	rc = pgmR3SaveRomRanges(pVM, pSSM);
2086	if (RT_SUCCESS(rc))
2087	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2088	if (RT_SUCCESS(rc))
2089	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2090	if (RT_SUCCESS(rc))
2091	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2092	if (RT_SUCCESS(rc))
2093	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2094	if (RT_SUCCESS(rc))
2095	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2096	}
2097	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2098	}
2099
2100	PGM_UNLOCK(pVM);
2101	return rc;
2102	}
2103
2104
2105	/**
2106	* @callback_method_impl{FNSSMINTSAVEDONE}
2107	*/
2108	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2109	{
2110	/*
2111	* Do per page type cleanups first.
2112	*/
2113	if (pVM->pgm.s.LiveSave.fActive)
2114	{
2115	pgmR3DoneRomPages(pVM);
2116	pgmR3DoneMmio2Pages(pVM);
2117	pgmR3DoneRamPages(pVM);
2118	}
2119
2120	/*
2121	* Clear the live save indicator and disengage write monitoring.
2122	*/
2123	PGM_LOCK_VOID(pVM);
2124	pVM->pgm.s.LiveSave.fActive = false;
2125	/** @todo this is blindly assuming that we're the only user of write
2126	* monitoring. Fix this when more users are added. */
2127	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2128	PGM_UNLOCK(pVM);
2129
2130	NOREF(pSSM);
2131	return VINF_SUCCESS;
2132	}
2133
2134
2135	/**
2136	* @callback_method_impl{FNSSMINTLOADPREP}
2137	*/
2138	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2139	{
2140	/*
2141	* Call the reset function to make sure all the memory is cleared.
2142	*/
2143	PGMR3Reset(pVM);
2144	pVM->pgm.s.LiveSave.fActive = false;
2145	NOREF(pSSM);
2146	return VINF_SUCCESS;
2147	}
2148
2149
2150	/**
2151	* Load an ignored page.
2152	*
2153	* @returns VBox status code.
2154	* @param pSSM The saved state handle.
2155	*/
2156	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2157	{
2158	uint8_t abPage[GUEST_PAGE_SIZE];
2159	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2160	}
2161
2162
2163	/**
2164	* Compares a page with an old save type value.
2165	*
2166	* @returns true if equal, false if not.
2167	* @param pPage The page to compare.
2168	* @param uOldType The old type value from the saved state.
2169	*/
2170	DECLINLINE(bool) pgmR3CompareNewAndOldPageTypes(PPGMPAGE pPage, uint8_t uOldType)
2171	{
2172	uint8_t uOldPageType;
2173	switch (PGM_PAGE_GET_TYPE(pPage))
2174	{
2175	case PGMPAGETYPE_INVALID: uOldPageType = PGMPAGETYPE_OLD_INVALID; break;
2176	case PGMPAGETYPE_RAM: uOldPageType = PGMPAGETYPE_OLD_RAM; break;
2177	case PGMPAGETYPE_MMIO2: uOldPageType = PGMPAGETYPE_OLD_MMIO2; break;
2178	case PGMPAGETYPE_MMIO2_ALIAS_MMIO: uOldPageType = PGMPAGETYPE_OLD_MMIO2_ALIAS_MMIO; break;
2179	case PGMPAGETYPE_ROM_SHADOW: uOldPageType = PGMPAGETYPE_OLD_ROM_SHADOW; break;
2180	case PGMPAGETYPE_ROM: uOldPageType = PGMPAGETYPE_OLD_ROM; break;
2181	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: RT_FALL_THRU();
2182	case PGMPAGETYPE_MMIO: uOldPageType = PGMPAGETYPE_OLD_MMIO; break;
2183	default:
2184	AssertFailed();
2185	uOldPageType = PGMPAGETYPE_OLD_INVALID;
2186	break;
2187	}
2188	return uOldPageType == uOldType;
2189	}
2190
2191
2192	/**
2193	* Loads a page without any bits in the saved state, i.e. making sure it's
2194	* really zero.
2195	*
2196	* @returns VBox status code.
2197	* @param pVM The cross context VM structure.
2198	* @param uOldType The page type or PGMPAGETYPE_OLD_INVALID (old saved
2199	* state).
2200	* @param pPage The guest page tracking structure.
2201	* @param GCPhys The page address.
2202	* @param pRam The ram range (logging).
2203	*/
2204	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2205	{
2206	if ( uOldType != PGMPAGETYPE_OLD_INVALID
2207	&& !pgmR3CompareNewAndOldPageTypes(pPage, uOldType))
2208	return VERR_SSM_UNEXPECTED_DATA;
2209
2210	/* I think this should be sufficient. */
2211	if ( !PGM_PAGE_IS_ZERO(pPage)
2212	&& !PGM_PAGE_IS_BALLOONED(pPage))
2213	return VERR_SSM_UNEXPECTED_DATA;
2214
2215	NOREF(pVM);
2216	NOREF(GCPhys);
2217	NOREF(pRam);
2218	return VINF_SUCCESS;
2219	}
2220
2221
2222	/**
2223	* Loads a page from the saved state.
2224	*
2225	* @returns VBox status code.
2226	* @param pVM The cross context VM structure.
2227	* @param pSSM The SSM handle.
2228	* @param uOldType The page type or PGMPAGETYPE_OLD_INVALID (old saved
2229	* state).
2230	* @param pPage The guest page tracking structure.
2231	* @param GCPhys The page address.
2232	* @param pRam The ram range (logging).
2233	*/
2234	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2235	{
2236	/*
2237	* Match up the type, dealing with MMIO2 aliases (dropped).
2238	*/
2239	AssertLogRelMsgReturn( uOldType == PGMPAGETYPE_INVALID
2240	\|\| pgmR3CompareNewAndOldPageTypes(pPage, uOldType)
2241	/* kudge for the expanded PXE bios (r67885) - @bugref{5687}: */
2242	\|\| ( uOldType == PGMPAGETYPE_OLD_RAM
2243	&& GCPhys >= 0xed000
2244	&& GCPhys <= 0xeffff
2245	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM)
2246	,
2247	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2248	VERR_SSM_UNEXPECTED_DATA);
2249
2250	/*
2251	* Load the page.
2252	*/
2253	PGMPAGEMAPLOCK PgMpLck;
2254	void *pvPage;
2255	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage, &PgMpLck);
2256	if (RT_SUCCESS(rc))
2257	{
2258	rc = SSMR3GetMem(pSSM, pvPage, GUEST_PAGE_SIZE);
2259	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2260	}
2261
2262	return rc;
2263	}
2264
2265
2266	/**
2267	* Loads a page (counter part to pgmR3SavePage).
2268	*
2269	* @returns VBox status code, fully bitched errors.
2270	* @param pVM The cross context VM structure.
2271	* @param pSSM The SSM handle.
2272	* @param uOldType The page type.
2273	* @param pPage The page.
2274	* @param GCPhys The page address.
2275	* @param pRam The RAM range (for error messages).
2276	*/
2277	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2278	{
2279	uint8_t uState;
2280	int rc = SSMR3GetU8(pSSM, &uState);
2281	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2282	if (uState == 0 /* zero */)
2283	rc = pgmR3LoadPageZeroOld(pVM, uOldType, pPage, GCPhys, pRam);
2284	else if (uState == 1)
2285	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uOldType, pPage, GCPhys, pRam);
2286	else
2287	rc = VERR_PGM_INVALID_SAVED_PAGE_STATE;
2288	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uOldType=%d GCPhys=%RGp %s rc=%Rrc\n",
2289	pPage, uState, uOldType, GCPhys, pRam->pszDesc, rc),
2290	rc);
2291	return VINF_SUCCESS;
2292	}
2293
2294
2295	/**
2296	* Loads a shadowed ROM page.
2297	*
2298	* @returns VBox status code, errors are fully bitched.
2299	* @param pVM The cross context VM structure.
2300	* @param pSSM The saved state handle.
2301	* @param pPage The page.
2302	* @param GCPhys The page address.
2303	* @param pRam The RAM range (for error messages).
2304	*/
2305	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2306	{
2307	/*
2308	* Load and set the protection first, then load the two pages, the first
2309	* one is the active the other is the passive.
2310	*/
2311	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2312	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2313
2314	uint8_t uProt;
2315	int rc = SSMR3GetU8(pSSM, &uProt);
2316	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2317	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2318	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2319	&& enmProt < PGMROMPROT_END,
2320	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2321	VERR_SSM_UNEXPECTED_DATA);
2322
2323	if (pRomPage->enmProt != enmProt)
2324	{
2325	rc = PGMR3PhysRomProtect(pVM, GCPhys, GUEST_PAGE_SIZE, enmProt);
2326	AssertLogRelRCReturn(rc, rc);
2327	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2328	}
2329
2330	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2331	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2332	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2333	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2334
2335	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2336	* used down the line (will the 2nd page will be written to the first
2337	* one because of a false TLB hit since the TLB is using GCPhys and
2338	* doesn't check the HCPhys of the desired page). */
2339	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2340	if (RT_SUCCESS(rc))
2341	{
2342	pPageActive = pPage;
2343	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2344	}
2345	return rc;
2346	}
2347
2348	/**
2349	* Ram range flags and bits for older versions of the saved state.
2350	*
2351	* @returns VBox status code.
2352	*
2353	* @param pVM The cross context VM structure.
2354	* @param pSSM The SSM handle.
2355	* @param uVersion The saved state version.
2356	*/
2357	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2358	{
2359	PPGM pPGM = &pVM->pgm.s;
2360
2361	/*
2362	* Ram range flags and bits.
2363	*/
2364	uint32_t i = 0;
2365	for (PPGMRAMRANGE pRam = pPGM->pRamRangesXR3; ; pRam = pRam->pNextR3, i++)
2366	{
2367	/* Check the sequence number / separator. */
2368	uint32_t u32Sep;
2369	int rc = SSMR3GetU32(pSSM, &u32Sep);
2370	if (RT_FAILURE(rc))
2371	return rc;
2372	if (u32Sep == ~0U)
2373	break;
2374	if (u32Sep != i)
2375	{
2376	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2377	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2378	}
2379	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2380
2381	/* Get the range details. */
2382	RTGCPHYS GCPhys;
2383	SSMR3GetGCPhys(pSSM, &GCPhys);
2384	RTGCPHYS GCPhysLast;
2385	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2386	RTGCPHYS cb;
2387	SSMR3GetGCPhys(pSSM, &cb);
2388	uint8_t fHaveBits;
2389	rc = SSMR3GetU8(pSSM, &fHaveBits);
2390	if (RT_FAILURE(rc))
2391	return rc;
2392	if (fHaveBits & ~1)
2393	{
2394	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2395	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2396	}
2397	size_t cchDesc = 0;
2398	char szDesc[256];
2399	szDesc[0] = '\0';
2400	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2401	{
2402	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2403	if (RT_FAILURE(rc))
2404	return rc;
2405	/* Since we've modified the description strings in r45878, only compare
2406	them if the saved state is more recent. */
2407	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2408	cchDesc = strlen(szDesc);
2409	}
2410
2411	/*
2412	* Match it up with the current range.
2413	*
2414	* Note there is a hack for dealing with the high BIOS mapping
2415	* in the old saved state format, this means we might not have
2416	* a 1:1 match on success.
2417	*/
2418	if ( ( GCPhys != pRam->GCPhys
2419	\|\| GCPhysLast != pRam->GCPhysLast
2420	\|\| cb != pRam->cb
2421	\|\| ( cchDesc
2422	&& strcmp(szDesc, pRam->pszDesc)) )
2423	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2424	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2425	\|\| GCPhys != UINT32_C(0xfff80000)
2426	\|\| GCPhysLast != UINT32_C(0xffffffff)
2427	\|\| pRam->GCPhysLast != GCPhysLast
2428	\|\| pRam->GCPhys < GCPhys
2429	\|\| !fHaveBits)
2430	)
2431	{
2432	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2433	"State : %RGp-%RGp %RGp bytes %s %s\n",
2434	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2435	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2436	/*
2437	* If we're loading a state for debugging purpose, don't make a fuss if
2438	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2439	*/
2440	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2441	\|\| GCPhys < 8 * _1M)
2442	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2443	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2444	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2445	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2446
2447	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2448	continue;
2449	}
2450
2451	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> GUEST_PAGE_SHIFT;
2452	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2453	{
2454	/*
2455	* Load the pages one by one.
2456	*/
2457	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2458	{
2459	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT) + pRam->GCPhys;
2460	PPGMPAGE pPage = &pRam->aPages[iPage];
2461	uint8_t uOldType;
2462	rc = SSMR3GetU8(pSSM, &uOldType);
2463	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2464	if (uOldType == PGMPAGETYPE_OLD_ROM_SHADOW)
2465	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2466	else
2467	rc = pgmR3LoadPageOld(pVM, pSSM, uOldType, pPage, GCPhysPage, pRam);
2468	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2469	}
2470	}
2471	else
2472	{
2473	/*
2474	* Old format.
2475	*/
2476
2477	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2478	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2479	uint32_t fFlags = 0;
2480	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2481	{
2482	uint16_t u16Flags;
2483	rc = SSMR3GetU16(pSSM, &u16Flags);
2484	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2485	fFlags \|= u16Flags;
2486	}
2487
2488	/* Load the bits */
2489	if ( !fHaveBits
2490	&& GCPhysLast < UINT32_C(0xe0000000))
2491	{
2492	/*
2493	* Dynamic chunks.
2494	*/
2495	const uint32_t cPagesInChunk = (110241024) >> GUEST_PAGE_SHIFT;
2496	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2497	("cPages=%#x cPagesInChunk=%#x GCPhys=%RGp %s\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2498	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2499
2500	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2501	{
2502	uint8_t fPresent;
2503	rc = SSMR3GetU8(pSSM, &fPresent);
2504	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2505	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2506	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2507	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2508
2509	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2510	{
2511	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT) + pRam->GCPhys;
2512	PPGMPAGE pPage = &pRam->aPages[iPage];
2513	if (fPresent)
2514	{
2515	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO
2516	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO)
2517	rc = pgmR3LoadPageToDevNullOld(pSSM);
2518	else
2519	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2520	}
2521	else
2522	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2523	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2524	}
2525	}
2526	}
2527	else if (pRam->pvR3)
2528	{
2529	/*
2530	* MMIO2.
2531	*/
2532	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2533	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2534	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2535	AssertLogRelMsgReturn(pRam->pvR3,
2536	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2537	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2538
2539	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2540	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2541	}
2542	else if (GCPhysLast < UINT32_C(0xfff80000))
2543	{
2544	/*
2545	* PCI MMIO, no pages saved.
2546	*/
2547	}
2548	else
2549	{
2550	/*
2551	* Load the 0xfff80000..0xffffffff BIOS range.
2552	* It starts with X reserved pages that we have to skip over since
2553	* the RAMRANGE create by the new code won't include those.
2554	*/
2555	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2556	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2557	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2558	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2559	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2560	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2561	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2562
2563	/* Skip wasted reserved pages before the ROM. */
2564	while (GCPhys < pRam->GCPhys)
2565	{
2566	rc = pgmR3LoadPageToDevNullOld(pSSM);
2567	AssertLogRelRCReturn(rc, rc);
2568	GCPhys += GUEST_PAGE_SIZE;
2569	}
2570
2571	/* Load the bios pages. */
2572	cPages = pRam->cb >> GUEST_PAGE_SHIFT;
2573	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2574	{
2575	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT) + pRam->GCPhys;
2576	PPGMPAGE pPage = &pRam->aPages[iPage];
2577
2578	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2579	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2580	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2581	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2582	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2583	}
2584	}
2585	}
2586	}
2587
2588	return VINF_SUCCESS;
2589	}
2590
2591
2592	/**
2593	* Worker for pgmR3Load and pgmR3LoadLocked.
2594	*
2595	* @returns VBox status code.
2596	*
2597	* @param pVM The cross context VM structure.
2598	* @param pSSM The SSM handle.
2599	* @param uVersion The PGM saved state unit version.
2600	* @param uPass The pass number.
2601	*
2602	* @todo This needs splitting up if more record types or code twists are
2603	* added...
2604	*/
2605	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2606	{
2607	NOREF(uPass);
2608
2609	/*
2610	* Process page records until we hit the terminator.
2611	*/
2612	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2613	PPGMRAMRANGE pRamHint = NULL;
2614	uint8_t id = UINT8_MAX;
2615	uint32_t iPage = UINT32_MAX - 10;
2616	PPGMROMRANGE pRom = NULL;
2617	PPGMREGMMIO2RANGE pRegMmio = NULL;
2618
2619	/*
2620	* We batch up pages that should be freed instead of calling GMM for
2621	* each and every one of them. Note that we'll lose the pages in most
2622	* failure paths - this should probably be addressed one day.
2623	*/
2624	uint32_t cPendingPages = 0;
2625	PGMMFREEPAGESREQ pReq;
2626	int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2627	AssertLogRelRCReturn(rc, rc);
2628
2629	for (;;)
2630	{
2631	/*
2632	* Get the record type and flags.
2633	*/
2634	uint8_t u8;
2635	rc = SSMR3GetU8(pSSM, &u8);
2636	if (RT_FAILURE(rc))
2637	return rc;
2638	if (u8 == PGM_STATE_REC_END)
2639	{
2640	/*
2641	* Finish off any pages pending freeing.
2642	*/
2643	if (cPendingPages)
2644	{
2645	Log(("pgmR3LoadMemory: GMMR3FreePagesPerform pVM=%p cPendingPages=%u\n", pVM, cPendingPages));
2646	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2647	AssertLogRelRCReturn(rc, rc);
2648	}
2649	GMMR3FreePagesCleanup(pReq);
2650	return VINF_SUCCESS;
2651	}
2652	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2653	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2654	{
2655	/*
2656	* RAM page.
2657	*/
2658	case PGM_STATE_REC_RAM_ZERO:
2659	case PGM_STATE_REC_RAM_RAW:
2660	case PGM_STATE_REC_RAM_BALLOONED:
2661	{
2662	/*
2663	* Get the address and resolve it into a page descriptor.
2664	*/
2665	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2666	GCPhys += GUEST_PAGE_SIZE;
2667	else
2668	{
2669	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2670	if (RT_FAILURE(rc))
2671	return rc;
2672	}
2673	AssertLogRelMsgReturn(!(GCPhys & GUEST_PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2674
2675	PPGMPAGE pPage;
2676	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
2677	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2678
2679	/*
2680	* Take action according to the record type.
2681	*/
2682	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2683	{
2684	case PGM_STATE_REC_RAM_ZERO:
2685	{
2686	if (PGM_PAGE_IS_ZERO(pPage))
2687	break;
2688
2689	/* Ballooned pages must be unmarked (live snapshot and
2690	teleportation scenarios). */
2691	if (PGM_PAGE_IS_BALLOONED(pPage))
2692	{
2693	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2694	if (uVersion == PGM_SAVED_STATE_VERSION_BALLOON_BROKEN)
2695	break;
2696	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2697	break;
2698	}
2699
2700	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_UNEXPECTED_PAGE_STATE);
2701
2702	/* If this is a ROM page, we must clear it and not try to
2703	* free it. Ditto if the VM is using RamPreAlloc (see
2704	* @bugref{6318}). */
2705	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM
2706	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM_SHADOW
2707	#ifdef VBOX_WITH_PGM_NEM_MODE
2708	\|\| pVM->pgm.s.fNemMode
2709	#endif
2710	\|\| pVM->pgm.s.fRamPreAlloc)
2711	{
2712	PGMPAGEMAPLOCK PgMpLck;
2713	void *pvDstPage;
2714	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2715	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2716
2717	RT_BZERO(pvDstPage, GUEST_PAGE_SIZE);
2718	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2719	}
2720	/* Free it only if it's not part of a previously
2721	allocated large page (no need to clear the page). */
2722	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2723	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2724	{
2725	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys, (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
2726	AssertRCReturn(rc, rc);
2727	}
2728	/** @todo handle large pages (see @bugref{5545}) */
2729	break;
2730	}
2731
2732	case PGM_STATE_REC_RAM_BALLOONED:
2733	{
2734	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2735	if (PGM_PAGE_IS_BALLOONED(pPage))
2736	break;
2737
2738	/* We don't map ballooned pages in our shadow page tables, let's
2739	just free it if allocated and mark as ballooned. See @bugref{5515}. */
2740	if (PGM_PAGE_IS_ALLOCATED(pPage))
2741	{
2742	/** @todo handle large pages + ballooning when it works. (see @bugref{5515},
2743	* @bugref{5545}). */
2744	AssertLogRelMsgReturn( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2745	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED,
2746	("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_LOAD_UNEXPECTED_PAGE_TYPE);
2747
2748	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys, (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
2749	AssertRCReturn(rc, rc);
2750	}
2751	Assert(PGM_PAGE_IS_ZERO(pPage));
2752	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
2753	break;
2754	}
2755
2756	case PGM_STATE_REC_RAM_RAW:
2757	{
2758	PGMPAGEMAPLOCK PgMpLck;
2759	void *pvDstPage;
2760	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2761	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2762	rc = SSMR3GetMem(pSSM, pvDstPage, GUEST_PAGE_SIZE);
2763	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2764	if (RT_FAILURE(rc))
2765	return rc;
2766	break;
2767	}
2768
2769	default:
2770	AssertMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2771	}
2772	id = UINT8_MAX;
2773	break;
2774	}
2775
2776	/*
2777	* MMIO2 page.
2778	*/
2779	case PGM_STATE_REC_MMIO2_RAW:
2780	case PGM_STATE_REC_MMIO2_ZERO:
2781	{
2782	/*
2783	* Get the ID + page number and resolved that into a MMIO2 page.
2784	*/
2785	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2786	iPage++;
2787	else
2788	{
2789	SSMR3GetU8(pSSM, &id);
2790	rc = SSMR3GetU32(pSSM, &iPage);
2791	if (RT_FAILURE(rc))
2792	return rc;
2793	}
2794	if ( !pRegMmio
2795	\|\| pRegMmio->idSavedState != id)
2796	{
2797	for (pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
2798	if (pRegMmio->idSavedState == id)
2799	break;
2800	AssertLogRelMsgReturn(pRegMmio, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_MMIO2_RANGE_NOT_FOUND);
2801	}
2802	AssertLogRelMsgReturn(iPage < (pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT),
2803	("iPage=%#x cb=%RGp %s\n", iPage, pRegMmio->RamRange.cb, pRegMmio->RamRange.pszDesc),
2804	VERR_PGM_SAVED_MMIO2_PAGE_NOT_FOUND);
2805	void pvDstPage = (uint8_t )pRegMmio->RamRange.pvR3 + ((size_t)iPage << GUEST_PAGE_SHIFT);
2806
2807	/*
2808	* Load the page bits.
2809	*/
2810	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2811	RT_BZERO(pvDstPage, GUEST_PAGE_SIZE);
2812	else
2813	{
2814	rc = SSMR3GetMem(pSSM, pvDstPage, GUEST_PAGE_SIZE);
2815	if (RT_FAILURE(rc))
2816	return rc;
2817	}
2818	GCPhys = NIL_RTGCPHYS;
2819	break;
2820	}
2821
2822	/*
2823	* ROM pages.
2824	*/
2825	case PGM_STATE_REC_ROM_VIRGIN:
2826	case PGM_STATE_REC_ROM_SHW_RAW:
2827	case PGM_STATE_REC_ROM_SHW_ZERO:
2828	case PGM_STATE_REC_ROM_PROT:
2829	{
2830	/*
2831	* Get the ID + page number and resolved that into a ROM page descriptor.
2832	*/
2833	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2834	iPage++;
2835	else
2836	{
2837	SSMR3GetU8(pSSM, &id);
2838	rc = SSMR3GetU32(pSSM, &iPage);
2839	if (RT_FAILURE(rc))
2840	return rc;
2841	}
2842	if ( !pRom
2843	\|\| pRom->idSavedState != id)
2844	{
2845	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2846	if (pRom->idSavedState == id)
2847	break;
2848	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_ROM_RANGE_NOT_FOUND);
2849	}
2850	AssertLogRelMsgReturn(iPage < (pRom->cb >> GUEST_PAGE_SHIFT),
2851	("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc),
2852	VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2853	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2854	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
2855
2856	/*
2857	* Get and set the protection.
2858	*/
2859	uint8_t u8Prot;
2860	rc = SSMR3GetU8(pSSM, &u8Prot);
2861	if (RT_FAILURE(rc))
2862	return rc;
2863	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2864	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_PGM_SAVED_ROM_PAGE_PROT);
2865
2866	if (enmProt != pRomPage->enmProt)
2867	{
2868	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2869	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2870	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2871	GCPhys, enmProt, pRom->pszDesc);
2872	rc = PGMR3PhysRomProtect(pVM, GCPhys, GUEST_PAGE_SIZE, enmProt);
2873	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2874	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2875	}
2876	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2877	break; /* done */
2878
2879	/*
2880	* Get the right page descriptor.
2881	*/
2882	PPGMPAGE pRealPage;
2883	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2884	{
2885	case PGM_STATE_REC_ROM_VIRGIN:
2886	if (!PGMROMPROT_IS_ROM(enmProt))
2887	pRealPage = &pRomPage->Virgin;
2888	else
2889	pRealPage = NULL;
2890	break;
2891
2892	case PGM_STATE_REC_ROM_SHW_RAW:
2893	case PGM_STATE_REC_ROM_SHW_ZERO:
2894	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2895	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2896	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2897	GCPhys, enmProt, pRom->pszDesc);
2898	if (PGMROMPROT_IS_ROM(enmProt))
2899	pRealPage = &pRomPage->Shadow;
2900	else
2901	pRealPage = NULL;
2902	break;
2903
2904	default: AssertLogRelFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE); /* shut up gcc */
2905	}
2906	#ifdef VBOX_WITH_PGM_NEM_MODE
2907	bool const fAltPage = pRealPage != NULL;
2908	#endif
2909	if (!pRealPage)
2910	{
2911	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pRealPage, &pRamHint);
2912	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2913	}
2914
2915	/*
2916	* Make it writable and map it (if necessary).
2917	*/
2918	void *pvDstPage = NULL;
2919	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2920	{
2921	case PGM_STATE_REC_ROM_SHW_ZERO:
2922	if ( PGM_PAGE_IS_ZERO(pRealPage)
2923	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2924	break;
2925	/** @todo implement zero page replacing. */
2926	RT_FALL_THRU();
2927	case PGM_STATE_REC_ROM_VIRGIN:
2928	case PGM_STATE_REC_ROM_SHW_RAW:
2929	#ifdef VBOX_WITH_PGM_NEM_MODE
2930	if (fAltPage && pVM->pgm.s.fNemMode)
2931	pvDstPage = &pRom->pbR3Alternate[iPage << GUEST_PAGE_SHIFT];
2932	else
2933	#endif
2934	{
2935	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2936	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2937	}
2938	break;
2939	}
2940
2941	/*
2942	* Load the bits.
2943	*/
2944	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2945	{
2946	case PGM_STATE_REC_ROM_SHW_ZERO:
2947	if (pvDstPage)
2948	RT_BZERO(pvDstPage, GUEST_PAGE_SIZE);
2949	break;
2950
2951	case PGM_STATE_REC_ROM_VIRGIN:
2952	case PGM_STATE_REC_ROM_SHW_RAW:
2953	rc = SSMR3GetMem(pSSM, pvDstPage, GUEST_PAGE_SIZE);
2954	if (RT_FAILURE(rc))
2955	return rc;
2956	break;
2957	}
2958	GCPhys = NIL_RTGCPHYS;
2959	break;
2960	}
2961
2962	/*
2963	* Unknown type.
2964	*/
2965	default:
2966	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2967	}
2968	} /* forever */
2969	}
2970
2971
2972	/**
2973	* Worker for pgmR3Load.
2974	*
2975	* @returns VBox status code.
2976	*
2977	* @param pVM The cross context VM structure.
2978	* @param pSSM The SSM handle.
2979	* @param uVersion The saved state version.
2980	*/
2981	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2982	{
2983	PPGM pPGM = &pVM->pgm.s;
2984	int rc;
2985	uint32_t u32Sep;
2986
2987	/*
2988	* Load basic data (required / unaffected by relocation).
2989	*/
2990	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2991	{
2992	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2993	rc = SSMR3GetStructEx(pSSM, pPGM, sizeof(pPGM), 0 /fFlags/, &s_aPGMFields[0], NULL /pvUser*/);
2994	else
2995	rc = SSMR3GetStructEx(pSSM, pPGM, sizeof(pPGM), 0 /fFlags/, &s_aPGMFieldsPreBalloon[0], NULL /pvUser*/);
2996
2997	AssertLogRelRCReturn(rc, rc);
2998
2999	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3000	{
3001	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
3002	rc = SSMR3GetStruct(pSSM, &pVM->apCpusR3[i]->pgm.s, &s_aPGMCpuFieldsPrePae[0]);
3003	else
3004	rc = SSMR3GetStruct(pSSM, &pVM->apCpusR3[i]->pgm.s, &s_aPGMCpuFields[0]);
3005	AssertLogRelRCReturn(rc, rc);
3006	}
3007	}
3008	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
3009	{
3010	AssertRelease(pVM->cCpus == 1);
3011
3012	PGMOLD pgmOld;
3013	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
3014	AssertLogRelRCReturn(rc, rc);
3015
3016	PVMCPU pVCpu0 = pVM->apCpusR3[0];
3017	pVCpu0->pgm.s.fA20Enabled = pgmOld.fA20Enabled;
3018	pVCpu0->pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
3019	pVCpu0->pgm.s.enmGuestMode = pgmOld.enmGuestMode;
3020	}
3021	else
3022	{
3023	AssertRelease(pVM->cCpus == 1);
3024
3025	SSMR3Skip(pSSM, sizeof(bool));
3026	RTGCPTR GCPtrIgn;
3027	SSMR3GetGCPtr(pSSM, &GCPtrIgn);
3028	SSMR3Skip(pSSM, sizeof(uint32_t));
3029
3030	uint32_t cbRamSizeIgnored;
3031	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
3032	if (RT_FAILURE(rc))
3033	return rc;
3034	PVMCPU pVCpu0 = pVM->apCpusR3[0];
3035	SSMR3GetGCPhys(pSSM, &pVCpu0->pgm.s.GCPhysA20Mask);
3036
3037	uint32_t u32 = 0;
3038	SSMR3GetUInt(pSSM, &u32);
3039	pVCpu0->pgm.s.fA20Enabled = !!u32;
3040	SSMR3GetUInt(pSSM, &pVCpu0->pgm.s.fSyncFlags);
3041	RTUINT uGuestMode;
3042	SSMR3GetUInt(pSSM, &uGuestMode);
3043	pVCpu0->pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
3044
3045	/* check separator. */
3046	SSMR3GetU32(pSSM, &u32Sep);
3047	if (RT_FAILURE(rc))
3048	return rc;
3049	if (u32Sep != (uint32_t)~0)
3050	{
3051	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
3052	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3053	}
3054	}
3055
3056	/*
3057	* Fix the A20 mask.
3058	*/
3059	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3060	{
3061	PVMCPU pVCpu = pVM->apCpusR3[i];
3062	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
3063	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
3064	}
3065
3066	/*
3067	* The guest mappings - skipped now, see re-fixation in the caller.
3068	*/
3069	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
3070	{
3071	for (uint32_t i = 0; ; i++)
3072	{
3073	rc = SSMR3GetU32(pSSM, &u32Sep); /* sequence number */
3074	if (RT_FAILURE(rc))
3075	return rc;
3076	if (u32Sep == ~0U)
3077	break;
3078	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3079
3080	char szDesc[256];
3081	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
3082	if (RT_FAILURE(rc))
3083	return rc;
3084	RTGCPTR GCPtrIgnore;
3085	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
3086	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
3087	if (RT_FAILURE(rc))
3088	return rc;
3089	}
3090	}
3091
3092	/*
3093	* Load the RAM contents.
3094	*/
3095	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
3096	{
3097	if (!pVM->pgm.s.LiveSave.fActive)
3098	{
3099	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3100	{
3101	rc = pgmR3LoadRamConfig(pVM, pSSM);
3102	if (RT_FAILURE(rc))
3103	return rc;
3104	}
3105	rc = pgmR3LoadRomRanges(pVM, pSSM);
3106	if (RT_FAILURE(rc))
3107	return rc;
3108	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3109	if (RT_FAILURE(rc))
3110	return rc;
3111	}
3112
3113	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, SSM_PASS_FINAL);
3114	}
3115	else
3116	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
3117
3118	/* Refresh balloon accounting. */
3119	if (pVM->pgm.s.cBalloonedPages)
3120	{
3121	Log(("pgmR3LoadFinalLocked: pVM=%p cBalloonedPages=%#x\n", pVM, pVM->pgm.s.cBalloonedPages));
3122	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
3123	AssertRCReturn(rc, rc);
3124	}
3125	return rc;
3126	}
3127
3128
3129	/**
3130	* @callback_method_impl{FNSSMINTLOADEXEC}
3131	*/
3132	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3133	{
3134	int rc;
3135
3136	/*
3137	* Validate version.
3138	*/
3139	if ( ( uPass != SSM_PASS_FINAL
3140	&& uVersion != PGM_SAVED_STATE_VERSION
3141	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3142	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3143	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3144	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3145	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
3146	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3147	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3148	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3149	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
3150	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
3151	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3152	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3153	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3154	)
3155	{
3156	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3157	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3158	}
3159
3160	/*
3161	* Do the loading while owning the lock because a bunch of the functions
3162	* we're using requires this.
3163	*/
3164	if (uPass != SSM_PASS_FINAL)
3165	{
3166	PGM_LOCK_VOID(pVM);
3167	if (uPass != 0)
3168	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3169	else
3170	{
3171	pVM->pgm.s.LiveSave.fActive = true;
3172	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3173	rc = pgmR3LoadRamConfig(pVM, pSSM);
3174	else
3175	rc = VINF_SUCCESS;
3176	if (RT_SUCCESS(rc))
3177	rc = pgmR3LoadRomRanges(pVM, pSSM);
3178	if (RT_SUCCESS(rc))
3179	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3180	if (RT_SUCCESS(rc))
3181	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3182	}
3183	PGM_UNLOCK(pVM);
3184	}
3185	else
3186	{
3187	PGM_LOCK_VOID(pVM);
3188	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3189	pVM->pgm.s.LiveSave.fActive = false;
3190	PGM_UNLOCK(pVM);
3191	if (RT_SUCCESS(rc))
3192	{
3193	/*
3194	* We require a full resync now.
3195	*/
3196	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3197	{
3198	PVMCPU pVCpu = pVM->apCpusR3[i];
3199	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3200	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3201	/** @todo For guest PAE, we might get the wrong
3202	* aGCPhysGstPaePDs values now. We should used the
3203	* saved ones... Postponing this since it nothing new
3204	* and PAE/PDPTR needs some general readjusting, see
3205	* @bugref{5880}. */
3206	}
3207
3208	pgmR3HandlerPhysicalUpdateAll(pVM);
3209
3210	/*
3211	* Change the paging mode (indirectly restores PGMCPU::GCPhysCR3).
3212	* (Requires the CPUM state to be restored already!)
3213	*/
3214	if (CPUMR3IsStateRestorePending(pVM))
3215	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3216	N_("PGM was unexpectedly restored before CPUM"));
3217
3218	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3219	{
3220	PVMCPU pVCpu = pVM->apCpusR3[i];
3221
3222	rc = PGMHCChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode, false /* fForce */);
3223	AssertLogRelRCReturn(rc, rc);
3224
3225	#if !defined(VBOX_VMM_TARGET_ARMV8)
3226	/* Update the PSE, NX flags and validity masks. */
3227	pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3228	PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3229	#endif
3230	}
3231	}
3232	}
3233
3234	return rc;
3235	}
3236
3237
3238	/**
3239	* @callback_method_impl{FNSSMINTLOADDONE}
3240	*/
3241	static DECLCALLBACK(int) pgmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3242	{
3243	pVM->pgm.s.fRestoreRomPagesOnReset = true;
3244	NOREF(pSSM);
3245	return VINF_SUCCESS;
3246	}
3247
3248
3249	/**
3250	* Registers the saved state callbacks with SSM.
3251	*
3252	* @returns VBox status code.
3253	* @param pVM The cross context VM structure.
3254	* @param cbRam The RAM size.
3255	*/
3256	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3257	{
3258	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3259	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3260	NULL, pgmR3SaveExec, pgmR3SaveDone,
3261	pgmR3LoadPrep, pgmR3Load, pgmR3LoadDone);
3262	}
3263

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMSavedState.cpp@ 104557

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