PGMSavedState.cpp@ 102828

Last change on this file since 102828 was 99051, checked in by vboxsync, 22 months ago
VMM: More ARMv8 x86/amd64 separation work, VBoxVMMArm compiles and links now, bugref:10385
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1	/* $Id: PGMSavedState.cpp 99051 2023-03-19 16:40:06Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_PGM
33	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
34	#include <VBox/vmm/pgm.h>
35	#include <VBox/vmm/stam.h>
36	#include <VBox/vmm/ssm.h>
37	#include <VBox/vmm/pdmdrv.h>
38	#include <VBox/vmm/pdmdev.h>
39	#include "PGMInternal.h"
40	#include <VBox/vmm/vmcc.h>
41	#include "PGMInline.h"
42
43	#include <VBox/param.h>
44	#include <VBox/err.h>
45
46	#include <iprt/asm.h>
47	#include <iprt/assert.h>
48	#include <iprt/crc.h>
49	#include <iprt/mem.h>
50	#include <iprt/sha.h>
51	#include <iprt/string.h>
52	#include <iprt/thread.h>
53
54
55	/*********************************************************************************************************************************
56	* Defined Constants And Macros *
57	*********************************************************************************************************************************/
58	/** Saved state data unit version. */
59	#define PGM_SAVED_STATE_VERSION 14
60	/** Saved state data unit version before the PAE PDPE registers. */
61	#define PGM_SAVED_STATE_VERSION_PRE_PAE 13
62	/** Saved state data unit version after this includes ballooned page flags in
63	* the state (see @bugref{5515}). */
64	#define PGM_SAVED_STATE_VERSION_BALLOON_BROKEN 12
65	/** Saved state before the balloon change. */
66	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
67	/** Saved state data unit version used during 3.1 development, misses the RAM
68	* config. */
69	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
70	/** Saved state data unit version for 3.0 (pre teleportation). */
71	#define PGM_SAVED_STATE_VERSION_3_0_0 9
72	/** Saved state data unit version for 2.2.2 and later. */
73	#define PGM_SAVED_STATE_VERSION_2_2_2 8
74	/** Saved state data unit version for 2.2.0. */
75	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
76	/** Saved state data unit version. */
77	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
78
79
80	/** @name Sparse state record types
81	* @{ */
82	/** Zero page. No data. */
83	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
84	/** Raw page. */
85	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
86	/** Raw MMIO2 page. */
87	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
88	/** Zero MMIO2 page. */
89	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
90	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
91	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
92	/** Raw shadowed ROM page. The protection (8-bit) precedes the raw bits. */
93	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
94	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
95	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
96	/** ROM protection (8-bit). */
97	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
98	/** Ballooned page. No data. */
99	#define PGM_STATE_REC_RAM_BALLOONED UINT8_C(0x08)
100	/** The last record type. */
101	#define PGM_STATE_REC_LAST PGM_STATE_REC_RAM_BALLOONED
102	/** End marker. */
103	#define PGM_STATE_REC_END UINT8_C(0xff)
104	/** Flag indicating that the data is preceded by the page address.
105	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
106	* range ID and a 32-bit page index.
107	*/
108	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
109	/** @} */
110
111	/** The CRC-32 for a zero page. */
112	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
113	/** The CRC-32 for a zero half page. */
114	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
115
116
117
118	/** @name Old Page types used in older saved states.
119	* @{ */
120	/** Old saved state: The usual invalid zero entry. */
121	#define PGMPAGETYPE_OLD_INVALID 0
122	/** Old saved state: RAM page. (RWX) */
123	#define PGMPAGETYPE_OLD_RAM 1
124	/** Old saved state: MMIO2 page. (RWX) */
125	#define PGMPAGETYPE_OLD_MMIO2 1
126	/** Old saved state: MMIO2 page aliased over an MMIO page. (RWX)
127	* See PGMHandlerPhysicalPageAlias(). */
128	#define PGMPAGETYPE_OLD_MMIO2_ALIAS_MMIO 2
129	/** Old saved state: Shadowed ROM. (RWX) */
130	#define PGMPAGETYPE_OLD_ROM_SHADOW 3
131	/** Old saved state: ROM page. (R-X) */
132	#define PGMPAGETYPE_OLD_ROM 4
133	/** Old saved state: MMIO page. (---) */
134	#define PGMPAGETYPE_OLD_MMIO 5
135	/** @} */
136
137
138	/*********************************************************************************************************************************
139	* Structures and Typedefs *
140	*********************************************************************************************************************************/
141	/** For loading old saved states. (pre-smp) */
142	typedef struct
143	{
144	/** If set no conflict checks are required. (boolean) */
145	bool fMappingsFixed;
146	/** Size of fixed mapping */
147	uint32_t cbMappingFixed;
148	/** Base address (GC) of fixed mapping */
149	RTGCPTR GCPtrMappingFixed;
150	/** A20 gate mask.
151	* Our current approach to A20 emulation is to let REM do it and don't bother
152	* anywhere else. The interesting guests will be operating with it enabled anyway.
153	* But should the need arise, we'll subject physical addresses to this mask. */
154	RTGCPHYS GCPhysA20Mask;
155	/** A20 gate state - boolean! */
156	bool fA20Enabled;
157	/** The guest paging mode. */
158	PGMMODE enmGuestMode;
159	} PGMOLD;
160
161
162	/*********************************************************************************************************************************
163	* Global Variables *
164	*********************************************************************************************************************************/
165	/** PGM fields to save/load. */
166
167	static const SSMFIELD s_aPGMFields[] =
168	{
169	SSMFIELD_ENTRY_OLD( fMappingsFixed, sizeof(bool)),
170	SSMFIELD_ENTRY_OLD_GCPTR( GCPtrMappingFixed),
171	SSMFIELD_ENTRY_OLD( cbMappingFixed, sizeof(uint32_t)),
172	SSMFIELD_ENTRY( PGM, cBalloonedPages),
173	SSMFIELD_ENTRY_TERM()
174	};
175
176	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
177	{
178	SSMFIELD_ENTRY_OLD( fMappingsFixed, sizeof(bool)),
179	SSMFIELD_ENTRY_OLD_GCPTR( GCPtrMappingFixed),
180	SSMFIELD_ENTRY_OLD( cbMappingFixed, sizeof(uint32_t)),
181	SSMFIELD_ENTRY_TERM()
182	};
183
184	static const SSMFIELD s_aPGMCpuFields[] =
185	{
186	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
187	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
188	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
189	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[0]),
190	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[1]),
191	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[2]),
192	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[3]),
193	SSMFIELD_ENTRY_TERM()
194	};
195
196	static const SSMFIELD s_aPGMCpuFieldsPrePae[] =
197	{
198	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
199	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
200	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
201	SSMFIELD_ENTRY_TERM()
202	};
203
204	static const SSMFIELD s_aPGMFields_Old[] =
205	{
206	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
207	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
208	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
209	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
210	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
211	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
212	SSMFIELD_ENTRY_TERM()
213	};
214
215
216	/**
217	* Find the ROM tracking structure for the given page.
218	*
219	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
220	* that it's a ROM page.
221	* @param pVM The cross context VM structure.
222	* @param GCPhys The address of the ROM page.
223	*/
224	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
225	{
226	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
227	pRomRange;
228	pRomRange = pRomRange->CTX_SUFF(pNext))
229	{
230	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
231	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
232	return &pRomRange->aPages[off >> GUEST_PAGE_SHIFT];
233	}
234	return NULL;
235	}
236
237
238	/**
239	* Prepares the ROM pages for a live save.
240	*
241	* @returns VBox status code.
242	* @param pVM The cross context VM structure.
243	*/
244	static int pgmR3PrepRomPages(PVM pVM)
245	{
246	/*
247	* Initialize the live save tracking in the ROM page descriptors.
248	*/
249	PGM_LOCK_VOID(pVM);
250	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
251	{
252	PPGMRAMRANGE pRamHint = NULL;;
253	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
254
255	for (uint32_t iPage = 0; iPage < cPages; iPage++)
256	{
257	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
258	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
259	pRom->aPages[iPage].LiveSave.fDirty = true;
260	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
261	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
262	{
263	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
264	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
265	else
266	{
267	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
268	PPGMPAGE pPage;
269	int rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
270	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
271	if (RT_SUCCESS(rc))
272	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
273	else
274	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
275	}
276	}
277	}
278
279	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
280	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
281	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
282	}
283	PGM_UNLOCK(pVM);
284
285	return VINF_SUCCESS;
286	}
287
288
289	/**
290	* Assigns IDs to the ROM ranges and saves them.
291	*
292	* @returns VBox status code.
293	* @param pVM The cross context VM structure.
294	* @param pSSM Saved state handle.
295	*/
296	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
297	{
298	PGM_LOCK_VOID(pVM);
299	uint8_t id = 1;
300	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
301	{
302	pRom->idSavedState = id;
303	SSMR3PutU8(pSSM, id);
304	SSMR3PutStrZ(pSSM, ""); /* device name */
305	SSMR3PutU32(pSSM, 0); /* device instance */
306	SSMR3PutU8(pSSM, 0); /* region */
307	SSMR3PutStrZ(pSSM, pRom->pszDesc);
308	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
309	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
310	if (RT_FAILURE(rc))
311	break;
312	}
313	PGM_UNLOCK(pVM);
314	return SSMR3PutU8(pSSM, UINT8_MAX);
315	}
316
317
318	/**
319	* Loads the ROM range ID assignments.
320	*
321	* @returns VBox status code.
322	*
323	* @param pVM The cross context VM structure.
324	* @param pSSM The saved state handle.
325	*/
326	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
327	{
328	PGM_LOCK_ASSERT_OWNER(pVM);
329
330	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
331	pRom->idSavedState = UINT8_MAX;
332
333	for (;;)
334	{
335	/*
336	* Read the data.
337	*/
338	uint8_t id;
339	int rc = SSMR3GetU8(pSSM, &id);
340	if (RT_FAILURE(rc))
341	return rc;
342	if (id == UINT8_MAX)
343	{
344	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
345	if (pRom->idSavedState != UINT8_MAX)
346	{ /* likely */ }
347	else if (pRom->fFlags & PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE)
348	LogRel(("PGM: The '%s' ROM was not found in the saved state, but it is marked as maybe-missing, so that's probably okay.\n",
349	pRom->pszDesc));
350	else
351	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
352	("The '%s' ROM was not found in the saved state. Probably due to some misconfiguration\n",
353	pRom->pszDesc));
354	return VINF_SUCCESS; /* the end */
355	}
356	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
357
358	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
359	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
360	AssertLogRelRCReturn(rc, rc);
361
362	uint32_t uInstance;
363	SSMR3GetU32(pSSM, &uInstance);
364	uint8_t iRegion;
365	SSMR3GetU8(pSSM, &iRegion);
366
367	char szDesc[64];
368	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
369	AssertLogRelRCReturn(rc, rc);
370
371	RTGCPHYS GCPhys;
372	SSMR3GetGCPhys(pSSM, &GCPhys);
373	RTGCPHYS cb;
374	rc = SSMR3GetGCPhys(pSSM, &cb);
375	if (RT_FAILURE(rc))
376	return rc;
377	AssertLogRelMsgReturn(!(GCPhys & GUEST_PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
378	AssertLogRelMsgReturn(!(cb & GUEST_PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
379
380	/*
381	* Locate a matching ROM range.
382	*/
383	AssertLogRelMsgReturn( uInstance == 0
384	&& iRegion == 0
385	&& szDevName[0] == '\0',
386	("GCPhys=%RGp %s\n", GCPhys, szDesc),
387	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
388	PPGMROMRANGE pRom;
389	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
390	{
391	if ( pRom->idSavedState == UINT8_MAX
392	&& !strcmp(pRom->pszDesc, szDesc))
393	{
394	pRom->idSavedState = id;
395	break;
396	}
397	}
398	if (!pRom)
399	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
400	} /* forever */
401	}
402
403
404	/**
405	* Scan ROM pages.
406	*
407	* @param pVM The cross context VM structure.
408	*/
409	static void pgmR3ScanRomPages(PVM pVM)
410	{
411	/*
412	* The shadow ROMs.
413	*/
414	PGM_LOCK_VOID(pVM);
415	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
416	{
417	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
418	{
419	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
420	for (uint32_t iPage = 0; iPage < cPages; iPage++)
421	{
422	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
423	if (pRomPage->LiveSave.fWrittenTo)
424	{
425	pRomPage->LiveSave.fWrittenTo = false;
426	if (!pRomPage->LiveSave.fDirty)
427	{
428	pRomPage->LiveSave.fDirty = true;
429	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
430	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
431	}
432	pRomPage->LiveSave.fDirtiedRecently = true;
433	}
434	else
435	pRomPage->LiveSave.fDirtiedRecently = false;
436	}
437	}
438	}
439	PGM_UNLOCK(pVM);
440	}
441
442
443	/**
444	* Takes care of the virgin ROM pages in the first pass.
445	*
446	* This is an attempt at simplifying the handling of ROM pages a little bit.
447	* This ASSUMES that no new ROM ranges will be added and that they won't be
448	* relinked in any way.
449	*
450	* @param pVM The cross context VM structure.
451	* @param pSSM The SSM handle.
452	* @param fLiveSave Whether we're in a live save or not.
453	*/
454	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
455	{
456	PGM_LOCK_VOID(pVM);
457	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
458	{
459	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
460	for (uint32_t iPage = 0; iPage < cPages; iPage++)
461	{
462	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
463	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
464
465	/* Get the virgin page descriptor. */
466	PPGMPAGE pPage;
467	if (PGMROMPROT_IS_ROM(enmProt))
468	pPage = pgmPhysGetPage(pVM, GCPhys);
469	else
470	pPage = &pRom->aPages[iPage].Virgin;
471
472	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
473	int rc = VINF_SUCCESS;
474	char abPage[GUEST_PAGE_SIZE];
475	if ( !PGM_PAGE_IS_ZERO(pPage)
476	&& !PGM_PAGE_IS_BALLOONED(pPage))
477	{
478	void const *pvPage;
479	#ifdef VBOX_WITH_PGM_NEM_MODE
480	if (!PGMROMPROT_IS_ROM(enmProt) && pVM->pgm.s.fNemMode)
481	pvPage = &pRom->pbR3Alternate[iPage << GUEST_PAGE_SHIFT];
482	else
483	#endif
484	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
485	if (RT_SUCCESS(rc))
486	memcpy(abPage, pvPage, GUEST_PAGE_SIZE);
487	}
488	else
489	RT_ZERO(abPage);
490	PGM_UNLOCK(pVM);
491	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
492
493	/* Save it. */
494	if (iPage > 0)
495	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
496	else
497	{
498	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
499	SSMR3PutU8(pSSM, pRom->idSavedState);
500	SSMR3PutU32(pSSM, iPage);
501	}
502	SSMR3PutU8(pSSM, (uint8_t)enmProt);
503	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
504	if (RT_FAILURE(rc))
505	return rc;
506
507	/* Update state. */
508	PGM_LOCK_VOID(pVM);
509	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
510	if (fLiveSave)
511	{
512	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
513	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
514	pVM->pgm.s.LiveSave.cSavedPages++;
515	}
516	}
517	}
518	PGM_UNLOCK(pVM);
519	return VINF_SUCCESS;
520	}
521
522
523	/**
524	* Saves dirty pages in the shadowed ROM ranges.
525	*
526	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
527	*
528	* @returns VBox status code.
529	* @param pVM The cross context VM structure.
530	* @param pSSM The SSM handle.
531	* @param fLiveSave Whether it's a live save or not.
532	* @param fFinalPass Whether this is the final pass or not.
533	*/
534	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
535	{
536	/*
537	* The Shadowed ROMs.
538	*
539	* ASSUMES that the ROM ranges are fixed.
540	* ASSUMES that all the ROM ranges are mapped.
541	*/
542	PGM_LOCK_VOID(pVM);
543	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
544	{
545	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
546	{
547	uint32_t const cPages = pRom->cb >> GUEST_PAGE_SHIFT;
548	uint32_t iPrevPage = cPages;
549	for (uint32_t iPage = 0; iPage < cPages; iPage++)
550	{
551	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
552	if ( !fLiveSave
553	\|\| ( pRomPage->LiveSave.fDirty
554	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
555	&& !pRomPage->LiveSave.fWrittenTo)
556	\|\| fFinalPass
557	)
558	)
559	)
560	{
561	uint8_t abPage[GUEST_PAGE_SIZE];
562	PGMROMPROT enmProt = pRomPage->enmProt;
563	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
564	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(pVM, GCPhys);
565	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage); Assert(!PGM_PAGE_IS_BALLOONED(pPage)); /* Shouldn't be ballooned. */
566	int rc = VINF_SUCCESS;
567	if (!fZero)
568	{
569	void const *pvPage;
570	#ifdef VBOX_WITH_PGM_NEM_MODE
571	if (PGMROMPROT_IS_ROM(enmProt) && pVM->pgm.s.fNemMode)
572	pvPage = &pRom->pbR3Alternate[iPage << GUEST_PAGE_SHIFT];
573	else
574	#endif
575	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
576	if (RT_SUCCESS(rc))
577	memcpy(abPage, pvPage, GUEST_PAGE_SIZE);
578	}
579	if (fLiveSave && RT_SUCCESS(rc))
580	{
581	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
582	pRomPage->LiveSave.fDirty = false;
583	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
584	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
585	pVM->pgm.s.LiveSave.cSavedPages++;
586	}
587	PGM_UNLOCK(pVM);
588	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
589
590	if (iPage - 1U == iPrevPage && iPage > 0)
591	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
592	else
593	{
594	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
595	SSMR3PutU8(pSSM, pRom->idSavedState);
596	SSMR3PutU32(pSSM, iPage);
597	}
598	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
599	if (!fZero)
600	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
601	if (RT_FAILURE(rc))
602	return rc;
603
604	PGM_LOCK_VOID(pVM);
605	iPrevPage = iPage;
606	}
607	/*
608	* In the final pass, make sure the protection is in sync.
609	*/
610	else if ( fFinalPass
611	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
612	{
613	PGMROMPROT enmProt = pRomPage->enmProt;
614	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
615	PGM_UNLOCK(pVM);
616
617	if (iPage - 1U == iPrevPage && iPage > 0)
618	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
619	else
620	{
621	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
622	SSMR3PutU8(pSSM, pRom->idSavedState);
623	SSMR3PutU32(pSSM, iPage);
624	}
625	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
626	if (RT_FAILURE(rc))
627	return rc;
628
629	PGM_LOCK_VOID(pVM);
630	iPrevPage = iPage;
631	}
632	}
633	}
634	}
635	PGM_UNLOCK(pVM);
636	return VINF_SUCCESS;
637	}
638
639
640	/**
641	* Cleans up ROM pages after a live save.
642	*
643	* @param pVM The cross context VM structure.
644	*/
645	static void pgmR3DoneRomPages(PVM pVM)
646	{
647	NOREF(pVM);
648	}
649
650
651	/**
652	* Prepares the MMIO2 pages for a live save.
653	*
654	* @returns VBox status code.
655	* @param pVM The cross context VM structure.
656	*/
657	static int pgmR3PrepMmio2Pages(PVM pVM)
658	{
659	/*
660	* Initialize the live save tracking in the MMIO2 ranges.
661	* ASSUME nothing changes here.
662	*/
663	PGM_LOCK_VOID(pVM);
664	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
665	{
666	uint32_t const cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
667	PGM_UNLOCK(pVM);
668
669	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM,
670	sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
671	if (!paLSPages)
672	return VERR_NO_MEMORY;
673	for (uint32_t iPage = 0; iPage < cPages; iPage++)
674	{
675	/* Initialize it as a dirty zero page. */
676	paLSPages[iPage].fDirty = true;
677	paLSPages[iPage].cUnchangedScans = 0;
678	paLSPages[iPage].fZero = true;
679	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
680	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
681	}
682
683	PGM_LOCK_VOID(pVM);
684	pRegMmio->paLSPages = paLSPages;
685	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
686	}
687	PGM_UNLOCK(pVM);
688	return VINF_SUCCESS;
689	}
690
691
692	/**
693	* Assigns IDs to the MMIO2 ranges and saves them.
694	*
695	* @returns VBox status code.
696	* @param pVM The cross context VM structure.
697	* @param pSSM Saved state handle.
698	*/
699	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
700	{
701	PGM_LOCK_VOID(pVM);
702	uint8_t id = 1;
703	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
704	{
705	pRegMmio->idSavedState = id;
706	SSMR3PutU8(pSSM, id);
707	SSMR3PutStrZ(pSSM, pRegMmio->pDevInsR3->pReg->szName);
708	SSMR3PutU32(pSSM, pRegMmio->pDevInsR3->iInstance);
709	SSMR3PutU8(pSSM, pRegMmio->iRegion);
710	SSMR3PutStrZ(pSSM, pRegMmio->RamRange.pszDesc);
711	int rc = SSMR3PutGCPhys(pSSM, pRegMmio->RamRange.cb);
712	if (RT_FAILURE(rc))
713	break;
714	id++;
715	}
716	PGM_UNLOCK(pVM);
717	return SSMR3PutU8(pSSM, UINT8_MAX);
718	}
719
720
721	/**
722	* Loads the MMIO2 range ID assignments.
723	*
724	* @returns VBox status code.
725	*
726	* @param pVM The cross context VM structure.
727	* @param pSSM The saved state handle.
728	*/
729	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
730	{
731	PGM_LOCK_ASSERT_OWNER(pVM);
732
733	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
734	pRegMmio->idSavedState = UINT8_MAX;
735
736	for (;;)
737	{
738	/*
739	* Read the data.
740	*/
741	uint8_t id;
742	int rc = SSMR3GetU8(pSSM, &id);
743	if (RT_FAILURE(rc))
744	return rc;
745	if (id == UINT8_MAX)
746	{
747	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
748	AssertLogRelMsg(pRegMmio->idSavedState != UINT8_MAX, ("%s\n", pRegMmio->RamRange.pszDesc));
749	return VINF_SUCCESS; /* the end */
750	}
751	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
752
753	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
754	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
755	AssertLogRelRCReturn(rc, rc);
756
757	uint32_t uInstance;
758	SSMR3GetU32(pSSM, &uInstance);
759	uint8_t iRegion;
760	SSMR3GetU8(pSSM, &iRegion);
761
762	char szDesc[64];
763	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
764	AssertLogRelRCReturn(rc, rc);
765
766	RTGCPHYS cb;
767	rc = SSMR3GetGCPhys(pSSM, &cb);
768	AssertLogRelMsgReturn(!(cb & GUEST_PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
769
770	/*
771	* Locate a matching MMIO2 range.
772	*/
773	PPGMREGMMIO2RANGE pRegMmio;
774	for (pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
775	{
776	if ( pRegMmio->idSavedState == UINT8_MAX
777	&& pRegMmio->iRegion == iRegion
778	&& pRegMmio->pDevInsR3->iInstance == uInstance
779	&& !strcmp(pRegMmio->pDevInsR3->pReg->szName, szDevName))
780	{
781	pRegMmio->idSavedState = id;
782	break;
783	}
784	}
785	if (!pRegMmio)
786	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
787	szDesc, szDevName, uInstance, iRegion);
788
789	/*
790	* Validate the configuration, the size of the MMIO2 region should be
791	* the same.
792	*/
793	if (cb != pRegMmio->RamRange.cb)
794	{
795	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
796	pRegMmio->RamRange.pszDesc, cb, pRegMmio->RamRange.cb));
797	if (cb > pRegMmio->RamRange.cb) /* bad idea? */
798	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
799	pRegMmio->RamRange.pszDesc, cb, pRegMmio->RamRange.cb);
800	}
801	} /* forever */
802	}
803
804
805	/**
806	* Scans one MMIO2 page.
807	*
808	* @returns True if changed, false if unchanged.
809	*
810	* @param pVM The cross context VM structure.
811	* @param pbPage The page bits.
812	* @param pLSPage The live save tracking structure for the page.
813	*
814	*/
815	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
816	{
817	/*
818	* Special handling of zero pages.
819	*/
820	bool const fZero = pLSPage->fZero;
821	if (fZero)
822	{
823	if (ASMMemIsZero(pbPage, GUEST_PAGE_SIZE))
824	{
825	/* Not modified. */
826	if (pLSPage->fDirty)
827	pLSPage->cUnchangedScans++;
828	return false;
829	}
830
831	pLSPage->fZero = false;
832	pLSPage->u32CrcH1 = RTCrc32(pbPage, GUEST_PAGE_SIZE / 2);
833	}
834	else
835	{
836	/*
837	* CRC the first half, if it doesn't match the page is dirty and
838	* we won't check the 2nd half (we'll do that next time).
839	*/
840	uint32_t u32CrcH1 = RTCrc32(pbPage, GUEST_PAGE_SIZE / 2);
841	if (u32CrcH1 == pLSPage->u32CrcH1)
842	{
843	uint32_t u32CrcH2 = RTCrc32(pbPage + GUEST_PAGE_SIZE / 2, GUEST_PAGE_SIZE / 2);
844	if (u32CrcH2 == pLSPage->u32CrcH2)
845	{
846	/* Probably not modified. */
847	if (pLSPage->fDirty)
848	pLSPage->cUnchangedScans++;
849	return false;
850	}
851
852	pLSPage->u32CrcH2 = u32CrcH2;
853	}
854	else
855	{
856	pLSPage->u32CrcH1 = u32CrcH1;
857	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
858	&& ASMMemIsZero(pbPage, GUEST_PAGE_SIZE))
859	{
860	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
861	pLSPage->fZero = true;
862	}
863	}
864	}
865
866	/* dirty page path */
867	pLSPage->cUnchangedScans = 0;
868	if (!pLSPage->fDirty)
869	{
870	pLSPage->fDirty = true;
871	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
872	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
873	if (fZero)
874	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
875	}
876	return true;
877	}
878
879
880	/**
881	* Scan for MMIO2 page modifications.
882	*
883	* @param pVM The cross context VM structure.
884	* @param uPass The pass number.
885	*/
886	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
887	{
888	/*
889	* Since this is a bit expensive we lower the scan rate after a little while.
890	*/
891	if ( ( (uPass & 3) != 0
892	&& uPass > 10)
893	\|\| uPass == SSM_PASS_FINAL)
894	return;
895
896	PGM_LOCK_VOID(pVM); /* paranoia */
897	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
898	{
899	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
900	uint32_t cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
901	PGM_UNLOCK(pVM);
902
903	for (uint32_t iPage = 0; iPage < cPages; iPage++)
904	{
905	uint8_t const pbPage = (uint8_t const )pRegMmio->pvR3 + iPage * GUEST_PAGE_SIZE;
906	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
907	}
908
909	PGM_LOCK_VOID(pVM);
910	}
911	PGM_UNLOCK(pVM);
912
913	}
914
915
916	/**
917	* Save quiescent MMIO2 pages.
918	*
919	* @returns VBox status code.
920	* @param pVM The cross context VM structure.
921	* @param pSSM The SSM handle.
922	* @param fLiveSave Whether it's a live save or not.
923	* @param uPass The pass number.
924	*/
925	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
926	{
927	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
928	* device that we wish to know about changes.) */
929
930	int rc = VINF_SUCCESS;
931	if (uPass == SSM_PASS_FINAL)
932	{
933	/*
934	* The mop up round.
935	*/
936	PGM_LOCK_VOID(pVM);
937	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3;
938	pRegMmio && RT_SUCCESS(rc);
939	pRegMmio = pRegMmio->pNextR3)
940	{
941	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
942	uint8_t const pbPage = (uint8_t const )pRegMmio->RamRange.pvR3;
943	uint32_t cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
944	uint32_t iPageLast = cPages;
945	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += GUEST_PAGE_SIZE)
946	{
947	uint8_t u8Type;
948	if (!fLiveSave)
949	u8Type = ASMMemIsZero(pbPage, GUEST_PAGE_SIZE) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
950	else
951	{
952	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
953	if ( !paLSPages[iPage].fDirty
954	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
955	{
956	if (paLSPages[iPage].fZero)
957	continue;
958
959	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
960	RTSha1(pbPage, GUEST_PAGE_SIZE, abSha1Hash);
961	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
962	continue;
963	}
964	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
965	pVM->pgm.s.LiveSave.cSavedPages++;
966	}
967
968	if (iPage != 0 && iPage == iPageLast + 1)
969	rc = SSMR3PutU8(pSSM, u8Type);
970	else
971	{
972	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
973	SSMR3PutU8(pSSM, pRegMmio->idSavedState);
974	rc = SSMR3PutU32(pSSM, iPage);
975	}
976	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
977	rc = SSMR3PutMem(pSSM, pbPage, GUEST_PAGE_SIZE);
978	if (RT_FAILURE(rc))
979	break;
980	iPageLast = iPage;
981	}
982	}
983	PGM_UNLOCK(pVM);
984	}
985	/*
986	* Reduce the rate after a little while since the current MMIO2 approach is
987	* a bit expensive.
988	* We position it two passes after the scan pass to avoid saving busy pages.
989	*/
990	else if ( uPass <= 10
991	\|\| (uPass & 3) == 2)
992	{
993	PGM_LOCK_VOID(pVM);
994	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3;
995	pRegMmio && RT_SUCCESS(rc);
996	pRegMmio = pRegMmio->pNextR3)
997	{
998	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
999	uint8_t const pbPage = (uint8_t const )pRegMmio->RamRange.pvR3;
1000	uint32_t cPages = pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT;
1001	uint32_t iPageLast = cPages;
1002	PGM_UNLOCK(pVM);
1003
1004	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += GUEST_PAGE_SIZE)
1005	{
1006	/* Skip clean pages and pages which hasn't quiesced. */
1007	if (!paLSPages[iPage].fDirty)
1008	continue;
1009	if (paLSPages[iPage].cUnchangedScans < 3)
1010	continue;
1011	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
1012	continue;
1013
1014	/* Save it. */
1015	bool const fZero = paLSPages[iPage].fZero;
1016	uint8_t abPage[GUEST_PAGE_SIZE];
1017	if (!fZero)
1018	{
1019	memcpy(abPage, pbPage, GUEST_PAGE_SIZE);
1020	RTSha1(abPage, GUEST_PAGE_SIZE, paLSPages[iPage].abSha1Saved);
1021	}
1022
1023	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
1024	if (iPage != 0 && iPage == iPageLast + 1)
1025	rc = SSMR3PutU8(pSSM, u8Type);
1026	else
1027	{
1028	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
1029	SSMR3PutU8(pSSM, pRegMmio->idSavedState);
1030	rc = SSMR3PutU32(pSSM, iPage);
1031	}
1032	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
1033	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
1034	if (RT_FAILURE(rc))
1035	break;
1036
1037	/* Housekeeping. */
1038	paLSPages[iPage].fDirty = false;
1039	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
1040	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
1041	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
1042	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
1043	pVM->pgm.s.LiveSave.cSavedPages++;
1044	iPageLast = iPage;
1045	}
1046
1047	PGM_LOCK_VOID(pVM);
1048	}
1049	PGM_UNLOCK(pVM);
1050	}
1051
1052	return rc;
1053	}
1054
1055
1056	/**
1057	* Cleans up MMIO2 pages after a live save.
1058	*
1059	* @param pVM The cross context VM structure.
1060	*/
1061	static void pgmR3DoneMmio2Pages(PVM pVM)
1062	{
1063	/*
1064	* Free the tracking structures for the MMIO2 pages.
1065	* We do the freeing outside the lock in case the VM is running.
1066	*/
1067	PGM_LOCK_VOID(pVM);
1068	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
1069	{
1070	void *pvMmio2ToFree = pRegMmio->paLSPages;
1071	if (pvMmio2ToFree)
1072	{
1073	pRegMmio->paLSPages = NULL;
1074	PGM_UNLOCK(pVM);
1075	MMR3HeapFree(pvMmio2ToFree);
1076	PGM_LOCK_VOID(pVM);
1077	}
1078	}
1079	PGM_UNLOCK(pVM);
1080	}
1081
1082
1083	/**
1084	* Prepares the RAM pages for a live save.
1085	*
1086	* @returns VBox status code.
1087	* @param pVM The cross context VM structure.
1088	*/
1089	static int pgmR3PrepRamPages(PVM pVM)
1090	{
1091
1092	/*
1093	* Try allocating tracking structures for the ram ranges.
1094	*
1095	* To avoid lock contention, we leave the lock every time we're allocating
1096	* a new array. This means we'll have to ditch the allocation and start
1097	* all over again if the RAM range list changes in-between.
1098	*
1099	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1100	* for cleaning up.
1101	*/
1102	PPGMRAMRANGE pCur;
1103	PGM_LOCK_VOID(pVM);
1104	do
1105	{
1106	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1107	{
1108	if ( !pCur->paLSPages
1109	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1110	{
1111	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1112	uint32_t const cPages = pCur->cb >> GUEST_PAGE_SHIFT;
1113	PGM_UNLOCK(pVM);
1114	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1115	if (!paLSPages)
1116	return VERR_NO_MEMORY;
1117	PGM_LOCK_VOID(pVM);
1118	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1119	{
1120	PGM_UNLOCK(pVM);
1121	MMR3HeapFree(paLSPages);
1122	PGM_LOCK_VOID(pVM);
1123	break; /* try again */
1124	}
1125	pCur->paLSPages = paLSPages;
1126
1127	/*
1128	* Initialize the array.
1129	*/
1130	uint32_t iPage = cPages;
1131	while (iPage-- > 0)
1132	{
1133	/** @todo yield critsect! (after moving this away from EMT0) */
1134	PCPGMPAGE pPage = &pCur->aPages[iPage];
1135	paLSPages[iPage].cDirtied = 0;
1136	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1137	paLSPages[iPage].fWriteMonitored = 0;
1138	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1139	paLSPages[iPage].u2Reserved = 0;
1140	switch (PGM_PAGE_GET_TYPE(pPage))
1141	{
1142	case PGMPAGETYPE_RAM:
1143	if ( PGM_PAGE_IS_ZERO(pPage)
1144	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1145	{
1146	paLSPages[iPage].fZero = 1;
1147	paLSPages[iPage].fShared = 0;
1148	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1149	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1150	#endif
1151	}
1152	else if (PGM_PAGE_IS_SHARED(pPage))
1153	{
1154	paLSPages[iPage].fZero = 0;
1155	paLSPages[iPage].fShared = 1;
1156	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1157	paLSPages[iPage].u32Crc = UINT32_MAX;
1158	#endif
1159	}
1160	else
1161	{
1162	paLSPages[iPage].fZero = 0;
1163	paLSPages[iPage].fShared = 0;
1164	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1165	paLSPages[iPage].u32Crc = UINT32_MAX;
1166	#endif
1167	}
1168	paLSPages[iPage].fIgnore = 0;
1169	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1170	break;
1171
1172	case PGMPAGETYPE_ROM_SHADOW:
1173	case PGMPAGETYPE_ROM:
1174	{
1175	paLSPages[iPage].fZero = 0;
1176	paLSPages[iPage].fShared = 0;
1177	paLSPages[iPage].fDirty = 0;
1178	paLSPages[iPage].fIgnore = 1;
1179	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1180	paLSPages[iPage].u32Crc = UINT32_MAX;
1181	#endif
1182	pVM->pgm.s.LiveSave.cIgnoredPages++;
1183	break;
1184	}
1185
1186	default:
1187	AssertMsgFailed(("%R[pgmpage]", pPage));
1188	RT_FALL_THRU();
1189	case PGMPAGETYPE_MMIO2:
1190	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1191	paLSPages[iPage].fZero = 0;
1192	paLSPages[iPage].fShared = 0;
1193	paLSPages[iPage].fDirty = 0;
1194	paLSPages[iPage].fIgnore = 1;
1195	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1196	paLSPages[iPage].u32Crc = UINT32_MAX;
1197	#endif
1198	pVM->pgm.s.LiveSave.cIgnoredPages++;
1199	break;
1200
1201	case PGMPAGETYPE_MMIO:
1202	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
1203	paLSPages[iPage].fZero = 0;
1204	paLSPages[iPage].fShared = 0;
1205	paLSPages[iPage].fDirty = 0;
1206	paLSPages[iPage].fIgnore = 1;
1207	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1208	paLSPages[iPage].u32Crc = UINT32_MAX;
1209	#endif
1210	pVM->pgm.s.LiveSave.cIgnoredPages++;
1211	break;
1212	}
1213	}
1214	}
1215	}
1216	} while (pCur);
1217	PGM_UNLOCK(pVM);
1218
1219	return VINF_SUCCESS;
1220	}
1221
1222
1223	/**
1224	* Saves the RAM configuration.
1225	*
1226	* @returns VBox status code.
1227	* @param pVM The cross context VM structure.
1228	* @param pSSM The saved state handle.
1229	*/
1230	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1231	{
1232	uint32_t cbRamHole = 0;
1233	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1234	AssertRCReturn(rc, rc);
1235
1236	uint64_t cbRam = 0;
1237	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1238	AssertRCReturn(rc, rc);
1239
1240	SSMR3PutU32(pSSM, cbRamHole);
1241	return SSMR3PutU64(pSSM, cbRam);
1242	}
1243
1244
1245	/**
1246	* Loads and verifies the RAM configuration.
1247	*
1248	* @returns VBox status code.
1249	* @param pVM The cross context VM structure.
1250	* @param pSSM The saved state handle.
1251	*/
1252	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1253	{
1254	uint32_t cbRamHoleCfg = 0;
1255	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1256	AssertRCReturn(rc, rc);
1257
1258	uint64_t cbRamCfg = 0;
1259	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1260	AssertRCReturn(rc, rc);
1261
1262	uint32_t cbRamHoleSaved;
1263	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1264
1265	uint64_t cbRamSaved;
1266	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1267	AssertRCReturn(rc, rc);
1268
1269	if ( cbRamHoleCfg != cbRamHoleSaved
1270	\|\| cbRamCfg != cbRamSaved)
1271	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1272	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1273	return VINF_SUCCESS;
1274	}
1275
1276	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1277
1278	/**
1279	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1280	* info with it.
1281	*
1282	* @param pVM The cross context VM structure.
1283	* @param pCur The current RAM range.
1284	* @param paLSPages The current array of live save page tracking
1285	* structures.
1286	* @param iPage The page index.
1287	*/
1288	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1289	{
1290	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1291	PGMPAGEMAPLOCK PgMpLck;
1292	void const *pvPage;
1293	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1294	if (RT_SUCCESS(rc))
1295	{
1296	paLSPages[iPage].u32Crc = RTCrc32(pvPage, GUEST_PAGE_SIZE);
1297	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1298	}
1299	else
1300	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1301	}
1302
1303
1304	/**
1305	* Verifies the CRC-32 for a page given it's raw bits.
1306	*
1307	* @param pvPage The page bits.
1308	* @param pCur The current RAM range.
1309	* @param paLSPages The current array of live save page tracking
1310	* structures.
1311	* @param iPage The page index.
1312	*/
1313	static void pgmR3StateVerifyCrc32ForPage(void const pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char pszWhere)
1314	{
1315	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1316	{
1317	uint32_t u32Crc = RTCrc32(pvPage, GUEST_PAGE_SIZE);
1318	Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1319	&& !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1320	\|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1321	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1322	("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1323	pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1324	}
1325	}
1326
1327
1328	/**
1329	* Verifies the CRC-32 for a RAM page.
1330	*
1331	* @param pVM The cross context VM structure.
1332	* @param pCur The current RAM range.
1333	* @param paLSPages The current array of live save page tracking
1334	* structures.
1335	* @param iPage The page index.
1336	*/
1337	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1338	{
1339	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1340	{
1341	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1342	PGMPAGEMAPLOCK PgMpLck;
1343	void const *pvPage;
1344	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1345	if (RT_SUCCESS(rc))
1346	{
1347	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1348	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1349	}
1350	}
1351	}
1352
1353	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1354
1355	/**
1356	* Scan for RAM page modifications and reprotect them.
1357	*
1358	* @param pVM The cross context VM structure.
1359	* @param fFinalPass Whether this is the final pass or not.
1360	*/
1361	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1362	{
1363	/*
1364	* The RAM.
1365	*/
1366	RTGCPHYS GCPhysCur = 0;
1367	PPGMRAMRANGE pCur;
1368	PGM_LOCK_VOID(pVM);
1369	do
1370	{
1371	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1372	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1373	{
1374	if ( pCur->GCPhysLast > GCPhysCur
1375	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1376	{
1377	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1378	uint32_t cPages = pCur->cb >> GUEST_PAGE_SHIFT;
1379	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> GUEST_PAGE_SHIFT;
1380	GCPhysCur = 0;
1381	for (; iPage < cPages; iPage++)
1382	{
1383	/* Do yield first. */
1384	if ( !fFinalPass
1385	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1386	&& (iPage & 0x7ff) == 0x100
1387	#endif
1388	&& PDMR3CritSectYield(pVM, &pVM->pgm.s.CritSectX)
1389	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1390	{
1391	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1392	break; /* restart */
1393	}
1394
1395	/* Skip already ignored pages. */
1396	if (paLSPages[iPage].fIgnore)
1397	continue;
1398
1399	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1400	{
1401	/*
1402	* A RAM page.
1403	*/
1404	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1405	{
1406	case PGM_PAGE_STATE_ALLOCATED:
1407	/** @todo Optimize this: Don't always re-enable write
1408	* monitoring if the page is known to be very busy. */
1409	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1410	{
1411	AssertMsg(paLSPages[iPage].fWriteMonitored,
1412	("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT), &pCur->aPages[iPage]));
1413	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1414	Assert(pVM->pgm.s.cWrittenToPages > 0);
1415	pVM->pgm.s.cWrittenToPages--;
1416	}
1417	else
1418	{
1419	AssertMsg(!paLSPages[iPage].fWriteMonitored,
1420	("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT), &pCur->aPages[iPage]));
1421	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1422	}
1423
1424	if (!paLSPages[iPage].fDirty)
1425	{
1426	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1427	if (paLSPages[iPage].fZero)
1428	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1429	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1430	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1431	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1432	}
1433
1434	pgmPhysPageWriteMonitor(pVM, &pCur->aPages[iPage],
1435	pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT));
1436	paLSPages[iPage].fWriteMonitored = 1;
1437	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1438	paLSPages[iPage].fDirty = 1;
1439	paLSPages[iPage].fZero = 0;
1440	paLSPages[iPage].fShared = 0;
1441	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1442	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1443	#endif
1444	break;
1445
1446	case PGM_PAGE_STATE_WRITE_MONITORED:
1447	Assert(paLSPages[iPage].fWriteMonitored);
1448	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1449	{
1450	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1451	if (paLSPages[iPage].fWriteMonitoredJustNow)
1452	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1453	else
1454	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1455	#endif
1456	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1457	}
1458	else
1459	{
1460	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1461	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1462	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1463	#endif
1464	if (!paLSPages[iPage].fDirty)
1465	{
1466	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1467	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1468	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1469	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1470	}
1471	}
1472	break;
1473
1474	case PGM_PAGE_STATE_ZERO:
1475	case PGM_PAGE_STATE_BALLOONED:
1476	if (!paLSPages[iPage].fZero)
1477	{
1478	if (!paLSPages[iPage].fDirty)
1479	{
1480	paLSPages[iPage].fDirty = 1;
1481	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1482	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1483	}
1484	paLSPages[iPage].fZero = 1;
1485	paLSPages[iPage].fShared = 0;
1486	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1487	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1488	#endif
1489	}
1490	break;
1491
1492	case PGM_PAGE_STATE_SHARED:
1493	if (!paLSPages[iPage].fShared)
1494	{
1495	if (!paLSPages[iPage].fDirty)
1496	{
1497	paLSPages[iPage].fDirty = 1;
1498	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1499	if (paLSPages[iPage].fZero)
1500	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1501	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1502	}
1503	paLSPages[iPage].fZero = 0;
1504	paLSPages[iPage].fShared = 1;
1505	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1506	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1507	#endif
1508	}
1509	break;
1510	}
1511	}
1512	else
1513	{
1514	/*
1515	* All other types => Ignore the page.
1516	*/
1517	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1518	paLSPages[iPage].fIgnore = 1;
1519	if (paLSPages[iPage].fWriteMonitored)
1520	{
1521	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1522	* pages! */
1523	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1524	{
1525	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1526	PGM_PAGE_SET_STATE(pVM, &pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1527	Assert(pVM->pgm.s.cMonitoredPages > 0);
1528	pVM->pgm.s.cMonitoredPages--;
1529	}
1530	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1531	{
1532	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1533	Assert(pVM->pgm.s.cWrittenToPages > 0);
1534	pVM->pgm.s.cWrittenToPages--;
1535	}
1536	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1537	}
1538
1539	/** @todo the counting doesn't quite work out here. fix later? */
1540	if (paLSPages[iPage].fDirty)
1541	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1542	else
1543	{
1544	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1545	if (paLSPages[iPage].fZero)
1546	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1547	}
1548	pVM->pgm.s.LiveSave.cIgnoredPages++;
1549	}
1550	} /* for each page in range */
1551
1552	if (GCPhysCur != 0)
1553	break; /* Yield + ramrange change */
1554	GCPhysCur = pCur->GCPhysLast;
1555	}
1556	} /* for each range */
1557	} while (pCur);
1558	PGM_UNLOCK(pVM);
1559	}
1560
1561
1562	/**
1563	* Save quiescent RAM pages.
1564	*
1565	* @returns VBox status code.
1566	* @param pVM The cross context VM structure.
1567	* @param pSSM The SSM handle.
1568	* @param fLiveSave Whether it's a live save or not.
1569	* @param uPass The pass number.
1570	*/
1571	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1572	{
1573	NOREF(fLiveSave);
1574
1575	/*
1576	* The RAM.
1577	*/
1578	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1579	RTGCPHYS GCPhysCur = 0;
1580	PPGMRAMRANGE pCur;
1581
1582	PGM_LOCK_VOID(pVM);
1583	do
1584	{
1585	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1586	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1587	{
1588	if ( pCur->GCPhysLast > GCPhysCur
1589	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1590	{
1591	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1592	uint32_t cPages = pCur->cb >> GUEST_PAGE_SHIFT;
1593	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> GUEST_PAGE_SHIFT;
1594	GCPhysCur = 0;
1595	for (; iPage < cPages; iPage++)
1596	{
1597	/* Do yield first. */
1598	if ( uPass != SSM_PASS_FINAL
1599	&& (iPage & 0x7ff) == 0x100
1600	&& PDMR3CritSectYield(pVM, &pVM->pgm.s.CritSectX)
1601	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1602	{
1603	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1604	break; /* restart */
1605	}
1606
1607	PPGMPAGE pCurPage = &pCur->aPages[iPage];
1608
1609	/*
1610	* Only save pages that haven't changed since last scan and are dirty.
1611	*/
1612	if ( uPass != SSM_PASS_FINAL
1613	&& paLSPages)
1614	{
1615	if (!paLSPages[iPage].fDirty)
1616	continue;
1617	if (paLSPages[iPage].fWriteMonitoredJustNow)
1618	continue;
1619	if (paLSPages[iPage].fIgnore)
1620	continue;
1621	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1622	continue;
1623	if ( PGM_PAGE_GET_STATE(pCurPage)
1624	!= ( paLSPages[iPage].fZero
1625	? PGM_PAGE_STATE_ZERO
1626	: paLSPages[iPage].fShared
1627	? PGM_PAGE_STATE_SHARED
1628	: PGM_PAGE_STATE_WRITE_MONITORED))
1629	continue;
1630	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1631	continue;
1632	}
1633	else
1634	{
1635	if ( paLSPages
1636	&& !paLSPages[iPage].fDirty
1637	&& !paLSPages[iPage].fIgnore)
1638	{
1639	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1640	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1641	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1642	#endif
1643	continue;
1644	}
1645	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1646	continue;
1647	}
1648
1649	/*
1650	* Do the saving outside the PGM critsect since SSM may block on I/O.
1651	*/
1652	int rc;
1653	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
1654	bool fZero = PGM_PAGE_IS_ZERO(pCurPage);
1655	bool fBallooned = PGM_PAGE_IS_BALLOONED(pCurPage);
1656	bool fSkipped = false;
1657
1658	if (!fZero && !fBallooned)
1659	{
1660	/*
1661	* Copy the page and then save it outside the lock (since any
1662	* SSM call may block).
1663	*/
1664	uint8_t abPage[GUEST_PAGE_SIZE];
1665	PGMPAGEMAPLOCK PgMpLck;
1666	void const *pvPage;
1667	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pCurPage, GCPhys, &pvPage, &PgMpLck);
1668	if (RT_SUCCESS(rc))
1669	{
1670	memcpy(abPage, pvPage, GUEST_PAGE_SIZE);
1671	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1672	if (paLSPages)
1673	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1674	#endif
1675	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1676	}
1677	PGM_UNLOCK(pVM);
1678	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1679
1680	/* Try save some memory when restoring. */
1681	if (!ASMMemIsZero(pvPage, GUEST_PAGE_SIZE))
1682	{
1683	if (GCPhys == GCPhysLast + GUEST_PAGE_SIZE)
1684	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1685	else
1686	{
1687	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1688	SSMR3PutGCPhys(pSSM, GCPhys);
1689	}
1690	rc = SSMR3PutMem(pSSM, abPage, GUEST_PAGE_SIZE);
1691	}
1692	else
1693	{
1694	if (GCPhys == GCPhysLast + GUEST_PAGE_SIZE)
1695	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1696	else
1697	{
1698	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1699	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1700	}
1701	}
1702	}
1703	else
1704	{
1705	/*
1706	* Dirty zero or ballooned page.
1707	*/
1708	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1709	if (paLSPages)
1710	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1711	#endif
1712	PGM_UNLOCK(pVM);
1713
1714	uint8_t u8RecType = fBallooned ? PGM_STATE_REC_RAM_BALLOONED : PGM_STATE_REC_RAM_ZERO;
1715	if (GCPhys == GCPhysLast + GUEST_PAGE_SIZE)
1716	rc = SSMR3PutU8(pSSM, u8RecType);
1717	else
1718	{
1719	SSMR3PutU8(pSSM, u8RecType \| PGM_STATE_REC_FLAG_ADDR);
1720	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1721	}
1722	}
1723	if (RT_FAILURE(rc))
1724	return rc;
1725
1726	PGM_LOCK_VOID(pVM);
1727	if (!fSkipped)
1728	GCPhysLast = GCPhys;
1729	if (paLSPages)
1730	{
1731	paLSPages[iPage].fDirty = 0;
1732	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1733	if (fZero)
1734	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1735	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1736	pVM->pgm.s.LiveSave.cSavedPages++;
1737	}
1738	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1739	{
1740	GCPhysCur = GCPhys \| GUEST_PAGE_OFFSET_MASK;
1741	break; /* restart */
1742	}
1743
1744	} /* for each page in range */
1745
1746	if (GCPhysCur != 0)
1747	break; /* Yield + ramrange change */
1748	GCPhysCur = pCur->GCPhysLast;
1749	}
1750	} /* for each range */
1751	} while (pCur);
1752
1753	PGM_UNLOCK(pVM);
1754
1755	return VINF_SUCCESS;
1756	}
1757
1758
1759	/**
1760	* Cleans up RAM pages after a live save.
1761	*
1762	* @param pVM The cross context VM structure.
1763	*/
1764	static void pgmR3DoneRamPages(PVM pVM)
1765	{
1766	/*
1767	* Free the tracking arrays and disable write monitoring.
1768	*
1769	* Play nice with the PGM lock in case we're called while the VM is still
1770	* running. This means we have to delay the freeing since we wish to use
1771	* paLSPages as an indicator of which RAM ranges which we need to scan for
1772	* write monitored pages.
1773	*/
1774	void *pvToFree = NULL;
1775	PPGMRAMRANGE pCur;
1776	uint32_t cMonitoredPages = 0;
1777	PGM_LOCK_VOID(pVM);
1778	do
1779	{
1780	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1781	{
1782	if (pCur->paLSPages)
1783	{
1784	if (pvToFree)
1785	{
1786	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1787	PGM_UNLOCK(pVM);
1788	MMR3HeapFree(pvToFree);
1789	pvToFree = NULL;
1790	PGM_LOCK_VOID(pVM);
1791	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1792	break; /* start over again. */
1793	}
1794
1795	pvToFree = pCur->paLSPages;
1796	pCur->paLSPages = NULL;
1797
1798	uint32_t iPage = pCur->cb >> GUEST_PAGE_SHIFT;
1799	while (iPage--)
1800	{
1801	PPGMPAGE pPage = &pCur->aPages[iPage];
1802	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1803	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1804	{
1805	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
1806	cMonitoredPages++;
1807	}
1808	}
1809	}
1810	}
1811	} while (pCur);
1812
1813	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1814	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1815	pVM->pgm.s.cMonitoredPages = 0;
1816	else
1817	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1818
1819	PGM_UNLOCK(pVM);
1820
1821	MMR3HeapFree(pvToFree);
1822	pvToFree = NULL;
1823	}
1824
1825
1826	/**
1827	* @callback_method_impl{FNSSMINTLIVEEXEC}
1828	*/
1829	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1830	{
1831	int rc;
1832
1833	/*
1834	* Save the MMIO2 and ROM range IDs in pass 0.
1835	*/
1836	if (uPass == 0)
1837	{
1838	rc = pgmR3SaveRamConfig(pVM, pSSM);
1839	if (RT_FAILURE(rc))
1840	return rc;
1841	rc = pgmR3SaveRomRanges(pVM, pSSM);
1842	if (RT_FAILURE(rc))
1843	return rc;
1844	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1845	if (RT_FAILURE(rc))
1846	return rc;
1847	}
1848	/*
1849	* Reset the page-per-second estimate to avoid inflation by the initial
1850	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1851	*/
1852	else if (uPass == 7)
1853	{
1854	pVM->pgm.s.LiveSave.cSavedPages = 0;
1855	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1856	}
1857
1858	/*
1859	* Do the scanning.
1860	*/
1861	pgmR3ScanRomPages(pVM);
1862	pgmR3ScanMmio2Pages(pVM, uPass);
1863	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1864	pgmR3PoolClearAll(pVM, true /fFlushRemTlb/); /** @todo this could perhaps be optimized a bit. */
1865
1866	/*
1867	* Save the pages.
1868	*/
1869	if (uPass == 0)
1870	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1871	else
1872	rc = VINF_SUCCESS;
1873	if (RT_SUCCESS(rc))
1874	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1875	if (RT_SUCCESS(rc))
1876	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1877	if (RT_SUCCESS(rc))
1878	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1879	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1880
1881	return rc;
1882	}
1883
1884
1885	/**
1886	* @callback_method_impl{FNSSMINTLIVEVOTE}
1887	*/
1888	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1889	{
1890	/*
1891	* Update and calculate parameters used in the decision making.
1892	*/
1893	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1894
1895	/* update history. */
1896	PGM_LOCK_VOID(pVM);
1897	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1898	PGM_UNLOCK(pVM);
1899	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1900	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1901	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1902	+ cWrittenToPages;
1903	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1904	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1905	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1906
1907	/* calc shortterm average (4 passes). */
1908	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1909	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1910	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1911	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1912	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1913	uint32_t const cDirtyPagesShort = cTotal / 4;
1914	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1915
1916	/* calc longterm average. */
1917	cTotal = 0;
1918	if (uPass < cHistoryEntries)
1919	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1920	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1921	else
1922	for (i = 0; i < cHistoryEntries; i++)
1923	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1924	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1925	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1926
1927	/* estimate the speed */
1928	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1929	uint32_t cPagesPerSecond = (uint32_t)( (long double)pVM->pgm.s.LiveSave.cSavedPages
1930	/ ((long double)cNsElapsed / 1000000000.0) );
1931	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1932
1933	/*
1934	* Try make a decision.
1935	*/
1936	if ( cDirtyPagesShort <= cDirtyPagesLong
1937	&& ( cDirtyNow <= cDirtyPagesShort
1938	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1939	)
1940	)
1941	{
1942	if (uPass > 10)
1943	{
1944	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1945	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1946	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1947	if (cMsMaxDowntime < 32)
1948	cMsMaxDowntime = 32;
1949	if ( ( cMsLeftLong <= cMsMaxDowntime
1950	&& cMsLeftShort < cMsMaxDowntime)
1951	\|\| cMsLeftShort < cMsMaxDowntime / 2
1952	)
1953	{
1954	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1955	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1956	return VINF_SUCCESS;
1957	}
1958	}
1959	else
1960	{
1961	if ( ( cDirtyPagesShort <= 128
1962	&& cDirtyPagesLong <= 1024)
1963	\|\| cDirtyPagesLong <= 256
1964	)
1965	{
1966	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1967	return VINF_SUCCESS;
1968	}
1969	}
1970	}
1971
1972	/*
1973	* Come up with a completion percentage. Currently this is a simple
1974	* dirty page (long term) vs. total pages ratio + some pass trickery.
1975	*/
1976	unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1977	/ (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1978	if (uPctDirty <= 100)
1979	SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1980	else
1981	AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1982	uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1983
1984	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1985	}
1986
1987
1988	/**
1989	* @callback_method_impl{FNSSMINTLIVEPREP}
1990	*
1991	* This will attempt to allocate and initialize the tracking structures. It
1992	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1993	* pgmR3SaveDone will do the cleanups.
1994	*/
1995	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1996	{
1997	/*
1998	* Indicate that we will be using the write monitoring.
1999	*/
2000	PGM_LOCK_VOID(pVM);
2001	/** @todo find a way of mediating this when more users are added. */
2002	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
2003	{
2004	PGM_UNLOCK(pVM);
2005	AssertLogRelFailedReturn(VERR_PGM_WRITE_MONITOR_ENGAGED);
2006	}
2007	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
2008	PGM_UNLOCK(pVM);
2009
2010	/*
2011	* Initialize the statistics.
2012	*/
2013	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
2014	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
2015	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
2016	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
2017	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
2018	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
2019	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
2020	pVM->pgm.s.LiveSave.fActive = true;
2021	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
2022	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
2023	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
2024	pVM->pgm.s.LiveSave.cSavedPages = 0;
2025	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
2026	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
2027
2028	/*
2029	* Per page type.
2030	*/
2031	int rc = pgmR3PrepRomPages(pVM);
2032	if (RT_SUCCESS(rc))
2033	rc = pgmR3PrepMmio2Pages(pVM);
2034	if (RT_SUCCESS(rc))
2035	rc = pgmR3PrepRamPages(pVM);
2036
2037	NOREF(pSSM);
2038	return rc;
2039	}
2040
2041
2042	/**
2043	* @callback_method_impl{FNSSMINTSAVEEXEC}
2044	*/
2045	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2046	{
2047	PPGM pPGM = &pVM->pgm.s;
2048
2049	/*
2050	* Lock PGM and set the no-more-writes indicator.
2051	*/
2052	PGM_LOCK_VOID(pVM);
2053	pVM->pgm.s.fNoMorePhysWrites = true;
2054
2055	/*
2056	* Save basic data (required / unaffected by relocation).
2057	*/
2058	int rc = SSMR3PutStructEx(pSSM, pPGM, sizeof(pPGM), 0 /fFlags/, &s_aPGMFields[0], NULL /pvUser*/);
2059
2060	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus && RT_SUCCESS(rc); idCpu++)
2061	rc = SSMR3PutStruct(pSSM, &pVM->apCpusR3[idCpu]->pgm.s, &s_aPGMCpuFields[0]);
2062
2063	/*
2064	* Save the (remainder of the) memory.
2065	*/
2066	if (RT_SUCCESS(rc))
2067	{
2068	if (pVM->pgm.s.LiveSave.fActive)
2069	{
2070	pgmR3ScanRomPages(pVM);
2071	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2072	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2073
2074	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2075	if (RT_SUCCESS(rc))
2076	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2077	if (RT_SUCCESS(rc))
2078	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2079	}
2080	else
2081	{
2082	rc = pgmR3SaveRamConfig(pVM, pSSM);
2083	if (RT_SUCCESS(rc))
2084	rc = pgmR3SaveRomRanges(pVM, pSSM);
2085	if (RT_SUCCESS(rc))
2086	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2087	if (RT_SUCCESS(rc))
2088	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2089	if (RT_SUCCESS(rc))
2090	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2091	if (RT_SUCCESS(rc))
2092	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2093	if (RT_SUCCESS(rc))
2094	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2095	}
2096	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2097	}
2098
2099	PGM_UNLOCK(pVM);
2100	return rc;
2101	}
2102
2103
2104	/**
2105	* @callback_method_impl{FNSSMINTSAVEDONE}
2106	*/
2107	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2108	{
2109	/*
2110	* Do per page type cleanups first.
2111	*/
2112	if (pVM->pgm.s.LiveSave.fActive)
2113	{
2114	pgmR3DoneRomPages(pVM);
2115	pgmR3DoneMmio2Pages(pVM);
2116	pgmR3DoneRamPages(pVM);
2117	}
2118
2119	/*
2120	* Clear the live save indicator and disengage write monitoring.
2121	*/
2122	PGM_LOCK_VOID(pVM);
2123	pVM->pgm.s.LiveSave.fActive = false;
2124	/** @todo this is blindly assuming that we're the only user of write
2125	* monitoring. Fix this when more users are added. */
2126	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2127	PGM_UNLOCK(pVM);
2128
2129	NOREF(pSSM);
2130	return VINF_SUCCESS;
2131	}
2132
2133
2134	/**
2135	* @callback_method_impl{FNSSMINTLOADPREP}
2136	*/
2137	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2138	{
2139	/*
2140	* Call the reset function to make sure all the memory is cleared.
2141	*/
2142	PGMR3Reset(pVM);
2143	pVM->pgm.s.LiveSave.fActive = false;
2144	NOREF(pSSM);
2145	return VINF_SUCCESS;
2146	}
2147
2148
2149	/**
2150	* Load an ignored page.
2151	*
2152	* @returns VBox status code.
2153	* @param pSSM The saved state handle.
2154	*/
2155	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2156	{
2157	uint8_t abPage[GUEST_PAGE_SIZE];
2158	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2159	}
2160
2161
2162	/**
2163	* Compares a page with an old save type value.
2164	*
2165	* @returns true if equal, false if not.
2166	* @param pPage The page to compare.
2167	* @param uOldType The old type value from the saved state.
2168	*/
2169	DECLINLINE(bool) pgmR3CompareNewAndOldPageTypes(PPGMPAGE pPage, uint8_t uOldType)
2170	{
2171	uint8_t uOldPageType;
2172	switch (PGM_PAGE_GET_TYPE(pPage))
2173	{
2174	case PGMPAGETYPE_INVALID: uOldPageType = PGMPAGETYPE_OLD_INVALID; break;
2175	case PGMPAGETYPE_RAM: uOldPageType = PGMPAGETYPE_OLD_RAM; break;
2176	case PGMPAGETYPE_MMIO2: uOldPageType = PGMPAGETYPE_OLD_MMIO2; break;
2177	case PGMPAGETYPE_MMIO2_ALIAS_MMIO: uOldPageType = PGMPAGETYPE_OLD_MMIO2_ALIAS_MMIO; break;
2178	case PGMPAGETYPE_ROM_SHADOW: uOldPageType = PGMPAGETYPE_OLD_ROM_SHADOW; break;
2179	case PGMPAGETYPE_ROM: uOldPageType = PGMPAGETYPE_OLD_ROM; break;
2180	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: RT_FALL_THRU();
2181	case PGMPAGETYPE_MMIO: uOldPageType = PGMPAGETYPE_OLD_MMIO; break;
2182	default:
2183	AssertFailed();
2184	uOldPageType = PGMPAGETYPE_OLD_INVALID;
2185	break;
2186	}
2187	return uOldPageType == uOldType;
2188	}
2189
2190
2191	/**
2192	* Loads a page without any bits in the saved state, i.e. making sure it's
2193	* really zero.
2194	*
2195	* @returns VBox status code.
2196	* @param pVM The cross context VM structure.
2197	* @param uOldType The page type or PGMPAGETYPE_OLD_INVALID (old saved
2198	* state).
2199	* @param pPage The guest page tracking structure.
2200	* @param GCPhys The page address.
2201	* @param pRam The ram range (logging).
2202	*/
2203	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2204	{
2205	if ( uOldType != PGMPAGETYPE_OLD_INVALID
2206	&& !pgmR3CompareNewAndOldPageTypes(pPage, uOldType))
2207	return VERR_SSM_UNEXPECTED_DATA;
2208
2209	/* I think this should be sufficient. */
2210	if ( !PGM_PAGE_IS_ZERO(pPage)
2211	&& !PGM_PAGE_IS_BALLOONED(pPage))
2212	return VERR_SSM_UNEXPECTED_DATA;
2213
2214	NOREF(pVM);
2215	NOREF(GCPhys);
2216	NOREF(pRam);
2217	return VINF_SUCCESS;
2218	}
2219
2220
2221	/**
2222	* Loads a page from the saved state.
2223	*
2224	* @returns VBox status code.
2225	* @param pVM The cross context VM structure.
2226	* @param pSSM The SSM handle.
2227	* @param uOldType The page type or PGMPAGETYPE_OLD_INVALID (old saved
2228	* state).
2229	* @param pPage The guest page tracking structure.
2230	* @param GCPhys The page address.
2231	* @param pRam The ram range (logging).
2232	*/
2233	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2234	{
2235	/*
2236	* Match up the type, dealing with MMIO2 aliases (dropped).
2237	*/
2238	AssertLogRelMsgReturn( uOldType == PGMPAGETYPE_INVALID
2239	\|\| pgmR3CompareNewAndOldPageTypes(pPage, uOldType)
2240	/* kudge for the expanded PXE bios (r67885) - @bugref{5687}: */
2241	\|\| ( uOldType == PGMPAGETYPE_OLD_RAM
2242	&& GCPhys >= 0xed000
2243	&& GCPhys <= 0xeffff
2244	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM)
2245	,
2246	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2247	VERR_SSM_UNEXPECTED_DATA);
2248
2249	/*
2250	* Load the page.
2251	*/
2252	PGMPAGEMAPLOCK PgMpLck;
2253	void *pvPage;
2254	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage, &PgMpLck);
2255	if (RT_SUCCESS(rc))
2256	{
2257	rc = SSMR3GetMem(pSSM, pvPage, GUEST_PAGE_SIZE);
2258	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2259	}
2260
2261	return rc;
2262	}
2263
2264
2265	/**
2266	* Loads a page (counter part to pgmR3SavePage).
2267	*
2268	* @returns VBox status code, fully bitched errors.
2269	* @param pVM The cross context VM structure.
2270	* @param pSSM The SSM handle.
2271	* @param uOldType The page type.
2272	* @param pPage The page.
2273	* @param GCPhys The page address.
2274	* @param pRam The RAM range (for error messages).
2275	*/
2276	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2277	{
2278	uint8_t uState;
2279	int rc = SSMR3GetU8(pSSM, &uState);
2280	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2281	if (uState == 0 /* zero */)
2282	rc = pgmR3LoadPageZeroOld(pVM, uOldType, pPage, GCPhys, pRam);
2283	else if (uState == 1)
2284	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uOldType, pPage, GCPhys, pRam);
2285	else
2286	rc = VERR_PGM_INVALID_SAVED_PAGE_STATE;
2287	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uOldType=%d GCPhys=%RGp %s rc=%Rrc\n",
2288	pPage, uState, uOldType, GCPhys, pRam->pszDesc, rc),
2289	rc);
2290	return VINF_SUCCESS;
2291	}
2292
2293
2294	/**
2295	* Loads a shadowed ROM page.
2296	*
2297	* @returns VBox status code, errors are fully bitched.
2298	* @param pVM The cross context VM structure.
2299	* @param pSSM The saved state handle.
2300	* @param pPage The page.
2301	* @param GCPhys The page address.
2302	* @param pRam The RAM range (for error messages).
2303	*/
2304	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2305	{
2306	/*
2307	* Load and set the protection first, then load the two pages, the first
2308	* one is the active the other is the passive.
2309	*/
2310	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2311	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2312
2313	uint8_t uProt;
2314	int rc = SSMR3GetU8(pSSM, &uProt);
2315	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2316	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2317	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2318	&& enmProt < PGMROMPROT_END,
2319	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2320	VERR_SSM_UNEXPECTED_DATA);
2321
2322	if (pRomPage->enmProt != enmProt)
2323	{
2324	rc = PGMR3PhysRomProtect(pVM, GCPhys, GUEST_PAGE_SIZE, enmProt);
2325	AssertLogRelRCReturn(rc, rc);
2326	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2327	}
2328
2329	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2330	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2331	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2332	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2333
2334	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2335	* used down the line (will the 2nd page will be written to the first
2336	* one because of a false TLB hit since the TLB is using GCPhys and
2337	* doesn't check the HCPhys of the desired page). */
2338	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2339	if (RT_SUCCESS(rc))
2340	{
2341	pPageActive = pPage;
2342	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2343	}
2344	return rc;
2345	}
2346
2347	/**
2348	* Ram range flags and bits for older versions of the saved state.
2349	*
2350	* @returns VBox status code.
2351	*
2352	* @param pVM The cross context VM structure.
2353	* @param pSSM The SSM handle.
2354	* @param uVersion The saved state version.
2355	*/
2356	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2357	{
2358	PPGM pPGM = &pVM->pgm.s;
2359
2360	/*
2361	* Ram range flags and bits.
2362	*/
2363	uint32_t i = 0;
2364	for (PPGMRAMRANGE pRam = pPGM->pRamRangesXR3; ; pRam = pRam->pNextR3, i++)
2365	{
2366	/* Check the sequence number / separator. */
2367	uint32_t u32Sep;
2368	int rc = SSMR3GetU32(pSSM, &u32Sep);
2369	if (RT_FAILURE(rc))
2370	return rc;
2371	if (u32Sep == ~0U)
2372	break;
2373	if (u32Sep != i)
2374	{
2375	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2376	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2377	}
2378	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2379
2380	/* Get the range details. */
2381	RTGCPHYS GCPhys;
2382	SSMR3GetGCPhys(pSSM, &GCPhys);
2383	RTGCPHYS GCPhysLast;
2384	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2385	RTGCPHYS cb;
2386	SSMR3GetGCPhys(pSSM, &cb);
2387	uint8_t fHaveBits;
2388	rc = SSMR3GetU8(pSSM, &fHaveBits);
2389	if (RT_FAILURE(rc))
2390	return rc;
2391	if (fHaveBits & ~1)
2392	{
2393	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2394	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2395	}
2396	size_t cchDesc = 0;
2397	char szDesc[256];
2398	szDesc[0] = '\0';
2399	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2400	{
2401	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2402	if (RT_FAILURE(rc))
2403	return rc;
2404	/* Since we've modified the description strings in r45878, only compare
2405	them if the saved state is more recent. */
2406	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2407	cchDesc = strlen(szDesc);
2408	}
2409
2410	/*
2411	* Match it up with the current range.
2412	*
2413	* Note there is a hack for dealing with the high BIOS mapping
2414	* in the old saved state format, this means we might not have
2415	* a 1:1 match on success.
2416	*/
2417	if ( ( GCPhys != pRam->GCPhys
2418	\|\| GCPhysLast != pRam->GCPhysLast
2419	\|\| cb != pRam->cb
2420	\|\| ( cchDesc
2421	&& strcmp(szDesc, pRam->pszDesc)) )
2422	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2423	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2424	\|\| GCPhys != UINT32_C(0xfff80000)
2425	\|\| GCPhysLast != UINT32_C(0xffffffff)
2426	\|\| pRam->GCPhysLast != GCPhysLast
2427	\|\| pRam->GCPhys < GCPhys
2428	\|\| !fHaveBits)
2429	)
2430	{
2431	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2432	"State : %RGp-%RGp %RGp bytes %s %s\n",
2433	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2434	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2435	/*
2436	* If we're loading a state for debugging purpose, don't make a fuss if
2437	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2438	*/
2439	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2440	\|\| GCPhys < 8 * _1M)
2441	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2442	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2443	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2444	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2445
2446	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2447	continue;
2448	}
2449
2450	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> GUEST_PAGE_SHIFT;
2451	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2452	{
2453	/*
2454	* Load the pages one by one.
2455	*/
2456	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2457	{
2458	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT) + pRam->GCPhys;
2459	PPGMPAGE pPage = &pRam->aPages[iPage];
2460	uint8_t uOldType;
2461	rc = SSMR3GetU8(pSSM, &uOldType);
2462	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2463	if (uOldType == PGMPAGETYPE_OLD_ROM_SHADOW)
2464	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2465	else
2466	rc = pgmR3LoadPageOld(pVM, pSSM, uOldType, pPage, GCPhysPage, pRam);
2467	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2468	}
2469	}
2470	else
2471	{
2472	/*
2473	* Old format.
2474	*/
2475
2476	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2477	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2478	uint32_t fFlags = 0;
2479	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2480	{
2481	uint16_t u16Flags;
2482	rc = SSMR3GetU16(pSSM, &u16Flags);
2483	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2484	fFlags \|= u16Flags;
2485	}
2486
2487	/* Load the bits */
2488	if ( !fHaveBits
2489	&& GCPhysLast < UINT32_C(0xe0000000))
2490	{
2491	/*
2492	* Dynamic chunks.
2493	*/
2494	const uint32_t cPagesInChunk = (110241024) >> GUEST_PAGE_SHIFT;
2495	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2496	("cPages=%#x cPagesInChunk=%#x GCPhys=%RGp %s\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2497	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2498
2499	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2500	{
2501	uint8_t fPresent;
2502	rc = SSMR3GetU8(pSSM, &fPresent);
2503	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2504	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2505	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2506	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2507
2508	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2509	{
2510	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT) + pRam->GCPhys;
2511	PPGMPAGE pPage = &pRam->aPages[iPage];
2512	if (fPresent)
2513	{
2514	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO
2515	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO)
2516	rc = pgmR3LoadPageToDevNullOld(pSSM);
2517	else
2518	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2519	}
2520	else
2521	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2522	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2523	}
2524	}
2525	}
2526	else if (pRam->pvR3)
2527	{
2528	/*
2529	* MMIO2.
2530	*/
2531	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2532	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2533	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2534	AssertLogRelMsgReturn(pRam->pvR3,
2535	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2536	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2537
2538	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2539	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2540	}
2541	else if (GCPhysLast < UINT32_C(0xfff80000))
2542	{
2543	/*
2544	* PCI MMIO, no pages saved.
2545	*/
2546	}
2547	else
2548	{
2549	/*
2550	* Load the 0xfff80000..0xffffffff BIOS range.
2551	* It starts with X reserved pages that we have to skip over since
2552	* the RAMRANGE create by the new code won't include those.
2553	*/
2554	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2555	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2556	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2557	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2558	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2559	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2560	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2561
2562	/* Skip wasted reserved pages before the ROM. */
2563	while (GCPhys < pRam->GCPhys)
2564	{
2565	rc = pgmR3LoadPageToDevNullOld(pSSM);
2566	GCPhys += GUEST_PAGE_SIZE;
2567	}
2568
2569	/* Load the bios pages. */
2570	cPages = pRam->cb >> GUEST_PAGE_SHIFT;
2571	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2572	{
2573	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT) + pRam->GCPhys;
2574	PPGMPAGE pPage = &pRam->aPages[iPage];
2575
2576	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2577	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2578	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2579	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2580	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2581	}
2582	}
2583	}
2584	}
2585
2586	return VINF_SUCCESS;
2587	}
2588
2589
2590	/**
2591	* Worker for pgmR3Load and pgmR3LoadLocked.
2592	*
2593	* @returns VBox status code.
2594	*
2595	* @param pVM The cross context VM structure.
2596	* @param pSSM The SSM handle.
2597	* @param uVersion The PGM saved state unit version.
2598	* @param uPass The pass number.
2599	*
2600	* @todo This needs splitting up if more record types or code twists are
2601	* added...
2602	*/
2603	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2604	{
2605	NOREF(uPass);
2606
2607	/*
2608	* Process page records until we hit the terminator.
2609	*/
2610	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2611	PPGMRAMRANGE pRamHint = NULL;
2612	uint8_t id = UINT8_MAX;
2613	uint32_t iPage = UINT32_MAX - 10;
2614	PPGMROMRANGE pRom = NULL;
2615	PPGMREGMMIO2RANGE pRegMmio = NULL;
2616
2617	/*
2618	* We batch up pages that should be freed instead of calling GMM for
2619	* each and every one of them. Note that we'll lose the pages in most
2620	* failure paths - this should probably be addressed one day.
2621	*/
2622	uint32_t cPendingPages = 0;
2623	PGMMFREEPAGESREQ pReq;
2624	int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2625	AssertLogRelRCReturn(rc, rc);
2626
2627	for (;;)
2628	{
2629	/*
2630	* Get the record type and flags.
2631	*/
2632	uint8_t u8;
2633	rc = SSMR3GetU8(pSSM, &u8);
2634	if (RT_FAILURE(rc))
2635	return rc;
2636	if (u8 == PGM_STATE_REC_END)
2637	{
2638	/*
2639	* Finish off any pages pending freeing.
2640	*/
2641	if (cPendingPages)
2642	{
2643	Log(("pgmR3LoadMemory: GMMR3FreePagesPerform pVM=%p cPendingPages=%u\n", pVM, cPendingPages));
2644	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2645	AssertLogRelRCReturn(rc, rc);
2646	}
2647	GMMR3FreePagesCleanup(pReq);
2648	return VINF_SUCCESS;
2649	}
2650	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2651	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2652	{
2653	/*
2654	* RAM page.
2655	*/
2656	case PGM_STATE_REC_RAM_ZERO:
2657	case PGM_STATE_REC_RAM_RAW:
2658	case PGM_STATE_REC_RAM_BALLOONED:
2659	{
2660	/*
2661	* Get the address and resolve it into a page descriptor.
2662	*/
2663	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2664	GCPhys += GUEST_PAGE_SIZE;
2665	else
2666	{
2667	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2668	if (RT_FAILURE(rc))
2669	return rc;
2670	}
2671	AssertLogRelMsgReturn(!(GCPhys & GUEST_PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2672
2673	PPGMPAGE pPage;
2674	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
2675	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2676
2677	/*
2678	* Take action according to the record type.
2679	*/
2680	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2681	{
2682	case PGM_STATE_REC_RAM_ZERO:
2683	{
2684	if (PGM_PAGE_IS_ZERO(pPage))
2685	break;
2686
2687	/* Ballooned pages must be unmarked (live snapshot and
2688	teleportation scenarios). */
2689	if (PGM_PAGE_IS_BALLOONED(pPage))
2690	{
2691	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2692	if (uVersion == PGM_SAVED_STATE_VERSION_BALLOON_BROKEN)
2693	break;
2694	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2695	break;
2696	}
2697
2698	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_UNEXPECTED_PAGE_STATE);
2699
2700	/* If this is a ROM page, we must clear it and not try to
2701	* free it. Ditto if the VM is using RamPreAlloc (see
2702	* @bugref{6318}). */
2703	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM
2704	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM_SHADOW
2705	#ifdef VBOX_WITH_PGM_NEM_MODE
2706	\|\| pVM->pgm.s.fNemMode
2707	#endif
2708	\|\| pVM->pgm.s.fRamPreAlloc)
2709	{
2710	PGMPAGEMAPLOCK PgMpLck;
2711	void *pvDstPage;
2712	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2713	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2714
2715	RT_BZERO(pvDstPage, GUEST_PAGE_SIZE);
2716	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2717	}
2718	/* Free it only if it's not part of a previously
2719	allocated large page (no need to clear the page). */
2720	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2721	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2722	{
2723	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys, (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
2724	AssertRCReturn(rc, rc);
2725	}
2726	/** @todo handle large pages (see @bugref{5545}) */
2727	break;
2728	}
2729
2730	case PGM_STATE_REC_RAM_BALLOONED:
2731	{
2732	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2733	if (PGM_PAGE_IS_BALLOONED(pPage))
2734	break;
2735
2736	/* We don't map ballooned pages in our shadow page tables, let's
2737	just free it if allocated and mark as ballooned. See @bugref{5515}. */
2738	if (PGM_PAGE_IS_ALLOCATED(pPage))
2739	{
2740	/** @todo handle large pages + ballooning when it works. (see @bugref{5515},
2741	* @bugref{5545}). */
2742	AssertLogRelMsgReturn( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2743	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED,
2744	("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_LOAD_UNEXPECTED_PAGE_TYPE);
2745
2746	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys, (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
2747	AssertRCReturn(rc, rc);
2748	}
2749	Assert(PGM_PAGE_IS_ZERO(pPage));
2750	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
2751	break;
2752	}
2753
2754	case PGM_STATE_REC_RAM_RAW:
2755	{
2756	PGMPAGEMAPLOCK PgMpLck;
2757	void *pvDstPage;
2758	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2759	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2760	rc = SSMR3GetMem(pSSM, pvDstPage, GUEST_PAGE_SIZE);
2761	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2762	if (RT_FAILURE(rc))
2763	return rc;
2764	break;
2765	}
2766
2767	default:
2768	AssertMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2769	}
2770	id = UINT8_MAX;
2771	break;
2772	}
2773
2774	/*
2775	* MMIO2 page.
2776	*/
2777	case PGM_STATE_REC_MMIO2_RAW:
2778	case PGM_STATE_REC_MMIO2_ZERO:
2779	{
2780	/*
2781	* Get the ID + page number and resolved that into a MMIO2 page.
2782	*/
2783	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2784	iPage++;
2785	else
2786	{
2787	SSMR3GetU8(pSSM, &id);
2788	rc = SSMR3GetU32(pSSM, &iPage);
2789	if (RT_FAILURE(rc))
2790	return rc;
2791	}
2792	if ( !pRegMmio
2793	\|\| pRegMmio->idSavedState != id)
2794	{
2795	for (pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
2796	if (pRegMmio->idSavedState == id)
2797	break;
2798	AssertLogRelMsgReturn(pRegMmio, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_MMIO2_RANGE_NOT_FOUND);
2799	}
2800	AssertLogRelMsgReturn(iPage < (pRegMmio->RamRange.cb >> GUEST_PAGE_SHIFT),
2801	("iPage=%#x cb=%RGp %s\n", iPage, pRegMmio->RamRange.cb, pRegMmio->RamRange.pszDesc),
2802	VERR_PGM_SAVED_MMIO2_PAGE_NOT_FOUND);
2803	void pvDstPage = (uint8_t )pRegMmio->RamRange.pvR3 + ((size_t)iPage << GUEST_PAGE_SHIFT);
2804
2805	/*
2806	* Load the page bits.
2807	*/
2808	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2809	RT_BZERO(pvDstPage, GUEST_PAGE_SIZE);
2810	else
2811	{
2812	rc = SSMR3GetMem(pSSM, pvDstPage, GUEST_PAGE_SIZE);
2813	if (RT_FAILURE(rc))
2814	return rc;
2815	}
2816	GCPhys = NIL_RTGCPHYS;
2817	break;
2818	}
2819
2820	/*
2821	* ROM pages.
2822	*/
2823	case PGM_STATE_REC_ROM_VIRGIN:
2824	case PGM_STATE_REC_ROM_SHW_RAW:
2825	case PGM_STATE_REC_ROM_SHW_ZERO:
2826	case PGM_STATE_REC_ROM_PROT:
2827	{
2828	/*
2829	* Get the ID + page number and resolved that into a ROM page descriptor.
2830	*/
2831	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2832	iPage++;
2833	else
2834	{
2835	SSMR3GetU8(pSSM, &id);
2836	rc = SSMR3GetU32(pSSM, &iPage);
2837	if (RT_FAILURE(rc))
2838	return rc;
2839	}
2840	if ( !pRom
2841	\|\| pRom->idSavedState != id)
2842	{
2843	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2844	if (pRom->idSavedState == id)
2845	break;
2846	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_ROM_RANGE_NOT_FOUND);
2847	}
2848	AssertLogRelMsgReturn(iPage < (pRom->cb >> GUEST_PAGE_SHIFT),
2849	("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc),
2850	VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2851	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2852	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << GUEST_PAGE_SHIFT);
2853
2854	/*
2855	* Get and set the protection.
2856	*/
2857	uint8_t u8Prot;
2858	rc = SSMR3GetU8(pSSM, &u8Prot);
2859	if (RT_FAILURE(rc))
2860	return rc;
2861	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2862	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_PGM_SAVED_ROM_PAGE_PROT);
2863
2864	if (enmProt != pRomPage->enmProt)
2865	{
2866	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2867	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2868	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2869	GCPhys, enmProt, pRom->pszDesc);
2870	rc = PGMR3PhysRomProtect(pVM, GCPhys, GUEST_PAGE_SIZE, enmProt);
2871	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2872	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2873	}
2874	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2875	break; /* done */
2876
2877	/*
2878	* Get the right page descriptor.
2879	*/
2880	PPGMPAGE pRealPage;
2881	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2882	{
2883	case PGM_STATE_REC_ROM_VIRGIN:
2884	if (!PGMROMPROT_IS_ROM(enmProt))
2885	pRealPage = &pRomPage->Virgin;
2886	else
2887	pRealPage = NULL;
2888	break;
2889
2890	case PGM_STATE_REC_ROM_SHW_RAW:
2891	case PGM_STATE_REC_ROM_SHW_ZERO:
2892	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2893	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2894	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2895	GCPhys, enmProt, pRom->pszDesc);
2896	if (PGMROMPROT_IS_ROM(enmProt))
2897	pRealPage = &pRomPage->Shadow;
2898	else
2899	pRealPage = NULL;
2900	break;
2901
2902	default: AssertLogRelFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE); /* shut up gcc */
2903	}
2904	#ifdef VBOX_WITH_PGM_NEM_MODE
2905	bool const fAltPage = pRealPage != NULL;
2906	#endif
2907	if (!pRealPage)
2908	{
2909	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pRealPage, &pRamHint);
2910	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2911	}
2912
2913	/*
2914	* Make it writable and map it (if necessary).
2915	*/
2916	void *pvDstPage = NULL;
2917	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2918	{
2919	case PGM_STATE_REC_ROM_SHW_ZERO:
2920	if ( PGM_PAGE_IS_ZERO(pRealPage)
2921	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2922	break;
2923	/** @todo implement zero page replacing. */
2924	RT_FALL_THRU();
2925	case PGM_STATE_REC_ROM_VIRGIN:
2926	case PGM_STATE_REC_ROM_SHW_RAW:
2927	#ifdef VBOX_WITH_PGM_NEM_MODE
2928	if (fAltPage && pVM->pgm.s.fNemMode)
2929	pvDstPage = &pRom->pbR3Alternate[iPage << GUEST_PAGE_SHIFT];
2930	else
2931	#endif
2932	{
2933	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2934	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2935	}
2936	break;
2937	}
2938
2939	/*
2940	* Load the bits.
2941	*/
2942	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2943	{
2944	case PGM_STATE_REC_ROM_SHW_ZERO:
2945	if (pvDstPage)
2946	RT_BZERO(pvDstPage, GUEST_PAGE_SIZE);
2947	break;
2948
2949	case PGM_STATE_REC_ROM_VIRGIN:
2950	case PGM_STATE_REC_ROM_SHW_RAW:
2951	rc = SSMR3GetMem(pSSM, pvDstPage, GUEST_PAGE_SIZE);
2952	if (RT_FAILURE(rc))
2953	return rc;
2954	break;
2955	}
2956	GCPhys = NIL_RTGCPHYS;
2957	break;
2958	}
2959
2960	/*
2961	* Unknown type.
2962	*/
2963	default:
2964	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2965	}
2966	} /* forever */
2967	}
2968
2969
2970	/**
2971	* Worker for pgmR3Load.
2972	*
2973	* @returns VBox status code.
2974	*
2975	* @param pVM The cross context VM structure.
2976	* @param pSSM The SSM handle.
2977	* @param uVersion The saved state version.
2978	*/
2979	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2980	{
2981	PPGM pPGM = &pVM->pgm.s;
2982	int rc;
2983	uint32_t u32Sep;
2984
2985	/*
2986	* Load basic data (required / unaffected by relocation).
2987	*/
2988	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2989	{
2990	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2991	rc = SSMR3GetStructEx(pSSM, pPGM, sizeof(pPGM), 0 /fFlags/, &s_aPGMFields[0], NULL /pvUser*/);
2992	else
2993	rc = SSMR3GetStructEx(pSSM, pPGM, sizeof(pPGM), 0 /fFlags/, &s_aPGMFieldsPreBalloon[0], NULL /pvUser*/);
2994
2995	AssertLogRelRCReturn(rc, rc);
2996
2997	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2998	{
2999	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
3000	rc = SSMR3GetStruct(pSSM, &pVM->apCpusR3[i]->pgm.s, &s_aPGMCpuFieldsPrePae[0]);
3001	else
3002	rc = SSMR3GetStruct(pSSM, &pVM->apCpusR3[i]->pgm.s, &s_aPGMCpuFields[0]);
3003	AssertLogRelRCReturn(rc, rc);
3004	}
3005	}
3006	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
3007	{
3008	AssertRelease(pVM->cCpus == 1);
3009
3010	PGMOLD pgmOld;
3011	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
3012	AssertLogRelRCReturn(rc, rc);
3013
3014	PVMCPU pVCpu0 = pVM->apCpusR3[0];
3015	pVCpu0->pgm.s.fA20Enabled = pgmOld.fA20Enabled;
3016	pVCpu0->pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
3017	pVCpu0->pgm.s.enmGuestMode = pgmOld.enmGuestMode;
3018	}
3019	else
3020	{
3021	AssertRelease(pVM->cCpus == 1);
3022
3023	SSMR3Skip(pSSM, sizeof(bool));
3024	RTGCPTR GCPtrIgn;
3025	SSMR3GetGCPtr(pSSM, &GCPtrIgn);
3026	SSMR3Skip(pSSM, sizeof(uint32_t));
3027
3028	uint32_t cbRamSizeIgnored;
3029	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
3030	if (RT_FAILURE(rc))
3031	return rc;
3032	PVMCPU pVCpu0 = pVM->apCpusR3[0];
3033	SSMR3GetGCPhys(pSSM, &pVCpu0->pgm.s.GCPhysA20Mask);
3034
3035	uint32_t u32 = 0;
3036	SSMR3GetUInt(pSSM, &u32);
3037	pVCpu0->pgm.s.fA20Enabled = !!u32;
3038	SSMR3GetUInt(pSSM, &pVCpu0->pgm.s.fSyncFlags);
3039	RTUINT uGuestMode;
3040	SSMR3GetUInt(pSSM, &uGuestMode);
3041	pVCpu0->pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
3042
3043	/* check separator. */
3044	SSMR3GetU32(pSSM, &u32Sep);
3045	if (RT_FAILURE(rc))
3046	return rc;
3047	if (u32Sep != (uint32_t)~0)
3048	{
3049	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
3050	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3051	}
3052	}
3053
3054	/*
3055	* Fix the A20 mask.
3056	*/
3057	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3058	{
3059	PVMCPU pVCpu = pVM->apCpusR3[i];
3060	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
3061	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
3062	}
3063
3064	/*
3065	* The guest mappings - skipped now, see re-fixation in the caller.
3066	*/
3067	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
3068	{
3069	for (uint32_t i = 0; ; i++)
3070	{
3071	rc = SSMR3GetU32(pSSM, &u32Sep); /* sequence number */
3072	if (RT_FAILURE(rc))
3073	return rc;
3074	if (u32Sep == ~0U)
3075	break;
3076	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3077
3078	char szDesc[256];
3079	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
3080	if (RT_FAILURE(rc))
3081	return rc;
3082	RTGCPTR GCPtrIgnore;
3083	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
3084	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
3085	if (RT_FAILURE(rc))
3086	return rc;
3087	}
3088	}
3089
3090	/*
3091	* Load the RAM contents.
3092	*/
3093	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
3094	{
3095	if (!pVM->pgm.s.LiveSave.fActive)
3096	{
3097	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3098	{
3099	rc = pgmR3LoadRamConfig(pVM, pSSM);
3100	if (RT_FAILURE(rc))
3101	return rc;
3102	}
3103	rc = pgmR3LoadRomRanges(pVM, pSSM);
3104	if (RT_FAILURE(rc))
3105	return rc;
3106	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3107	if (RT_FAILURE(rc))
3108	return rc;
3109	}
3110
3111	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, SSM_PASS_FINAL);
3112	}
3113	else
3114	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
3115
3116	/* Refresh balloon accounting. */
3117	if (pVM->pgm.s.cBalloonedPages)
3118	{
3119	Log(("pgmR3LoadFinalLocked: pVM=%p cBalloonedPages=%#x\n", pVM, pVM->pgm.s.cBalloonedPages));
3120	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
3121	AssertRCReturn(rc, rc);
3122	}
3123	return rc;
3124	}
3125
3126
3127	/**
3128	* @callback_method_impl{FNSSMINTLOADEXEC}
3129	*/
3130	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3131	{
3132	int rc;
3133
3134	/*
3135	* Validate version.
3136	*/
3137	if ( ( uPass != SSM_PASS_FINAL
3138	&& uVersion != PGM_SAVED_STATE_VERSION
3139	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3140	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3141	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3142	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3143	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
3144	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3145	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3146	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3147	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
3148	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
3149	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3150	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3151	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3152	)
3153	{
3154	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3155	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3156	}
3157
3158	/*
3159	* Do the loading while owning the lock because a bunch of the functions
3160	* we're using requires this.
3161	*/
3162	if (uPass != SSM_PASS_FINAL)
3163	{
3164	PGM_LOCK_VOID(pVM);
3165	if (uPass != 0)
3166	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3167	else
3168	{
3169	pVM->pgm.s.LiveSave.fActive = true;
3170	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3171	rc = pgmR3LoadRamConfig(pVM, pSSM);
3172	else
3173	rc = VINF_SUCCESS;
3174	if (RT_SUCCESS(rc))
3175	rc = pgmR3LoadRomRanges(pVM, pSSM);
3176	if (RT_SUCCESS(rc))
3177	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3178	if (RT_SUCCESS(rc))
3179	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3180	}
3181	PGM_UNLOCK(pVM);
3182	}
3183	else
3184	{
3185	PGM_LOCK_VOID(pVM);
3186	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3187	pVM->pgm.s.LiveSave.fActive = false;
3188	PGM_UNLOCK(pVM);
3189	if (RT_SUCCESS(rc))
3190	{
3191	/*
3192	* We require a full resync now.
3193	*/
3194	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3195	{
3196	PVMCPU pVCpu = pVM->apCpusR3[i];
3197	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3198	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3199	/** @todo For guest PAE, we might get the wrong
3200	* aGCPhysGstPaePDs values now. We should used the
3201	* saved ones... Postponing this since it nothing new
3202	* and PAE/PDPTR needs some general readjusting, see
3203	* @bugref{5880}. */
3204	}
3205
3206	pgmR3HandlerPhysicalUpdateAll(pVM);
3207
3208	/*
3209	* Change the paging mode (indirectly restores PGMCPU::GCPhysCR3).
3210	* (Requires the CPUM state to be restored already!)
3211	*/
3212	if (CPUMR3IsStateRestorePending(pVM))
3213	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3214	N_("PGM was unexpectedly restored before CPUM"));
3215
3216	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3217	{
3218	PVMCPU pVCpu = pVM->apCpusR3[i];
3219
3220	rc = PGMHCChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode, false /* fForce */);
3221	AssertLogRelRCReturn(rc, rc);
3222
3223	#if !defined(VBOX_VMM_TARGET_ARMV8)
3224	/* Update the PSE, NX flags and validity masks. */
3225	pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3226	PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3227	#endif
3228	}
3229	}
3230	}
3231
3232	return rc;
3233	}
3234
3235
3236	/**
3237	* @callback_method_impl{FNSSMINTLOADDONE}
3238	*/
3239	static DECLCALLBACK(int) pgmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3240	{
3241	pVM->pgm.s.fRestoreRomPagesOnReset = true;
3242	NOREF(pSSM);
3243	return VINF_SUCCESS;
3244	}
3245
3246
3247	/**
3248	* Registers the saved state callbacks with SSM.
3249	*
3250	* @returns VBox status code.
3251	* @param pVM The cross context VM structure.
3252	* @param cbRam The RAM size.
3253	*/
3254	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3255	{
3256	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3257	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3258	NULL, pgmR3SaveExec, pgmR3SaveDone,
3259	pgmR3LoadPrep, pgmR3Load, pgmR3LoadDone);
3260	}
3261

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMSavedState.cpp@ 102828

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