VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 44399

Last change on this file since 44399 was 44399, checked in by vboxsync, 12 years ago

DBGF,DBGC,++: PVM -> PUVM. Some refactoring and cleanup as well.

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1/* $Id: PGM.cpp 44399 2013-01-27 21:12:53Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @page pg_pgm PGM - The Page Manager and Monitor
20 *
21 * @see grp_pgm,
22 * @ref pg_pgm_pool,
23 * @ref pg_pgm_phys.
24 *
25 *
26 * @section sec_pgm_modes Paging Modes
27 *
28 * There are three memory contexts: Host Context (HC), Guest Context (GC)
29 * and intermediate context. When talking about paging HC can also be referred
30 * to as "host paging", and GC referred to as "shadow paging".
31 *
32 * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33 * is defined by the host operating system. The mode used in the shadow paging mode
34 * depends on the host paging mode and what the mode the guest is currently in. The
35 * following relation between the two is defined:
36 *
37 * @verbatim
38 Host > 32-bit | PAE | AMD64 |
39 Guest | | | |
40 ==v================================
41 32-bit 32-bit PAE PAE
42 -------|--------|--------|--------|
43 PAE PAE PAE PAE
44 -------|--------|--------|--------|
45 AMD64 AMD64 AMD64 AMD64
46 -------|--------|--------|--------| @endverbatim
47 *
48 * All configuration except those in the diagonal (upper left) are expected to
49 * require special effort from the switcher (i.e. a bit slower).
50 *
51 *
52 *
53 *
54 * @section sec_pgm_shw The Shadow Memory Context
55 *
56 *
57 * [..]
58 *
59 * Because of guest context mappings requires PDPT and PML4 entries to allow
60 * writing on AMD64, the two upper levels will have fixed flags whatever the
61 * guest is thinking of using there. So, when shadowing the PD level we will
62 * calculate the effective flags of PD and all the higher levels. In legacy
63 * PAE mode this only applies to the PWT and PCD bits (the rest are
64 * ignored/reserved/MBZ). We will ignore those bits for the present.
65 *
66 *
67 *
68 * @section sec_pgm_int The Intermediate Memory Context
69 *
70 * The world switch goes thru an intermediate memory context which purpose it is
71 * to provide different mappings of the switcher code. All guest mappings are also
72 * present in this context.
73 *
74 * The switcher code is mapped at the same location as on the host, at an
75 * identity mapped location (physical equals virtual address), and at the
76 * hypervisor location. The identity mapped location is for when the world
77 * switches that involves disabling paging.
78 *
79 * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80 * simplifies switching guest CPU mode and consistency at the cost of more
81 * code to do the work. All memory use for those page tables is located below
82 * 4GB (this includes page tables for guest context mappings).
83 *
84 *
85 * @subsection subsec_pgm_int_gc Guest Context Mappings
86 *
87 * During assignment and relocation of a guest context mapping the intermediate
88 * memory context is used to verify the new location.
89 *
90 * Guest context mappings are currently restricted to below 4GB, for reasons
91 * of simplicity. This may change when we implement AMD64 support.
92 *
93 *
94 *
95 *
96 * @section sec_pgm_misc Misc
97 *
98 *
99 * @subsection sec_pgm_misc_A20 The A20 Gate
100 *
101 * PGM implements the A20 gate masking when translating a virtual guest address
102 * into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
103 * the code reading the guest page table entries during shadowing. The masking
104 * is done consistenly for all CPU modes, paged ones included. Large pages are
105 * also masked correctly. (On current CPUs, experiments indicates that AMD does
106 * not apply A20M in paged modes and intel only does it for the 2nd MB of
107 * memory.)
108 *
109 * The A20 gate implementation is per CPU core. It can be configured on a per
110 * core basis via the keyboard device and PC architecture device. This is
111 * probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
112 * guest OSes try pushing things anyway, so who cares. (On current real systems
113 * the A20M signal is probably only sent to the boot CPU and it affects all
114 * thread and probably all cores in that package.)
115 *
116 * The keyboard device and the PC architecture device doesn't OR their A20
117 * config bits together, rather they are currently implemented such that they
118 * mirror the CPU state. So, flipping the bit in either of them will change the
119 * A20 state. (On real hardware the bits of the two devices should probably be
120 * ORed together to indicate enabled, i.e. both needs to be cleared to disable
121 * A20 masking.)
122 *
123 * The A20 state will change immediately, transmeta fashion. There is no delays
124 * due to buses, wiring or other physical stuff. (On real hardware there are
125 * normally delays, the delays differs between the two devices and probably also
126 * between chipsets and CPU generations. Note that it's said that transmeta CPUs
127 * does the change immediately like us, they apparently intercept/handles the
128 * port accesses in microcode. Neat.)
129 *
130 * @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
131 *
132 *
133 * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
134 *
135 * The differences between legacy PAE and long mode PAE are:
136 * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
137 * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
138 * usual meanings while 6 is ignored (AMD). This means that upon switching to
139 * legacy PAE mode we'll have to clear these bits and when going to long mode
140 * they must be set. This applies to both intermediate and shadow contexts,
141 * however we don't need to do it for the intermediate one since we're
142 * executing with CR0.WP at that time.
143 * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
144 * a page aligned one is required.
145 *
146 *
147 * @section sec_pgm_handlers Access Handlers
148 *
149 * Placeholder.
150 *
151 *
152 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
153 *
154 * Placeholder.
155 *
156 *
157 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
158 *
159 * We currently implement three types of virtual access handlers: ALL, WRITE
160 * and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
161 *
162 * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
163 * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
164 * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
165 * rest of this section is going to be about these handlers.
166 *
167 * We'll go thru the life cycle of a handler and try make sense of it all, don't know
168 * how successful this is gonna be...
169 *
170 * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
171 * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
172 * and create a new node that is inserted into the AVL tree (range key). Then
173 * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
174 *
175 * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
176 *
177 * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
178 * via the current guest CR3 and update the physical page -> virtual handler
179 * translation. Needless to say, this doesn't exactly scale very well. If any changes
180 * are detected, it will flag a virtual bit update just like we did on registration.
181 * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
182 *
183 * 2b. The virtual bit update process will iterate all the pages covered by all the
184 * virtual handlers and update the PGMPAGE virtual handler state to the max of all
185 * virtual handlers on that page.
186 *
187 * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
188 * we don't miss any alias mappings of the monitored pages.
189 *
190 * 2d. SyncCR3 will then proceed with syncing the CR3 table.
191 *
192 * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
193 * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
194 * will call the handlers like in the next step. If the physical mapping has
195 * changed we will - some time in the future - perform a handler callback
196 * (optional) and update the physical -> virtual handler cache.
197 *
198 * 4. \#PF(,write) on a page in the range. This will cause the handler to
199 * be invoked.
200 *
201 * 5. The guest invalidates the page and changes the physical backing or
202 * unmaps it. This should cause the invalidation callback to be invoked
203 * (it might not yet be 100% perfect). Exactly what happens next... is
204 * this where we mess up and end up out of sync for a while?
205 *
206 * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
207 * We will then set all PGMPAGEs in the physical -> virtual handler cache for
208 * this handler to NONE and trigger a full PGM resync (basically the same
209 * as int step 1). Which means 2 is executed again.
210 *
211 *
212 * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
213 *
214 * There is a bunch of things that needs to be done to make the virtual handlers
215 * work 100% correctly and work more efficiently.
216 *
217 * The first bit hasn't been implemented yet because it's going to slow the
218 * whole mess down even more, and besides it seems to be working reliably for
219 * our current uses. OTOH, some of the optimizations might end up more or less
220 * implementing the missing bits, so we'll see.
221 *
222 * On the optimization side, the first thing to do is to try avoid unnecessary
223 * cache flushing. Then try team up with the shadowing code to track changes
224 * in mappings by means of access to them (shadow in), updates to shadows pages,
225 * invlpg, and shadow PT discarding (perhaps).
226 *
227 * Some idea that have popped up for optimization for current and new features:
228 * - bitmap indicating where there are virtual handlers installed.
229 * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
230 * - Further optimize this by min/max (needs min/max avl getters).
231 * - Shadow page table entry bit (if any left)?
232 *
233 */
234
235
236/** @page pg_pgm_phys PGM Physical Guest Memory Management
237 *
238 *
239 * Objectives:
240 * - Guest RAM over-commitment using memory ballooning,
241 * zero pages and general page sharing.
242 * - Moving or mirroring a VM onto a different physical machine.
243 *
244 *
245 * @subsection subsec_pgmPhys_Definitions Definitions
246 *
247 * Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
248 * machinery associated with it.
249 *
250 *
251 *
252 *
253 * @subsection subsec_pgmPhys_AllocPage Allocating a page.
254 *
255 * Initially we map *all* guest memory to the (per VM) zero page, which
256 * means that none of the read functions will cause pages to be allocated.
257 *
258 * Exception, access bit in page tables that have been shared. This must
259 * be handled, but we must also make sure PGMGst*Modify doesn't make
260 * unnecessary modifications.
261 *
262 * Allocation points:
263 * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
264 * - Replacing a zero page mapping at \#PF.
265 * - Replacing a shared page mapping at \#PF.
266 * - ROM registration (currently MMR3RomRegister).
267 * - VM restore (pgmR3Load).
268 *
269 * For the first three it would make sense to keep a few pages handy
270 * until we've reached the max memory commitment for the VM.
271 *
272 * For the ROM registration, we know exactly how many pages we need
273 * and will request these from ring-0. For restore, we will save
274 * the number of non-zero pages in the saved state and allocate
275 * them up front. This would allow the ring-0 component to refuse
276 * the request if the isn't sufficient memory available for VM use.
277 *
278 * Btw. for both ROM and restore allocations we won't be requiring
279 * zeroed pages as they are going to be filled instantly.
280 *
281 *
282 * @subsection subsec_pgmPhys_FreePage Freeing a page
283 *
284 * There are a few points where a page can be freed:
285 * - After being replaced by the zero page.
286 * - After being replaced by a shared page.
287 * - After being ballooned by the guest additions.
288 * - At reset.
289 * - At restore.
290 *
291 * When freeing one or more pages they will be returned to the ring-0
292 * component and replaced by the zero page.
293 *
294 * The reasoning for clearing out all the pages on reset is that it will
295 * return us to the exact same state as on power on, and may thereby help
296 * us reduce the memory load on the system. Further it might have a
297 * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
298 *
299 * On restore, as mention under the allocation topic, pages should be
300 * freed / allocated depending on how many is actually required by the
301 * new VM state. The simplest approach is to do like on reset, and free
302 * all non-ROM pages and then allocate what we need.
303 *
304 * A measure to prevent some fragmentation, would be to let each allocation
305 * chunk have some affinity towards the VM having allocated the most pages
306 * from it. Also, try make sure to allocate from allocation chunks that
307 * are almost full. Admittedly, both these measures might work counter to
308 * our intentions and its probably not worth putting a lot of effort,
309 * cpu time or memory into this.
310 *
311 *
312 * @subsection subsec_pgmPhys_SharePage Sharing a page
313 *
314 * The basic idea is that there there will be a idle priority kernel
315 * thread walking the non-shared VM pages hashing them and looking for
316 * pages with the same checksum. If such pages are found, it will compare
317 * them byte-by-byte to see if they actually are identical. If found to be
318 * identical it will allocate a shared page, copy the content, check that
319 * the page didn't change while doing this, and finally request both the
320 * VMs to use the shared page instead. If the page is all zeros (special
321 * checksum and byte-by-byte check) it will request the VM that owns it
322 * to replace it with the zero page.
323 *
324 * To make this efficient, we will have to make sure not to try share a page
325 * that will change its contents soon. This part requires the most work.
326 * A simple idea would be to request the VM to write monitor the page for
327 * a while to make sure it isn't modified any time soon. Also, it may
328 * make sense to skip pages that are being write monitored since this
329 * information is readily available to the thread if it works on the
330 * per-VM guest memory structures (presently called PGMRAMRANGE).
331 *
332 *
333 * @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
334 *
335 * The pages are organized in allocation chunks in ring-0, this is a necessity
336 * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
337 * could easily work on a page-by-page basis if we liked. Whether this is possible
338 * or efficient on NT I don't quite know.) Fragmentation within these chunks may
339 * become a problem as part of the idea here is that we wish to return memory to
340 * the host system.
341 *
342 * For instance, starting two VMs at the same time, they will both allocate the
343 * guest memory on-demand and if permitted their page allocations will be
344 * intermixed. Shut down one of the two VMs and it will be difficult to return
345 * any memory to the host system because the page allocation for the two VMs are
346 * mixed up in the same allocation chunks.
347 *
348 * To further complicate matters, when pages are freed because they have been
349 * ballooned or become shared/zero the whole idea is that the page is supposed
350 * to be reused by another VM or returned to the host system. This will cause
351 * allocation chunks to contain pages belonging to different VMs and prevent
352 * returning memory to the host when one of those VM shuts down.
353 *
354 * The only way to really deal with this problem is to move pages. This can
355 * either be done at VM shutdown and or by the idle priority worker thread
356 * that will be responsible for finding sharable/zero pages. The mechanisms
357 * involved for coercing a VM to move a page (or to do it for it) will be
358 * the same as when telling it to share/zero a page.
359 *
360 *
361 * @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
362 *
363 * There's a difficult balance between keeping the per-page tracking structures
364 * (global and guest page) easy to use and keeping them from eating too much
365 * memory. We have limited virtual memory resources available when operating in
366 * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
367 * tracking structures will be attempted designed such that we can deal with up
368 * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
369 *
370 *
371 * @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
372 *
373 * @see pg_GMM
374 *
375 * @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
376 *
377 * Fixed info is the physical address of the page (HCPhys) and the page id
378 * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
379 * Today we've restricting ourselves to 40(-12) bits because this is the current
380 * restrictions of all AMD64 implementations (I think Barcelona will up this
381 * to 48(-12) bits, not that it really matters) and I needed the bits for
382 * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
383 * decent range for the page id: 2^(28+12) = 1024TB.
384 *
385 * In additions to these, we'll have to keep maintaining the page flags as we
386 * currently do. Although it wouldn't harm to optimize these quite a bit, like
387 * for instance the ROM shouldn't depend on having a write handler installed
388 * in order for it to become read-only. A RO/RW bit should be considered so
389 * that the page syncing code doesn't have to mess about checking multiple
390 * flag combinations (ROM || RW handler || write monitored) in order to
391 * figure out how to setup a shadow PTE. But this of course, is second
392 * priority at present. Current this requires 12 bits, but could probably
393 * be optimized to ~8.
394 *
395 * Then there's the 24 bits used to track which shadow page tables are
396 * currently mapping a page for the purpose of speeding up physical
397 * access handlers, and thereby the page pool cache. More bit for this
398 * purpose wouldn't hurt IIRC.
399 *
400 * Then there is a new bit in which we need to record what kind of page
401 * this is, shared, zero, normal or write-monitored-normal. This'll
402 * require 2 bits. One bit might be needed for indicating whether a
403 * write monitored page has been written to. And yet another one or
404 * two for tracking migration status. 3-4 bits total then.
405 *
406 * Whatever is left will can be used to record the sharabilitiy of a
407 * page. The page checksum will not be stored in the per-VM table as
408 * the idle thread will not be permitted to do modifications to it.
409 * It will instead have to keep its own working set of potentially
410 * shareable pages and their check sums and stuff.
411 *
412 * For the present we'll keep the current packing of the
413 * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
414 * we'll have to change it to a struct with a total of 128-bits at
415 * our disposal.
416 *
417 * The initial layout will be like this:
418 * @verbatim
419 RTHCPHYS HCPhys; The current stuff.
420 63:40 Current shadow PT tracking stuff.
421 39:12 The physical page frame number.
422 11:0 The current flags.
423 uint32_t u28PageId : 28; The page id.
424 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
425 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
426 uint32_t u1Reserved : 1; Reserved for later.
427 uint32_t u32Reserved; Reserved for later, mostly sharing stats.
428 @endverbatim
429 *
430 * The final layout will be something like this:
431 * @verbatim
432 RTHCPHYS HCPhys; The current stuff.
433 63:48 High page id (12+).
434 47:12 The physical page frame number.
435 11:0 Low page id.
436 uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
437 uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
438 uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
439 uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
440 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
441 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
442 uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
443 uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
444 @endverbatim
445 *
446 * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
447 * around that I'm afraid. It means that the cost of dealing out 32GB of memory
448 * to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
449 * example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
450 *
451 * A couple of cost examples for the total cost per-VM + kernel.
452 * 32-bit Windows and 32-bit linux:
453 * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
454 * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
455 * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
456 * 64-bit Windows and 64-bit linux:
457 * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
458 * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
459 * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
460 *
461 * UPDATE - 2007-09-27:
462 * Will need a ballooned flag/state too because we cannot
463 * trust the guest 100% and reporting the same page as ballooned more
464 * than once will put the GMM off balance.
465 *
466 *
467 * @subsection subsec_pgmPhys_Serializing Serializing Access
468 *
469 * Initially, we'll try a simple scheme:
470 *
471 * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
472 * by the EMT thread of that VM while in the pgm critsect.
473 * - Other threads in the VM process that needs to make reliable use of
474 * the per-VM RAM tracking structures will enter the critsect.
475 * - No process external thread or kernel thread will ever try enter
476 * the pgm critical section, as that just won't work.
477 * - The idle thread (and similar threads) doesn't not need 100% reliable
478 * data when performing it tasks as the EMT thread will be the one to
479 * do the actual changes later anyway. So, as long as it only accesses
480 * the main ram range, it can do so by somehow preventing the VM from
481 * being destroyed while it works on it...
482 *
483 * - The over-commitment management, including the allocating/freeing
484 * chunks, is serialized by a ring-0 mutex lock (a fast one since the
485 * more mundane mutex implementation is broken on Linux).
486 * - A separate mutex is protecting the set of allocation chunks so
487 * that pages can be shared or/and freed up while some other VM is
488 * allocating more chunks. This mutex can be take from under the other
489 * one, but not the other way around.
490 *
491 *
492 * @subsection subsec_pgmPhys_Request VM Request interface
493 *
494 * When in ring-0 it will become necessary to send requests to a VM so it can
495 * for instance move a page while defragmenting during VM destroy. The idle
496 * thread will make use of this interface to request VMs to setup shared
497 * pages and to perform write monitoring of pages.
498 *
499 * I would propose an interface similar to the current VMReq interface, similar
500 * in that it doesn't require locking and that the one sending the request may
501 * wait for completion if it wishes to. This shouldn't be very difficult to
502 * realize.
503 *
504 * The requests themselves are also pretty simple. They are basically:
505 * -# Check that some precondition is still true.
506 * -# Do the update.
507 * -# Update all shadow page tables involved with the page.
508 *
509 * The 3rd step is identical to what we're already doing when updating a
510 * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
511 *
512 *
513 *
514 * @section sec_pgmPhys_MappingCaches Mapping Caches
515 *
516 * In order to be able to map in and out memory and to be able to support
517 * guest with more RAM than we've got virtual address space, we'll employing
518 * a mapping cache. Normally ring-0 and ring-3 can share the same cache,
519 * however on 32-bit darwin the ring-0 code is running in a different memory
520 * context and therefore needs a separate cache. In raw-mode context we also
521 * need a separate cache. The 32-bit darwin mapping cache and the one for
522 * raw-mode context share a lot of code, see PGMRZDYNMAP.
523 *
524 *
525 * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
526 *
527 * We've considered implementing the ring-3 mapping cache page based but found
528 * that this was bother some when one had to take into account TLBs+SMP and
529 * portability (missing the necessary APIs on several platforms). There were
530 * also some performance concerns with this approach which hadn't quite been
531 * worked out.
532 *
533 * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
534 * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
535 * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
536 * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
537 * costly than a single page, although how much more costly is uncertain. We'll
538 * try address this by using a very big cache, preferably bigger than the actual
539 * VM RAM size if possible. The current VM RAM sizes should give some idea for
540 * 32-bit boxes, while on 64-bit we can probably get away with employing an
541 * unlimited cache.
542 *
543 * The cache have to parts, as already indicated, the ring-3 side and the
544 * ring-0 side.
545 *
546 * The ring-0 will be tied to the page allocator since it will operate on the
547 * memory objects it contains. It will therefore require the first ring-0 mutex
548 * discussed in @ref subsec_pgmPhys_Serializing. We
549 * some double house keeping wrt to who has mapped what I think, since both
550 * VMMR0.r0 and RTR0MemObj will keep track of mapping relations
551 *
552 * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
553 * require anyone that desires to do changes to the mapping cache to do that
554 * from within this critsect. Alternatively, we could employ a separate critsect
555 * for serializing changes to the mapping cache as this would reduce potential
556 * contention with other threads accessing mappings unrelated to the changes
557 * that are in process. We can see about this later, contention will show
558 * up in the statistics anyway, so it'll be simple to tell.
559 *
560 * The organization of the ring-3 part will be very much like how the allocation
561 * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
562 * having to walk the tree all the time, we'll have a couple of lookaside entries
563 * like in we do for I/O ports and MMIO in IOM.
564 *
565 * The simplified flow of a PGMPhysRead/Write function:
566 * -# Enter the PGM critsect.
567 * -# Lookup GCPhys in the ram ranges and get the Page ID.
568 * -# Calc the Allocation Chunk ID from the Page ID.
569 * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
570 * If not found in cache:
571 * -# Call ring-0 and request it to be mapped and supply
572 * a chunk to be unmapped if the cache is maxed out already.
573 * -# Insert the new mapping into the AVL tree (id + R3 address).
574 * -# Update the relevant lookaside entry and return the mapping address.
575 * -# Do the read/write according to monitoring flags and everything.
576 * -# Leave the critsect.
577 *
578 *
579 * @section sec_pgmPhys_Fallback Fallback
580 *
581 * Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
582 * API and thus require a fallback.
583 *
584 * So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
585 * will return to the ring-3 caller (and later ring-0) and asking it to seed
586 * the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
587 * then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
588 * "SeededAllocPages" call to ring-0.
589 *
590 * The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
591 * all page sharing (zero page detection will continue). It will also force
592 * all allocations to come from the VM which seeded the page. Both these
593 * measures are taken to make sure that there will never be any need for
594 * mapping anything into ring-3 - everything will be mapped already.
595 *
596 * Whether we'll continue to use the current MM locked memory management
597 * for this I don't quite know (I'd prefer not to and just ditch that all
598 * together), we'll see what's simplest to do.
599 *
600 *
601 *
602 * @section sec_pgmPhys_Changes Changes
603 *
604 * Breakdown of the changes involved?
605 */
606
607/*******************************************************************************
608* Header Files *
609*******************************************************************************/
610#define LOG_GROUP LOG_GROUP_PGM
611#include <VBox/vmm/dbgf.h>
612#include <VBox/vmm/pgm.h>
613#include <VBox/vmm/cpum.h>
614#include <VBox/vmm/iom.h>
615#include <VBox/sup.h>
616#include <VBox/vmm/mm.h>
617#include <VBox/vmm/em.h>
618#include <VBox/vmm/stam.h>
619#ifdef VBOX_WITH_REM
620# include <VBox/vmm/rem.h>
621#endif
622#include <VBox/vmm/selm.h>
623#include <VBox/vmm/ssm.h>
624#include <VBox/vmm/hm.h>
625#include "PGMInternal.h"
626#include <VBox/vmm/vm.h>
627#include <VBox/vmm/uvm.h>
628#include "PGMInline.h"
629
630#include <VBox/dbg.h>
631#include <VBox/param.h>
632#include <VBox/err.h>
633
634#include <iprt/asm.h>
635#include <iprt/asm-amd64-x86.h>
636#include <iprt/assert.h>
637#include <iprt/env.h>
638#include <iprt/mem.h>
639#include <iprt/file.h>
640#include <iprt/string.h>
641#include <iprt/thread.h>
642
643
644/*******************************************************************************
645* Internal Functions *
646*******************************************************************************/
647static int pgmR3InitPaging(PVM pVM);
648static int pgmR3InitStats(PVM pVM);
649static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
650static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
651static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
652static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
653static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
654static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
655#ifdef VBOX_STRICT
656static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
657#endif
658static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
659static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
660static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
661
662#ifdef VBOX_WITH_DEBUGGER
663static FNDBGCCMD pgmR3CmdError;
664static FNDBGCCMD pgmR3CmdSync;
665static FNDBGCCMD pgmR3CmdSyncAlways;
666# ifdef VBOX_STRICT
667static FNDBGCCMD pgmR3CmdAssertCR3;
668# endif
669static FNDBGCCMD pgmR3CmdPhysToFile;
670#endif
671
672
673/*******************************************************************************
674* Global Variables *
675*******************************************************************************/
676#ifdef VBOX_WITH_DEBUGGER
677/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
678static const DBGCVARDESC g_aPgmErrorArgs[] =
679{
680 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
681 { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
682};
683
684static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
685{
686 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
687 { 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
688 { 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
689};
690
691# ifdef DEBUG_sandervl
692static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
693{
694 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
695 { 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
696 { 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
697};
698# endif
699
700/** Command descriptors. */
701static const DBGCCMD g_aCmds[] =
702{
703 /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
704 { "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
705 { "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
706 { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
707# ifdef VBOX_STRICT
708 { "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
709# ifdef VBOX_WITH_PAGE_SHARING
710 { "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
711 { "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
712# endif
713# endif
714 { "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
715 { "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
716};
717#endif
718
719
720
721
722/*
723 * Shadow - 32-bit mode
724 */
725#define PGM_SHW_TYPE PGM_TYPE_32BIT
726#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
727#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
728#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
729#include "PGMShw.h"
730
731/* Guest - real mode */
732#define PGM_GST_TYPE PGM_TYPE_REAL
733#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
734#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
735#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
736#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
737#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
738#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
739#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
740#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
741#include "PGMBth.h"
742#include "PGMGstDefs.h"
743#include "PGMGst.h"
744#undef BTH_PGMPOOLKIND_PT_FOR_PT
745#undef BTH_PGMPOOLKIND_ROOT
746#undef PGM_BTH_NAME
747#undef PGM_BTH_NAME_RC_STR
748#undef PGM_BTH_NAME_R0_STR
749#undef PGM_GST_TYPE
750#undef PGM_GST_NAME
751#undef PGM_GST_NAME_RC_STR
752#undef PGM_GST_NAME_R0_STR
753
754/* Guest - protected mode */
755#define PGM_GST_TYPE PGM_TYPE_PROT
756#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
757#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
758#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
759#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
760#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
761#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
762#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
763#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
764#include "PGMBth.h"
765#include "PGMGstDefs.h"
766#include "PGMGst.h"
767#undef BTH_PGMPOOLKIND_PT_FOR_PT
768#undef BTH_PGMPOOLKIND_ROOT
769#undef PGM_BTH_NAME
770#undef PGM_BTH_NAME_RC_STR
771#undef PGM_BTH_NAME_R0_STR
772#undef PGM_GST_TYPE
773#undef PGM_GST_NAME
774#undef PGM_GST_NAME_RC_STR
775#undef PGM_GST_NAME_R0_STR
776
777/* Guest - 32-bit mode */
778#define PGM_GST_TYPE PGM_TYPE_32BIT
779#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
780#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
781#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
782#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
783#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
784#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
785#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
786#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
787#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
788#include "PGMBth.h"
789#include "PGMGstDefs.h"
790#include "PGMGst.h"
791#undef BTH_PGMPOOLKIND_PT_FOR_BIG
792#undef BTH_PGMPOOLKIND_PT_FOR_PT
793#undef BTH_PGMPOOLKIND_ROOT
794#undef PGM_BTH_NAME
795#undef PGM_BTH_NAME_RC_STR
796#undef PGM_BTH_NAME_R0_STR
797#undef PGM_GST_TYPE
798#undef PGM_GST_NAME
799#undef PGM_GST_NAME_RC_STR
800#undef PGM_GST_NAME_R0_STR
801
802#undef PGM_SHW_TYPE
803#undef PGM_SHW_NAME
804#undef PGM_SHW_NAME_RC_STR
805#undef PGM_SHW_NAME_R0_STR
806
807
808/*
809 * Shadow - PAE mode
810 */
811#define PGM_SHW_TYPE PGM_TYPE_PAE
812#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
813#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
814#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
815#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
816#include "PGMShw.h"
817
818/* Guest - real mode */
819#define PGM_GST_TYPE PGM_TYPE_REAL
820#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
821#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
822#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
823#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
824#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
825#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
826#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
827#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
828#include "PGMGstDefs.h"
829#include "PGMBth.h"
830#undef BTH_PGMPOOLKIND_PT_FOR_PT
831#undef BTH_PGMPOOLKIND_ROOT
832#undef PGM_BTH_NAME
833#undef PGM_BTH_NAME_RC_STR
834#undef PGM_BTH_NAME_R0_STR
835#undef PGM_GST_TYPE
836#undef PGM_GST_NAME
837#undef PGM_GST_NAME_RC_STR
838#undef PGM_GST_NAME_R0_STR
839
840/* Guest - protected mode */
841#define PGM_GST_TYPE PGM_TYPE_PROT
842#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
843#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
844#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
845#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
846#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
847#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
848#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
849#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
850#include "PGMGstDefs.h"
851#include "PGMBth.h"
852#undef BTH_PGMPOOLKIND_PT_FOR_PT
853#undef BTH_PGMPOOLKIND_ROOT
854#undef PGM_BTH_NAME
855#undef PGM_BTH_NAME_RC_STR
856#undef PGM_BTH_NAME_R0_STR
857#undef PGM_GST_TYPE
858#undef PGM_GST_NAME
859#undef PGM_GST_NAME_RC_STR
860#undef PGM_GST_NAME_R0_STR
861
862/* Guest - 32-bit mode */
863#define PGM_GST_TYPE PGM_TYPE_32BIT
864#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
865#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
866#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
867#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
868#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
869#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
870#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
871#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
872#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
873#include "PGMGstDefs.h"
874#include "PGMBth.h"
875#undef BTH_PGMPOOLKIND_PT_FOR_BIG
876#undef BTH_PGMPOOLKIND_PT_FOR_PT
877#undef BTH_PGMPOOLKIND_ROOT
878#undef PGM_BTH_NAME
879#undef PGM_BTH_NAME_RC_STR
880#undef PGM_BTH_NAME_R0_STR
881#undef PGM_GST_TYPE
882#undef PGM_GST_NAME
883#undef PGM_GST_NAME_RC_STR
884#undef PGM_GST_NAME_R0_STR
885
886/* Guest - PAE mode */
887#define PGM_GST_TYPE PGM_TYPE_PAE
888#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
889#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
890#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
891#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
892#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
893#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
894#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
895#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
896#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
897#include "PGMBth.h"
898#include "PGMGstDefs.h"
899#include "PGMGst.h"
900#undef BTH_PGMPOOLKIND_PT_FOR_BIG
901#undef BTH_PGMPOOLKIND_PT_FOR_PT
902#undef BTH_PGMPOOLKIND_ROOT
903#undef PGM_BTH_NAME
904#undef PGM_BTH_NAME_RC_STR
905#undef PGM_BTH_NAME_R0_STR
906#undef PGM_GST_TYPE
907#undef PGM_GST_NAME
908#undef PGM_GST_NAME_RC_STR
909#undef PGM_GST_NAME_R0_STR
910
911#undef PGM_SHW_TYPE
912#undef PGM_SHW_NAME
913#undef PGM_SHW_NAME_RC_STR
914#undef PGM_SHW_NAME_R0_STR
915
916
917/*
918 * Shadow - AMD64 mode
919 */
920#define PGM_SHW_TYPE PGM_TYPE_AMD64
921#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
922#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
923#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
924#include "PGMShw.h"
925
926#ifdef VBOX_WITH_64_BITS_GUESTS
927/* Guest - AMD64 mode */
928# define PGM_GST_TYPE PGM_TYPE_AMD64
929# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
930# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
931# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
932# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
933# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
934# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
935# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
936# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
937# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
938# include "PGMBth.h"
939# include "PGMGstDefs.h"
940# include "PGMGst.h"
941# undef BTH_PGMPOOLKIND_PT_FOR_BIG
942# undef BTH_PGMPOOLKIND_PT_FOR_PT
943# undef BTH_PGMPOOLKIND_ROOT
944# undef PGM_BTH_NAME
945# undef PGM_BTH_NAME_RC_STR
946# undef PGM_BTH_NAME_R0_STR
947# undef PGM_GST_TYPE
948# undef PGM_GST_NAME
949# undef PGM_GST_NAME_RC_STR
950# undef PGM_GST_NAME_R0_STR
951#endif /* VBOX_WITH_64_BITS_GUESTS */
952
953#undef PGM_SHW_TYPE
954#undef PGM_SHW_NAME
955#undef PGM_SHW_NAME_RC_STR
956#undef PGM_SHW_NAME_R0_STR
957
958
959/*
960 * Shadow - Nested paging mode
961 */
962#define PGM_SHW_TYPE PGM_TYPE_NESTED
963#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
964#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
965#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
966#include "PGMShw.h"
967
968/* Guest - real mode */
969#define PGM_GST_TYPE PGM_TYPE_REAL
970#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
971#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
972#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
973#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
974#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
975#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
976#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
977#include "PGMGstDefs.h"
978#include "PGMBth.h"
979#undef BTH_PGMPOOLKIND_PT_FOR_PT
980#undef PGM_BTH_NAME
981#undef PGM_BTH_NAME_RC_STR
982#undef PGM_BTH_NAME_R0_STR
983#undef PGM_GST_TYPE
984#undef PGM_GST_NAME
985#undef PGM_GST_NAME_RC_STR
986#undef PGM_GST_NAME_R0_STR
987
988/* Guest - protected mode */
989#define PGM_GST_TYPE PGM_TYPE_PROT
990#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
991#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
992#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
993#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
994#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
995#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
996#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
997#include "PGMGstDefs.h"
998#include "PGMBth.h"
999#undef BTH_PGMPOOLKIND_PT_FOR_PT
1000#undef PGM_BTH_NAME
1001#undef PGM_BTH_NAME_RC_STR
1002#undef PGM_BTH_NAME_R0_STR
1003#undef PGM_GST_TYPE
1004#undef PGM_GST_NAME
1005#undef PGM_GST_NAME_RC_STR
1006#undef PGM_GST_NAME_R0_STR
1007
1008/* Guest - 32-bit mode */
1009#define PGM_GST_TYPE PGM_TYPE_32BIT
1010#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1011#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1012#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1013#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
1014#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
1015#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
1016#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1017#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1018#include "PGMGstDefs.h"
1019#include "PGMBth.h"
1020#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1021#undef BTH_PGMPOOLKIND_PT_FOR_PT
1022#undef PGM_BTH_NAME
1023#undef PGM_BTH_NAME_RC_STR
1024#undef PGM_BTH_NAME_R0_STR
1025#undef PGM_GST_TYPE
1026#undef PGM_GST_NAME
1027#undef PGM_GST_NAME_RC_STR
1028#undef PGM_GST_NAME_R0_STR
1029
1030/* Guest - PAE mode */
1031#define PGM_GST_TYPE PGM_TYPE_PAE
1032#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1033#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1034#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1035#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1036#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1037#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1038#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1039#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1040#include "PGMGstDefs.h"
1041#include "PGMBth.h"
1042#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1043#undef BTH_PGMPOOLKIND_PT_FOR_PT
1044#undef PGM_BTH_NAME
1045#undef PGM_BTH_NAME_RC_STR
1046#undef PGM_BTH_NAME_R0_STR
1047#undef PGM_GST_TYPE
1048#undef PGM_GST_NAME
1049#undef PGM_GST_NAME_RC_STR
1050#undef PGM_GST_NAME_R0_STR
1051
1052#ifdef VBOX_WITH_64_BITS_GUESTS
1053/* Guest - AMD64 mode */
1054# define PGM_GST_TYPE PGM_TYPE_AMD64
1055# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1056# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1057# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1058# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1059# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1060# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1061# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1062# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1063# include "PGMGstDefs.h"
1064# include "PGMBth.h"
1065# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1066# undef BTH_PGMPOOLKIND_PT_FOR_PT
1067# undef PGM_BTH_NAME
1068# undef PGM_BTH_NAME_RC_STR
1069# undef PGM_BTH_NAME_R0_STR
1070# undef PGM_GST_TYPE
1071# undef PGM_GST_NAME
1072# undef PGM_GST_NAME_RC_STR
1073# undef PGM_GST_NAME_R0_STR
1074#endif /* VBOX_WITH_64_BITS_GUESTS */
1075
1076#undef PGM_SHW_TYPE
1077#undef PGM_SHW_NAME
1078#undef PGM_SHW_NAME_RC_STR
1079#undef PGM_SHW_NAME_R0_STR
1080
1081
1082/*
1083 * Shadow - EPT
1084 */
1085#define PGM_SHW_TYPE PGM_TYPE_EPT
1086#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1087#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1088#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1089#include "PGMShw.h"
1090
1091/* Guest - real mode */
1092#define PGM_GST_TYPE PGM_TYPE_REAL
1093#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1094#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1095#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1096#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1097#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1098#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1099#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1100#include "PGMGstDefs.h"
1101#include "PGMBth.h"
1102#undef BTH_PGMPOOLKIND_PT_FOR_PT
1103#undef PGM_BTH_NAME
1104#undef PGM_BTH_NAME_RC_STR
1105#undef PGM_BTH_NAME_R0_STR
1106#undef PGM_GST_TYPE
1107#undef PGM_GST_NAME
1108#undef PGM_GST_NAME_RC_STR
1109#undef PGM_GST_NAME_R0_STR
1110
1111/* Guest - protected mode */
1112#define PGM_GST_TYPE PGM_TYPE_PROT
1113#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1114#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1115#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1116#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1117#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1118#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1119#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1120#include "PGMGstDefs.h"
1121#include "PGMBth.h"
1122#undef BTH_PGMPOOLKIND_PT_FOR_PT
1123#undef PGM_BTH_NAME
1124#undef PGM_BTH_NAME_RC_STR
1125#undef PGM_BTH_NAME_R0_STR
1126#undef PGM_GST_TYPE
1127#undef PGM_GST_NAME
1128#undef PGM_GST_NAME_RC_STR
1129#undef PGM_GST_NAME_R0_STR
1130
1131/* Guest - 32-bit mode */
1132#define PGM_GST_TYPE PGM_TYPE_32BIT
1133#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1134#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1135#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1136#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1137#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1138#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1139#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1140#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1141#include "PGMGstDefs.h"
1142#include "PGMBth.h"
1143#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1144#undef BTH_PGMPOOLKIND_PT_FOR_PT
1145#undef PGM_BTH_NAME
1146#undef PGM_BTH_NAME_RC_STR
1147#undef PGM_BTH_NAME_R0_STR
1148#undef PGM_GST_TYPE
1149#undef PGM_GST_NAME
1150#undef PGM_GST_NAME_RC_STR
1151#undef PGM_GST_NAME_R0_STR
1152
1153/* Guest - PAE mode */
1154#define PGM_GST_TYPE PGM_TYPE_PAE
1155#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1156#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1157#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1158#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1159#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1160#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1161#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1162#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1163#include "PGMGstDefs.h"
1164#include "PGMBth.h"
1165#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1166#undef BTH_PGMPOOLKIND_PT_FOR_PT
1167#undef PGM_BTH_NAME
1168#undef PGM_BTH_NAME_RC_STR
1169#undef PGM_BTH_NAME_R0_STR
1170#undef PGM_GST_TYPE
1171#undef PGM_GST_NAME
1172#undef PGM_GST_NAME_RC_STR
1173#undef PGM_GST_NAME_R0_STR
1174
1175#ifdef VBOX_WITH_64_BITS_GUESTS
1176/* Guest - AMD64 mode */
1177# define PGM_GST_TYPE PGM_TYPE_AMD64
1178# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1179# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1180# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1181# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1182# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1183# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1184# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1185# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1186# include "PGMGstDefs.h"
1187# include "PGMBth.h"
1188# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1189# undef BTH_PGMPOOLKIND_PT_FOR_PT
1190# undef PGM_BTH_NAME
1191# undef PGM_BTH_NAME_RC_STR
1192# undef PGM_BTH_NAME_R0_STR
1193# undef PGM_GST_TYPE
1194# undef PGM_GST_NAME
1195# undef PGM_GST_NAME_RC_STR
1196# undef PGM_GST_NAME_R0_STR
1197#endif /* VBOX_WITH_64_BITS_GUESTS */
1198
1199#undef PGM_SHW_TYPE
1200#undef PGM_SHW_NAME
1201#undef PGM_SHW_NAME_RC_STR
1202#undef PGM_SHW_NAME_R0_STR
1203
1204
1205
1206/**
1207 * Initiates the paging of VM.
1208 *
1209 * @returns VBox status code.
1210 * @param pVM Pointer to VM structure.
1211 */
1212VMMR3DECL(int) PGMR3Init(PVM pVM)
1213{
1214 LogFlow(("PGMR3Init:\n"));
1215 PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1216 int rc;
1217
1218 /*
1219 * Assert alignment and sizes.
1220 */
1221 AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1222 AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1223 AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1224
1225 /*
1226 * Init the structure.
1227 */
1228#ifdef PGM_WITHOUT_MAPPINGS
1229 pVM->pgm.s.fMappingsDisabled = true;
1230#endif
1231 pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1232 pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1233
1234 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1235 {
1236 pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1237 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1238 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1239 }
1240
1241 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1242 {
1243 pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1244 pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1245 pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1246 }
1247
1248 /* Init the per-CPU part. */
1249 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1250 {
1251 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1252 PPGMCPU pPGM = &pVCpu->pgm.s;
1253
1254 pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1255 pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1256 pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1257
1258 pPGM->enmShadowMode = PGMMODE_INVALID;
1259 pPGM->enmGuestMode = PGMMODE_INVALID;
1260
1261 pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1262
1263 pPGM->pGst32BitPdR3 = NULL;
1264 pPGM->pGstPaePdptR3 = NULL;
1265 pPGM->pGstAmd64Pml4R3 = NULL;
1266#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1267 pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1268 pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1269 pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1270#endif
1271 pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1272 pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1273 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1274 {
1275 pPGM->apGstPaePDsR3[i] = NULL;
1276#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1277 pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1278#endif
1279 pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1280 pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1281 pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1282 pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1283 }
1284
1285 pPGM->fA20Enabled = true;
1286 pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
1287 }
1288
1289 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1290 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1291 pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1292
1293 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1294#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1295 true
1296#else
1297 false
1298#endif
1299 );
1300 AssertLogRelRCReturn(rc, rc);
1301
1302#if HC_ARCH_BITS == 32
1303# ifdef RT_OS_DARWIN
1304 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1305# else
1306 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1307# endif
1308#else
1309 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1310#endif
1311 AssertLogRelRCReturn(rc, rc);
1312 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1313 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1314
1315 /*
1316 * Get the configured RAM size - to estimate saved state size.
1317 */
1318 uint64_t cbRam;
1319 rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1320 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1321 cbRam = 0;
1322 else if (RT_SUCCESS(rc))
1323 {
1324 if (cbRam < PAGE_SIZE)
1325 cbRam = 0;
1326 cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1327 }
1328 else
1329 {
1330 AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1331 return rc;
1332 }
1333
1334 /*
1335 * Check for PCI pass-through.
1336 */
1337 rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1338 AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1339 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough || pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1340
1341#ifdef VBOX_WITH_STATISTICS
1342 /*
1343 * Allocate memory for the statistics before someone tries to use them.
1344 */
1345 size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1346 void *pv;
1347 rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1348 AssertRCReturn(rc, rc);
1349
1350 pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1351 pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1352 pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1353 pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1354
1355 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1356 {
1357 pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1358 pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1359 pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1360
1361 pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1362 }
1363#endif /* VBOX_WITH_STATISTICS */
1364
1365 /*
1366 * Register callbacks, string formatters and the saved state data unit.
1367 */
1368#ifdef VBOX_STRICT
1369 VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1370#endif
1371 PGMRegisterStringFormatTypes();
1372
1373 rc = pgmR3InitSavedState(pVM, cbRam);
1374 if (RT_FAILURE(rc))
1375 return rc;
1376
1377 /*
1378 * Initialize the PGM critical section and flush the phys TLBs
1379 */
1380 rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1381 AssertRCReturn(rc, rc);
1382
1383 PGMR3PhysChunkInvalidateTLB(pVM);
1384 pgmPhysInvalidatePageMapTLB(pVM);
1385
1386 /*
1387 * For the time being we sport a full set of handy pages in addition to the base
1388 * memory to simplify things.
1389 */
1390 rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1391 AssertRCReturn(rc, rc);
1392
1393 /*
1394 * Trees
1395 */
1396 rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1397 if (RT_SUCCESS(rc))
1398 {
1399 pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1400 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1401
1402 /*
1403 * Allocate the zero page.
1404 */
1405 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1406 }
1407 if (RT_SUCCESS(rc))
1408 {
1409 pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1410 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1411 pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1412 AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1413
1414 /*
1415 * Allocate the invalid MMIO page.
1416 * (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1417 */
1418 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1419 }
1420 if (RT_SUCCESS(rc))
1421 {
1422 ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1423 pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1424 AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1425 pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1426
1427 /*
1428 * Init the paging.
1429 */
1430 rc = pgmR3InitPaging(pVM);
1431 }
1432 if (RT_SUCCESS(rc))
1433 {
1434 /*
1435 * Init the page pool.
1436 */
1437 rc = pgmR3PoolInit(pVM);
1438 }
1439 if (RT_SUCCESS(rc))
1440 {
1441 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1442 {
1443 PVMCPU pVCpu = &pVM->aCpus[i];
1444 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1445 if (RT_FAILURE(rc))
1446 break;
1447 }
1448 }
1449
1450 if (RT_SUCCESS(rc))
1451 {
1452 /*
1453 * Info & statistics
1454 */
1455 DBGFR3InfoRegisterInternal(pVM, "mode",
1456 "Shows the current paging mode. "
1457 "Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1458 pgmR3InfoMode);
1459 DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1460 "Dumps all the entries in the top level paging table. No arguments.",
1461 pgmR3InfoCr3);
1462 DBGFR3InfoRegisterInternal(pVM, "phys",
1463 "Dumps all the physical address ranges. No arguments.",
1464 pgmR3PhysInfo);
1465 DBGFR3InfoRegisterInternal(pVM, "handlers",
1466 "Dumps physical, virtual and hyper virtual handlers. "
1467 "Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1468 "Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1469 pgmR3InfoHandlers);
1470 DBGFR3InfoRegisterInternal(pVM, "mappings",
1471 "Dumps guest mappings.",
1472 pgmR3MapInfo);
1473
1474 pgmR3InitStats(pVM);
1475
1476#ifdef VBOX_WITH_DEBUGGER
1477 /*
1478 * Debugger commands.
1479 */
1480 static bool s_fRegisteredCmds = false;
1481 if (!s_fRegisteredCmds)
1482 {
1483 int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1484 if (RT_SUCCESS(rc2))
1485 s_fRegisteredCmds = true;
1486 }
1487#endif
1488 return VINF_SUCCESS;
1489 }
1490
1491 /* Almost no cleanup necessary, MM frees all memory. */
1492 PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1493
1494 return rc;
1495}
1496
1497
1498/**
1499 * Init paging.
1500 *
1501 * Since we need to check what mode the host is operating in before we can choose
1502 * the right paging functions for the host we have to delay this until R0 has
1503 * been initialized.
1504 *
1505 * @returns VBox status code.
1506 * @param pVM Pointer to the VM.
1507 */
1508static int pgmR3InitPaging(PVM pVM)
1509{
1510 /*
1511 * Force a recalculation of modes and switcher so everyone gets notified.
1512 */
1513 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1514 {
1515 PVMCPU pVCpu = &pVM->aCpus[i];
1516
1517 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1518 pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1519 }
1520
1521 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1522
1523 /*
1524 * Allocate static mapping space for whatever the cr3 register
1525 * points to and in the case of PAE mode to the 4 PDs.
1526 */
1527 int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1528 if (RT_FAILURE(rc))
1529 {
1530 AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1531 return rc;
1532 }
1533 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1534
1535 /*
1536 * Allocate pages for the three possible intermediate contexts
1537 * (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1538 * for the sake of simplicity. The AMD64 uses the PAE for the
1539 * lower levels, making the total number of pages 11 (3 + 7 + 1).
1540 *
1541 * We assume that two page tables will be enought for the core code
1542 * mappings (HC virtual and identity).
1543 */
1544 pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1545 pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1546 pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1547 pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1548 pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1549 pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1550 pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1551 pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1552 pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1553 pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1554 pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1555 pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1556
1557 pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1558 AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1559 pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1560 AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1561 pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1562 AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1563
1564 /*
1565 * Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1566 */
1567 ASMMemZeroPage(pVM->pgm.s.pInterPD);
1568 ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1569 ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1570
1571 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1572 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1573
1574 ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1575 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1576 {
1577 ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1578 pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P | PGM_PLXFLAGS_PERMANENT
1579 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1580 }
1581
1582 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1583 {
1584 const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1585 pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
1586 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1587 }
1588
1589 RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1590 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1591 pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
1592 | HCPhysInterPaePDPT64;
1593
1594 /*
1595 * Initialize paging workers and mode from current host mode
1596 * and the guest running in real mode.
1597 */
1598 pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1599 switch (pVM->pgm.s.enmHostMode)
1600 {
1601 case SUPPAGINGMODE_32_BIT:
1602 case SUPPAGINGMODE_32_BIT_GLOBAL:
1603 case SUPPAGINGMODE_PAE:
1604 case SUPPAGINGMODE_PAE_GLOBAL:
1605 case SUPPAGINGMODE_PAE_NX:
1606 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1607 break;
1608
1609 case SUPPAGINGMODE_AMD64:
1610 case SUPPAGINGMODE_AMD64_GLOBAL:
1611 case SUPPAGINGMODE_AMD64_NX:
1612 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1613#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1614 if (ARCH_BITS != 64)
1615 {
1616 AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1617 LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1618 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1619 }
1620#endif
1621 break;
1622 default:
1623 AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1624 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1625 }
1626 rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1627 if (RT_SUCCESS(rc))
1628 {
1629 LogFlow(("pgmR3InitPaging: returns successfully\n"));
1630#if HC_ARCH_BITS == 64
1631 LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1632 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1633 LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1634 MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1635 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1636 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1637 MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1638#endif
1639
1640 /*
1641 * Log the host paging mode. It may come in handy.
1642 */
1643 const char *pszHostMode;
1644 switch (pVM->pgm.s.enmHostMode)
1645 {
1646 case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1647 case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1648 case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1649 case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1650 case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1651 case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1652 case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1653 case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1654 case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1655 case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1656 default: pszHostMode = "???"; break;
1657 }
1658 LogRel(("Host paging mode: %s\n", pszHostMode));
1659
1660 return VINF_SUCCESS;
1661 }
1662
1663 LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1664 return rc;
1665}
1666
1667
1668/**
1669 * Init statistics
1670 * @returns VBox status code.
1671 */
1672static int pgmR3InitStats(PVM pVM)
1673{
1674 PPGM pPGM = &pVM->pgm.s;
1675 int rc;
1676
1677 /*
1678 * Release statistics.
1679 */
1680 /* Common - misc variables */
1681 STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1682 STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1683 STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1684 STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1685 STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1686 STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1687 STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1688 STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1689 STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1690 STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1691 STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1692 STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1693 STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1694 STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1695 STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1696 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1697 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1698 STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1699 STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1700
1701 STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1702 STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1703 STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1704
1705 STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1706
1707 /* Live save */
1708 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1709 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1710 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1711 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1712 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1713 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1714 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1715 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1716 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1717 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1718 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1719 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1720 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1721 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1722 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1723 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1724 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1725 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1726
1727#ifdef VBOX_WITH_STATISTICS
1728
1729# define PGM_REG_COUNTER(a, b, c) \
1730 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1731 AssertRC(rc);
1732
1733# define PGM_REG_COUNTER_BYTES(a, b, c) \
1734 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1735 AssertRC(rc);
1736
1737# define PGM_REG_PROFILE(a, b, c) \
1738 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1739 AssertRC(rc);
1740
1741 PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1742
1743 PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1744 PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1745 PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1746 PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1747 PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1748
1749 PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1750 PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1751 PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1752 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1753 PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1754 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1755 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1756 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1757 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1758 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1759
1760 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1761 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1762 PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1763 PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1764 PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1765 PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1766
1767 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1768 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1769 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1770 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1771 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1772 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1773 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1774 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1775
1776 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1777 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1778 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1779 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1780
1781 PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1782 PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1783 PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1784 PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1785
1786 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1787 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1788 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1789 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1790 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1791 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1792 PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1793 PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1794
1795 PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1796 PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1797/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1798 PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1799 PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1800/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1801
1802 PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1803 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1804 PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1805 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1806 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1807 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1808 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1809 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1810
1811 /* GC only: */
1812 PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1813 PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1814
1815 PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1816 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1817 PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1818 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1819 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1820 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1821 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1822 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1823
1824 PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1825 PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1826 PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1827 PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1828 PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1829 PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1830 PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1831
1832# undef PGM_REG_COUNTER
1833# undef PGM_REG_PROFILE
1834#endif
1835
1836 /*
1837 * Note! The layout below matches the member layout exactly!
1838 */
1839
1840 /*
1841 * Common - stats
1842 */
1843 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1844 {
1845 PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1846
1847#define PGM_REG_COUNTER(a, b, c) \
1848 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1849 AssertRC(rc);
1850#define PGM_REG_PROFILE(a, b, c) \
1851 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1852 AssertRC(rc);
1853
1854 PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1855 PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1856
1857#ifdef VBOX_WITH_STATISTICS
1858 PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1859
1860# if 0 /* rarely useful; leave for debugging. */
1861 for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1862 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1863 "The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1864 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1865 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1866 "The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1867# endif
1868 /* R0 only: */
1869 PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1870 PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1871
1872 /* RZ only: */
1873 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1874 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1875 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1876 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1877 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1878 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1879 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1880 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1881 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1882 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1883 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1884 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1885 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1886 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1887 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1888 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1889 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1890 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1891 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1892 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1893 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1894 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1895 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1896 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1897 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1898 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1899 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1900 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1901 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1902 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1903 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1904 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1905 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1906 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1907 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1908 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1909 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1910 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1911 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1912 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1913 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1914 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1915 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1916 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1917#if 0 /* rarely useful; leave for debugging. */
1918 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1919 STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1920 "The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1921#endif
1922 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1923 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1924 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1925 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1926 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1927
1928 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1929 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1930 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1931 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1932 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1933 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1934 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1935 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1936 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1937 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1938 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1939 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1940 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1941 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1942 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1943 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1944 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1945 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1946 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1947 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1948 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1949 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1950 //PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1951 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1952 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1953 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1954 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1955 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1956 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1957 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1958 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1959 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1960 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1961 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1962 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1963 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1964
1965 /* HC only: */
1966
1967 /* RZ & R3: */
1968 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1969 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1970 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1971 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1972 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1973 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1974 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1975 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1976 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1977 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1978 PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1979 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1980 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1981 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1982 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1983 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1984 PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1985 PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1986 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1987 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1988 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1989 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1990 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1991 PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1992 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1993 PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1994 PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1995 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1996 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1997 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1998 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1999 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2000 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2001 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2002 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2003 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2004 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2005 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2006 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2007 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2008 PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
2009 PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2010 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2011 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2012 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2013 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2014 PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2015
2016 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2017 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2018 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2019 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2020 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2021 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2022 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2023 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2024 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2025 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2026 PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2027 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2028 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2029 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2030 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2031 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2032 PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2033 PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2034 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2035 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2036 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2037 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2038 PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2039 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2040 PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2041 PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2042 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2043 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2044 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2045 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2046 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2047 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2048 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2049 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2050 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2051 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2052 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2053 PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2054 PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2055 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2056 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2057 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2058 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2059 PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2060#endif /* VBOX_WITH_STATISTICS */
2061
2062#undef PGM_REG_PROFILE
2063#undef PGM_REG_COUNTER
2064
2065 }
2066
2067 return VINF_SUCCESS;
2068}
2069
2070
2071/**
2072 * Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2073 *
2074 * The dynamic mapping area will also be allocated and initialized at this
2075 * time. We could allocate it during PGMR3Init of course, but the mapping
2076 * wouldn't be allocated at that time preventing us from setting up the
2077 * page table entries with the dummy page.
2078 *
2079 * @returns VBox status code.
2080 * @param pVM Pointer to the VM.
2081 */
2082VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2083{
2084 RTGCPTR GCPtr;
2085 int rc;
2086
2087 /*
2088 * Reserve space for the dynamic mappings.
2089 */
2090 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2091 if (RT_SUCCESS(rc))
2092 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2093
2094 if ( RT_SUCCESS(rc)
2095 && (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2096 {
2097 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2098 if (RT_SUCCESS(rc))
2099 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2100 }
2101 if (RT_SUCCESS(rc))
2102 {
2103 AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2104 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2105 }
2106 return rc;
2107}
2108
2109
2110/**
2111 * Ring-3 init finalizing.
2112 *
2113 * @returns VBox status code.
2114 * @param pVM Pointer to the VM.
2115 */
2116VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2117{
2118 int rc;
2119
2120 /*
2121 * Reserve space for the dynamic mappings.
2122 * Initialize the dynamic mapping pages with dummy pages to simply the cache.
2123 */
2124 /* get the pointer to the page table entries. */
2125 PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2126 AssertRelease(pMapping);
2127 const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2128 const unsigned iPT = off >> X86_PD_SHIFT;
2129 const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2130 pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2131 pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2132
2133 /* init cache area */
2134 RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2135 for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2136 {
2137 rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2138 AssertRCReturn(rc, rc);
2139 }
2140
2141 /*
2142 * Determine the max physical address width (MAXPHYADDR) and apply it to
2143 * all the mask members and stuff.
2144 */
2145 uint32_t cMaxPhysAddrWidth;
2146 uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2147 if ( uMaxExtLeaf >= 0x80000008
2148 && uMaxExtLeaf <= 0x80000fff)
2149 {
2150 cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2151 LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2152 cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2153 pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2154 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2155 pVM->pgm.s.HCPhysInvMmioPg |= RT_BIT_64(iBit);
2156 }
2157 else
2158 {
2159 LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2160 cMaxPhysAddrWidth = 48;
2161 pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2162 pVM->pgm.s.HCPhysInvMmioPg |= UINT64_C(0x000f0000000000);
2163 }
2164
2165 pVM->pgm.s.GCPhysInvAddrMask = 0;
2166 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2167 pVM->pgm.s.GCPhysInvAddrMask |= RT_BIT_64(iBit);
2168
2169 /*
2170 * Initialize the invalid paging entry masks, assuming NX is disabled.
2171 */
2172 uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2173 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2174 {
2175 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2176
2177 /** @todo The manuals are not entirely clear whether the physical
2178 * address width is relevant. See table 5-9 in the intel
2179 * manual vs the PDE4M descriptions. Write testcase (NP). */
2180 pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2181 | X86_PDE4M_MBZ_MASK;
2182
2183 pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask | X86_PTE_PAE_MBZ_MASK_NO_NX;
2184 pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask | X86_PDE_PAE_MBZ_MASK_NO_NX;
2185 pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2186 pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask | X86_PDPE_PAE_MBZ_MASK;
2187
2188 pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask | X86_PTE_LM_MBZ_MASK_NO_NX;
2189 pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask | X86_PDE_LM_MBZ_MASK_NX;
2190 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_LM_MBZ_MASK_NX;
2191 pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask | X86_PDPE_LM_MBZ_MASK_NO_NX;
2192 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask | X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2193 pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask | X86_PML4E_MBZ_MASK_NO_NX;
2194
2195 pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_G | X86_PTE_A | X86_PTE_D;
2196 pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A;
2197 pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A;
2198 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2199 X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_G | X86_PDE4M_A | X86_PDE4M_D;
2200 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
2201 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
2202 }
2203
2204 /*
2205 * Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2206 * Intel only goes up to 36 bits, so we stick to 36 as well.
2207 * Update: More recent intel manuals specifies 40 bits just like AMD.
2208 */
2209 uint32_t u32Dummy, u32Features;
2210 CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2211 if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2212 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2213 else
2214 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2215
2216 /*
2217 * Allocate memory if we're supposed to do that.
2218 */
2219 if (pVM->pgm.s.fRamPreAlloc)
2220 rc = pgmR3PhysRamPreAllocate(pVM);
2221
2222 LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2223 return rc;
2224}
2225
2226
2227/**
2228 * Init phase completed callback.
2229 *
2230 * @returns VBox status code.
2231 * @param pVM Pointer to the VM.
2232 * @param enmWhat What has been completed.
2233 * @thread EMT(0)
2234 */
2235VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2236{
2237 switch (enmWhat)
2238 {
2239 case VMINITCOMPLETED_HM:
2240#ifdef VBOX_WITH_PCI_PASSTHROUGH
2241 if (pVM->pgm.s.fPciPassthrough)
2242 {
2243 AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2244 AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
2245 AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2246
2247 /*
2248 * Report assignments to the IOMMU (hope that's good enough for now).
2249 */
2250 if (pVM->pgm.s.fPciPassthrough)
2251 {
2252 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2253 AssertRCReturn(rc, rc);
2254 }
2255 }
2256#else
2257 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2258#endif
2259 break;
2260
2261 default:
2262 /* shut up gcc */
2263 break;
2264 }
2265
2266 return VINF_SUCCESS;
2267}
2268
2269
2270/**
2271 * Applies relocations to data and code managed by this component.
2272 *
2273 * This function will be called at init and whenever the VMM need to relocate it
2274 * self inside the GC.
2275 *
2276 * @param pVM The VM.
2277 * @param offDelta Relocation delta relative to old location.
2278 */
2279VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2280{
2281 LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2282
2283 /*
2284 * Paging stuff.
2285 */
2286 pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2287
2288 pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2289
2290 /* Shadow, guest and both mode switch & relocation for each VCPU. */
2291 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2292 {
2293 PVMCPU pVCpu = &pVM->aCpus[i];
2294
2295 pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2296
2297 PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2298 PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2299 PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2300 }
2301
2302 /*
2303 * Trees.
2304 */
2305 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2306
2307 /*
2308 * Ram ranges.
2309 */
2310 if (pVM->pgm.s.pRamRangesXR3)
2311 {
2312 /* Update the pSelfRC pointers and relink them. */
2313 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2314 if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2315 pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2316 pgmR3PhysRelinkRamRanges(pVM);
2317
2318 /* Flush the RC TLB. */
2319 for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2320 pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2321 }
2322
2323 /*
2324 * Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2325 * be mapped and thus not included in the above exercise.
2326 */
2327 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2328 if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2329 pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2330
2331 /*
2332 * Update the two page directories with all page table mappings.
2333 * (One or more of them have changed, that's why we're here.)
2334 */
2335 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2336 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2337 pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2338
2339 /* Relocate GC addresses of Page Tables. */
2340 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2341 {
2342 for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2343 {
2344 pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2345 pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2346 }
2347 }
2348
2349 /*
2350 * Dynamic page mapping area.
2351 */
2352 pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2353 pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2354 pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2355
2356 if (pVM->pgm.s.pRCDynMap)
2357 {
2358 pVM->pgm.s.pRCDynMap += offDelta;
2359 PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2360
2361 pDynMap->paPages += offDelta;
2362 PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2363
2364 for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2365 {
2366 paPages[iPage].pvPage += offDelta;
2367 paPages[iPage].uPte.pLegacy += offDelta;
2368 paPages[iPage].uPte.pPae += offDelta;
2369 }
2370 }
2371
2372 /*
2373 * The Zero page.
2374 */
2375 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2376#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2377 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
2378#else
2379 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2380#endif
2381
2382 /*
2383 * Physical and virtual handlers.
2384 */
2385 RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2386 pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2387 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2388 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2389
2390 /*
2391 * The page pool.
2392 */
2393 pgmR3PoolRelocate(pVM);
2394
2395#ifdef VBOX_WITH_STATISTICS
2396 /*
2397 * Statistics.
2398 */
2399 pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2400 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2401 pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2402#endif
2403}
2404
2405
2406/**
2407 * Callback function for relocating a physical access handler.
2408 *
2409 * @returns 0 (continue enum)
2410 * @param pNode Pointer to a PGMPHYSHANDLER node.
2411 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2412 * not certain the delta will fit in a void pointer for all possible configs.
2413 */
2414static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2415{
2416 PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2417 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2418 if (pHandler->pfnHandlerRC)
2419 pHandler->pfnHandlerRC += offDelta;
2420 if (pHandler->pvUserRC >= 0x10000)
2421 pHandler->pvUserRC += offDelta;
2422 return 0;
2423}
2424
2425
2426/**
2427 * Callback function for relocating a virtual access handler.
2428 *
2429 * @returns 0 (continue enum)
2430 * @param pNode Pointer to a PGMVIRTHANDLER node.
2431 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2432 * not certain the delta will fit in a void pointer for all possible configs.
2433 */
2434static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2435{
2436 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2437 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2438 Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2439 || pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2440 Assert(pHandler->pfnHandlerRC);
2441 pHandler->pfnHandlerRC += offDelta;
2442 return 0;
2443}
2444
2445
2446/**
2447 * Callback function for relocating a virtual access handler for the hypervisor mapping.
2448 *
2449 * @returns 0 (continue enum)
2450 * @param pNode Pointer to a PGMVIRTHANDLER node.
2451 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2452 * not certain the delta will fit in a void pointer for all possible configs.
2453 */
2454static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2455{
2456 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2457 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2458 Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2459 Assert(pHandler->pfnHandlerRC);
2460 pHandler->pfnHandlerRC += offDelta;
2461 return 0;
2462}
2463
2464
2465/**
2466 * Resets a virtual CPU when unplugged.
2467 *
2468 * @param pVM Pointer to the VM.
2469 * @param pVCpu Pointer to the VMCPU.
2470 */
2471VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2472{
2473 int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2474 AssertRC(rc);
2475
2476 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2477 AssertRC(rc);
2478
2479 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2480
2481 pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2482
2483 /*
2484 * Re-init other members.
2485 */
2486 pVCpu->pgm.s.fA20Enabled = true;
2487 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2488
2489 /*
2490 * Clear the FFs PGM owns.
2491 */
2492 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2493 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2494}
2495
2496
2497/**
2498 * The VM is being reset.
2499 *
2500 * For the PGM component this means that any PD write monitors
2501 * needs to be removed.
2502 *
2503 * @param pVM Pointer to the VM.
2504 */
2505VMMR3DECL(void) PGMR3Reset(PVM pVM)
2506{
2507 int rc;
2508
2509 LogFlow(("PGMR3Reset:\n"));
2510 VM_ASSERT_EMT(pVM);
2511
2512 pgmLock(pVM);
2513
2514 /*
2515 * Unfix any fixed mappings and disable CR3 monitoring.
2516 */
2517 pVM->pgm.s.fMappingsFixed = false;
2518 pVM->pgm.s.fMappingsFixedRestored = false;
2519 pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2520 pVM->pgm.s.cbMappingFixed = 0;
2521
2522 /*
2523 * Exit the guest paging mode before the pgm pool gets reset.
2524 * Important to clean up the amd64 case.
2525 */
2526 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2527 {
2528 PVMCPU pVCpu = &pVM->aCpus[i];
2529 rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2530 AssertRC(rc);
2531 }
2532
2533#ifdef DEBUG
2534 DBGFR3_INFO_LOG(pVM, "mappings", NULL);
2535 DBGFR3_INFO_LOG(pVM, "handlers", "all nostat");
2536#endif
2537
2538 /*
2539 * Switch mode back to real mode. (before resetting the pgm pool!)
2540 */
2541 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2542 {
2543 PVMCPU pVCpu = &pVM->aCpus[i];
2544
2545 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2546 AssertRC(rc);
2547
2548 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2549 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2550 }
2551
2552 /*
2553 * Reset the shadow page pool.
2554 */
2555 pgmR3PoolReset(pVM);
2556
2557 /*
2558 * Re-init various other members and clear the FFs that PGM owns.
2559 */
2560 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2561 {
2562 PVMCPU pVCpu = &pVM->aCpus[i];
2563
2564 pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2565 PGMNotifyNxeChanged(pVCpu, false);
2566
2567 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2568 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2569
2570 if (!pVCpu->pgm.s.fA20Enabled)
2571 {
2572 pVCpu->pgm.s.fA20Enabled = true;
2573 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2574#ifdef PGM_WITH_A20
2575 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2576 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2577 pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2578 HMFlushTLB(pVCpu);
2579#endif
2580 }
2581 }
2582
2583 /*
2584 * Reset (zero) RAM and shadow ROM pages.
2585 */
2586 rc = pgmR3PhysRamReset(pVM);
2587 if (RT_SUCCESS(rc))
2588 rc = pgmR3PhysRomReset(pVM);
2589
2590
2591 pgmUnlock(pVM);
2592 AssertReleaseRC(rc);
2593}
2594
2595
2596#ifdef VBOX_STRICT
2597/**
2598 * VM state change callback for clearing fNoMorePhysWrites after
2599 * a snapshot has been created.
2600 */
2601static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2602{
2603 if ( enmState == VMSTATE_RUNNING
2604 || enmState == VMSTATE_RESUMING)
2605 pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2606 NOREF(enmOldState); NOREF(pvUser);
2607}
2608#endif
2609
2610/**
2611 * Private API to reset fNoMorePhysWrites.
2612 */
2613VMMR3DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2614{
2615 pVM->pgm.s.fNoMorePhysWrites = false;
2616}
2617
2618/**
2619 * Terminates the PGM.
2620 *
2621 * @returns VBox status code.
2622 * @param pVM Pointer to VM structure.
2623 */
2624VMMR3DECL(int) PGMR3Term(PVM pVM)
2625{
2626 /* Must free shared pages here. */
2627 pgmLock(pVM);
2628 pgmR3PhysRamTerm(pVM);
2629 pgmR3PhysRomTerm(pVM);
2630 pgmUnlock(pVM);
2631
2632 PGMDeregisterStringFormatTypes();
2633 return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2634}
2635
2636
2637/**
2638 * Show paging mode.
2639 *
2640 * @param pVM Pointer to the VM.
2641 * @param pHlp The info helpers.
2642 * @param pszArgs "all" (default), "guest", "shadow" or "host".
2643 */
2644static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2645{
2646 /* digest argument. */
2647 bool fGuest, fShadow, fHost;
2648 if (pszArgs)
2649 pszArgs = RTStrStripL(pszArgs);
2650 if (!pszArgs || !*pszArgs || strstr(pszArgs, "all"))
2651 fShadow = fHost = fGuest = true;
2652 else
2653 {
2654 fShadow = fHost = fGuest = false;
2655 if (strstr(pszArgs, "guest"))
2656 fGuest = true;
2657 if (strstr(pszArgs, "shadow"))
2658 fShadow = true;
2659 if (strstr(pszArgs, "host"))
2660 fHost = true;
2661 }
2662
2663 /** @todo SMP support! */
2664 /* print info. */
2665 if (fGuest)
2666 pHlp->pfnPrintf(pHlp, "Guest paging mode: %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2667 PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2668 pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled", pVM->aCpus[0].pgm.s.cA20Changes.c);
2669 if (fShadow)
2670 pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2671 if (fHost)
2672 {
2673 const char *psz;
2674 switch (pVM->pgm.s.enmHostMode)
2675 {
2676 case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2677 case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2678 case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2679 case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2680 case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2681 case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2682 case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2683 case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2684 case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2685 case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2686 case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2687 default: psz = "unknown"; break;
2688 }
2689 pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2690 }
2691}
2692
2693
2694/**
2695 * Dump registered MMIO ranges to the log.
2696 *
2697 * @param pVM Pointer to the VM.
2698 * @param pHlp The info helpers.
2699 * @param pszArgs Arguments, ignored.
2700 */
2701static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2702{
2703 NOREF(pszArgs);
2704 pHlp->pfnPrintf(pHlp,
2705 "RAM ranges (pVM=%p)\n"
2706 "%.*s %.*s\n",
2707 pVM,
2708 sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2709 sizeof(RTHCPTR) * 2, "pvHC ");
2710
2711 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2712 pHlp->pfnPrintf(pHlp,
2713 "%RGp-%RGp %RHv %s\n",
2714 pCur->GCPhys,
2715 pCur->GCPhysLast,
2716 pCur->pvR3,
2717 pCur->pszDesc);
2718}
2719
2720
2721/**
2722 * Dump the page directory to the log.
2723 *
2724 * @param pVM Pointer to the VM.
2725 * @param pHlp The info helpers.
2726 * @param pszArgs Arguments, ignored.
2727 */
2728static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2729{
2730 /** @todo SMP support!! */
2731 PVMCPU pVCpu = &pVM->aCpus[0];
2732
2733/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2734 /* Big pages supported? */
2735 const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2736
2737 /* Global pages supported? */
2738 const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2739
2740 NOREF(pszArgs);
2741
2742 /*
2743 * Get page directory addresses.
2744 */
2745 pgmLock(pVM);
2746 PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2747 Assert(pPDSrc);
2748
2749 /*
2750 * Iterate the page directory.
2751 */
2752 for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2753 {
2754 X86PDE PdeSrc = pPDSrc->a[iPD];
2755 if (PdeSrc.n.u1Present)
2756 {
2757 if (PdeSrc.b.u1Size && fPSE)
2758 pHlp->pfnPrintf(pHlp,
2759 "%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2760 iPD,
2761 pgmGstGet4MBPhysPage(pVM, PdeSrc),
2762 PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2763 else
2764 pHlp->pfnPrintf(pHlp,
2765 "%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2766 iPD,
2767 (RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2768 PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2769 }
2770 }
2771 pgmUnlock(pVM);
2772}
2773
2774
2775/**
2776 * Service a VMMCALLRING3_PGM_LOCK call.
2777 *
2778 * @returns VBox status code.
2779 * @param pVM Pointer to the VM.
2780 */
2781VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2782{
2783 int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2784 AssertRC(rc);
2785 return rc;
2786}
2787
2788
2789/**
2790 * Converts a PGMMODE value to a PGM_TYPE_* \#define.
2791 *
2792 * @returns PGM_TYPE_*.
2793 * @param pgmMode The mode value to convert.
2794 */
2795DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2796{
2797 switch (pgmMode)
2798 {
2799 case PGMMODE_REAL: return PGM_TYPE_REAL;
2800 case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2801 case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2802 case PGMMODE_PAE:
2803 case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2804 case PGMMODE_AMD64:
2805 case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2806 case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2807 case PGMMODE_EPT: return PGM_TYPE_EPT;
2808 default:
2809 AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2810 }
2811}
2812
2813
2814/**
2815 * Gets the index into the paging mode data array of a SHW+GST mode.
2816 *
2817 * @returns PGM::paPagingData index.
2818 * @param uShwType The shadow paging mode type.
2819 * @param uGstType The guest paging mode type.
2820 */
2821DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2822{
2823 Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2824 Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2825 return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2826 + (uGstType - PGM_TYPE_REAL);
2827}
2828
2829
2830/**
2831 * Gets the index into the paging mode data array of a SHW+GST mode.
2832 *
2833 * @returns PGM::paPagingData index.
2834 * @param enmShw The shadow paging mode.
2835 * @param enmGst The guest paging mode.
2836 */
2837DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2838{
2839 Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2840 Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2841 return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2842}
2843
2844
2845/**
2846 * Calculates the max data index.
2847 * @returns The number of entries in the paging data array.
2848 */
2849DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2850{
2851 return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2852}
2853
2854
2855/**
2856 * Initializes the paging mode data kept in PGM::paModeData.
2857 *
2858 * @param pVM Pointer to the VM.
2859 * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2860 * This is used early in the init process to avoid trouble with PDM
2861 * not being initialized yet.
2862 */
2863static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2864{
2865 PPGMMODEDATA pModeData;
2866 int rc;
2867
2868 /*
2869 * Allocate the array on the first call.
2870 */
2871 if (!pVM->pgm.s.paModeData)
2872 {
2873 pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2874 AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2875 }
2876
2877 /*
2878 * Initialize the array entries.
2879 */
2880 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2881 pModeData->uShwType = PGM_TYPE_32BIT;
2882 pModeData->uGstType = PGM_TYPE_REAL;
2883 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2884 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2885 rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2886
2887 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2888 pModeData->uShwType = PGM_TYPE_32BIT;
2889 pModeData->uGstType = PGM_TYPE_PROT;
2890 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2891 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2892 rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2893
2894 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2895 pModeData->uShwType = PGM_TYPE_32BIT;
2896 pModeData->uGstType = PGM_TYPE_32BIT;
2897 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2898 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2899 rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2900
2901 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2902 pModeData->uShwType = PGM_TYPE_PAE;
2903 pModeData->uGstType = PGM_TYPE_REAL;
2904 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2905 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2906 rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907
2908 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2909 pModeData->uShwType = PGM_TYPE_PAE;
2910 pModeData->uGstType = PGM_TYPE_PROT;
2911 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2912 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2913 rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2914
2915 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2916 pModeData->uShwType = PGM_TYPE_PAE;
2917 pModeData->uGstType = PGM_TYPE_32BIT;
2918 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2919 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2920 rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2921
2922 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2923 pModeData->uShwType = PGM_TYPE_PAE;
2924 pModeData->uGstType = PGM_TYPE_PAE;
2925 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2926 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2927 rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2928
2929#ifdef VBOX_WITH_64_BITS_GUESTS
2930 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2931 pModeData->uShwType = PGM_TYPE_AMD64;
2932 pModeData->uGstType = PGM_TYPE_AMD64;
2933 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2934 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2935 rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2936#endif
2937
2938 /* The nested paging mode. */
2939 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2940 pModeData->uShwType = PGM_TYPE_NESTED;
2941 pModeData->uGstType = PGM_TYPE_REAL;
2942 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2943 rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2944
2945 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2946 pModeData->uShwType = PGM_TYPE_NESTED;
2947 pModeData->uGstType = PGM_TYPE_PROT;
2948 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2949 rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2950
2951 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2952 pModeData->uShwType = PGM_TYPE_NESTED;
2953 pModeData->uGstType = PGM_TYPE_32BIT;
2954 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2955 rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2956
2957 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2958 pModeData->uShwType = PGM_TYPE_NESTED;
2959 pModeData->uGstType = PGM_TYPE_PAE;
2960 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2961 rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2962
2963#ifdef VBOX_WITH_64_BITS_GUESTS
2964 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2965 pModeData->uShwType = PGM_TYPE_NESTED;
2966 pModeData->uGstType = PGM_TYPE_AMD64;
2967 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2968 rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2969#endif
2970
2971 /* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2972 switch (pVM->pgm.s.enmHostMode)
2973 {
2974#if HC_ARCH_BITS == 32
2975 case SUPPAGINGMODE_32_BIT:
2976 case SUPPAGINGMODE_32_BIT_GLOBAL:
2977 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2978 {
2979 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2980 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2981 }
2982# ifdef VBOX_WITH_64_BITS_GUESTS
2983 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2984 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2985# endif
2986 break;
2987
2988 case SUPPAGINGMODE_PAE:
2989 case SUPPAGINGMODE_PAE_NX:
2990 case SUPPAGINGMODE_PAE_GLOBAL:
2991 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2992 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2993 {
2994 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2995 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2996 }
2997# ifdef VBOX_WITH_64_BITS_GUESTS
2998 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2999 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3000# endif
3001 break;
3002#endif /* HC_ARCH_BITS == 32 */
3003
3004#if HC_ARCH_BITS == 64 || defined(RT_OS_DARWIN)
3005 case SUPPAGINGMODE_AMD64:
3006 case SUPPAGINGMODE_AMD64_GLOBAL:
3007 case SUPPAGINGMODE_AMD64_NX:
3008 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3009# ifdef VBOX_WITH_64_BITS_GUESTS
3010 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3011# else
3012 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3013# endif
3014 {
3015 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3016 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3017 }
3018 break;
3019#endif /* HC_ARCH_BITS == 64 || RT_OS_DARWIN */
3020
3021 default:
3022 AssertFailed();
3023 break;
3024 }
3025
3026 /* Extended paging (EPT) / Intel VT-x */
3027 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3028 pModeData->uShwType = PGM_TYPE_EPT;
3029 pModeData->uGstType = PGM_TYPE_REAL;
3030 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3031 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3032 rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3033
3034 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3035 pModeData->uShwType = PGM_TYPE_EPT;
3036 pModeData->uGstType = PGM_TYPE_PROT;
3037 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3038 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3039 rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3040
3041 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3042 pModeData->uShwType = PGM_TYPE_EPT;
3043 pModeData->uGstType = PGM_TYPE_32BIT;
3044 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3045 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3046 rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3047
3048 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3049 pModeData->uShwType = PGM_TYPE_EPT;
3050 pModeData->uGstType = PGM_TYPE_PAE;
3051 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3052 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3053 rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3054
3055#ifdef VBOX_WITH_64_BITS_GUESTS
3056 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3057 pModeData->uShwType = PGM_TYPE_EPT;
3058 pModeData->uGstType = PGM_TYPE_AMD64;
3059 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3060 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3061 rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3062#endif
3063 return VINF_SUCCESS;
3064}
3065
3066
3067/**
3068 * Switch to different (or relocated in the relocate case) mode data.
3069 *
3070 * @param pVM Pointer to the VM.
3071 * @param pVCpu Pointer to the VMCPU.
3072 * @param enmShw The shadow paging mode.
3073 * @param enmGst The guest paging mode.
3074 */
3075static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3076{
3077 PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3078
3079 Assert(pModeData->uGstType == pgmModeToType(enmGst));
3080 Assert(pModeData->uShwType == pgmModeToType(enmShw));
3081
3082 /* shadow */
3083 pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3084 pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3085 pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3086 Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3087 pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3088
3089 pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3090 pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3091
3092 pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3093 pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3094
3095
3096 /* guest */
3097 pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3098 pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3099 pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3100 Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3101 pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3102 pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3103 pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3104 pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3105 pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3106 pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3107 pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3108 pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3109
3110 /* both */
3111 pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3112 pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3113 pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3114 Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3115 pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3116 pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3117#ifdef VBOX_STRICT
3118 pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3119#endif
3120 pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3121 pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3122
3123 pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3124 pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3125 pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3126 pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3127 pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3128#ifdef VBOX_STRICT
3129 pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3130#endif
3131 pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3132 pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3133
3134 pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3135 pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3136 pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3137 pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3138 pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3139#ifdef VBOX_STRICT
3140 pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3141#endif
3142 pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3143 pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3144}
3145
3146
3147/**
3148 * Calculates the shadow paging mode.
3149 *
3150 * @returns The shadow paging mode.
3151 * @param pVM Pointer to the VM.
3152 * @param enmGuestMode The guest mode.
3153 * @param enmHostMode The host mode.
3154 * @param enmShadowMode The current shadow mode.
3155 * @param penmSwitcher Where to store the switcher to use.
3156 * VMMSWITCHER_INVALID means no change.
3157 */
3158static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3159{
3160 VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3161 switch (enmGuestMode)
3162 {
3163 /*
3164 * When switching to real or protected mode we don't change
3165 * anything since it's likely that we'll switch back pretty soon.
3166 *
3167 * During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3168 * and is supposed to determine which shadow paging and switcher to
3169 * use during init.
3170 */
3171 case PGMMODE_REAL:
3172 case PGMMODE_PROTECTED:
3173 if ( enmShadowMode != PGMMODE_INVALID
3174 && !HMIsEnabled(pVM) /* always switch in hm mode! */)
3175 break; /* (no change) */
3176
3177 switch (enmHostMode)
3178 {
3179 case SUPPAGINGMODE_32_BIT:
3180 case SUPPAGINGMODE_32_BIT_GLOBAL:
3181 enmShadowMode = PGMMODE_32_BIT;
3182 enmSwitcher = VMMSWITCHER_32_TO_32;
3183 break;
3184
3185 case SUPPAGINGMODE_PAE:
3186 case SUPPAGINGMODE_PAE_NX:
3187 case SUPPAGINGMODE_PAE_GLOBAL:
3188 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3189 enmShadowMode = PGMMODE_PAE;
3190 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3191#ifdef DEBUG_bird
3192 if (RTEnvExist("VBOX_32BIT"))
3193 {
3194 enmShadowMode = PGMMODE_32_BIT;
3195 enmSwitcher = VMMSWITCHER_PAE_TO_32;
3196 }
3197#endif
3198 break;
3199
3200 case SUPPAGINGMODE_AMD64:
3201 case SUPPAGINGMODE_AMD64_GLOBAL:
3202 case SUPPAGINGMODE_AMD64_NX:
3203 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3204 enmShadowMode = PGMMODE_PAE;
3205 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3206#ifdef DEBUG_bird
3207 if (RTEnvExist("VBOX_32BIT"))
3208 {
3209 enmShadowMode = PGMMODE_32_BIT;
3210 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3211 }
3212#endif
3213 break;
3214
3215 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3216 }
3217 break;
3218
3219 case PGMMODE_32_BIT:
3220 switch (enmHostMode)
3221 {
3222 case SUPPAGINGMODE_32_BIT:
3223 case SUPPAGINGMODE_32_BIT_GLOBAL:
3224 enmShadowMode = PGMMODE_32_BIT;
3225 enmSwitcher = VMMSWITCHER_32_TO_32;
3226 break;
3227
3228 case SUPPAGINGMODE_PAE:
3229 case SUPPAGINGMODE_PAE_NX:
3230 case SUPPAGINGMODE_PAE_GLOBAL:
3231 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3232 enmShadowMode = PGMMODE_PAE;
3233 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3234#ifdef DEBUG_bird
3235 if (RTEnvExist("VBOX_32BIT"))
3236 {
3237 enmShadowMode = PGMMODE_32_BIT;
3238 enmSwitcher = VMMSWITCHER_PAE_TO_32;
3239 }
3240#endif
3241 break;
3242
3243 case SUPPAGINGMODE_AMD64:
3244 case SUPPAGINGMODE_AMD64_GLOBAL:
3245 case SUPPAGINGMODE_AMD64_NX:
3246 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3247 enmShadowMode = PGMMODE_PAE;
3248 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3249#ifdef DEBUG_bird
3250 if (RTEnvExist("VBOX_32BIT"))
3251 {
3252 enmShadowMode = PGMMODE_32_BIT;
3253 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3254 }
3255#endif
3256 break;
3257
3258 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3259 }
3260 break;
3261
3262 case PGMMODE_PAE:
3263 case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3264 switch (enmHostMode)
3265 {
3266 case SUPPAGINGMODE_32_BIT:
3267 case SUPPAGINGMODE_32_BIT_GLOBAL:
3268 enmShadowMode = PGMMODE_PAE;
3269 enmSwitcher = VMMSWITCHER_32_TO_PAE;
3270 break;
3271
3272 case SUPPAGINGMODE_PAE:
3273 case SUPPAGINGMODE_PAE_NX:
3274 case SUPPAGINGMODE_PAE_GLOBAL:
3275 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3276 enmShadowMode = PGMMODE_PAE;
3277 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3278 break;
3279
3280 case SUPPAGINGMODE_AMD64:
3281 case SUPPAGINGMODE_AMD64_GLOBAL:
3282 case SUPPAGINGMODE_AMD64_NX:
3283 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3284 enmShadowMode = PGMMODE_PAE;
3285 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3286 break;
3287
3288 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3289 }
3290 break;
3291
3292 case PGMMODE_AMD64:
3293 case PGMMODE_AMD64_NX:
3294 switch (enmHostMode)
3295 {
3296 case SUPPAGINGMODE_32_BIT:
3297 case SUPPAGINGMODE_32_BIT_GLOBAL:
3298 enmShadowMode = PGMMODE_AMD64;
3299 enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3300 break;
3301
3302 case SUPPAGINGMODE_PAE:
3303 case SUPPAGINGMODE_PAE_NX:
3304 case SUPPAGINGMODE_PAE_GLOBAL:
3305 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3306 enmShadowMode = PGMMODE_AMD64;
3307 enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3308 break;
3309
3310 case SUPPAGINGMODE_AMD64:
3311 case SUPPAGINGMODE_AMD64_GLOBAL:
3312 case SUPPAGINGMODE_AMD64_NX:
3313 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3314 enmShadowMode = PGMMODE_AMD64;
3315 enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3316 break;
3317
3318 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3319 }
3320 break;
3321
3322
3323 default:
3324 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3325 *penmSwitcher = VMMSWITCHER_INVALID;
3326 return PGMMODE_INVALID;
3327 }
3328 /* Override the shadow mode is nested paging is active. */
3329 pVM->pgm.s.fNestedPaging = HMIsNestedPagingActive(pVM);
3330 if (pVM->pgm.s.fNestedPaging)
3331 enmShadowMode = HMGetShwPagingMode(pVM);
3332
3333 *penmSwitcher = enmSwitcher;
3334 return enmShadowMode;
3335}
3336
3337
3338/**
3339 * Performs the actual mode change.
3340 * This is called by PGMChangeMode and pgmR3InitPaging().
3341 *
3342 * @returns VBox status code. May suspend or power off the VM on error, but this
3343 * will trigger using FFs and not status codes.
3344 *
3345 * @param pVM Pointer to the VM.
3346 * @param pVCpu Pointer to the VMCPU.
3347 * @param enmGuestMode The new guest mode. This is assumed to be different from
3348 * the current mode.
3349 */
3350VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3351{
3352#if HC_ARCH_BITS == 32
3353 bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3354#endif
3355 bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3356
3357 Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3358 STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3359
3360 /*
3361 * Calc the shadow mode and switcher.
3362 */
3363 VMMSWITCHER enmSwitcher;
3364 PGMMODE enmShadowMode;
3365 enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3366
3367#ifdef VBOX_WITH_RAW_MODE
3368 if (enmSwitcher != VMMSWITCHER_INVALID)
3369 {
3370 /*
3371 * Select new switcher.
3372 */
3373 int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3374 if (RT_FAILURE(rc))
3375 {
3376 AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3377 return rc;
3378 }
3379 }
3380#endif
3381
3382 /*
3383 * Exit old mode(s).
3384 */
3385#if HC_ARCH_BITS == 32
3386 /* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3387 const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3388 && enmShadowMode == PGMMODE_NESTED);
3389#else
3390 const bool fForceShwEnterExit = false;
3391#endif
3392 /* shadow */
3393 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3394 || fForceShwEnterExit)
3395 {
3396 LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3397 if (PGM_SHW_PFN(Exit, pVCpu))
3398 {
3399 int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3400 if (RT_FAILURE(rc))
3401 {
3402 AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3403 return rc;
3404 }
3405 }
3406
3407 }
3408 else
3409 LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3410
3411 /* guest */
3412 if (PGM_GST_PFN(Exit, pVCpu))
3413 {
3414 int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3415 if (RT_FAILURE(rc))
3416 {
3417 AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3418 return rc;
3419 }
3420 }
3421
3422 /*
3423 * Load new paging mode data.
3424 */
3425 pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3426
3427 /*
3428 * Enter new shadow mode (if changed).
3429 */
3430 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3431 || fForceShwEnterExit)
3432 {
3433 int rc;
3434 pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3435 switch (enmShadowMode)
3436 {
3437 case PGMMODE_32_BIT:
3438 rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3439 break;
3440 case PGMMODE_PAE:
3441 case PGMMODE_PAE_NX:
3442 rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3443 break;
3444 case PGMMODE_AMD64:
3445 case PGMMODE_AMD64_NX:
3446 rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3447 break;
3448 case PGMMODE_NESTED:
3449 rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3450 break;
3451 case PGMMODE_EPT:
3452 rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3453 break;
3454 case PGMMODE_REAL:
3455 case PGMMODE_PROTECTED:
3456 default:
3457 AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3458 return VERR_INTERNAL_ERROR;
3459 }
3460 if (RT_FAILURE(rc))
3461 {
3462 AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3463 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3464 return rc;
3465 }
3466 }
3467
3468 /*
3469 * Always flag the necessary updates
3470 */
3471 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3472
3473 /*
3474 * Enter the new guest and shadow+guest modes.
3475 */
3476 int rc = -1;
3477 int rc2 = -1;
3478 RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3479 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3480 switch (enmGuestMode)
3481 {
3482 case PGMMODE_REAL:
3483 rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3484 switch (pVCpu->pgm.s.enmShadowMode)
3485 {
3486 case PGMMODE_32_BIT:
3487 rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3488 break;
3489 case PGMMODE_PAE:
3490 case PGMMODE_PAE_NX:
3491 rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3492 break;
3493 case PGMMODE_NESTED:
3494 rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3495 break;
3496 case PGMMODE_EPT:
3497 rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3498 break;
3499 case PGMMODE_AMD64:
3500 case PGMMODE_AMD64_NX:
3501 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3502 default: AssertFailed(); break;
3503 }
3504 break;
3505
3506 case PGMMODE_PROTECTED:
3507 rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3508 switch (pVCpu->pgm.s.enmShadowMode)
3509 {
3510 case PGMMODE_32_BIT:
3511 rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3512 break;
3513 case PGMMODE_PAE:
3514 case PGMMODE_PAE_NX:
3515 rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3516 break;
3517 case PGMMODE_NESTED:
3518 rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3519 break;
3520 case PGMMODE_EPT:
3521 rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3522 break;
3523 case PGMMODE_AMD64:
3524 case PGMMODE_AMD64_NX:
3525 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3526 default: AssertFailed(); break;
3527 }
3528 break;
3529
3530 case PGMMODE_32_BIT:
3531 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3532 rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3533 switch (pVCpu->pgm.s.enmShadowMode)
3534 {
3535 case PGMMODE_32_BIT:
3536 rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3537 break;
3538 case PGMMODE_PAE:
3539 case PGMMODE_PAE_NX:
3540 rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3541 break;
3542 case PGMMODE_NESTED:
3543 rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3544 break;
3545 case PGMMODE_EPT:
3546 rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3547 break;
3548 case PGMMODE_AMD64:
3549 case PGMMODE_AMD64_NX:
3550 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3551 default: AssertFailed(); break;
3552 }
3553 break;
3554
3555 case PGMMODE_PAE_NX:
3556 case PGMMODE_PAE:
3557 {
3558 uint32_t u32Dummy, u32Features;
3559
3560 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3561 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3562 return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3563 N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3564
3565 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3566 rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3567 switch (pVCpu->pgm.s.enmShadowMode)
3568 {
3569 case PGMMODE_PAE:
3570 case PGMMODE_PAE_NX:
3571 rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3572 break;
3573 case PGMMODE_NESTED:
3574 rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3575 break;
3576 case PGMMODE_EPT:
3577 rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3578 break;
3579 case PGMMODE_32_BIT:
3580 case PGMMODE_AMD64:
3581 case PGMMODE_AMD64_NX:
3582 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3583 default: AssertFailed(); break;
3584 }
3585 break;
3586 }
3587
3588#ifdef VBOX_WITH_64_BITS_GUESTS
3589 case PGMMODE_AMD64_NX:
3590 case PGMMODE_AMD64:
3591 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3592 rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3593 switch (pVCpu->pgm.s.enmShadowMode)
3594 {
3595 case PGMMODE_AMD64:
3596 case PGMMODE_AMD64_NX:
3597 rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3598 break;
3599 case PGMMODE_NESTED:
3600 rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3601 break;
3602 case PGMMODE_EPT:
3603 rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3604 break;
3605 case PGMMODE_32_BIT:
3606 case PGMMODE_PAE:
3607 case PGMMODE_PAE_NX:
3608 AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3609 default: AssertFailed(); break;
3610 }
3611 break;
3612#endif
3613
3614 default:
3615 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3616 rc = VERR_NOT_IMPLEMENTED;
3617 break;
3618 }
3619
3620 /* status codes. */
3621 AssertRC(rc);
3622 AssertRC(rc2);
3623 if (RT_SUCCESS(rc))
3624 {
3625 rc = rc2;
3626 if (RT_SUCCESS(rc)) /* no informational status codes. */
3627 rc = VINF_SUCCESS;
3628 }
3629
3630 /* Notify HM as well. */
3631 HMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3632 return rc;
3633}
3634
3635
3636/**
3637 * Called by pgmPoolFlushAllInt prior to flushing the pool.
3638 *
3639 * @returns VBox status code, fully asserted.
3640 * @param pVCpu Pointer to the VMCPU.
3641 */
3642int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3643{
3644 /* Unmap the old CR3 value before flushing everything. */
3645 int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3646 AssertRC(rc);
3647
3648 /* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3649 rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3650 AssertRC(rc);
3651 Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3652 return rc;
3653}
3654
3655
3656/**
3657 * Called by pgmPoolFlushAllInt after flushing the pool.
3658 *
3659 * @returns VBox status code, fully asserted.
3660 * @param pVM Pointer to the VM.
3661 * @param pVCpu Pointer to the VMCPU.
3662 */
3663int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3664{
3665 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3666 int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3667 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3668 AssertRCReturn(rc, rc);
3669 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3670
3671 Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3672 AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3673 || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3674 ("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3675 return rc;
3676}
3677
3678
3679/**
3680 * Called by PGMR3PhysSetA20 after changing the A20 state.
3681 *
3682 * @param pVCpu Pointer to the VMCPU.
3683 */
3684void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3685{
3686 /** @todo Probably doing a bit too much here. */
3687 int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3688 AssertReleaseRC(rc);
3689 rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3690 AssertReleaseRC(rc);
3691}
3692
3693
3694#ifdef VBOX_WITH_DEBUGGER
3695
3696/**
3697 * @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
3698 */
3699static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3700{
3701 /*
3702 * Validate input.
3703 */
3704 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3705 PVM pVM = pUVM->pVM;
3706 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 || (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
3707
3708 if (!cArgs)
3709 {
3710 /*
3711 * Print the list of error injection locations with status.
3712 */
3713 DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
3714 DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3715 }
3716 else
3717 {
3718 /*
3719 * String switch on where to inject the error.
3720 */
3721 bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3722 const char *pszWhere = paArgs[0].u.pszString;
3723 if (!strcmp(pszWhere, "handy"))
3724 ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3725 else
3726 return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
3727 DBGCCmdHlpPrintf(pCmdHlp, "done\n");
3728 }
3729 return VINF_SUCCESS;
3730}
3731
3732
3733/**
3734 * @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
3735 */
3736static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3737{
3738 /*
3739 * Validate input.
3740 */
3741 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3742 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3743 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3744 if (!pVCpu)
3745 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3746
3747 /*
3748 * Force page directory sync.
3749 */
3750 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3751
3752 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
3753 if (RT_FAILURE(rc))
3754 return rc;
3755
3756 return VINF_SUCCESS;
3757}
3758
3759#ifdef VBOX_STRICT
3760
3761/**
3762 * EMT callback for pgmR3CmdAssertCR3.
3763 *
3764 * @returns VBox status code.
3765 * @param pUVM The user mode VM handle.
3766 * @param pcErrors Where to return the error count.
3767 */
3768static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
3769{
3770 PVM pVM = pUVM->pVM;
3771 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3772 PVMCPU pVCpu = VMMGetCpu(pVM);
3773
3774 *pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3775
3776 return VINF_SUCCESS;
3777}
3778
3779
3780/**
3781 * @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
3782 */
3783static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3784{
3785 /*
3786 * Validate input.
3787 */
3788 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3789 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3790
3791 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
3792 if (RT_FAILURE(rc))
3793 return rc;
3794
3795 unsigned cErrors = 0;
3796 rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
3797 if (RT_FAILURE(rc))
3798 return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
3799 if (cErrors > 0)
3800 return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
3801 return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
3802}
3803
3804#endif /* VBOX_STRICT */
3805
3806/**
3807 * @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
3808 */
3809static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3810{
3811 /*
3812 * Validate input.
3813 */
3814 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3815 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3816 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3817 if (!pVCpu)
3818 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3819
3820 /*
3821 * Force page directory sync.
3822 */
3823 int rc;
3824 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3825 {
3826 ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3827 rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
3828 }
3829 else
3830 {
3831 ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3832 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3833 rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
3834 }
3835 return rc;
3836}
3837
3838
3839/**
3840 * @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
3841 */
3842static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3843{
3844 /*
3845 * Validate input.
3846 */
3847 NOREF(pCmd);
3848 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3849 PVM pVM = pUVM->pVM;
3850 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 || cArgs == 2);
3851 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType != DBGCVAR_TYPE_STRING);
3852 if (cArgs == 2)
3853 {
3854 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[2].enmType != DBGCVAR_TYPE_STRING);
3855 if (strcmp(paArgs[1].u.pszString, "nozero"))
3856 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3857 }
3858 bool fIncZeroPgs = cArgs < 2;
3859
3860 /*
3861 * Open the output file and get the ram parameters.
3862 */
3863 RTFILE hFile;
3864 int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
3865 if (RT_FAILURE(rc))
3866 return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3867
3868 uint32_t cbRamHole = 0;
3869 CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3870 uint64_t cbRam = 0;
3871 CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
3872 RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3873
3874 /*
3875 * Dump the physical memory, page by page.
3876 */
3877 RTGCPHYS GCPhys = 0;
3878 char abZeroPg[PAGE_SIZE];
3879 RT_ZERO(abZeroPg);
3880
3881 pgmLock(pVM);
3882 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3883 pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3884 pRam = pRam->pNextR3)
3885 {
3886 /* fill the gap */
3887 if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3888 {
3889 while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3890 {
3891 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3892 GCPhys += PAGE_SIZE;
3893 }
3894 }
3895
3896 PCPGMPAGE pPage = &pRam->aPages[0];
3897 while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3898 {
3899 if ( PGM_PAGE_IS_ZERO(pPage)
3900 || PGM_PAGE_IS_BALLOONED(pPage))
3901 {
3902 if (fIncZeroPgs)
3903 {
3904 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3905 if (RT_FAILURE(rc))
3906 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3907 }
3908 }
3909 else
3910 {
3911 switch (PGM_PAGE_GET_TYPE(pPage))
3912 {
3913 case PGMPAGETYPE_RAM:
3914 case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3915 case PGMPAGETYPE_ROM:
3916 case PGMPAGETYPE_MMIO2:
3917 {
3918 void const *pvPage;
3919 PGMPAGEMAPLOCK Lock;
3920 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3921 if (RT_SUCCESS(rc))
3922 {
3923 rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3924 PGMPhysReleasePageMappingLock(pVM, &Lock);
3925 if (RT_FAILURE(rc))
3926 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3927 }
3928 else
3929 DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3930 break;
3931 }
3932
3933 default:
3934 AssertFailed();
3935 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3936 case PGMPAGETYPE_MMIO:
3937 if (fIncZeroPgs)
3938 {
3939 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3940 if (RT_FAILURE(rc))
3941 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3942 }
3943 break;
3944 }
3945 }
3946
3947
3948 /* advance */
3949 GCPhys += PAGE_SIZE;
3950 pPage++;
3951 }
3952 }
3953 pgmUnlock(pVM);
3954
3955 RTFileClose(hFile);
3956 if (RT_SUCCESS(rc))
3957 return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
3958 return VINF_SUCCESS;
3959}
3960
3961#endif /* VBOX_WITH_DEBUGGER */
3962
3963/**
3964 * pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3965 */
3966typedef struct PGMCHECKINTARGS
3967{
3968 bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
3969 PPGMPHYSHANDLER pPrevPhys;
3970 PPGMVIRTHANDLER pPrevVirt;
3971 PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3972 PVM pVM;
3973} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3974
3975/**
3976 * Validate a node in the physical handler tree.
3977 *
3978 * @returns 0 on if ok, other wise 1.
3979 * @param pNode The handler node.
3980 * @param pvUser pVM.
3981 */
3982static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3983{
3984 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3985 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3986 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3987 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3988 AssertReleaseMsg( !pArgs->pPrevPhys
3989 || (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3990 ("pPrevPhys=%p %RGp-%RGp %s\n"
3991 " pCur=%p %RGp-%RGp %s\n",
3992 pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3993 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3994 pArgs->pPrevPhys = pCur;
3995 return 0;
3996}
3997
3998
3999/**
4000 * Validate a node in the virtual handler tree.
4001 *
4002 * @returns 0 on if ok, other wise 1.
4003 * @param pNode The handler node.
4004 * @param pvUser pVM.
4005 */
4006static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4007{
4008 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4009 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4010 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4011 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4012 AssertReleaseMsg( !pArgs->pPrevVirt
4013 || (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4014 ("pPrevVirt=%p %RGv-%RGv %s\n"
4015 " pCur=%p %RGv-%RGv %s\n",
4016 pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4017 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4018 for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4019 {
4020 AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4021 ("pCur=%p %RGv-%RGv %s\n"
4022 "iPage=%d offVirtHandle=%#x expected %#x\n",
4023 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4024 iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4025 }
4026 pArgs->pPrevVirt = pCur;
4027 return 0;
4028}
4029
4030
4031/**
4032 * Validate a node in the virtual handler tree.
4033 *
4034 * @returns 0 on if ok, other wise 1.
4035 * @param pNode The handler node.
4036 * @param pvUser pVM.
4037 */
4038static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4039{
4040 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4041 PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4042 AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4043 AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4044 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4045 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4046 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4047 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4048 " pCur=%p %RGp-%RGp\n",
4049 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4050 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4051 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4052 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4053 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4054 " pCur=%p %RGp-%RGp\n",
4055 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4056 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4057 AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD),
4058 ("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4059 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4060 if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4061 {
4062 PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4063 for (;;)
4064 {
4065 pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4066 AssertReleaseMsg(pCur2 != pCur,
4067 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4068 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4069 AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4070 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4071 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4072 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4073 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4074 AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4075 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4076 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4077 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4078 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4079 AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4080 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4081 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4082 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4083 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4084 if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4085 break;
4086 }
4087 }
4088
4089 pArgs->pPrevPhys2Virt = pCur;
4090 return 0;
4091}
4092
4093
4094/**
4095 * Perform an integrity check on the PGM component.
4096 *
4097 * @returns VINF_SUCCESS if everything is fine.
4098 * @returns VBox error status after asserting on integrity breach.
4099 * @param pVM Pointer to the VM.
4100 */
4101VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4102{
4103 AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4104
4105 /*
4106 * Check the trees.
4107 */
4108 int cErrors = 0;
4109 const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4110 const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4111 PGMCHECKINTARGS Args = s_LeftToRight;
4112 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4113 Args = s_RightToLeft;
4114 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4115 Args = s_LeftToRight;
4116 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4117 Args = s_RightToLeft;
4118 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4119 Args = s_LeftToRight;
4120 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4121 Args = s_RightToLeft;
4122 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4123 Args = s_LeftToRight;
4124 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4125 Args = s_RightToLeft;
4126 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4127
4128 return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4129}
4130
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