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source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp@ 93115

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1/* $Id: PDMDevMiscHlp.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Misc. Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/apic.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmm.h>
30
31#include <VBox/log.h>
32#include <VBox/err.h>
33#include <VBox/msi.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36#include <iprt/thread.h>
37
38
39#include "PDMInline.h"
40#include "dtrace/VBoxVMM.h"
41
42
43
44/** @name Ring-3 PIC Helpers
45 * @{
46 */
47
48/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
49static DECLCALLBACK(void) pdmR3PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
50{
51 PDMDEV_ASSERT_DEVINS(pDevIns);
52 PVM pVM = pDevIns->Internal.s.pVMR3;
53 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
54
55 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
56 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
57
58 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
59}
60
61
62/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
63static DECLCALLBACK(void) pdmR3PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
64{
65 PDMDEV_ASSERT_DEVINS(pDevIns);
66 PVM pVM = pDevIns->Internal.s.pVMR3;
67 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
68
69 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
70 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
71
72 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
73}
74
75
76/** @interface_method_impl{PDMPICHLP,pfnLock} */
77static DECLCALLBACK(int) pdmR3PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
78{
79 PDMDEV_ASSERT_DEVINS(pDevIns);
80 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
81}
82
83
84/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
85static DECLCALLBACK(void) pdmR3PicHlp_Unlock(PPDMDEVINS pDevIns)
86{
87 PDMDEV_ASSERT_DEVINS(pDevIns);
88 pdmUnlock(pDevIns->Internal.s.pVMR3);
89}
90
91
92/**
93 * PIC Device Helpers.
94 */
95const PDMPICHLP g_pdmR3DevPicHlp =
96{
97 PDM_PICHLP_VERSION,
98 pdmR3PicHlp_SetInterruptFF,
99 pdmR3PicHlp_ClearInterruptFF,
100 pdmR3PicHlp_Lock,
101 pdmR3PicHlp_Unlock,
102 PDM_PICHLP_VERSION /* the end */
103};
104
105/** @} */
106
107
108/** @name Ring-3 I/O APIC Helpers
109 * @{
110 */
111
112/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
113static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
114 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
115 uint8_t u8TriggerMode, uint32_t uTagSrc)
116{
117 PDMDEV_ASSERT_DEVINS(pDevIns);
118 PVM pVM = pDevIns->Internal.s.pVMR3;
119 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
120 pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
121 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
122}
123
124
125/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
126static DECLCALLBACK(int) pdmR3IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
127{
128 PDMDEV_ASSERT_DEVINS(pDevIns);
129 LogFlow(("pdmR3IoApicHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
130 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
131}
132
133
134/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
135static DECLCALLBACK(void) pdmR3IoApicHlp_Unlock(PPDMDEVINS pDevIns)
136{
137 PDMDEV_ASSERT_DEVINS(pDevIns);
138 LogFlow(("pdmR3IoApicHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
139 pdmUnlock(pDevIns->Internal.s.pVMR3);
140}
141
142
143/** @interface_method_impl{PDMIOAPICHLP,pfnLockIsOwner} */
144static DECLCALLBACK(bool) pdmR3IoApicHlp_LockIsOwner(PPDMDEVINS pDevIns)
145{
146 PDMDEV_ASSERT_DEVINS(pDevIns);
147 LogFlow(("pdmR3IoApicHlp_LockIsOwner: caller='%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
148 return pdmLockIsOwner(pDevIns->Internal.s.pVMR3);
149}
150
151
152/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
153static DECLCALLBACK(int) pdmR3IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
154{
155 PDMDEV_ASSERT_DEVINS(pDevIns);
156 LogFlow(("pdmR3IoApicHlp_IommuRemapMsi: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
157 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
158
159#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
160 if (pdmIommuIsPresent(pDevIns))
161 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
162#else
163 RT_NOREF(pDevIns, idDevice);
164#endif
165 return VERR_IOMMU_NOT_PRESENT;
166}
167
168
169/**
170 * I/O APIC Device Helpers.
171 */
172const PDMIOAPICHLP g_pdmR3DevIoApicHlp =
173{
174 PDM_IOAPICHLP_VERSION,
175 pdmR3IoApicHlp_ApicBusDeliver,
176 pdmR3IoApicHlp_Lock,
177 pdmR3IoApicHlp_Unlock,
178 pdmR3IoApicHlp_LockIsOwner,
179 pdmR3IoApicHlp_IommuMsiRemap,
180 PDM_IOAPICHLP_VERSION /* the end */
181};
182
183/** @} */
184
185
186
187
188/** @name Ring-3 PCI Bus Helpers
189 * @{
190 */
191
192/** @interface_method_impl{PDMPCIHLPR3,pfnIsaSetIrq} */
193static DECLCALLBACK(void) pdmR3PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
194{
195 PDMDEV_ASSERT_DEVINS(pDevIns);
196 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
197 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
198}
199
200
201/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */
202static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
203{
204 PDMDEV_ASSERT_DEVINS(pDevIns);
205 Log4(("pdmR3PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
206 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, uBusDevFn, iIrq, iLevel, uTagSrc);
207}
208
209
210/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */
211static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
212{
213 PDMDEV_ASSERT_DEVINS(pDevIns);
214 Assert(PCIBDF_IS_VALID(uBusDevFn));
215 Log4(("pdmR3PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi (Addr=%#RX64 Data=%#x) uTagSrc=%#x\n", uBusDevFn,
216 pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
217 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, uBusDevFn, pMsi, uTagSrc);
218}
219
220
221/** @interface_method_impl{PDMPCIHLPR3,pfnLock} */
222static DECLCALLBACK(int) pdmR3PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
223{
224 PDMDEV_ASSERT_DEVINS(pDevIns);
225 LogFlow(("pdmR3PciHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
226 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
227}
228
229
230/** @interface_method_impl{PDMPCIHLPR3,pfnUnlock} */
231static DECLCALLBACK(void) pdmR3PciHlp_Unlock(PPDMDEVINS pDevIns)
232{
233 PDMDEV_ASSERT_DEVINS(pDevIns);
234 LogFlow(("pdmR3PciHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
235 pdmUnlock(pDevIns->Internal.s.pVMR3);
236}
237
238
239/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
240static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
241{
242 PDMDEV_ASSERT_DEVINS(pDevIns);
243 PVM pVM = pDevIns->Internal.s.pVMR3;
244 AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
245 PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
246 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
247 return pRetDevIns;
248}
249
250
251/**
252 * PCI Bus Device Helpers.
253 */
254const PDMPCIHLPR3 g_pdmR3DevPciHlp =
255{
256 PDM_PCIHLPR3_VERSION,
257 pdmR3PciHlp_IsaSetIrq,
258 pdmR3PciHlp_IoApicSetIrq,
259 pdmR3PciHlp_IoApicSendMsi,
260 pdmR3PciHlp_Lock,
261 pdmR3PciHlp_Unlock,
262 pdmR3PciHlp_GetBusByNo,
263 PDM_PCIHLPR3_VERSION, /* the end */
264};
265
266/** @} */
267
268
269/** @name Ring-3 IOMMU Helpers
270 * @{
271 */
272
273/** @interface_method_impl{PDMIOMMUHLPR3,pfnLock} */
274static DECLCALLBACK(int) pdmR3IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
275{
276 PDMDEV_ASSERT_DEVINS(pDevIns);
277 LogFlowFunc(("caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
278 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
279}
280
281
282/** @interface_method_impl{PDMIOMMUHLPR3,pfnUnlock} */
283static DECLCALLBACK(void) pdmR3IommuHlp_Unlock(PPDMDEVINS pDevIns)
284{
285 PDMDEV_ASSERT_DEVINS(pDevIns);
286 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
287 pdmUnlock(pDevIns->Internal.s.pVMR3);
288}
289
290
291/** @interface_method_impl{PDMIOMMUHLPR3,pfnLockIsOwner} */
292static DECLCALLBACK(bool) pdmR3IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
293{
294 PDMDEV_ASSERT_DEVINS(pDevIns);
295 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
296 return pdmLockIsOwner(pDevIns->Internal.s.pVMR3);
297}
298
299
300/** @interface_method_impl{PDMIOMMUHLPR3,pfnSendMsi} */
301static DECLCALLBACK(void) pdmR3IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
302{
303 PDMDEV_ASSERT_DEVINS(pDevIns);
304 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
305 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, NIL_PCIBDF, pMsi, uTagSrc);
306}
307
308
309/**
310 * IOMMU Device Helpers.
311 */
312const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp =
313{
314 PDM_IOMMUHLPR3_VERSION,
315 pdmR3IommuHlp_Lock,
316 pdmR3IommuHlp_Unlock,
317 pdmR3IommuHlp_LockIsOwner,
318 pdmR3IommuHlp_SendMsi,
319 PDM_IOMMUHLPR3_VERSION /* the end */
320};
321
322/** @} */
323
324
325/** @name Ring-3 HPET Helpers
326 * @{
327 */
328
329/** @interface_method_impl{PDMHPETHLPR3,pfnSetLegacyMode} */
330static DECLCALLBACK(int) pdmR3HpetHlp_SetLegacyMode(PPDMDEVINS pDevIns, bool fActivated)
331{
332 PDMDEV_ASSERT_DEVINS(pDevIns);
333 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: fActivated=%RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fActivated));
334
335 size_t i;
336 int rc = VINF_SUCCESS;
337 static const char * const s_apszDevsToNotify[] =
338 {
339 "i8254",
340 "mc146818"
341 };
342 for (i = 0; i < RT_ELEMENTS(s_apszDevsToNotify); i++)
343 {
344 PPDMIBASE pBase;
345 rc = PDMR3QueryDevice(pDevIns->Internal.s.pVMR3->pUVM, "i8254", 0, &pBase);
346 if (RT_SUCCESS(rc))
347 {
348 PPDMIHPETLEGACYNOTIFY pPort = PDMIBASE_QUERY_INTERFACE(pBase, PDMIHPETLEGACYNOTIFY);
349 AssertLogRelMsgBreakStmt(pPort, ("%s\n", s_apszDevsToNotify[i]), rc = VERR_PDM_HPET_LEGACY_NOTIFY_MISSING);
350 pPort->pfnModeChanged(pPort, fActivated);
351 }
352 else if ( rc == VERR_PDM_DEVICE_NOT_FOUND
353 || rc == VERR_PDM_DEVICE_INSTANCE_NOT_FOUND)
354 rc = VINF_SUCCESS; /* the device isn't configured, ignore. */
355 else
356 AssertLogRelMsgFailedBreak(("%s -> %Rrc\n", s_apszDevsToNotify[i], rc));
357 }
358
359 /* Don't bother cleaning up, any failure here will cause a guru meditation. */
360
361 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
362 return rc;
363}
364
365
366/** @interface_method_impl{PDMHPETHLPR3,pfnSetIrq} */
367static DECLCALLBACK(int) pdmR3HpetHlp_SetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
368{
369 PDMDEV_ASSERT_DEVINS(pDevIns);
370 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
371 PVM pVM = pDevIns->Internal.s.pVMR3;
372
373 pdmLock(pVM);
374 uint32_t uTagSrc;
375 if (iLevel & PDM_IRQ_LEVEL_HIGH)
376 {
377 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
378 if (iLevel == PDM_IRQ_LEVEL_HIGH)
379 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
380 else
381 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
382 }
383 else
384 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
385
386 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
387
388 if (iLevel == PDM_IRQ_LEVEL_LOW)
389 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
390 pdmUnlock(pVM);
391 return 0;
392}
393
394
395/**
396 * HPET Device Helpers.
397 */
398const PDMHPETHLPR3 g_pdmR3DevHpetHlp =
399{
400 PDM_HPETHLPR3_VERSION,
401 pdmR3HpetHlp_SetLegacyMode,
402 pdmR3HpetHlp_SetIrq,
403 PDM_HPETHLPR3_VERSION, /* the end */
404};
405
406/** @} */
407
408
409/** @name Ring-3 Raw PCI Device Helpers
410 * @{
411 */
412
413/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
414static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
415{
416 PDMDEV_ASSERT_DEVINS(pDevIns);
417 PVM pVM = pDevIns->Internal.s.pVMR3;
418 VM_ASSERT_EMT(pVM);
419
420 RTRCPTR pRCHelpers = NIL_RTRCPTR;
421 if (VM_IS_RAW_MODE_ENABLED(pVM))
422 {
423 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
424 AssertReleaseRC(rc);
425 AssertRelease(pRCHelpers);
426 }
427
428 LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
429 pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
430 return pRCHelpers;
431}
432
433
434/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetR0Helpers} */
435static DECLCALLBACK(PCPDMPCIRAWHLPR0) pdmR3PciRawHlp_GetR0Helpers(PPDMDEVINS pDevIns)
436{
437 PDMDEV_ASSERT_DEVINS(pDevIns);
438 PVM pVM = pDevIns->Internal.s.pVMR3;
439 VM_ASSERT_EMT(pVM);
440 PCPDMHPETHLPR0 pR0Helpers = NIL_RTR0PTR;
441 int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciRawHlp", &pR0Helpers);
442 AssertReleaseRC(rc);
443 AssertRelease(pR0Helpers);
444 LogFlow(("pdmR3PciRawHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
445 pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
446 return pR0Helpers;
447}
448
449
450/**
451 * Raw PCI Device Helpers.
452 */
453const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp =
454{
455 PDM_PCIRAWHLPR3_VERSION,
456 pdmR3PciRawHlp_GetRCHelpers,
457 pdmR3PciRawHlp_GetR0Helpers,
458 PDM_PCIRAWHLPR3_VERSION, /* the end */
459};
460
461/** @} */
462
463
464/* none yet */
465
466/**
467 * Firmware Device Helpers.
468 */
469const PDMFWHLPR3 g_pdmR3DevFirmwareHlp =
470{
471 PDM_FWHLPR3_VERSION,
472 PDM_FWHLPR3_VERSION
473};
474
475/**
476 * DMAC Device Helpers.
477 */
478const PDMDMACHLP g_pdmR3DevDmacHlp =
479{
480 PDM_DMACHLP_VERSION
481};
482
483
484
485
486/* none yet */
487
488/**
489 * RTC Device Helpers.
490 */
491const PDMRTCHLP g_pdmR3DevRtcHlp =
492{
493 PDM_RTCHLP_VERSION
494};
495
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