PDMDevHlp.cpp@ 106022

Last change on this file since 106022 was 106022, checked in by vboxsync, 3 months ago
VMM/PDM: Added PDMR3DriverEnumInstances for use by Console::i_onNATDnsChanged, introducing a read/write lock for the core PDM lists (devices, drivers, usb devices, and more). Medium risk since it involves new locking.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 254.7 KB

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1	/* $Id: PDMDevHlp.cpp 106022 2024-09-12 09:44:36Z vboxsync $ */
2	/** @file
3	* PDM - Pluggable Device and Driver Manager, Device Helpers.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_PDM_DEVICE
33	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
34	#include "PDMInternal.h"
35	#include <VBox/vmm/pdm.h>
36	#include <VBox/vmm/mm.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/pgm.h>
39	#include <VBox/vmm/iom.h>
40	#include <VBox/vmm/dbgf.h>
41	#include <VBox/vmm/ssm.h>
42	#include <VBox/vmm/vmapi.h>
43	#include <VBox/vmm/vmm.h>
44	#include <VBox/vmm/vmcc.h>
45
46	#include <VBox/version.h>
47	#include <VBox/log.h>
48	#include <VBox/pci.h>
49	#include <VBox/err.h>
50	#include <iprt/asm.h>
51	#include <iprt/assert.h>
52	#include <iprt/ctype.h>
53	#include <iprt/string.h>
54	#include <iprt/thread.h>
55	#include <iprt/mem.h>
56
57	#include "dtrace/VBoxVMM.h"
58	#include "PDMInline.h"
59
60
61	/*********************************************************************************************************************************
62	* Defined Constants And Macros *
63	*********************************************************************************************************************************/
64	/** @def PDM_DEVHLP_DEADLOCK_DETECTION
65	* Define this to enable the deadlock detection when accessing physical memory.
66	*/
67	#if /defined(DEBUG_bird) \|\|/ defined(DOXYGEN_RUNNING)
68	# define PDM_DEVHLP_DEADLOCK_DETECTION /*< @todo enable DevHlp deadlock detection! /
69	#endif
70
71
72
73	/** @name R3 DevHlp
74	* @{
75	*/
76
77
78	/** @interface_method_impl{PDMDEVHLPR3,pfnIoPortCreateEx} */
79	static DECLCALLBACK(int) pdmR3DevHlp_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
80	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
81	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
82	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
83	{
84	PDMDEV_ASSERT_DEVINS(pDevIns);
85	LogFlow(("pdmR3DevHlp_IoPortCreateEx: caller='%s'/%d: cPorts=%#x fFlags=%#x pPciDev=%p iPciRegion=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p pszDesc=%p:{%s} paExtDescs=%p phIoPorts=%p\n",
86	pDevIns->pReg->szName, pDevIns->iInstance, cPorts, fFlags, pPciDev, iPciRegion, pfnOut, pfnIn, pfnOutStr, pfnInStr,
87	pvUser, pszDesc, pszDesc, paExtDescs, phIoPorts));
88	PVM pVM = pDevIns->Internal.s.pVMR3;
89	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
90	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
91
92	int rc = IOMR3IoPortCreate(pVM, pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
93	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
94
95	LogFlow(("pdmR3DevHlp_IoPortCreateEx: caller='%s'/%d: returns %Rrc (*phIoPorts=%#x)\n",
96	pDevIns->pReg->szName, pDevIns->iInstance, rc, *phIoPorts));
97	return rc;
98	}
99
100
101	/** @interface_method_impl{PDMDEVHLPR3,pfnIoPortMap} */
102	static DECLCALLBACK(int) pdmR3DevHlp_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
103	{
104	PDMDEV_ASSERT_DEVINS(pDevIns);
105	LogFlow(("pdmR3DevHlp_IoPortMap: caller='%s'/%d: hIoPorts=%#x Port=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, Port));
106	PVM pVM = pDevIns->Internal.s.pVMR3;
107	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
108
109	int rc = IOMR3IoPortMap(pVM, pDevIns, hIoPorts, Port);
110
111	LogFlow(("pdmR3DevHlp_IoPortMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
112	return rc;
113	}
114
115
116	/** @interface_method_impl{PDMDEVHLPR3,pfnIoPortUnmap} */
117	static DECLCALLBACK(int) pdmR3DevHlp_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
118	{
119	PDMDEV_ASSERT_DEVINS(pDevIns);
120	LogFlow(("pdmR3DevHlp_IoPortMap: caller='%s'/%d: hIoPorts=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts));
121	PVM pVM = pDevIns->Internal.s.pVMR3;
122	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
123
124	int rc = IOMR3IoPortUnmap(pVM, pDevIns, hIoPorts);
125
126	LogFlow(("pdmR3DevHlp_IoPortMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
127	return rc;
128	}
129
130
131	/** @interface_method_impl{PDMDEVHLPR3,pfnIoPortGetMappingAddress} */
132	static DECLCALLBACK(uint32_t) pdmR3DevHlp_IoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
133	{
134	PDMDEV_ASSERT_DEVINS(pDevIns);
135	LogFlow(("pdmR3DevHlp_IoPortGetMappingAddress: caller='%s'/%d: hIoPorts=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts));
136
137	uint32_t uAddress = IOMR3IoPortGetMappingAddress(pDevIns->Internal.s.pVMR3, pDevIns, hIoPorts);
138
139	LogFlow(("pdmR3DevHlp_IoPortGetMappingAddress: caller='%s'/%d: returns %#RX32\n", pDevIns->pReg->szName, pDevIns->iInstance, uAddress));
140	return uAddress;
141	}
142
143
144	/** @interface_method_impl{PDMDEVHLPR3,pfnIoPortRead} */
145	static DECLCALLBACK(VBOXSTRICTRC) pdmR3DevHlp_IoPortRead(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)
146	{
147	PDMDEV_ASSERT_DEVINS(pDevIns);
148	LogFlow(("pdmR3DevHlp_IoPortRead: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
149	PVM pVM = pDevIns->Internal.s.pVMR3;
150	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
151
152	PVMCPU pVCpu = VMMGetCpu(pVM);
153	AssertPtrReturn(pVCpu, VERR_ACCESS_DENIED);
154
155	VBOXSTRICTRC rcStrict = IOMIOPortRead(pVM, pVCpu, Port, pu32Value, cbValue);
156
157	LogFlow(("pdmR3DevHlp_IoPortRead: caller='%s'/%d: returns %Rrc\n",
158	pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict)));
159	return rcStrict;
160	}
161
162
163	/** @interface_method_impl{PDMDEVHLPR3,pfnIoPortWrite} */
164	static DECLCALLBACK(VBOXSTRICTRC) pdmR3DevHlp_IoPortWrite(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue)
165	{
166	PDMDEV_ASSERT_DEVINS(pDevIns);
167	LogFlow(("pdmR3DevHlp_IoPortWrite: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
168	PVM pVM = pDevIns->Internal.s.pVMR3;
169	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
170
171	PVMCPU pVCpu = VMMGetCpu(pVM);
172	AssertPtrReturn(pVCpu, VERR_ACCESS_DENIED);
173
174	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, Port, u32Value, cbValue);
175
176	LogFlow(("pdmR3DevHlp_IoPortWrite: caller='%s'/%d: returns %Rrc\n",
177	pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict)));
178	return rcStrict;
179	}
180
181
182	/** @interface_method_impl{PDMDEVHLPR3,pfnMmioCreateEx} */
183	static DECLCALLBACK(int) pdmR3DevHlp_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, uint32_t fFlags,
184	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
185	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
186	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
187	{
188	PDMDEV_ASSERT_DEVINS(pDevIns);
189	LogFlow(("pdmR3DevHlp_MmioCreateEx: caller='%s'/%d: cbRegion=%#RGp fFlags=%#x pPciDev=%p iPciRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p pszDesc=%p:{%s} phRegion=%p\n",
190	pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, fFlags, pPciDev, iPciRegion, pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, pszDesc, phRegion));
191	PVM pVM = pDevIns->Internal.s.pVMR3;
192	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
193	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
194
195	if (pDevIns->iInstance > 0)
196	{
197	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
198	AssertReturn(pszDesc, VERR_NO_STR_MEMORY);
199	}
200
201	/* HACK ALERT! Round the size up to page size. The PCI bus should do something similar before mapping it. */
202	/** @todo It's possible we need to do dummy MMIO fill-in of the PCI bus or
203	* guest adds more alignment to an region. */
204	cbRegion = RT_ALIGN_T(cbRegion, GUEST_PAGE_SIZE, RTGCPHYS);
205
206	int rc = IOMR3MmioCreate(pVM, pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
207	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
208
209	LogFlow(("pdmR3DevHlp_MmioCreateEx: caller='%s'/%d: returns %Rrc (*phRegion=%#x)\n",
210	pDevIns->pReg->szName, pDevIns->iInstance, rc, *phRegion));
211	return rc;
212	}
213
214
215	/** @interface_method_impl{PDMDEVHLPR3,pfnMmioMap} */
216	static DECLCALLBACK(int) pdmR3DevHlp_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
217	{
218	PDMDEV_ASSERT_DEVINS(pDevIns);
219	LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: hRegion=%#x GCPhys=%#RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, GCPhys));
220
221	PVM const pVM = pDevIns->Internal.s.pVMR3;
222	PVMCPU const pVCpu = VMMGetCpu(pVM);
223	AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
224
225	int rc = IOMR3MmioMap(pVM, pVCpu, pDevIns, hRegion, GCPhys);
226
227	LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
228	return rc;
229	}
230
231
232	/** @interface_method_impl{PDMDEVHLPR3,pfnMmioUnmap} */
233	static DECLCALLBACK(int) pdmR3DevHlp_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
234	{
235	PDMDEV_ASSERT_DEVINS(pDevIns);
236	LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: hRegion=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
237
238	PVM const pVM = pDevIns->Internal.s.pVMR3;
239	PVMCPU const pVCpu = VMMGetCpu(pVM);
240	AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
241
242	int rc = IOMR3MmioUnmap(pVM, pVCpu, pDevIns, hRegion);
243
244	LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
245	return rc;
246	}
247
248
249	/** @interface_method_impl{PDMDEVHLPR3,pfnMmioReduce} */
250	static DECLCALLBACK(int) pdmR3DevHlp_MmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
251	{
252	PDMDEV_ASSERT_DEVINS(pDevIns);
253	LogFlow(("pdmR3DevHlp_MmioReduce: caller='%s'/%d: hRegion=%#x cbRegion=%#RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, cbRegion));
254	PVM pVM = pDevIns->Internal.s.pVMR3;
255	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
256	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_LOADING, VERR_VM_INVALID_VM_STATE);
257
258	int rc = IOMR3MmioReduce(pVM, pDevIns, hRegion, cbRegion);
259
260	LogFlow(("pdmR3DevHlp_MmioReduce: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
261	return rc;
262	}
263
264
265	/** @interface_method_impl{PDMDEVHLPR3,pfnMmioGetMappingAddress} */
266	static DECLCALLBACK(RTGCPHYS) pdmR3DevHlp_MmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
267	{
268	PDMDEV_ASSERT_DEVINS(pDevIns);
269	LogFlow(("pdmR3DevHlp_MmioGetMappingAddress: caller='%s'/%d: hRegion=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
270
271	RTGCPHYS GCPhys = IOMR3MmioGetMappingAddress(pDevIns->Internal.s.pVMR3, pDevIns, hRegion);
272
273	LogFlow(("pdmR3DevHlp_MmioGetMappingAddress: caller='%s'/%d: returns %RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
274	return GCPhys;
275	}
276
277
278	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2Create} */
279	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
280	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
281	{
282	PDMDEV_ASSERT_DEVINS(pDevIns);
283	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
284	LogFlow(("pdmR3DevHlp_Mmio2Create: caller='%s'/%d: pPciDev=%p (%#x) iPciRegion=%#x cbRegion=%#RGp fFlags=%RX32 pszDesc=%p:{%s} ppvMapping=%p phRegion=%p\n",
285	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iPciRegion, cbRegion,
286	fFlags, pszDesc, pszDesc, ppvMapping, phRegion));
287	*ppvMapping = NULL;
288	*phRegion = NIL_PGMMMIO2HANDLE;
289	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
290
291	PVM const pVM = pDevIns->Internal.s.pVMR3;
292
293	AssertReturn(!(iPciRegion & UINT16_MAX), VERR_INVALID_PARAMETER); /* not implemented. */
294
295	/** @todo PGMR3PhysMmio2Register mangles the description, move it here and
296	* use a real string cache. */
297	int rc = PGMR3PhysMmio2Register(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iPciRegion >> 16,
298	cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
299
300	LogFlow(("pdmR3DevHlp_Mmio2Create: caller='%s'/%d: returns %Rrc *ppvMapping=%p phRegion=%#RX64\n",
301	pDevIns->pReg->szName, pDevIns->iInstance, rc, ppvMapping, phRegion));
302	return rc;
303	}
304
305
306	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2Destroy} */
307	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2Destroy(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
308	{
309	PDMDEV_ASSERT_DEVINS(pDevIns);
310	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
311	LogFlow(("pdmR3DevHlp_Mmio2Destroy: caller='%s'/%d: hRegion=%#RX64\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
312
313	int rc = PGMR3PhysMmio2Deregister(pDevIns->Internal.s.pVMR3, pDevIns, hRegion);
314
315	LogFlow(("pdmR3DevHlp_Mmio2Destroy: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
316	return rc;
317	}
318
319
320	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2Map} */
321	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
322	{
323	PDMDEV_ASSERT_DEVINS(pDevIns);
324	LogFlow(("pdmR3DevHlp_Mmio2Map: caller='%s'/%d: hRegion=%#RX64 GCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, GCPhys));
325
326	PVM pVM = pDevIns->Internal.s.pVMR3;
327	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
328
329	int rc = PGMR3PhysMmio2Map(pDevIns->Internal.s.pVMR3, pDevIns, hRegion, GCPhys);
330
331	LogFlow(("pdmR3DevHlp_Mmio2Map: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
332	return rc;
333	}
334
335
336	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2Unmap} */
337	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
338	{
339	PDMDEV_ASSERT_DEVINS(pDevIns);
340	LogFlow(("pdmR3DevHlp_Mmio2Unmap: caller='%s'/%d: hRegion=%#RX64\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
341
342	PVM pVM = pDevIns->Internal.s.pVMR3;
343	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
344
345	int rc = PGMR3PhysMmio2Unmap(pDevIns->Internal.s.pVMR3, pDevIns, hRegion, NIL_RTGCPHYS);
346
347	LogFlow(("pdmR3DevHlp_Mmio2Unmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
348	return rc;
349	}
350
351
352	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2Reduce} */
353	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
354	{
355	PDMDEV_ASSERT_DEVINS(pDevIns);
356	LogFlow(("pdmR3DevHlp_Mmio2Reduce: caller='%s'/%d: hRegion=%#RX64 cbRegion=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, cbRegion));
357	PVM pVM = pDevIns->Internal.s.pVMR3;
358	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
359	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_LOADING, VERR_VM_INVALID_VM_STATE);
360
361	int rc = PGMR3PhysMmio2Reduce(pDevIns->Internal.s.pVMR3, pDevIns, hRegion, cbRegion);
362
363	LogFlow(("pdmR3DevHlp_Mmio2Reduce: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
364	return rc;
365	}
366
367
368	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2GetMappingAddress} */
369	static DECLCALLBACK(RTGCPHYS) pdmR3DevHlp_Mmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
370	{
371	PDMDEV_ASSERT_DEVINS(pDevIns);
372	PVM pVM = pDevIns->Internal.s.pVMR3;
373	LogFlow(("pdmR3DevHlp_Mmio2GetMappingAddress: caller='%s'/%d: hRegion=%#RX64\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
374	VM_ASSERT_EMT0_RETURN(pVM, NIL_RTGCPHYS);
375
376	RTGCPHYS GCPhys = PGMR3PhysMmio2GetMappingAddress(pVM, pDevIns, hRegion);
377
378	LogFlow(("pdmR3DevHlp_Mmio2GetMappingAddress: caller='%s'/%d: returns %RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
379	return GCPhys;
380	}
381
382
383	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2QueryAndResetDirtyBitmap} */
384	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2QueryAndResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
385	void *pvBitmap, size_t cbBitmap)
386	{
387	PDMDEV_ASSERT_DEVINS(pDevIns);
388	PVM pVM = pDevIns->Internal.s.pVMR3;
389	LogFlow(("pdmR3DevHlp_Mmio2QueryAndResetDirtyBitmap: caller='%s'/%d: hRegion=%#RX64 pvBitmap=%p cbBitmap=%#zx\n",
390	pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pvBitmap, cbBitmap));
391
392	int rc = PGMR3PhysMmio2QueryAndResetDirtyBitmap(pVM, pDevIns, hRegion, pvBitmap, cbBitmap);
393
394	LogFlow(("pdmR3DevHlp_Mmio2QueryAndResetDirtyBitmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
395	return rc;
396	}
397
398
399	/** @interface_method_impl{PDMDEVHLPR3,pfnMmio2ControlDirtyPageTracking} */
400	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2ControlDirtyPageTracking(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled)
401	{
402	PDMDEV_ASSERT_DEVINS(pDevIns);
403	PVM pVM = pDevIns->Internal.s.pVMR3;
404	LogFlow(("pdmR3DevHlp_Mmio2ControlDirtyPageTracking: caller='%s'/%d: hRegion=%#RX64 fEnabled=%RTbool\n",
405	pDevIns->pReg->szName, pDevIns->iInstance, hRegion, fEnabled));
406
407	int rc = PGMR3PhysMmio2ControlDirtyPageTracking(pVM, pDevIns, hRegion, fEnabled);
408
409	LogFlow(("pdmR3DevHlp_Mmio2ControlDirtyPageTracking: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
410	return rc;
411	}
412
413
414	/**
415	* @copydoc PDMDEVHLPR3::pfnMmio2ChangeRegionNo
416	*/
417	static DECLCALLBACK(int) pdmR3DevHlp_Mmio2ChangeRegionNo(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion)
418	{
419	PDMDEV_ASSERT_DEVINS(pDevIns);
420	PVM pVM = pDevIns->Internal.s.pVMR3;
421	LogFlow(("pdmR3DevHlp_Mmio2ChangeRegionNo: caller='%s'/%d: hRegion=%#RX64 iNewRegion=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, iNewRegion));
422	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
423
424	int rc = PGMR3PhysMmio2ChangeRegionNo(pVM, pDevIns, hRegion, iNewRegion);
425
426	LogFlow(("pdmR3DevHlp_Mmio2ChangeRegionNo: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
427	return rc;
428	}
429
430
431	/** @interface_method_impl{PDMDEVHLPR3,pfnMmioMapMmio2Page} */
432	static DECLCALLBACK(int) pdmR3DevHlp_MmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
433	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
434	{
435	PDMDEV_ASSERT_DEVINS(pDevIns);
436	LogFlow(("pdmR3DevHlp_MmioMapMmio2Page: caller='%s'/%d: hRegion=%RX64 offRegion=%RGp hMmio2=%RX64 offMmio2=%RGp fPageFlags=%RX64\n",
437	pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offRegion, hMmio2, offMmio2, fPageFlags));
438
439	int rc = IOMMmioMapMmio2Page(pDevIns->Internal.s.pVMR3, pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
440
441	Log(("pdmR3DevHlp_MmioMapMmio2Page: caller='%s'/%d: returns %Rrc\n",
442	pDevIns->pReg->szName, pDevIns->iInstance, rc));
443	return rc;
444	}
445
446
447	/** @interface_method_impl{PDMDEVHLPR3,pfnMmioResetRegion} */
448	static DECLCALLBACK(int) pdmR3DevHlp_MmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
449	{
450	PDMDEV_ASSERT_DEVINS(pDevIns);
451	LogFlow(("pdmR3DevHlp_MmioResetRegion: caller='%s'/%d: hRegion=%RX64\n",
452	pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
453
454	int rc = IOMMmioResetRegion(pDevIns->Internal.s.pVMR3, pDevIns, hRegion);
455
456	Log(("pdmR3DevHlp_MmioResetRegion: caller='%s'/%d: returns %Rrc\n",
457	pDevIns->pReg->szName, pDevIns->iInstance, rc));
458	return rc;
459	}
460
461
462	/** @interface_method_impl{PDMDEVHLPR3,pfnROMRegister} */
463	static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
464	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
465	{
466	PDMDEV_ASSERT_DEVINS(pDevIns);
467	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
468	LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvBinary=%p cbBinary=%#x fFlags=%#RX32 pszDesc=%p:{%s}\n",
469	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc, pszDesc));
470
471	/** @todo can we mangle pszDesc? */
472	int rc = PGMR3PhysRomRegister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
473
474	LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
475	return rc;
476	}
477
478
479	/** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */
480	static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
481	{
482	PDMDEV_ASSERT_DEVINS(pDevIns);
483	LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n",
484	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt));
485
486	int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt);
487
488	LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
489	return rc;
490	}
491
492
493	/** @interface_method_impl{PDMDEVHLPR3,pfnSSMRegister} */
494	static DECLCALLBACK(int) pdmR3DevHlp_SSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
495	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
496	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
497	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
498	{
499	PDMDEV_ASSERT_DEVINS(pDevIns);
500	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
501	LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: uVersion=%#x cbGuess=%#x pszBefore=%p:{%s}\n"
502	" pfnLivePrep=%p pfnLiveExec=%p pfnLiveVote=%p pfnSavePrep=%p pfnSaveExec=%p pfnSaveDone=%p pfnLoadPrep=%p pfnLoadExec=%p pfnLoadDone=%p\n",
503	pDevIns->pReg->szName, pDevIns->iInstance, uVersion, cbGuess, pszBefore, pszBefore,
504	pfnLivePrep, pfnLiveExec, pfnLiveVote,
505	pfnSavePrep, pfnSaveExec, pfnSaveDone,
506	pfnLoadPrep, pfnLoadExec, pfnLoadDone));
507
508	int rc = SSMR3RegisterDevice(pDevIns->Internal.s.pVMR3, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance,
509	uVersion, cbGuess, pszBefore,
510	pfnLivePrep, pfnLiveExec, pfnLiveVote,
511	pfnSavePrep, pfnSaveExec, pfnSaveDone,
512	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
513
514	LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
515	return rc;
516	}
517
518
519	/** @interface_method_impl{PDMDEVHLPR3,pfnSSMRegisterLegacy} */
520	static DECLCALLBACK(int) pdmR3DevHlp_SSMRegisterLegacy(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
521	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
522	{
523	PDMDEV_ASSERT_DEVINS(pDevIns);
524	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
525	LogFlow(("pdmR3DevHlp_SSMRegisterLegacy: caller='%s'/%d: pszOldName=%p:{%s} pfnLoadPrep=%p pfnLoadExec=%p pfnLoadDone=%p\n",
526	pDevIns->pReg->szName, pDevIns->iInstance, pszOldName, pszOldName, pfnLoadPrep, pfnLoadExec, pfnLoadDone));
527
528	int rc = SSMR3RegisterDevice(pDevIns->Internal.s.pVMR3, pDevIns, pszOldName, pDevIns->iInstance,
529	0 /uVersion/, 0 /cbGuess/, NULL /pszBefore/,
530	NULL, NULL, NULL,
531	NULL, NULL, NULL,
532	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
533
534	LogFlow(("pdmR3DevHlp_SSMRegisterLegacy: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
535	return rc;
536	}
537
538
539	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerCreate} */
540	static DECLCALLBACK(int) pdmR3DevHlp_TimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
541	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer)
542	{
543	PDMDEV_ASSERT_DEVINS(pDevIns);
544	PVM pVM = pDevIns->Internal.s.pVMR3;
545	VM_ASSERT_EMT(pVM);
546	LogFlow(("pdmR3DevHlp_TimerCreate: caller='%s'/%d: enmClock=%d pfnCallback=%p pvUser=%p fFlags=%#x pszDesc=%p:{%s} phTimer=%p\n",
547	pDevIns->pReg->szName, pDevIns->iInstance, enmClock, pfnCallback, pvUser, fFlags, pszDesc, pszDesc, phTimer));
548
549	/* Mangle the timer name if there are more than one instance of this device. */
550	char szName[32];
551	AssertReturn(strlen(pszDesc) < sizeof(szName) - 3, VERR_INVALID_NAME);
552	if (pDevIns->iInstance > 0)
553	{
554	RTStrPrintf(szName, sizeof(szName), "%s[%u]", pszDesc, pDevIns->iInstance);
555	pszDesc = szName;
556	}
557
558	/* Clear the ring-0 flag if the device isn't configured for ring-0. */
559	if (fFlags & TMTIMER_FLAGS_RING0)
560	{
561	Assert(pDevIns->Internal.s.pDevR3->pReg->fFlags & PDM_DEVREG_FLAGS_R0);
562	if (!(pDevIns->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_R0_ENABLED))
563	fFlags &= ~TMTIMER_FLAGS_RING0;
564	}
565	else
566	Assert(fFlags & TMTIMER_FLAGS_NO_RING0 /* just to make sure all devices has been considered */);
567
568	int rc = TMR3TimerCreateDevice(pVM, pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
569
570	LogFlow(("pdmR3DevHlp_TimerCreate: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
571	return rc;
572	}
573
574
575	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerFromMicro} */
576	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
577	{
578	PDMDEV_ASSERT_DEVINS(pDevIns);
579	return TMTimerFromMicro(pDevIns->Internal.s.pVMR3, hTimer, cMicroSecs);
580	}
581
582
583	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerFromMilli} */
584	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
585	{
586	PDMDEV_ASSERT_DEVINS(pDevIns);
587	return TMTimerFromMilli(pDevIns->Internal.s.pVMR3, hTimer, cMilliSecs);
588	}
589
590
591	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerFromNano} */
592	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
593	{
594	PDMDEV_ASSERT_DEVINS(pDevIns);
595	return TMTimerFromNano(pDevIns->Internal.s.pVMR3, hTimer, cNanoSecs);
596	}
597
598	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerGet} */
599	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
600	{
601	PDMDEV_ASSERT_DEVINS(pDevIns);
602	return TMTimerGet(pDevIns->Internal.s.pVMR3, hTimer);
603	}
604
605
606	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerGetFreq} */
607	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
608	{
609	PDMDEV_ASSERT_DEVINS(pDevIns);
610	return TMTimerGetFreq(pDevIns->Internal.s.pVMR3, hTimer);
611	}
612
613
614	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerGetNano} */
615	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
616	{
617	PDMDEV_ASSERT_DEVINS(pDevIns);
618	return TMTimerGetNano(pDevIns->Internal.s.pVMR3, hTimer);
619	}
620
621
622	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerIsActive} */
623	static DECLCALLBACK(bool) pdmR3DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
624	{
625	PDMDEV_ASSERT_DEVINS(pDevIns);
626	return TMTimerIsActive(pDevIns->Internal.s.pVMR3, hTimer);
627	}
628
629
630	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerIsLockOwner} */
631	static DECLCALLBACK(bool) pdmR3DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
632	{
633	PDMDEV_ASSERT_DEVINS(pDevIns);
634	return TMTimerIsLockOwner(pDevIns->Internal.s.pVMR3, hTimer);
635	}
636
637
638	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerLockClock} */
639	static DECLCALLBACK(VBOXSTRICTRC) pdmR3DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
640	{
641	PDMDEV_ASSERT_DEVINS(pDevIns);
642	return TMTimerLock(pDevIns->Internal.s.pVMR3, hTimer, rcBusy);
643	}
644
645
646	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerLockClock2} */
647	static DECLCALLBACK(VBOXSTRICTRC) pdmR3DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
648	PPDMCRITSECT pCritSect, int rcBusy)
649	{
650	PDMDEV_ASSERT_DEVINS(pDevIns);
651	PVM const pVM = pDevIns->Internal.s.pVMR3;
652	VBOXSTRICTRC rc = TMTimerLock(pVM, hTimer, rcBusy);
653	if (rc == VINF_SUCCESS)
654	{
655	rc = PDMCritSectEnter(pVM, pCritSect, rcBusy);
656	if (rc == VINF_SUCCESS)
657	return rc;
658	AssertRC(VBOXSTRICTRC_VAL(rc));
659	TMTimerUnlock(pVM, hTimer);
660	}
661	else
662	AssertRC(VBOXSTRICTRC_VAL(rc));
663	return rc;
664	}
665
666
667	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSet} */
668	static DECLCALLBACK(int) pdmR3DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
669	{
670	PDMDEV_ASSERT_DEVINS(pDevIns);
671	return TMTimerSet(pDevIns->Internal.s.pVMR3, hTimer, uExpire);
672	}
673
674
675	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSetFrequencyHint} */
676	static DECLCALLBACK(int) pdmR3DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
677	{
678	PDMDEV_ASSERT_DEVINS(pDevIns);
679	return TMTimerSetFrequencyHint(pDevIns->Internal.s.pVMR3, hTimer, uHz);
680	}
681
682
683	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSetMicro} */
684	static DECLCALLBACK(int) pdmR3DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
685	{
686	PDMDEV_ASSERT_DEVINS(pDevIns);
687	return TMTimerSetMicro(pDevIns->Internal.s.pVMR3, hTimer, cMicrosToNext);
688	}
689
690
691	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSetMillies} */
692	static DECLCALLBACK(int) pdmR3DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
693	{
694	PDMDEV_ASSERT_DEVINS(pDevIns);
695	return TMTimerSetMillies(pDevIns->Internal.s.pVMR3, hTimer, cMilliesToNext);
696	}
697
698
699	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSetNano} */
700	static DECLCALLBACK(int) pdmR3DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
701	{
702	PDMDEV_ASSERT_DEVINS(pDevIns);
703	return TMTimerSetNano(pDevIns->Internal.s.pVMR3, hTimer, cNanosToNext);
704	}
705
706
707	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSetRelative} */
708	static DECLCALLBACK(int) pdmR3DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
709	{
710	PDMDEV_ASSERT_DEVINS(pDevIns);
711	return TMTimerSetRelative(pDevIns->Internal.s.pVMR3, hTimer, cTicksToNext, pu64Now);
712	}
713
714
715	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerStop} */
716	static DECLCALLBACK(int) pdmR3DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
717	{
718	PDMDEV_ASSERT_DEVINS(pDevIns);
719	return TMTimerStop(pDevIns->Internal.s.pVMR3, hTimer);
720	}
721
722
723	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerUnlockClock} */
724	static DECLCALLBACK(void) pdmR3DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
725	{
726	PDMDEV_ASSERT_DEVINS(pDevIns);
727	TMTimerUnlock(pDevIns->Internal.s.pVMR3, hTimer);
728	}
729
730
731	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerUnlockClock2} */
732	static DECLCALLBACK(void) pdmR3DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
733	{
734	PDMDEV_ASSERT_DEVINS(pDevIns);
735	PVM const pVM = pDevIns->Internal.s.pVMR3;
736	TMTimerUnlock(pVM, hTimer);
737	int rc = PDMCritSectLeave(pVM, pCritSect);
738	AssertRC(rc);
739	}
740
741
742	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSetCritSect} */
743	static DECLCALLBACK(int) pdmR3DevHlp_TimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
744	{
745	PDMDEV_ASSERT_DEVINS(pDevIns);
746	return TMR3TimerSetCritSect(pDevIns->Internal.s.pVMR3, hTimer, pCritSect);
747	}
748
749
750	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerSave} */
751	static DECLCALLBACK(int) pdmR3DevHlp_TimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
752	{
753	PDMDEV_ASSERT_DEVINS(pDevIns);
754	return TMR3TimerSave(pDevIns->Internal.s.pVMR3, hTimer, pSSM);
755	}
756
757
758	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerLoad} */
759	static DECLCALLBACK(int) pdmR3DevHlp_TimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
760	{
761	PDMDEV_ASSERT_DEVINS(pDevIns);
762	return TMR3TimerLoad(pDevIns->Internal.s.pVMR3, hTimer, pSSM);
763	}
764
765
766	/** @interface_method_impl{PDMDEVHLPR3,pfnTimerDestroy} */
767	static DECLCALLBACK(int) pdmR3DevHlp_TimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
768	{
769	PDMDEV_ASSERT_DEVINS(pDevIns);
770	return TMR3TimerDestroy(pDevIns->Internal.s.pVMR3, hTimer);
771	}
772
773
774	/** @interface_method_impl{PDMDEVHLPR3,pfnTMUtcNow} */
775	static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_TMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
776	{
777	PDMDEV_ASSERT_DEVINS(pDevIns);
778	LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: pTime=%p\n",
779	pDevIns->pReg->szName, pDevIns->iInstance, pTime));
780
781	pTime = TMR3UtcNow(pDevIns->Internal.s.pVMR3, pTime);
782
783	LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, RTTimeSpecGetNano(pTime)));
784	return pTime;
785	}
786
787
788	/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGet} */
789	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
790	{
791	PDMDEV_ASSERT_DEVINS(pDevIns);
792	LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d\n",
793	pDevIns->pReg->szName, pDevIns->iInstance));
794
795	uint64_t u64Time = TMVirtualSyncGet(pDevIns->Internal.s.pVMR3);
796
797	LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Time));
798	return u64Time;
799	}
800
801
802	/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetFreq} */
803	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
804	{
805	PDMDEV_ASSERT_DEVINS(pDevIns);
806	LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d\n",
807	pDevIns->pReg->szName, pDevIns->iInstance));
808
809	uint64_t u64Freq = TMVirtualGetFreq(pDevIns->Internal.s.pVMR3);
810
811	LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Freq));
812	return u64Freq;
813	}
814
815
816	/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetNano} */
817	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
818	{
819	PDMDEV_ASSERT_DEVINS(pDevIns);
820	LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d\n",
821	pDevIns->pReg->szName, pDevIns->iInstance));
822
823	uint64_t u64Time = TMVirtualGet(pDevIns->Internal.s.pVMR3);
824	uint64_t u64Nano = TMVirtualToNano(pDevIns->Internal.s.pVMR3, u64Time);
825
826	LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Nano));
827	return u64Nano;
828	}
829
830
831	/** @interface_method_impl{PDMDEVHLPR3,pfnTMCpuTicksPerSecond} */
832	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMCpuTicksPerSecond(PPDMDEVINS pDevIns)
833	{
834	PDMDEV_ASSERT_DEVINS(pDevIns);
835	LogFlow(("pdmR3DevHlp_TMCpuTicksPerSecond: caller='%s'/%d\n",
836	pDevIns->pReg->szName, pDevIns->iInstance));
837
838	uint64_t u64CpuTicksPerSec = TMCpuTicksPerSecond(pDevIns->Internal.s.pVMR3);
839
840	LogFlow(("pdmR3DevHlp_TMCpuTicksPerSecond: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64CpuTicksPerSec));
841	return u64CpuTicksPerSec;
842	}
843
844
845	/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
846	static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_GetSupDrvSession(PPDMDEVINS pDevIns)
847	{
848	PDMDEV_ASSERT_DEVINS(pDevIns);
849	LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d\n",
850	pDevIns->pReg->szName, pDevIns->iInstance));
851
852	PSUPDRVSESSION pSession = pDevIns->Internal.s.pVMR3->pSession;
853
854	LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d: returns %#p\n", pDevIns->pReg->szName, pDevIns->iInstance, pSession));
855	return pSession;
856	}
857
858
859	/** @interface_method_impl{PDMDEVHLPR3,pfnQueryGenericUserObject} */
860	static DECLCALLBACK(void *) pdmR3DevHlp_QueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
861	{
862	PDMDEV_ASSERT_DEVINS(pDevIns);
863	LogFlow(("pdmR3DevHlp_QueryGenericUserObject: caller='%s'/%d: pUuid=%p:%RTuuid\n",
864	pDevIns->pReg->szName, pDevIns->iInstance, pUuid, pUuid));
865
866	#if defined(DEBUG_bird) \|\| defined(DEBUG_ramshankar) \|\| defined(DEBUG_sunlover) \|\| defined(DEBUG_michael) \|\| defined(DEBUG_andy)
867	AssertMsgFailed(("'%s' wants %RTuuid - external only interface!\n", pDevIns->pReg->szName, pUuid));
868	#endif
869
870	void *pvRet;
871	PUVM pUVM = pDevIns->Internal.s.pVMR3->pUVM;
872	if (pUVM->pVmm2UserMethods->pfnQueryGenericObject)
873	pvRet = pUVM->pVmm2UserMethods->pfnQueryGenericObject(pUVM->pVmm2UserMethods, pUVM, pUuid);
874	else
875	pvRet = NULL;
876
877	LogRel(("pdmR3DevHlp_QueryGenericUserObject: caller='%s'/%d: returns %#p for %RTuuid\n",
878	pDevIns->pReg->szName, pDevIns->iInstance, pvRet, pUuid));
879	return pvRet;
880	}
881
882
883	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalTypeRegister} */
884	static DECLCALLBACK(int) pdmR3DevHlp_PGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
885	PFNPGMPHYSHANDLER pfnHandler, const char *pszDesc,
886	PPGMPHYSHANDLERTYPE phType)
887	{
888	PDMDEV_ASSERT_DEVINS(pDevIns);
889	PVM pVM = pDevIns->Internal.s.pVMR3;
890	LogFlow(("pdmR3DevHlp_PGMHandlerPhysicalTypeRegister: caller='%s'/%d: enmKind=%d pfnHandler=%p pszDesc=%p:{%s} phType=%p\n",
891	pDevIns->pReg->szName, pDevIns->iInstance, enmKind, pfnHandler, pszDesc, pszDesc, phType));
892
893	int rc = PGMR3HandlerPhysicalTypeRegister(pVM, enmKind,
894	pDevIns->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_R0_ENABLED
895	? PGMPHYSHANDLER_F_R0_DEVINS_IDX : 0,
896	pfnHandler, pszDesc, phType);
897
898	Log(("pdmR3DevHlp_PGMHandlerPhysicalTypeRegister: caller='%s'/%d: returns %Rrc\n",
899	pDevIns->pReg->szName, pDevIns->iInstance, rc));
900	return rc;
901	}
902
903
904	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalRegister} */
905	static DECLCALLBACK(int) pdmR3DevHlp_PGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
906	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc)
907	{
908	PDMDEV_ASSERT_DEVINS(pDevIns);
909	PVM pVM = pDevIns->Internal.s.pVMR3;
910	LogFlow(("pdmR3DevHlp_PGMHandlerPhysicalRegister: caller='%s'/%d: GCPhys=%RGp GCPhysLast=%RGp hType=%u pszDesc=%p:{%s}\n",
911	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, GCPhysLast, hType, pszDesc, pszDesc));
912
913	int rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType,
914	pDevIns->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_R0_ENABLED
915	? pDevIns->Internal.s.idxR0Device : (uintptr_t)pDevIns,
916	pszDesc);
917
918	Log(("pdmR3DevHlp_PGMHandlerPhysicalRegister: caller='%s'/%d: returns %Rrc\n",
919	pDevIns->pReg->szName, pDevIns->iInstance, rc));
920	return rc;
921	}
922
923
924	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalDeregister} */
925	static DECLCALLBACK(int) pdmR3DevHlp_PGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
926	{
927	PDMDEV_ASSERT_DEVINS(pDevIns);
928	PVM pVM = pDevIns->Internal.s.pVMR3;
929	LogFlow(("pdmR3DevHlp_PGMHandlerPhysicalDeregister: caller='%s'/%d: GCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
930
931	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
932
933	Log(("pdmR3DevHlp_PGMHandlerPhysicalDeregister: caller='%s'/%d: returns %Rrc\n",
934	pDevIns->pReg->szName, pDevIns->iInstance, rc));
935	return rc;
936	}
937
938
939	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalPageTempOff} */
940	static DECLCALLBACK(int) pdmR3DevHlp_PGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
941	{
942	PDMDEV_ASSERT_DEVINS(pDevIns);
943	PVM pVM = pDevIns->Internal.s.pVMR3;
944	LogFlow(("pdmR3DevHlp_PGMHandlerPhysicalPageTempOff: caller='%s'/%d: GCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
945
946	int rc = PGMHandlerPhysicalPageTempOff(pVM, GCPhys, GCPhysPage);
947
948	Log(("pdmR3DevHlp_PGMHandlerPhysicalPageTempOff: caller='%s'/%d: returns %Rrc\n",
949	pDevIns->pReg->szName, pDevIns->iInstance, rc));
950	return rc;
951	}
952
953
954	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalReset} */
955	static DECLCALLBACK(int) pdmR3DevHlp_PGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
956	{
957	PDMDEV_ASSERT_DEVINS(pDevIns);
958	PVM pVM = pDevIns->Internal.s.pVMR3;
959	LogFlow(("pdmR3DevHlp_PGMHandlerPhysicalReset: caller='%s'/%d: GCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
960
961	int rc = PGMHandlerPhysicalReset(pVM, GCPhys);
962
963	Log(("pdmR3DevHlp_PGMHandlerPhysicalReset: caller='%s'/%d: returns %Rrc\n",
964	pDevIns->pReg->szName, pDevIns->iInstance, rc));
965	return rc;
966	}
967
968
969	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */
970	static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
971	{
972	RT_NOREF(fFlags);
973
974	PDMDEV_ASSERT_DEVINS(pDevIns);
975	PVM pVM = pDevIns->Internal.s.pVMR3;
976	LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
977	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
978
979	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
980	if (!VM_IS_EMT(pVM))
981	{
982	char szNames[128];
983	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
984	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
985	}
986	#endif
987
988	VBOXSTRICTRC rcStrict;
989	if (VM_IS_EMT(pVM))
990	rcStrict = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
991	else
992	rcStrict = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
993	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
994
995	Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
996	return VBOXSTRICTRC_VAL(rcStrict);
997	}
998
999
1000	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */
1001	static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
1002	{
1003	RT_NOREF(fFlags);
1004
1005	PDMDEV_ASSERT_DEVINS(pDevIns);
1006	PVM pVM = pDevIns->Internal.s.pVMR3;
1007	LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
1008	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
1009
1010	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1011	if (!VM_IS_EMT(pVM))
1012	{
1013	char szNames[128];
1014	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
1015	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
1016	}
1017	#endif
1018
1019	VBOXSTRICTRC rcStrict;
1020	if (VM_IS_EMT(pVM))
1021	rcStrict = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
1022	else
1023	rcStrict = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
1024	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
1025
1026	Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
1027	return VBOXSTRICTRC_VAL(rcStrict);
1028	}
1029
1030
1031	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */
1032	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
1033	{
1034	PDMDEV_ASSERT_DEVINS(pDevIns);
1035	PVM pVM = pDevIns->Internal.s.pVMR3;
1036	LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
1037	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
1038	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1039
1040	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1041	if (!VM_IS_EMT(pVM))
1042	{
1043	char szNames[128];
1044	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
1045	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
1046	}
1047	#endif
1048
1049	int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock);
1050
1051	Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1052	return rc;
1053	}
1054
1055
1056	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */
1057	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)
1058	{
1059	PDMDEV_ASSERT_DEVINS(pDevIns);
1060	PVM pVM = pDevIns->Internal.s.pVMR3;
1061	LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
1062	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
1063	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1064
1065	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1066	if (!VM_IS_EMT(pVM))
1067	{
1068	char szNames[128];
1069	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
1070	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
1071	}
1072	#endif
1073
1074	int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock);
1075
1076	Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1077	return rc;
1078	}
1079
1080
1081	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */
1082	static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
1083	{
1084	PDMDEV_ASSERT_DEVINS(pDevIns);
1085	PVM pVM = pDevIns->Internal.s.pVMR3;
1086	LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n",
1087	pDevIns->pReg->szName, pDevIns->iInstance, pLock));
1088
1089	PGMPhysReleasePageMappingLock(pVM, pLock);
1090
1091	Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1092	}
1093
1094
1095	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysBulkGCPhys2CCPtr} */
1096	static DECLCALLBACK(int) pdmR3DevHlp_PhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1097	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
1098	{
1099	PDMDEV_ASSERT_DEVINS(pDevIns);
1100	PVM pVM = pDevIns->Internal.s.pVMR3;
1101	LogFlow(("pdmR3DevHlp_PhysBulkGCPhys2CCPtr: caller='%s'/%d: cPages=%#x paGCPhysPages=%p (%RGp,..) fFlags=%#x papvPages=%p paLocks=%p\n",
1102	pDevIns->pReg->szName, pDevIns->iInstance, cPages, paGCPhysPages, paGCPhysPages[0], fFlags, papvPages, paLocks));
1103	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1104	AssertReturn(cPages > 0, VERR_INVALID_PARAMETER);
1105
1106	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1107	if (!VM_IS_EMT(pVM))
1108	{
1109	char szNames[128];
1110	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
1111	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
1112	}
1113	#endif
1114
1115	int rc = PGMR3PhysBulkGCPhys2CCPtrExternal(pVM, cPages, paGCPhysPages, papvPages, paLocks);
1116
1117	Log(("pdmR3DevHlp_PhysBulkGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1118	return rc;
1119	}
1120
1121
1122	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysBulkGCPhys2CCPtrReadOnly} */
1123	static DECLCALLBACK(int) pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1124	uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks)
1125	{
1126	PDMDEV_ASSERT_DEVINS(pDevIns);
1127	PVM pVM = pDevIns->Internal.s.pVMR3;
1128	LogFlow(("pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly: caller='%s'/%d: cPages=%#x paGCPhysPages=%p (%RGp,...) fFlags=%#x papvPages=%p paLocks=%p\n",
1129	pDevIns->pReg->szName, pDevIns->iInstance, cPages, paGCPhysPages, paGCPhysPages[0], fFlags, papvPages, paLocks));
1130	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1131	AssertReturn(cPages > 0, VERR_INVALID_PARAMETER);
1132
1133	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1134	if (!VM_IS_EMT(pVM))
1135	{
1136	char szNames[128];
1137	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
1138	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
1139	}
1140	#endif
1141
1142	int rc = PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(pVM, cPages, paGCPhysPages, papvPages, paLocks);
1143
1144	Log(("pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1145	return rc;
1146	}
1147
1148
1149	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysBulkReleasePageMappingLocks} */
1150	static DECLCALLBACK(void) pdmR3DevHlp_PhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
1151	{
1152	PDMDEV_ASSERT_DEVINS(pDevIns);
1153	PVM pVM = pDevIns->Internal.s.pVMR3;
1154	LogFlow(("pdmR3DevHlp_PhysBulkReleasePageMappingLocks: caller='%s'/%d: cPages=%#x paLocks=%p\n",
1155	pDevIns->pReg->szName, pDevIns->iInstance, cPages, paLocks));
1156	Assert(cPages > 0);
1157
1158	PGMPhysBulkReleasePageMappingLocks(pVM, cPages, paLocks);
1159
1160	Log(("pdmR3DevHlp_PhysBulkReleasePageMappingLocks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1161	}
1162
1163
1164	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysIsGCPhysNormal} */
1165	static DECLCALLBACK(bool) pdmR3DevHlp_PhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1166	{
1167	PDMDEV_ASSERT_DEVINS(pDevIns);
1168	LogFlow(("pdmR3DevHlp_PhysIsGCPhysNormal: caller='%s'/%d: GCPhys=%RGp\n",
1169	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
1170
1171	bool fNormal = PGMPhysIsGCPhysNormal(pDevIns->Internal.s.pVMR3, GCPhys);
1172
1173	Log(("pdmR3DevHlp_PhysIsGCPhysNormal: caller='%s'/%d: returns %RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fNormal));
1174	return fNormal;
1175	}
1176
1177
1178	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysChangeMemBalloon} */
1179	static DECLCALLBACK(int) pdmR3DevHlp_PhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1180	{
1181	PDMDEV_ASSERT_DEVINS(pDevIns);
1182	LogFlow(("pdmR3DevHlp_PhysChangeMemBalloon: caller='%s'/%d: fInflate=%RTbool cPages=%u paPhysPage=%p\n",
1183	pDevIns->pReg->szName, pDevIns->iInstance, fInflate, cPages, paPhysPage));
1184
1185	int rc = PGMR3PhysChangeMemBalloon(pDevIns->Internal.s.pVMR3, fInflate, cPages, paPhysPage);
1186
1187	Log(("pdmR3DevHlp_PhysChangeMemBalloon: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1188	return rc;
1189	}
1190
1191
1192	/** @interface_method_impl{PDMDEVHLPR3,pfnCpuGetGuestArch} */
1193	static DECLCALLBACK(CPUMARCH) pdmR3DevHlp_CpuGetGuestArch(PPDMDEVINS pDevIns)
1194	{
1195	PDMDEV_ASSERT_DEVINS(pDevIns);
1196	PVM pVM = pDevIns->Internal.s.pVMR3;
1197	LogFlow(("pdmR3DevHlp_CpuGetGuestArch: caller='%s'/%d\n",
1198	pDevIns->pReg->szName, pDevIns->iInstance));
1199
1200	CPUMARCH enmArch = CPUMGetGuestArch(pVM);
1201
1202	Log(("pdmR3DevHlp_CpuGetGuestArch: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, enmArch));
1203	return enmArch;
1204	}
1205
1206
1207	/** @interface_method_impl{PDMDEVHLPR3,pfnCpuGetGuestMicroarch} */
1208	static DECLCALLBACK(CPUMMICROARCH) pdmR3DevHlp_CpuGetGuestMicroarch(PPDMDEVINS pDevIns)
1209	{
1210	PDMDEV_ASSERT_DEVINS(pDevIns);
1211	PVM pVM = pDevIns->Internal.s.pVMR3;
1212	LogFlow(("pdmR3DevHlp_CpuGetGuestMicroarch: caller='%s'/%d\n",
1213	pDevIns->pReg->szName, pDevIns->iInstance));
1214
1215	CPUMMICROARCH enmMicroarch = CPUMGetGuestMicroarch(pVM);
1216
1217	Log(("pdmR3DevHlp_CpuGetGuestMicroarch: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, enmMicroarch));
1218	return enmMicroarch;
1219	}
1220
1221
1222	/** @interface_method_impl{PDMDEVHLPR3,pfnCpuGetGuestAddrWidths} */
1223	static DECLCALLBACK(void) pdmR3DevHlp_CpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
1224	uint8_t *pcLinearAddrWidth)
1225	{
1226	PDMDEV_ASSERT_DEVINS(pDevIns);
1227	PVM pVM = pDevIns->Internal.s.pVMR3;
1228	LogFlow(("pdmR3DevHlp_CpuGetGuestAddrWidths: caller='%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
1229	AssertPtrReturnVoid(pcPhysAddrWidth);
1230	AssertPtrReturnVoid(pcLinearAddrWidth);
1231
1232	CPUMGetGuestAddrWidths(pVM, pcPhysAddrWidth, pcLinearAddrWidth);
1233
1234	Log(("pdmR3DevHlp_CpuGetGuestAddrWidths: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1235	}
1236
1237
1238	/** @interface_method_impl{PDMDEVHLPR3,pfnCpuGetGuestScalableBusFrequency} */
1239	static DECLCALLBACK(uint64_t) pdmR3DevHlp_CpuGetGuestScalableBusFrequency(PPDMDEVINS pDevIns)
1240	{
1241	PDMDEV_ASSERT_DEVINS(pDevIns);
1242	LogFlow(("pdmR3DevHlp_CpuGetGuestScalableBusFrequency: caller='%s'/%d\n",
1243	pDevIns->pReg->szName, pDevIns->iInstance));
1244
1245	#if defined(VBOX_VMM_TARGET_ARMV8)
1246	uint64_t u64Fsb = 0;
1247	AssertReleaseFailed();
1248	RT_NOREF(pDevIns);
1249	#else
1250	uint64_t u64Fsb = CPUMGetGuestScalableBusFrequency(pDevIns->Internal.s.pVMR3);
1251	#endif
1252
1253	Log(("pdmR3DevHlp_CpuGetGuestScalableBusFrequency: caller='%s'/%d: returns %#RX64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Fsb));
1254	return u64Fsb;
1255	}
1256
1257
1258	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */
1259	static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
1260	{
1261	PDMDEV_ASSERT_DEVINS(pDevIns);
1262	PVM pVM = pDevIns->Internal.s.pVMR3;
1263	VM_ASSERT_EMT(pVM);
1264	LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n",
1265	pDevIns->pReg->szName, pDevIns->iInstance, pvDst, GCVirtSrc, cb));
1266
1267	PVMCPU pVCpu = VMMGetCpu(pVM);
1268	if (!pVCpu)
1269	return VERR_ACCESS_DENIED;
1270	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1271	/** @todo SMP. */
1272	#endif
1273
1274	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb);
1275
1276	LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1277
1278	return rc;
1279	}
1280
1281
1282	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */
1283	static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
1284	{
1285	PDMDEV_ASSERT_DEVINS(pDevIns);
1286	PVM pVM = pDevIns->Internal.s.pVMR3;
1287	VM_ASSERT_EMT(pVM);
1288	LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n",
1289	pDevIns->pReg->szName, pDevIns->iInstance, GCVirtDst, pvSrc, cb));
1290
1291	PVMCPU pVCpu = VMMGetCpu(pVM);
1292	if (!pVCpu)
1293	return VERR_ACCESS_DENIED;
1294	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1295	/** @todo SMP. */
1296	#endif
1297
1298	int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb);
1299
1300	LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1301
1302	return rc;
1303	}
1304
1305
1306	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPtr2GCPhys} */
1307	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
1308	{
1309	PDMDEV_ASSERT_DEVINS(pDevIns);
1310	PVM pVM = pDevIns->Internal.s.pVMR3;
1311	VM_ASSERT_EMT(pVM);
1312	LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n",
1313	pDevIns->pReg->szName, pDevIns->iInstance, GCPtr, pGCPhys));
1314
1315	PVMCPU pVCpu = VMMGetCpu(pVM);
1316	if (!pVCpu)
1317	return VERR_ACCESS_DENIED;
1318	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1319	/** @todo SMP. */
1320	#endif
1321
1322	int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys);
1323
1324	LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc pGCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, pGCPhys));
1325
1326	return rc;
1327	}
1328
1329
1330	/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAlloc} */
1331	static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
1332	{
1333	PDMDEV_ASSERT_DEVINS(pDevIns);
1334	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1335
1336	void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1337
1338	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1339	return pv;
1340	}
1341
1342
1343	/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAllocZ} */
1344	static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
1345	{
1346	PDMDEV_ASSERT_DEVINS(pDevIns);
1347	LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1348
1349	void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1350
1351	LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1352	return pv;
1353	}
1354
1355
1356	/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAPrintfV} */
1357	static DECLCALLBACK(char ) pdmR3DevHlp_MMHeapAPrintfV(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va)
1358	{
1359	PDMDEV_ASSERT_DEVINS(pDevIns);
1360	LogFlow(("pdmR3DevHlp_MMHeapAPrintfV: caller='%s'/%d: enmTag=%u pszFormat=%p:{%s}\n",
1361	pDevIns->pReg->szName, pDevIns->iInstance, enmTag, pszFormat, pszFormat));
1362
1363	char *psz = MMR3HeapAPrintfV(pDevIns->Internal.s.pVMR3, enmTag, pszFormat, va);
1364
1365	LogFlow(("pdmR3DevHlp_MMHeapAPrintfV: caller='%s'/%d: returns %p:{%s}\n",
1366	pDevIns->pReg->szName, pDevIns->iInstance, psz, psz));
1367	return psz;
1368	}
1369
1370
1371	/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapFree} */
1372	static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv)
1373	{
1374	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1375	LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1376
1377	MMR3HeapFree(pv);
1378
1379	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1380	}
1381
1382
1383	/** @interface_method_impl{PDMDEVHLPR3,pfnMMPhysGetRamSize} */
1384	static DECLCALLBACK(uint64_t) pdmR3DevHlp_MMPhysGetRamSize(PPDMDEVINS pDevIns)
1385	{
1386	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1387	LogFlow(("pdmR3DevHlp_MMPhysGetRamSize: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1388
1389	uint64_t cb = MMR3PhysGetRamSize(pDevIns->Internal.s.pVMR3);
1390
1391	LogFlow(("pdmR3DevHlp_MMPhysGetRamSize: caller='%s'/%d: returns %RU64\n",
1392	pDevIns->pReg->szName, pDevIns->iInstance, cb));
1393	return cb;
1394	}
1395
1396
1397	/** @interface_method_impl{PDMDEVHLPR3,pfnMMPhysGetRamSizeBelow4GB} */
1398	static DECLCALLBACK(uint32_t) pdmR3DevHlp_MMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
1399	{
1400	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1401	LogFlow(("pdmR3DevHlp_MMPhysGetRamSizeBelow4GB: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1402
1403	uint32_t cb = MMR3PhysGetRamSizeBelow4GB(pDevIns->Internal.s.pVMR3);
1404
1405	LogFlow(("pdmR3DevHlp_MMPhysGetRamSizeBelow4GB: caller='%s'/%d: returns %RU32\n",
1406	pDevIns->pReg->szName, pDevIns->iInstance, cb));
1407	return cb;
1408	}
1409
1410
1411	/** @interface_method_impl{PDMDEVHLPR3,pfnMMPhysGetRamSizeAbove4GB} */
1412	static DECLCALLBACK(uint64_t) pdmR3DevHlp_MMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
1413	{
1414	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1415	LogFlow(("pdmR3DevHlp_MMPhysGetRamSizeAbove4GB: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1416
1417	uint64_t cb = MMR3PhysGetRamSizeAbove4GB(pDevIns->Internal.s.pVMR3);
1418
1419	LogFlow(("pdmR3DevHlp_MMPhysGetRamSizeAbove4GB: caller='%s'/%d: returns %RU64\n",
1420	pDevIns->pReg->szName, pDevIns->iInstance, cb));
1421	return cb;
1422	}
1423
1424
1425	/** @interface_method_impl{PDMDEVHLPR3,pfnVMState} */
1426	static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns)
1427	{
1428	PDMDEV_ASSERT_DEVINS(pDevIns);
1429
1430	VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
1431
1432	LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pReg->szName, pDevIns->iInstance,
1433	enmVMState, VMR3GetStateName(enmVMState)));
1434	return enmVMState;
1435	}
1436
1437
1438	/** @interface_method_impl{PDMDEVHLPR3,pfnVMTeleportedAndNotFullyResumedYet} */
1439	static DECLCALLBACK(bool) pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
1440	{
1441	PDMDEV_ASSERT_DEVINS(pDevIns);
1442
1443	bool fRc = VMR3TeleportedAndNotFullyResumedYet(pDevIns->Internal.s.pVMR3);
1444
1445	LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance,
1446	fRc));
1447	return fRc;
1448	}
1449
1450
1451	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetErrorV} */
1452	static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
1453	{
1454	PDMDEV_ASSERT_DEVINS(pDevIns);
1455	int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
1456	return rc;
1457	}
1458
1459
1460	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeErrorV} */
1461	static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char pszErrorId, const char pszFormat, va_list va)
1462	{
1463	PDMDEV_ASSERT_DEVINS(pDevIns);
1464	int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va);
1465	return rc;
1466	}
1467
1468
1469	/** @interface_method_impl{PDMDEVHLPR3,pfnVMWaitForDeviceReady} */
1470	static DECLCALLBACK(int) pdmR3DevHlp_VMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
1471	{
1472	PDMDEV_ASSERT_DEVINS(pDevIns);
1473	LogFlow(("pdmR3DevHlp_VMWaitForDeviceReady: caller='%s'/%d: idCpu=%u\n", pDevIns->pReg->szName, pDevIns->iInstance, idCpu));
1474
1475	int rc = VMR3WaitForDeviceReady(pDevIns->Internal.s.pVMR3, idCpu);
1476
1477	LogFlow(("pdmR3DevHlp_VMWaitForDeviceReady: caller='%s'/%d: returns %Rrc\n",
1478	pDevIns->pReg->szName, pDevIns->iInstance, rc));
1479	return rc;
1480	}
1481
1482
1483	/** @interface_method_impl{PDMDEVHLPR3,pfnVMNotifyCpuDeviceReady} */
1484	static DECLCALLBACK(int) pdmR3DevHlp_VMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
1485	{
1486	PDMDEV_ASSERT_DEVINS(pDevIns);
1487	LogFlow(("pdmR3DevHlp_VMNotifyCpuDeviceReady: caller='%s'/%d: idCpu=%u\n", pDevIns->pReg->szName, pDevIns->iInstance, idCpu));
1488
1489	int rc = VMR3NotifyCpuDeviceReady(pDevIns->Internal.s.pVMR3, idCpu);
1490
1491	LogFlow(("pdmR3DevHlp_VMNotifyCpuDeviceReady: caller='%s'/%d: returns %Rrc\n",
1492	pDevIns->pReg->szName, pDevIns->iInstance, rc));
1493	return rc;
1494	}
1495
1496
1497	/** @interface_method_impl{PDMDEVHLPR3,pfnVMReqCallNoWaitV} */
1498	static DECLCALLBACK(int) pdmR3DevHlp_VMReqCallNoWaitV(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args)
1499	{
1500	PDMDEV_ASSERT_DEVINS(pDevIns);
1501	LogFlow(("pdmR3DevHlp_VMReqCallNoWaitV: caller='%s'/%d: idDstCpu=%u pfnFunction=%p cArgs=%u\n",
1502	pDevIns->pReg->szName, pDevIns->iInstance, idDstCpu, pfnFunction, cArgs));
1503
1504	int rc = VMR3ReqCallVU(pDevIns->Internal.s.pVMR3->pUVM, idDstCpu, NULL, 0, VMREQFLAGS_VBOX_STATUS \| VMREQFLAGS_NO_WAIT,
1505	pfnFunction, cArgs, Args);
1506
1507	LogFlow(("pdmR3DevHlp_VMReqCallNoWaitV: caller='%s'/%d: returns %Rrc\n",
1508	pDevIns->pReg->szName, pDevIns->iInstance, rc));
1509	return rc;
1510	}
1511
1512
1513	/** @interface_method_impl{PDMDEVHLPR3,pfnVMReqPriorityCallWaitV} */
1514	static DECLCALLBACK(int) pdmR3DevHlp_VMReqPriorityCallWaitV(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args)
1515	{
1516	PDMDEV_ASSERT_DEVINS(pDevIns);
1517	LogFlow(("pdmR3DevHlp_VMReqCallNoWaitV: caller='%s'/%d: idDstCpu=%u pfnFunction=%p cArgs=%u\n",
1518	pDevIns->pReg->szName, pDevIns->iInstance, idDstCpu, pfnFunction, cArgs));
1519
1520	PVMREQ pReq;
1521	int rc = VMR3ReqCallVU(pDevIns->Internal.s.pVMR3->pUVM, idDstCpu, &pReq, RT_INDEFINITE_WAIT,
1522	VMREQFLAGS_VBOX_STATUS \| VMREQFLAGS_PRIORITY, pfnFunction, cArgs, Args);
1523	if (RT_SUCCESS(rc))
1524	rc = pReq->iStatus;
1525	VMR3ReqFree(pReq);
1526
1527	LogFlow(("pdmR3DevHlp_VMReqCallNoWaitV: caller='%s'/%d: returns %Rrc\n",
1528	pDevIns->pReg->szName, pDevIns->iInstance, rc));
1529	return rc;
1530	}
1531
1532
1533	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFStopV} */
1534	static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction, const char *pszFormat, va_list args)
1535	{
1536	PDMDEV_ASSERT_DEVINS(pDevIns);
1537	#ifdef LOG_ENABLED
1538	va_list va2;
1539	va_copy(va2, args);
1540	LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n",
1541	pDevIns->pReg->szName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2));
1542	va_end(va2);
1543	#endif
1544
1545	PVM pVM = pDevIns->Internal.s.pVMR3;
1546	VM_ASSERT_EMT(pVM);
1547	int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args);
1548	if (rc == VERR_DBGF_NOT_ATTACHED)
1549	rc = VINF_SUCCESS;
1550
1551	LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1552	return rc;
1553	}
1554
1555
1556	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegister} */
1557	static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
1558	{
1559	PDMDEV_ASSERT_DEVINS(pDevIns);
1560	LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",
1561	pDevIns->pReg->szName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));
1562
1563	PVM pVM = pDevIns->Internal.s.pVMR3;
1564	VM_ASSERT_EMT(pVM);
1565	int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns);
1566
1567	LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1568	return rc;
1569	}
1570
1571
1572	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegisterArgv} */
1573	static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
1574	{
1575	PDMDEV_ASSERT_DEVINS(pDevIns);
1576	LogFlow(("pdmR3DevHlp_DBGFInfoRegisterArgv: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",
1577	pDevIns->pReg->szName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));
1578
1579	PVM pVM = pDevIns->Internal.s.pVMR3;
1580	VM_ASSERT_EMT(pVM);
1581	int rc = DBGFR3InfoRegisterDeviceArgv(pVM, pszName, pszDesc, pfnHandler, pDevIns);
1582
1583	LogFlow(("pdmR3DevHlp_DBGFInfoRegisterArgv: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1584	return rc;
1585	}
1586
1587
1588	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFRegRegister} */
1589	static DECLCALLBACK(int) pdmR3DevHlp_DBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
1590	{
1591	PDMDEV_ASSERT_DEVINS(pDevIns);
1592	LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: paRegisters=%p\n",
1593	pDevIns->pReg->szName, pDevIns->iInstance, paRegisters));
1594
1595	PVM pVM = pDevIns->Internal.s.pVMR3;
1596	VM_ASSERT_EMT(pVM);
1597	int rc = DBGFR3RegRegisterDevice(pVM, paRegisters, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance);
1598
1599	LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1600	return rc;
1601	}
1602
1603
1604	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFTraceBuf} */
1605	static DECLCALLBACK(RTTRACEBUF) pdmR3DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1606	{
1607	PDMDEV_ASSERT_DEVINS(pDevIns);
1608	RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR3->hTraceBufR3;
1609	LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, hTraceBuf));
1610	return hTraceBuf;
1611	}
1612
1613
1614	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFReportBugCheck} */
1615	static DECLCALLBACK(VBOXSTRICTRC) pdmR3DevHlp_DBGFReportBugCheck(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
1616	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4)
1617	{
1618	PDMDEV_ASSERT_DEVINS(pDevIns);
1619	LogFlow(("pdmR3DevHlp_DBGFReportBugCheck: caller='%s'/%d: enmEvent=%u uBugCheck=%#x uP1=%#x uP2=%#x uP3=%#x uP4=%#x\n",
1620	pDevIns->pReg->szName, pDevIns->iInstance, enmEvent, uBugCheck, uP1, uP2, uP3, uP4));
1621
1622	PVM pVM = pDevIns->Internal.s.pVMR3;
1623	VM_ASSERT_EMT(pVM);
1624	VBOXSTRICTRC rcStrict = DBGFR3ReportBugCheck(pVM, VMMGetCpu(pVM), enmEvent, uBugCheck, uP1, uP2, uP3, uP4);
1625
1626	LogFlow(("pdmR3DevHlp_DBGFReportBugCheck: caller='%s'/%d: returns %Rrc\n",
1627	pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict)));
1628	return rcStrict;
1629	}
1630
1631
1632	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFCoreWrite} */
1633	static DECLCALLBACK(int) pdmR3DevHlp_DBGFCoreWrite(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile)
1634	{
1635	PDMDEV_ASSERT_DEVINS(pDevIns);
1636	LogFlow(("pdmR3DevHlp_DBGFCoreWrite: caller='%s'/%d: pszFilename=%p:{%s} fReplaceFile=%RTbool\n",
1637	pDevIns->pReg->szName, pDevIns->iInstance, pszFilename, pszFilename, fReplaceFile));
1638
1639	int rc = DBGFR3CoreWrite(pDevIns->Internal.s.pVMR3->pUVM, pszFilename, fReplaceFile);
1640
1641	LogFlow(("pdmR3DevHlp_DBGFCoreWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1642	return rc;
1643	}
1644
1645
1646	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoLogHlp} */
1647	static DECLCALLBACK(PCDBGFINFOHLP) pdmR3DevHlp_DBGFInfoLogHlp(PPDMDEVINS pDevIns)
1648	{
1649	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF(pDevIns);
1650	LogFlow(("pdmR3DevHlp_DBGFInfoLogHlp: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1651
1652	PCDBGFINFOHLP pHlp = DBGFR3InfoLogHlp();
1653
1654	LogFlow(("pdmR3DevHlp_DBGFInfoLogHlp: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pHlp));
1655	return pHlp;
1656	}
1657
1658
1659	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFRegNmQueryU64} */
1660	static DECLCALLBACK(int) pdmR3DevHlp_DBGFRegNmQueryU64(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64)
1661	{
1662	PDMDEV_ASSERT_DEVINS(pDevIns);
1663	LogFlow(("pdmR3DevHlp_DBGFRegNmQueryU64: caller='%s'/%d: idDefCpu=%u pszReg=%p:{%s} pu64=%p\n",
1664	pDevIns->pReg->szName, pDevIns->iInstance, idDefCpu, pszReg, pszReg, pu64));
1665
1666	int rc = DBGFR3RegNmQueryU64(pDevIns->Internal.s.pVMR3->pUVM, idDefCpu, pszReg, pu64);
1667
1668	LogFlow(("pdmR3DevHlp_DBGFRegNmQueryU64: caller='%s'/%d: returns %Rrc *pu64=%#RX64\n",
1669	pDevIns->pReg->szName, pDevIns->iInstance, rc, *pu64));
1670	return rc;
1671	}
1672
1673
1674	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFRegPrintfV} */
1675	static DECLCALLBACK(int) pdmR3DevHlp_DBGFRegPrintfV(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
1676	const char *pszFormat, va_list va)
1677	{
1678	PDMDEV_ASSERT_DEVINS(pDevIns);
1679	LogFlow(("pdmR3DevHlp_DBGFRegPrintfV: caller='%s'/%d: idCpu=%u pszBuf=%p cbBuf=%u pszFormat=%p:{%s}\n",
1680	pDevIns->pReg->szName, pDevIns->iInstance, idCpu, pszBuf, cbBuf, pszFormat, pszFormat));
1681
1682	int rc = DBGFR3RegPrintfV(pDevIns->Internal.s.pVMR3->pUVM, idCpu, pszBuf, cbBuf, pszFormat, va);
1683
1684	LogFlow(("pdmR3DevHlp_DBGFRegPrintfV: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1685	return rc;
1686	}
1687
1688
1689	/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegister} */
1690	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName,
1691	STAMUNIT enmUnit, const char *pszDesc)
1692	{
1693	PDMDEV_ASSERT_DEVINS(pDevIns);
1694	PVM pVM = pDevIns->Internal.s.pVMR3;
1695	VM_ASSERT_EMT(pVM);
1696
1697	int rc;
1698	if (*pszName == '/')
1699	rc = STAMR3Register(pVM, pvSample, enmType, STAMVISIBILITY_ALWAYS, pszName, enmUnit, pszDesc);
1700	/* Provide default device statistics prefix: */
1701	else if (pDevIns->pReg->cMaxInstances == 1)
1702	rc = STAMR3RegisterF(pVM, pvSample, enmType, STAMVISIBILITY_ALWAYS, enmUnit, pszDesc,
1703	"/Devices/%s/%s", pDevIns->pReg->szName, pszName);
1704	else
1705	rc = STAMR3RegisterF(pVM, pvSample, enmType, STAMVISIBILITY_ALWAYS, enmUnit, pszDesc,
1706	"/Devices/%s#%u/%s", pDevIns->pReg->szName, pDevIns->iInstance, pszName);
1707	AssertRC(rc);
1708	}
1709
1710
1711	/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterV} */
1712	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1713	STAMUNIT enmUnit, const char pszDesc, const char pszName, va_list args)
1714	{
1715	PDMDEV_ASSERT_DEVINS(pDevIns);
1716	PVM pVM = pDevIns->Internal.s.pVMR3;
1717	VM_ASSERT_EMT(pVM);
1718
1719	int rc;
1720	if (*pszName == '/')
1721	rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1722	else
1723	{
1724	/* Provide default device statistics prefix: */
1725	va_list vaCopy;
1726	va_copy(vaCopy, args);
1727	if (pDevIns->pReg->cMaxInstances == 1)
1728	rc = STAMR3RegisterF(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc,
1729	"/Devices/%s/%N", pDevIns->pReg->szName, pszName, &vaCopy);
1730	else
1731	rc = STAMR3RegisterF(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc,
1732	"/Devices/%s#%u/%N", pDevIns->pReg->szName, pDevIns->iInstance, pszName, &vaCopy);
1733	va_end(vaCopy);
1734	}
1735	AssertRC(rc);
1736	}
1737
1738
1739	/**
1740	* @interface_method_impl{PDMDEVHLPR3,pfnSTAMDeregisterByPrefix}
1741	*/
1742	static DECLCALLBACK(int) pdmR3DevHlp_STAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
1743	{
1744	PDMDEV_ASSERT_DEVINS(pDevIns);
1745	PVM pVM = pDevIns->Internal.s.pVMR3;
1746	VM_ASSERT_EMT(pVM);
1747
1748	int rc;
1749	if (*pszPrefix == '/')
1750	rc = STAMR3DeregisterByPrefix(pVM->pUVM, pszPrefix);
1751	else
1752	{
1753	char szQualifiedPrefix[1024];
1754	ssize_t cch;
1755	if (pDevIns->pReg->cMaxInstances == 1)
1756	cch = RTStrPrintf2(szQualifiedPrefix, sizeof(szQualifiedPrefix), "/Devices/%s/%s", pDevIns->pReg->szName, pszPrefix);
1757	else
1758	cch = RTStrPrintf2(szQualifiedPrefix, sizeof(szQualifiedPrefix), "/Devices/%s#%u/%s",
1759	pDevIns->pReg->szName, pDevIns->iInstance, pszPrefix);
1760	AssertReturn(cch > 0, VERR_OUT_OF_RANGE);
1761	rc = STAMR3DeregisterByPrefix(pVM->pUVM, szQualifiedPrefix);
1762	}
1763	AssertRC(rc);
1764	return rc;
1765	}
1766
1767
1768	/**
1769	* @interface_method_impl{PDMDEVHLPR3,pfnPCIRegister}
1770	*/
1771	static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
1772	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
1773	{
1774	PDMDEV_ASSERT_DEVINS(pDevIns);
1775	PVM pVM = pDevIns->Internal.s.pVMR3;
1776	VM_ASSERT_EMT(pVM);
1777	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: pPciDev=%p:{.config={%#.256Rhxs} fFlags=%#x uPciDevNo=%#x uPciFunNo=%#x pszName=%p:{%s}\n",
1778	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->abConfig, fFlags, uPciDevNo, uPciFunNo, pszName, pszName ? pszName : ""));
1779
1780	/*
1781	* Validate input.
1782	*/
1783	AssertLogRelMsgReturn(pDevIns->pReg->cMaxPciDevices > 0,
1784	("'%s'/%d: cMaxPciDevices is 0\n", pDevIns->pReg->szName, pDevIns->iInstance),
1785	VERR_WRONG_ORDER);
1786	AssertLogRelMsgReturn(RT_VALID_PTR(pPciDev),
1787	("'%s'/%d: Invalid pPciDev value: %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pPciDev),
1788	VERR_INVALID_POINTER);
1789	AssertLogRelMsgReturn(PDMPciDevGetVendorId(pPciDev),
1790	("'%s'/%d: Vendor ID is not set!\n", pDevIns->pReg->szName, pDevIns->iInstance),
1791	VERR_INVALID_POINTER);
1792	AssertLogRelMsgReturn( uPciDevNo < 32
1793	\|\| uPciDevNo == PDMPCIDEVREG_DEV_NO_FIRST_UNUSED
1794	\|\| uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV,
1795	("'%s'/%d: Invalid PCI device number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciDevNo),
1796	VERR_INVALID_PARAMETER);
1797	AssertLogRelMsgReturn( uPciFunNo < 8
1798	\|\| uPciFunNo == PDMPCIDEVREG_FUN_NO_FIRST_UNUSED,
1799	("'%s'/%d: Invalid PCI funcion number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciFunNo),
1800	VERR_INVALID_PARAMETER);
1801	AssertLogRelMsgReturn(!(fFlags & ~PDMPCIDEVREG_F_VALID_MASK),
1802	("'%s'/%d: Invalid flags: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, fFlags),
1803	VERR_INVALID_FLAGS);
1804	if (!pszName)
1805	pszName = pDevIns->pReg->szName;
1806	AssertLogRelReturn(RT_VALID_PTR(pszName), VERR_INVALID_POINTER);
1807	AssertLogRelReturn(!pPciDev->Int.s.fRegistered, VERR_PDM_NOT_PCI_DEVICE);
1808	AssertLogRelReturn(pPciDev == PDMDEV_GET_PPCIDEV(pDevIns, pPciDev->Int.s.idxSubDev), VERR_PDM_NOT_PCI_DEVICE);
1809	AssertLogRelReturn(pPciDev == PDMDEV_CALC_PPCIDEV(pDevIns, pPciDev->Int.s.idxSubDev), VERR_PDM_NOT_PCI_DEVICE);
1810	AssertMsgReturn(pPciDev->u32Magic == PDMPCIDEV_MAGIC, ("%#x\n", pPciDev->u32Magic), VERR_PDM_NOT_PCI_DEVICE);
1811
1812	/*
1813	* Check the registration order - must be following PDMDEVINSR3::apPciDevs.
1814	*/
1815	PPDMPCIDEV const pPrevPciDev = pPciDev->Int.s.idxSubDev == 0 ? NULL
1816	: PDMDEV_GET_PPCIDEV(pDevIns, pPciDev->Int.s.idxSubDev - 1);
1817	if (pPrevPciDev)
1818	{
1819	AssertLogRelReturn(pPrevPciDev->u32Magic == PDMPCIDEV_MAGIC, VERR_INVALID_MAGIC);
1820	AssertLogRelReturn(pPrevPciDev->Int.s.fRegistered, VERR_WRONG_ORDER);
1821	}
1822
1823	/*
1824	* Resolve the PCI configuration node for the device. The default (zero'th)
1825	* is the same as the PDM device, the rest are "PciCfg1..255" CFGM sub-nodes.
1826	*/
1827	PCFGMNODE pCfg = pDevIns->Internal.s.pCfgHandle;
1828	if (pPciDev->Int.s.idxSubDev > 0)
1829	pCfg = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "PciCfg%u", pPciDev->Int.s.idxSubDev);
1830
1831	/*
1832	* We resolve PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, the PCI bus handles
1833	* PDMPCIDEVREG_DEV_NO_FIRST_UNUSED and PDMPCIDEVREG_FUN_NO_FIRST_UNUSED.
1834	*/
1835	uint8_t const uPciDevNoRaw = uPciDevNo;
1836	uint32_t uDefPciBusNo = 0;
1837	if (uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV)
1838	{
1839	if (pPrevPciDev)
1840	{
1841	uPciDevNo = pPrevPciDev->uDevFn >> 3;
1842	uDefPciBusNo = pPrevPciDev->Int.s.idxPdmBus;
1843	}
1844	else
1845	{
1846	/* Look for PCI device registered with an earlier device instance so we can more
1847	easily have multiple functions spanning multiple PDM device instances. */
1848	PPDMDEVINS pPrevIns = pDevIns->Internal.s.pDevR3->pInstances;
1849	for (;;)
1850	{
1851	AssertLogRelMsgReturn(pPrevIns && pPrevIns != pDevIns,
1852	("'%s'/%d: Can't use PDMPCIDEVREG_DEV_NO_SAME_AS_PREV without a previously registered PCI device by the same or earlier PDM device instance!\n",
1853	pDevIns->pReg->szName, pDevIns->iInstance), VERR_WRONG_ORDER);
1854	if (pPrevIns->Internal.s.pNextR3 == pDevIns)
1855	break;
1856	pPrevIns = pPrevIns->Internal.s.pNextR3;
1857	}
1858
1859	PPDMPCIDEV pOtherPciDev = PDMDEV_GET_PPCIDEV(pPrevIns, 0);
1860	AssertLogRelMsgReturn(pOtherPciDev && pOtherPciDev->Int.s.fRegistered,
1861	("'%s'/%d: Can't use PDMPCIDEVREG_DEV_NO_SAME_AS_PREV without a previously registered PCI device by the same or earlier PDM device instance!\n",
1862	pDevIns->pReg->szName, pDevIns->iInstance),
1863	VERR_WRONG_ORDER);
1864	for (uint32_t iPrevPciDev = 1; iPrevPciDev < pDevIns->cPciDevs; iPrevPciDev++)
1865	{
1866	PPDMPCIDEV pCur = PDMDEV_GET_PPCIDEV(pPrevIns, iPrevPciDev);
1867	AssertBreak(pCur);
1868	if (!pCur->Int.s.fRegistered)
1869	break;
1870	pOtherPciDev = pCur;
1871	}
1872
1873	uPciDevNo = pOtherPciDev->uDevFn >> 3;
1874	uDefPciBusNo = pOtherPciDev->Int.s.idxPdmBus;
1875	}
1876	}
1877
1878	/*
1879	* Choose the PCI bus for the device.
1880	*
1881	* This is simple. If the device was configured for a particular bus, the PCIBusNo
1882	* configuration value will be set. If not the default bus is 0.
1883	*/
1884	/** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIBusNo, uint8_t, 0, 7, 0}
1885	* Selects the PCI bus number of a device. The default value isn't necessarily
1886	* zero if the device is registered using PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, it
1887	* will then also inherit the bus number from the previously registered device.
1888	*/
1889	uint8_t u8Bus;
1890	int rc = CFGMR3QueryU8Def(pCfg, "PCIBusNo", &u8Bus, (uint8_t)uDefPciBusNo);
1891	AssertLogRelMsgRCReturn(rc, ("Configuration error: PCIBusNo query failed with rc=%Rrc (%s/%d)\n",
1892	rc, pDevIns->pReg->szName, pDevIns->iInstance), rc);
1893	AssertLogRelMsgReturn(u8Bus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
1894	("Configuration error: PCIBusNo=%d, max is %d. (%s/%d)\n", u8Bus,
1895	RT_ELEMENTS(pVM->pdm.s.aPciBuses), pDevIns->pReg->szName, pDevIns->iInstance),
1896	VERR_PDM_NO_PCI_BUS);
1897	pPciDev->Int.s.idxPdmBus = u8Bus;
1898	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[u8Bus];
1899	if (pBus->pDevInsR3)
1900	{
1901	/*
1902	* Check the configuration for PCI device and function assignment.
1903	*/
1904	/** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIDeviceNo, uint8_t, 0, 31}
1905	* Overrides the default PCI device number of a device.
1906	*/
1907	uint8_t uCfgDevice;
1908	rc = CFGMR3QueryU8(pCfg, "PCIDeviceNo", &uCfgDevice);
1909	if (RT_SUCCESS(rc))
1910	{
1911	AssertMsgReturn(uCfgDevice <= 31,
1912	("Configuration error: PCIDeviceNo=%d, max is 31. (%s/%d/%d)\n",
1913	uCfgDevice, pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->Int.s.idxSubDev),
1914	VERR_PDM_BAD_PCI_CONFIG);
1915	uPciDevNo = uCfgDevice;
1916	}
1917	else
1918	AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT,
1919	("Configuration error: PCIDeviceNo query failed with rc=%Rrc (%s/%d/%d)\n",
1920	rc, pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->Int.s.idxSubDev),
1921	rc);
1922
1923	/** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIFunctionNo, uint8_t, 0, 7}
1924	* Overrides the default PCI function number of a device.
1925	*/
1926	uint8_t uCfgFunction;
1927	rc = CFGMR3QueryU8(pCfg, "PCIFunctionNo", &uCfgFunction);
1928	if (RT_SUCCESS(rc))
1929	{
1930	AssertMsgReturn(uCfgFunction <= 7,
1931	("Configuration error: PCIFunctionNo=%#x, max is 7. (%s/%d/%d)\n",
1932	uCfgFunction, pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->Int.s.idxSubDev),
1933	VERR_PDM_BAD_PCI_CONFIG);
1934	uPciFunNo = uCfgFunction;
1935	}
1936	else
1937	AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT,
1938	("Configuration error: PCIFunctionNo query failed with rc=%Rrc (%s/%d/%d)\n",
1939	rc, pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->Int.s.idxSubDev),
1940	rc);
1941
1942	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
1943	PPDMIOMMUR3 pIommu = &pVM->pdm.s.aIommus[0];
1944	PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
1945	if (pDevInsIommu)
1946	{
1947	/*
1948	* If the PCI device/function number has been explicitly specified via CFGM,
1949	* ensure it's not the BDF reserved for the southbridge I/O APIC expected
1950	* by linux guests when using an AMD IOMMU, see @bugref{9654#c23}.
1951	*
1952	* In the Intel IOMMU case, we re-use the same I/O APIC address to reserve a
1953	* PCI slot so the same check below is sufficient, see @bugref{9967#c13}.
1954	*/
1955	uint16_t const uDevFn = VBOX_PCI_DEVFN_MAKE(uPciDevNo, uPciFunNo);
1956	uint16_t const uBusDevFn = PCIBDF_MAKE(u8Bus, uDevFn);
1957	if (uBusDevFn == VBOX_PCI_BDF_SB_IOAPIC)
1958	{
1959	LogRel(("Configuration error: PCI BDF (%u:%u:%u) conflicts with SB I/O APIC (%s/%d/%d)\n", u8Bus,
1960	uCfgDevice, uCfgFunction, pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->Int.s.idxSubDev));
1961	return VERR_NOT_AVAILABLE;
1962	}
1963	}
1964	#endif
1965
1966	/*
1967	* Initialize the internal data. We only do the wipe and the members
1968	* owned by PDM, the PCI bus does the rest in the registration call.
1969	*/
1970	RT_ZERO(pPciDev->Int);
1971
1972	pPciDev->Int.s.idxDevCfg = pPciDev->Int.s.idxSubDev;
1973	pPciDev->Int.s.fReassignableDevNo = uPciDevNoRaw >= VBOX_PCI_MAX_DEVICES;
1974	pPciDev->Int.s.fReassignableFunNo = uPciFunNo >= VBOX_PCI_MAX_FUNCTIONS;
1975	pPciDev->Int.s.pDevInsR3 = pDevIns;
1976	pPciDev->Int.s.idxPdmBus = u8Bus;
1977	pPciDev->Int.s.fRegistered = true;
1978
1979	/* Set some of the public members too. */
1980	pPciDev->pszNameR3 = pszName;
1981
1982	/*
1983	* Call the pci bus device to do the actual registration.
1984	*/
1985	pdmLock(pVM);
1986	rc = pBus->pfnRegister(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
1987	pdmUnlock(pVM);
1988	if (RT_SUCCESS(rc))
1989	Log(("PDM: Registered device '%s'/%d as PCI device %d on bus %d\n",
1990	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->uDevFn, pBus->iBus));
1991	else
1992	pPciDev->Int.s.fRegistered = false;
1993	}
1994	else
1995	{
1996	AssertLogRelMsgFailed(("Configuration error: No PCI bus available. This could be related to init order too!\n"));
1997	rc = VERR_PDM_NO_PCI_BUS;
1998	}
1999
2000	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2001	return rc;
2002	}
2003
2004
2005	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegisterMsi} */
2006	static DECLCALLBACK(int) pdmR3DevHlp_PCIRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
2007	{
2008	PDMDEV_ASSERT_DEVINS(pDevIns);
2009	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2010	pPciDev = pDevIns->apPciDevs[0];
2011	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2012	LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: pPciDev=%p:{%#x} pMsgReg=%p:{cMsiVectors=%d, cMsixVectors=%d}\n",
2013	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, pMsiReg, pMsiReg->cMsiVectors, pMsiReg->cMsixVectors));
2014	PDMPCIDEV_ASSERT_VALID_RET(pDevIns, pPciDev);
2015
2016	AssertLogRelMsgReturn(pDevIns->pReg->cMaxPciDevices > 0,
2017	("'%s'/%d: cMaxPciDevices is 0\n", pDevIns->pReg->szName, pDevIns->iInstance),
2018	VERR_WRONG_ORDER);
2019	AssertLogRelMsgReturn(pMsiReg->cMsixVectors <= pDevIns->pReg->cMaxMsixVectors,
2020	("'%s'/%d: cMsixVectors=%u cMaxMsixVectors=%u\n",
2021	pDevIns->pReg->szName, pDevIns->iInstance, pMsiReg->cMsixVectors, pDevIns->pReg->cMaxMsixVectors),
2022	VERR_INVALID_FLAGS);
2023
2024	PVM pVM = pDevIns->Internal.s.pVMR3;
2025	size_t const idxBus = pPciDev->Int.s.idxPdmBus;
2026	AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_WRONG_ORDER);
2027	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
2028
2029	pdmLock(pVM);
2030	int rc;
2031	if (pBus->pfnRegisterMsi)
2032	rc = pBus->pfnRegisterMsi(pBus->pDevInsR3, pPciDev, pMsiReg);
2033	else
2034	rc = VERR_NOT_IMPLEMENTED;
2035	pdmUnlock(pVM);
2036
2037	LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2038	return rc;
2039	}
2040
2041
2042	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIIORegionRegister} */
2043	static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
2044	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
2045	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap)
2046	{
2047	PDMDEV_ASSERT_DEVINS(pDevIns);
2048	PVM pVM = pDevIns->Internal.s.pVMR3;
2049	VM_ASSERT_EMT(pVM);
2050	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2051	pPciDev = pDevIns->apPciDevs[0];
2052	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2053	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%d cbRegion=%RGp enmType=%d fFlags=%#x, hHandle=%#RX64 pfnMapUnmap=%p\n",
2054	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iRegion, cbRegion, enmType, fFlags, hHandle, pfnMapUnmap));
2055	PDMPCIDEV_ASSERT_VALID_RET(pDevIns, pPciDev);
2056
2057	/*
2058	* Validate input.
2059	*/
2060	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2061	AssertLogRelMsgReturn(VMR3GetState(pVM) == VMSTATE_CREATING,
2062	("caller='%s'/%d: %s\n", pDevIns->pReg->szName, pDevIns->iInstance, VMR3GetStateName(VMR3GetState(pVM))),
2063	VERR_WRONG_ORDER);
2064
2065	if (iRegion >= VBOX_PCI_NUM_REGIONS)
2066	{
2067	Assert(iRegion < VBOX_PCI_NUM_REGIONS);
2068	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (iRegion)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2069	return VERR_INVALID_PARAMETER;
2070	}
2071
2072	switch ((int)enmType)
2073	{
2074	case PCI_ADDRESS_SPACE_IO:
2075	/*
2076	* Sanity check: don't allow to register more than 32K of the PCI I/O space.
2077	*/
2078	AssertLogRelMsgReturn(cbRegion <= _32K,
2079	("caller='%s'/%d: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cbRegion),
2080	VERR_INVALID_PARAMETER);
2081	break;
2082
2083	case PCI_ADDRESS_SPACE_MEM:
2084	case PCI_ADDRESS_SPACE_MEM_PREFETCH:
2085	/*
2086	* Sanity check: Don't allow to register more than 2GB of the PCI MMIO space.
2087	*/
2088	AssertLogRelMsgReturn(cbRegion <= MM_MMIO_32_MAX,
2089	("caller='%s'/%d: %RGp (max %RGp)\n",
2090	pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, (RTGCPHYS)MM_MMIO_32_MAX),
2091	VERR_OUT_OF_RANGE);
2092	break;
2093
2094	case PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM:
2095	case PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH:
2096	/*
2097	* Sanity check: Don't allow to register more than 64GB of the 64-bit PCI MMIO space.
2098	*/
2099	AssertLogRelMsgReturn(cbRegion <= MM_MMIO_64_MAX,
2100	("caller='%s'/%d: %RGp (max %RGp)\n",
2101	pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, MM_MMIO_64_MAX),
2102	VERR_OUT_OF_RANGE);
2103	break;
2104
2105	default:
2106	AssertMsgFailed(("enmType=%#x is unknown\n", enmType));
2107	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (enmType)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2108	return VERR_INVALID_PARAMETER;
2109	}
2110
2111	AssertMsgReturn( pfnMapUnmap
2112	\|\| ( hHandle != UINT64_MAX
2113	&& (fFlags & PDMPCIDEV_IORGN_F_HANDLE_MASK) != PDMPCIDEV_IORGN_F_NO_HANDLE),
2114	("caller='%s'/%d: fFlags=%#x hHandle=%#RX64\n", pDevIns->pReg->szName, pDevIns->iInstance, fFlags, hHandle),
2115	VERR_INVALID_PARAMETER);
2116
2117	AssertMsgReturn(!(fFlags & ~PDMPCIDEV_IORGN_F_VALID_MASK), ("fFlags=%#x\n", fFlags), VERR_INVALID_FLAGS);
2118	int rc;
2119	switch (fFlags & PDMPCIDEV_IORGN_F_HANDLE_MASK)
2120	{
2121	case PDMPCIDEV_IORGN_F_NO_HANDLE:
2122	break;
2123	case PDMPCIDEV_IORGN_F_IOPORT_HANDLE:
2124	AssertReturn(enmType == PCI_ADDRESS_SPACE_IO, VERR_INVALID_FLAGS);
2125	rc = IOMR3IoPortValidateHandle(pVM, pDevIns, (IOMIOPORTHANDLE)hHandle);
2126	AssertRCReturn(rc, rc);
2127	break;
2128	case PDMPCIDEV_IORGN_F_MMIO_HANDLE:
2129	AssertReturn( (enmType & ~PCI_ADDRESS_SPACE_BAR64) == PCI_ADDRESS_SPACE_MEM
2130	\|\| (enmType & ~PCI_ADDRESS_SPACE_BAR64) == PCI_ADDRESS_SPACE_MEM_PREFETCH,
2131	VERR_INVALID_FLAGS);
2132	rc = IOMR3MmioValidateHandle(pVM, pDevIns, (IOMMMIOHANDLE)hHandle);
2133	AssertRCReturn(rc, rc);
2134	break;
2135	case PDMPCIDEV_IORGN_F_MMIO2_HANDLE:
2136	AssertReturn( (enmType & ~PCI_ADDRESS_SPACE_BAR64) == PCI_ADDRESS_SPACE_MEM
2137	\|\| (enmType & ~PCI_ADDRESS_SPACE_BAR64) == PCI_ADDRESS_SPACE_MEM_PREFETCH,
2138	VERR_INVALID_FLAGS);
2139	rc = PGMR3PhysMmio2ValidateHandle(pVM, pDevIns, (PGMMMIO2HANDLE)hHandle);
2140	AssertRCReturn(rc, rc);
2141	break;
2142	default:
2143	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
2144	break;
2145	}
2146
2147	/* This flag is required now. */
2148	AssertLogRelMsgReturn(fFlags & PDMPCIDEV_IORGN_F_NEW_STYLE,
2149	("'%s'/%d: Invalid flags: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, fFlags),
2150	VERR_INVALID_FLAGS);
2151
2152	/*
2153	* We're currently restricted to page aligned MMIO regions.
2154	*/
2155	if ( ((enmType & ~(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH)) == PCI_ADDRESS_SPACE_MEM)
2156	&& cbRegion != RT_ALIGN_64(cbRegion, GUEST_PAGE_SIZE))
2157	{
2158	Log(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: aligning cbRegion %RGp -> %RGp\n",
2159	pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, RT_ALIGN_64(cbRegion, GUEST_PAGE_SIZE)));
2160	cbRegion = RT_ALIGN_64(cbRegion, GUEST_PAGE_SIZE);
2161	}
2162
2163	/*
2164	* For registering PCI MMIO memory or PCI I/O memory, the size of the region must be a power of 2!
2165	*/
2166	int iLastSet = ASMBitLastSetU64(cbRegion);
2167	Assert(iLastSet > 0);
2168	uint64_t cbRegionAligned = RT_BIT_64(iLastSet - 1);
2169	if (cbRegion > cbRegionAligned)
2170	cbRegion = cbRegionAligned * 2; /* round up */
2171
2172	size_t const idxBus = pPciDev->Int.s.idxPdmBus;
2173	AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_WRONG_ORDER);
2174	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
2175
2176	pdmLock(pVM);
2177	rc = pBus->pfnIORegionRegister(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, fFlags, hHandle, pfnMapUnmap);
2178	pdmUnlock(pVM);
2179
2180	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2181	return rc;
2182	}
2183
2184
2185	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIInterceptConfigAccesses} */
2186	static DECLCALLBACK(int) pdmR3DevHlp_PCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
2187	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
2188	{
2189	PDMDEV_ASSERT_DEVINS(pDevIns);
2190	PVM pVM = pDevIns->Internal.s.pVMR3;
2191	VM_ASSERT_EMT(pVM);
2192	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2193	pPciDev = pDevIns->apPciDevs[0];
2194	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2195	LogFlow(("pdmR3DevHlp_PCIInterceptConfigAccesses: caller='%s'/%d: pPciDev=%p pfnRead=%p pfnWrite=%p\n",
2196	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, pfnWrite));
2197	PDMPCIDEV_ASSERT_VALID_RET(pDevIns, pPciDev);
2198
2199	/*
2200	* Validate input.
2201	*/
2202	AssertPtr(pfnRead);
2203	AssertPtr(pfnWrite);
2204	AssertPtr(pPciDev);
2205
2206	size_t const idxBus = pPciDev->Int.s.idxPdmBus;
2207	AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
2208	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
2209	AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
2210
2211	/*
2212	* Do the job.
2213	*/
2214	pdmLock(pVM);
2215	pBus->pfnInterceptConfigAccesses(pBus->pDevInsR3, pPciDev, pfnRead, pfnWrite);
2216	pdmUnlock(pVM);
2217
2218	LogFlow(("pdmR3DevHlp_PCIInterceptConfigAccesses: caller='%s'/%d: returns VINF_SUCCESS\n",
2219	pDevIns->pReg->szName, pDevIns->iInstance));
2220	return VINF_SUCCESS;
2221	}
2222
2223
2224	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIConfigWrite} */
2225	static DECLCALLBACK(VBOXSTRICTRC)
2226	pdmR3DevHlp_PCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value)
2227	{
2228	PDMDEV_ASSERT_DEVINS(pDevIns);
2229	PVM pVM = pDevIns->Internal.s.pVMR3;
2230	AssertPtrReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2231	LogFlow(("pdmR3DevHlp_PCIConfigWrite: caller='%s'/%d: pPciDev=%p uAddress=%#x cd=%d u32Value=%#x\n",
2232	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, uAddress, cb, u32Value));
2233
2234	/*
2235	* Resolve the bus.
2236	*/
2237	size_t const idxBus = pPciDev->Int.s.idxPdmBus;
2238	AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
2239	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
2240
2241	/*
2242	* Do the job.
2243	*/
2244	VBOXSTRICTRC rcStrict = pBus->pfnConfigWrite(pBus->pDevInsR3, pPciDev, uAddress, cb, u32Value);
2245
2246	LogFlow(("pdmR3DevHlp_PCIConfigWrite: caller='%s'/%d: returns %Rrc\n",
2247	pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict)));
2248	return rcStrict;
2249	}
2250
2251
2252	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIConfigRead} */
2253	static DECLCALLBACK(VBOXSTRICTRC)
2254	pdmR3DevHlp_PCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
2255	{
2256	PDMDEV_ASSERT_DEVINS(pDevIns);
2257	PVM pVM = pDevIns->Internal.s.pVMR3;
2258	AssertPtrReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2259	LogFlow(("pdmR3DevHlp_PCIConfigRead: caller='%s'/%d: pPciDev=%p uAddress=%#x cd=%d pu32Value=%p:{%#x}\n",
2260	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, uAddress, cb, pu32Value, *pu32Value));
2261
2262	/*
2263	* Resolve the bus.
2264	*/
2265	size_t const idxBus = pPciDev->Int.s.idxPdmBus;
2266	AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
2267	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
2268
2269	/*
2270	* Do the job.
2271	*/
2272	VBOXSTRICTRC rcStrict = pBus->pfnConfigRead(pBus->pDevInsR3, pPciDev, uAddress, cb, pu32Value);
2273
2274	LogFlow(("pdmR3DevHlp_PCIConfigRead: caller='%s'/%d: returns %Rrc (*pu32Value=%#x)\n",
2275	pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict), *pu32Value));
2276	return rcStrict;
2277	}
2278
2279
2280	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysRead} */
2281	static DECLCALLBACK(int)
2282	pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
2283	{
2284	PDMDEV_ASSERT_DEVINS(pDevIns);
2285	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2286	pPciDev = pDevIns->apPciDevs[0];
2287	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2288	PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
2289
2290	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
2291	/*
2292	* Just check the busmaster setting here and forward the request to the generic read helper.
2293	*/
2294	if (PCIDevIsBusmaster(pPciDev))
2295	{ /* likely */ }
2296	else
2297	{
2298	Log(("pdmR3DevHlp_PCIPhysRead: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
2299	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
2300	memset(pvBuf, 0xff, cbRead);
2301	return VERR_PDM_NOT_PCI_BUS_MASTER;
2302	}
2303	#endif
2304
2305	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
2306	int rc = pdmIommuMemAccessRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, fFlags);
2307	if ( rc == VERR_IOMMU_NOT_PRESENT
2308	\|\| rc == VERR_IOMMU_CANNOT_CALL_SELF)
2309	{ /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
2310	else
2311	return rc;
2312	#endif
2313
2314	return pDevIns->pHlpR3->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
2315	}
2316
2317
2318	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysWrite} */
2319	static DECLCALLBACK(int)
2320	pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
2321	{
2322	PDMDEV_ASSERT_DEVINS(pDevIns);
2323	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2324	pPciDev = pDevIns->apPciDevs[0];
2325	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2326	PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
2327
2328	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
2329	/*
2330	* Just check the busmaster setting here and forward the request to the generic read helper.
2331	*/
2332	if (PCIDevIsBusmaster(pPciDev))
2333	{ /* likely */ }
2334	else
2335	{
2336	Log(("pdmR3DevHlp_PCIPhysWrite: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
2337	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
2338	return VERR_PDM_NOT_PCI_BUS_MASTER;
2339	}
2340	#endif
2341
2342	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
2343	int rc = pdmIommuMemAccessWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, fFlags);
2344	if ( rc == VERR_IOMMU_NOT_PRESENT
2345	\|\| rc == VERR_IOMMU_CANNOT_CALL_SELF)
2346	{ /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
2347	else
2348	return rc;
2349	#endif
2350
2351	return pDevIns->pHlpR3->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
2352	}
2353
2354
2355	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysGCPhys2CCPtr} */
2356	static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
2357	uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
2358	{
2359	PDMDEV_ASSERT_DEVINS(pDevIns);
2360	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2361	pPciDev = pDevIns->apPciDevs[0];
2362	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2363	PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
2364
2365	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
2366	if (PCIDevIsBusmaster(pPciDev))
2367	{ /* likely */ }
2368	else
2369	{
2370	LogFunc(("caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp fFlags=%#RX32\n",
2371	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, fFlags));
2372	return VERR_PDM_NOT_PCI_BUS_MASTER;
2373	}
2374	#endif
2375
2376	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
2377	int rc = pdmR3IommuMemAccessWriteCCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
2378	if ( rc == VERR_IOMMU_NOT_PRESENT
2379	\|\| rc == VERR_IOMMU_CANNOT_CALL_SELF)
2380	{ /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
2381	else
2382	return rc;
2383	#endif
2384
2385	return pDevIns->pHlpR3->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
2386	}
2387
2388
2389	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysGCPhys2CCPtrReadOnly} */
2390	static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
2391	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock)
2392	{
2393	PDMDEV_ASSERT_DEVINS(pDevIns);
2394	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2395	pPciDev = pDevIns->apPciDevs[0];
2396	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2397	PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
2398
2399	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
2400	if (PCIDevIsBusmaster(pPciDev))
2401	{ /* likely */ }
2402	else
2403	{
2404	LogFunc(("caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp fFlags=%#RX32\n",
2405	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, fFlags));
2406	return VERR_PDM_NOT_PCI_BUS_MASTER;
2407	}
2408	#endif
2409
2410	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
2411	int rc = pdmR3IommuMemAccessReadCCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
2412	if ( rc == VERR_IOMMU_NOT_PRESENT
2413	\|\| rc == VERR_IOMMU_CANNOT_CALL_SELF)
2414	{ /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
2415	else
2416	return rc;
2417	#endif
2418
2419	return pDevIns->pHlpR3->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
2420	}
2421
2422
2423	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysBulkGCPhys2CCPtr} */
2424	static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
2425	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
2426	PPGMPAGEMAPLOCK paLocks)
2427	{
2428	PDMDEV_ASSERT_DEVINS(pDevIns);
2429	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2430	pPciDev = pDevIns->apPciDevs[0];
2431	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2432	PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
2433
2434	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
2435	if (PCIDevIsBusmaster(pPciDev))
2436	{ /* likely */ }
2437	else
2438	{
2439	LogFunc(("caller='%s'/%d: returns %Rrc - Not bus master! cPages=%zu fFlags=%#RX32\n",
2440	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, cPages, fFlags));
2441	return VERR_PDM_NOT_PCI_BUS_MASTER;
2442	}
2443	#endif
2444
2445	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
2446	int rc = pdmR3IommuMemAccessBulkWriteCCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
2447	if ( rc == VERR_IOMMU_NOT_PRESENT
2448	\|\| rc == VERR_IOMMU_CANNOT_CALL_SELF)
2449	{ /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
2450	else
2451	return rc;
2452	#endif
2453
2454	return pDevIns->pHlpR3->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
2455	}
2456
2457
2458	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysBulkGCPhys2CCPtrReadOnly} */
2459	static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
2460	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
2461	const void **papvPages, PPGMPAGEMAPLOCK paLocks)
2462	{
2463	PDMDEV_ASSERT_DEVINS(pDevIns);
2464	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2465	pPciDev = pDevIns->apPciDevs[0];
2466	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
2467	PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
2468
2469	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
2470	if (PCIDevIsBusmaster(pPciDev))
2471	{ /* likely */ }
2472	else
2473	{
2474	LogFunc(("caller='%s'/%d: returns %Rrc - Not bus master! cPages=%zu fFlags=%#RX32\n",
2475	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, cPages, fFlags));
2476	return VERR_PDM_NOT_PCI_BUS_MASTER;
2477	}
2478	#endif
2479
2480	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
2481	int rc = pdmR3IommuMemAccessBulkReadCCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
2482	if ( rc == VERR_IOMMU_NOT_PRESENT
2483	\|\| rc == VERR_IOMMU_CANNOT_CALL_SELF)
2484	{ /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
2485	else
2486	return rc;
2487	#endif
2488
2489	return pDevIns->pHlpR3->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
2490	}
2491
2492
2493	/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrq} */
2494	static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
2495	{
2496	PDMDEV_ASSERT_DEVINS(pDevIns);
2497	if (!pPciDev) /* NULL is an alias for the default PCI device. */
2498	pPciDev = pDevIns->apPciDevs[0];
2499	AssertReturnVoid(pPciDev);
2500	LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
2501	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
2502	PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
2503
2504	/*
2505	* Validate input.
2506	*/
2507	Assert(iIrq == 0);
2508	Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
2509
2510	/*
2511	* Must have a PCI device registered!
2512	*/
2513	PVM pVM = pDevIns->Internal.s.pVMR3;
2514	size_t const idxBus = pPciDev->Int.s.idxPdmBus;
2515	AssertReturnVoid(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses));
2516	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
2517
2518	pdmLock(pVM);
2519	uint32_t uTagSrc;
2520	if (iLevel & PDM_IRQ_LEVEL_HIGH)
2521	{
2522	pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
2523	if (iLevel == PDM_IRQ_LEVEL_HIGH)
2524	VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
2525	else
2526	VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
2527	}
2528	else
2529	uTagSrc = pDevIns->Internal.s.uLastIrqTag;
2530
2531	pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, iIrq, iLevel, uTagSrc);
2532
2533	if (iLevel == PDM_IRQ_LEVEL_LOW)
2534	VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
2535	pdmUnlock(pVM);
2536
2537	LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
2538	}
2539
2540
2541	/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrqNoWait} */
2542	static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
2543	{
2544	pdmR3DevHlp_PCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
2545	}
2546
2547
2548	/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrq} */
2549	static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2550	{
2551	PDMDEV_ASSERT_DEVINS(pDevIns);
2552	LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
2553
2554	/*
2555	* Validate input.
2556	*/
2557	#ifndef VBOX_VMM_TARGET_ARMV8
2558	Assert(iIrq < 16);
2559	#endif
2560	Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
2561
2562	PVM pVM = pDevIns->Internal.s.pVMR3;
2563
2564	/*
2565	* Do the job.
2566	*/
2567	pdmLock(pVM);
2568	uint32_t uTagSrc;
2569	if (iLevel & PDM_IRQ_LEVEL_HIGH)
2570	{
2571	pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
2572	if (iLevel == PDM_IRQ_LEVEL_HIGH)
2573	VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
2574	else
2575	VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
2576	}
2577	else
2578	uTagSrc = pDevIns->Internal.s.uLastIrqTag;
2579
2580	PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
2581
2582	if (iLevel == PDM_IRQ_LEVEL_LOW)
2583	VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
2584	pdmUnlock(pVM);
2585
2586	LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
2587	}
2588
2589
2590	/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrqNoWait} */
2591	static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2592	{
2593	pdmR3DevHlp_ISASetIrq(pDevIns, iIrq, iLevel);
2594	}
2595
2596
2597	/** @interface_method_impl{PDMDEVHLPR3,pfnDriverAttach} */
2598	static DECLCALLBACK(int) pdmR3DevHlp_DriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
2599	{
2600	PDMDEV_ASSERT_DEVINS(pDevIns);
2601	PVM const pVM = pDevIns->Internal.s.pVMR3;
2602	VM_ASSERT_EMT(pVM);
2603	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: iLun=%d pBaseInterface=%p ppBaseInterface=%p pszDesc=%p:{%s}\n",
2604	pDevIns->pReg->szName, pDevIns->iInstance, iLun, pBaseInterface, ppBaseInterface, pszDesc, pszDesc));
2605
2606	/*
2607	* Lookup the LUN, it might already be registered.
2608	*/
2609	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
2610
2611	PPDMLUN pLunPrev = NULL;
2612	PPDMLUN pLun = pDevIns->Internal.s.pLunsR3;
2613	for (; pLun; pLunPrev = pLun, pLun = pLun->pNext)
2614	if (pLun->iLun == iLun)
2615	break;
2616
2617	/*
2618	* Create the LUN if if wasn't found, else check if driver is already attached to it.
2619	*/
2620	if (!pLun)
2621	{
2622	if ( !pBaseInterface
2623	\|\| !pszDesc
2624	\|\| !*pszDesc)
2625	{
2626	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
2627	Assert(pBaseInterface);
2628	Assert(pszDesc \|\| *pszDesc);
2629	return VERR_INVALID_PARAMETER;
2630	}
2631
2632	pLun = (PPDMLUN)MMR3HeapAlloc(pVM, MM_TAG_PDM_LUN, sizeof(*pLun));
2633	if (!pLun)
2634	{
2635	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
2636	return VERR_NO_MEMORY;
2637	}
2638
2639	pLun->iLun = iLun;
2640	pLun->pNext = pLunPrev ? pLunPrev->pNext : NULL;
2641	pLun->pTop = NULL;
2642	pLun->pBottom = NULL;
2643	pLun->pDevIns = pDevIns;
2644	pLun->pUsbIns = NULL;
2645	pLun->pszDesc = pszDesc;
2646	pLun->pBase = pBaseInterface;
2647	if (!pLunPrev)
2648	pDevIns->Internal.s.pLunsR3 = pLun;
2649	else
2650	pLunPrev->pNext = pLun;
2651	Log(("pdmR3DevHlp_DriverAttach: Registered LUN#%d '%s' with device '%s'/%d.\n",
2652	iLun, pszDesc, pDevIns->pReg->szName, pDevIns->iInstance));
2653	}
2654	else if (pLun->pTop)
2655	{
2656	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
2657	AssertMsgFailed(("Already attached! The device should keep track of such things!\n"));
2658	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_DRIVER_ALREADY_ATTACHED));
2659	return VERR_PDM_DRIVER_ALREADY_ATTACHED;
2660	}
2661	Assert(pLun->pBase == pBaseInterface);
2662
2663
2664	/*
2665	* Get the attached driver configuration.
2666	*/
2667	int rc;
2668	PCFGMNODE const pNode = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "LUN#%u", iLun);
2669	if (pNode)
2670	rc = pdmR3DrvInstantiate(pVM, pNode, pBaseInterface, NULL /pDrvAbove/, pLun, ppBaseInterface);
2671	else
2672	rc = VERR_PDM_NO_ATTACHED_DRIVER;
2673
2674	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
2675
2676	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2677	return rc;
2678	}
2679
2680
2681	/** @interface_method_impl{PDMDEVHLPR3,pfnDriverDetach} */
2682	static DECLCALLBACK(int) pdmR3DevHlp_DriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
2683	{
2684	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
2685	LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: pDrvIns=%p\n",
2686	pDevIns->pReg->szName, pDevIns->iInstance, pDrvIns));
2687
2688	PVM const pVM = pDevIns->Internal.s.pVMR3;
2689	VM_ASSERT_EMT(pVM);
2690
2691	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
2692	int rc = pdmR3DrvDetach(pVM, pDrvIns, fFlags);
2693	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
2694
2695	LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2696	return rc;
2697	}
2698
2699
2700	/** @interface_method_impl{PDMDEVHLPR3,pfnDriverReconfigure} */
2701	static DECLCALLBACK(int) pdmR3DevHlp_DriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
2702	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
2703	{
2704	PDMDEV_ASSERT_DEVINS(pDevIns);
2705	PVM const pVM = pDevIns->Internal.s.pVMR3;
2706	VM_ASSERT_EMT(pVM);
2707	LogFlow(("pdmR3DevHlp_DriverReconfigure: caller='%s'/%d: iLun=%u cDepth=%u fFlags=%#x\n",
2708	pDevIns->pReg->szName, pDevIns->iInstance, iLun, cDepth, fFlags));
2709
2710	/*
2711	* Validate input.
2712	*/
2713	AssertReturn(cDepth <= 8, VERR_INVALID_PARAMETER);
2714	AssertPtrReturn(papszDrivers, VERR_INVALID_POINTER);
2715	AssertPtrNullReturn(papConfigs, VERR_INVALID_POINTER);
2716	for (uint32_t i = 0; i < cDepth; i++)
2717	{
2718	AssertPtrReturn(papszDrivers[i], VERR_INVALID_POINTER);
2719	size_t cchDriver = strlen(papszDrivers[i]);
2720	AssertReturn(cchDriver > 0 && cchDriver < RT_SIZEOFMEMB(PDMDRVREG, szName), VERR_OUT_OF_RANGE);
2721
2722	if (papConfigs)
2723	AssertPtrNullReturn(papConfigs[i], VERR_INVALID_POINTER);
2724	}
2725	AssertReturn(fFlags == 0, VERR_INVALID_FLAGS);
2726
2727	/*
2728	* Exclusively lock the core stuff (mind, pdmR3DrvDetach will leave + reenter).
2729	*/
2730	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
2731
2732	/*
2733	* Do we have to detach an existing driver first?
2734	*/
2735	for (PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; pLun; pLun = pLun->pNext)
2736	if (pLun->iLun == iLun)
2737	{
2738	if (pLun->pTop)
2739	{
2740	int rc = pdmR3DrvDetach(pVM, pLun->pTop, 0);
2741	AssertRCReturnStmt(rc, RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw), rc);
2742	}
2743	break;
2744	}
2745
2746	/*
2747	* Remove the old tree.
2748	*/
2749	PCFGMNODE pCfgDev = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "Devices/%s/%u/", pDevIns->pReg->szName, pDevIns->iInstance);
2750	AssertReturn(pCfgDev, VERR_INTERNAL_ERROR_2);
2751	PCFGMNODE pCfgLun = CFGMR3GetChildF(pCfgDev, "LUN#%u", iLun);
2752	if (pCfgLun)
2753	CFGMR3RemoveNode(pCfgLun);
2754
2755	/*
2756	* Construct a new tree.
2757	*/
2758	int rc = CFGMR3InsertNodeF(pCfgDev, &pCfgLun, "LUN#%u", iLun);
2759	AssertRCReturn(rc, rc);
2760	PCFGMNODE pCfgDrv = pCfgLun;
2761	for (uint32_t i = 0; i < cDepth; i++)
2762	{
2763	rc = CFGMR3InsertString(pCfgDrv, "Driver", papszDrivers[i]);
2764	AssertRCReturn(rc, rc);
2765	if (papConfigs && papConfigs[i])
2766	{
2767	rc = CFGMR3InsertSubTree(pCfgDrv, "Config", papConfigs[i], NULL);
2768	AssertRCReturn(rc, rc);
2769	papConfigs[i] = NULL;
2770	}
2771	else
2772	{
2773	rc = CFGMR3InsertNode(pCfgDrv, "Config", NULL);
2774	AssertRCReturn(rc, rc);
2775	}
2776
2777	if (i + 1 >= cDepth)
2778	break;
2779	rc = CFGMR3InsertNode(pCfgDrv, "AttachedDriver", &pCfgDrv);
2780	AssertRCReturn(rc, rc);
2781	}
2782
2783	/* Keep the lock till the end to serialize the CFGM changes. */
2784	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
2785	LogFlow(("pdmR3DevHlp_DriverReconfigure: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2786	return rc;
2787	}
2788
2789
2790	/** @interface_method_impl{PDMDEVHLPR3,pfnQueueCreate} */
2791	static DECLCALLBACK(int) pdmR3DevHlp_QueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
2792	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
2793	PDMQUEUEHANDLE *phQueue)
2794	{
2795	PDMDEV_ASSERT_DEVINS(pDevIns);
2796	LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fRZEnabled=%RTbool pszName=%p:{%s} phQueue=%p\n",
2797	pDevIns->pReg->szName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, pszName, phQueue));
2798
2799	PVM pVM = pDevIns->Internal.s.pVMR3;
2800	VM_ASSERT_EMT(pVM);
2801
2802	if (pDevIns->iInstance > 0)
2803	{
2804	pszName = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s_%u", pszName, pDevIns->iInstance);
2805	AssertLogRelReturn(pszName, VERR_NO_MEMORY);
2806	}
2807
2808	int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
2809
2810	LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: returns %Rrc *phQueue=%p\n",
2811	pDevIns->pReg->szName, pDevIns->iInstance, rc, *phQueue));
2812	return rc;
2813	}
2814
2815
2816	/** @interface_method_impl{PDMDEVHLPR3,pfnQueueAlloc} */
2817	static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR3DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
2818	{
2819	PDMDEV_ASSERT_DEVINS(pDevIns);
2820	return PDMQueueAlloc(pDevIns->Internal.s.pVMR3, hQueue, pDevIns);
2821	}
2822
2823
2824	/** @interface_method_impl{PDMDEVHLPR3,pfnQueueInsert} */
2825	static DECLCALLBACK(int) pdmR3DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
2826	{
2827	return PDMQueueInsert(pDevIns->Internal.s.pVMR3, hQueue, pDevIns, pItem);
2828	}
2829
2830
2831	/** @interface_method_impl{PDMDEVHLPR3,pfnQueueFlushIfNecessary} */
2832	static DECLCALLBACK(bool) pdmR3DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
2833	{
2834	return PDMQueueFlushIfNecessary(pDevIns->Internal.s.pVMR3, hQueue, pDevIns) == VINF_SUCCESS;
2835	}
2836
2837
2838	/** @interface_method_impl{PDMDEVHLPR3,pfnTaskCreate} */
2839	static DECLCALLBACK(int) pdmR3DevHlp_TaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
2840	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
2841	{
2842	PDMDEV_ASSERT_DEVINS(pDevIns);
2843	LogFlow(("pdmR3DevHlp_TaskTrigger: caller='%s'/%d: pfnCallback=%p fFlags=%#x pszName=%p:{%s} phTask=%p\n",
2844	pDevIns->pReg->szName, pDevIns->iInstance, pfnCallback, fFlags, pszName, pszName, phTask));
2845	PVM pVM = pDevIns->Internal.s.pVMR3;
2846	VM_ASSERT_EMT(pVM);
2847
2848	int rc = PDMR3TaskCreate(pVM, fFlags, pszName, PDMTASKTYPE_DEV, pDevIns, (PFNRT)pfnCallback, pvUser, phTask);
2849
2850	LogFlow(("pdmR3DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2851	return rc;
2852	}
2853
2854
2855	/** @interface_method_impl{PDMDEVHLPR3,pfnTaskTrigger} */
2856	static DECLCALLBACK(int) pdmR3DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
2857	{
2858	PDMDEV_ASSERT_DEVINS(pDevIns);
2859	LogFlow(("pdmR3DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
2860
2861	int rc = PDMTaskTrigger(pDevIns->Internal.s.pVMR3, PDMTASKTYPE_DEV, pDevIns, hTask);
2862
2863	LogFlow(("pdmR3DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2864	return rc;
2865	}
2866
2867
2868	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventCreate} */
2869	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
2870	{
2871	PDMDEV_ASSERT_DEVINS(pDevIns);
2872	LogFlow(("pdmR3DevHlp_SUPSemEventCreate: caller='%s'/%d: phEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, phEvent));
2873	PVM pVM = pDevIns->Internal.s.pVMR3;
2874	VM_ASSERT_EMT(pVM);
2875
2876	int rc = SUPSemEventCreate(pVM->pSession, phEvent);
2877
2878	LogFlow(("pdmR3DevHlp_SUPSemEventCreate: caller='%s'/%d: returns %Rrc phEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, phEvent));
2879	return rc;
2880	}
2881
2882
2883	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventClose} */
2884	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
2885	{
2886	PDMDEV_ASSERT_DEVINS(pDevIns);
2887	LogFlow(("pdmR3DevHlp_SUPSemEventClose: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
2888
2889	int rc = SUPSemEventClose(pDevIns->Internal.s.pVMR3->pSession, hEvent);
2890
2891	LogFlow(("pdmR3DevHlp_SUPSemEventClose: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2892	return rc;
2893	}
2894
2895
2896	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventSignal} */
2897	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
2898	{
2899	PDMDEV_ASSERT_DEVINS(pDevIns);
2900	LogFlow(("pdmR3DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
2901
2902	int rc = SUPSemEventSignal(pDevIns->Internal.s.pVMR3->pSession, hEvent);
2903
2904	LogFlow(("pdmR3DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2905	return rc;
2906	}
2907
2908
2909	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventWaitNoResume} */
2910	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
2911	{
2912	PDMDEV_ASSERT_DEVINS(pDevIns);
2913	LogFlow(("pdmR3DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
2914	pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
2915
2916	int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pVMR3->pSession, hEvent, cMillies);
2917
2918	LogFlow(("pdmR3DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2919	return rc;
2920	}
2921
2922
2923	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventWaitNsAbsIntr} */
2924	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
2925	{
2926	PDMDEV_ASSERT_DEVINS(pDevIns);
2927	LogFlow(("pdmR3DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
2928	pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
2929
2930	int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pVMR3->pSession, hEvent, uNsTimeout);
2931
2932	LogFlow(("pdmR3DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2933	return rc;
2934	}
2935
2936
2937	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventWaitNsRelIntr} */
2938	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
2939	{
2940	PDMDEV_ASSERT_DEVINS(pDevIns);
2941	LogFlow(("pdmR3DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
2942	pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
2943
2944	int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pVMR3->pSession, hEvent, cNsTimeout);
2945
2946	LogFlow(("pdmR3DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2947	return rc;
2948	}
2949
2950
2951	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventGetResolution} */
2952	static DECLCALLBACK(uint32_t) pdmR3DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
2953	{
2954	PDMDEV_ASSERT_DEVINS(pDevIns);
2955	LogFlow(("pdmR3DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
2956
2957	uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pVMR3->pSession);
2958
2959	LogFlow(("pdmR3DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
2960	return cNsResolution;
2961	}
2962
2963
2964	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiCreate} */
2965	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
2966	{
2967	PDMDEV_ASSERT_DEVINS(pDevIns);
2968	LogFlow(("pdmR3DevHlp_SUPSemEventMultiCreate: caller='%s'/%d: phEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, phEventMulti));
2969	PVM pVM = pDevIns->Internal.s.pVMR3;
2970	VM_ASSERT_EMT(pVM);
2971
2972	int rc = SUPSemEventMultiCreate(pVM->pSession, phEventMulti);
2973
2974	LogFlow(("pdmR3DevHlp_SUPSemEventMultiCreate: caller='%s'/%d: returns %Rrc phEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, phEventMulti));
2975	return rc;
2976	}
2977
2978
2979	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiClose} */
2980	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
2981	{
2982	PDMDEV_ASSERT_DEVINS(pDevIns);
2983	LogFlow(("pdmR3DevHlp_SUPSemEventMultiClose: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
2984
2985	int rc = SUPSemEventMultiClose(pDevIns->Internal.s.pVMR3->pSession, hEventMulti);
2986
2987	LogFlow(("pdmR3DevHlp_SUPSemEventMultiClose: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2988	return rc;
2989	}
2990
2991
2992	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiSignal} */
2993	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
2994	{
2995	PDMDEV_ASSERT_DEVINS(pDevIns);
2996	LogFlow(("pdmR3DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
2997
2998	int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pVMR3->pSession, hEventMulti);
2999
3000	LogFlow(("pdmR3DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3001	return rc;
3002	}
3003
3004
3005	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiReset} */
3006	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
3007	{
3008	PDMDEV_ASSERT_DEVINS(pDevIns);
3009	LogFlow(("pdmR3DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
3010
3011	int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pVMR3->pSession, hEventMulti);
3012
3013	LogFlow(("pdmR3DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3014	return rc;
3015	}
3016
3017
3018	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiWaitNoResume} */
3019	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
3020	uint32_t cMillies)
3021	{
3022	PDMDEV_ASSERT_DEVINS(pDevIns);
3023	LogFlow(("pdmR3DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
3024	pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
3025
3026	int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pVMR3->pSession, hEventMulti, cMillies);
3027
3028	LogFlow(("pdmR3DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3029	return rc;
3030	}
3031
3032
3033	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiWaitNsAbsIntr} */
3034	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
3035	uint64_t uNsTimeout)
3036	{
3037	PDMDEV_ASSERT_DEVINS(pDevIns);
3038	LogFlow(("pdmR3DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
3039	pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
3040
3041	int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pVMR3->pSession, hEventMulti, uNsTimeout);
3042
3043	LogFlow(("pdmR3DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3044	return rc;
3045	}
3046
3047
3048	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiWaitNsRelIntr} */
3049	static DECLCALLBACK(int) pdmR3DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
3050	uint64_t cNsTimeout)
3051	{
3052	PDMDEV_ASSERT_DEVINS(pDevIns);
3053	LogFlow(("pdmR3DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
3054	pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
3055
3056	int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pVMR3->pSession, hEventMulti, cNsTimeout);
3057
3058	LogFlow(("pdmR3DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3059	return rc;
3060	}
3061
3062
3063	/** @interface_method_impl{PDMDEVHLPR3,pfnSUPSemEventMultiGetResolution} */
3064	static DECLCALLBACK(uint32_t) pdmR3DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
3065	{
3066	PDMDEV_ASSERT_DEVINS(pDevIns);
3067	LogFlow(("pdmR3DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3068
3069	uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pVMR3->pSession);
3070
3071	LogFlow(("pdmR3DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
3072	return cNsResolution;
3073	}
3074
3075
3076	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectInit} */
3077	static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3078	const char *pszNameFmt, va_list va)
3079	{
3080	PDMDEV_ASSERT_DEVINS(pDevIns);
3081	LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n",
3082	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt));
3083
3084	PVM pVM = pDevIns->Internal.s.pVMR3;
3085	VM_ASSERT_EMT(pVM);
3086	int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
3087
3088	LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3089	return rc;
3090	}
3091
3092
3093	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNop} */
3094	static DECLCALLBACK(PPDMCRITSECT) pdmR3DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
3095	{
3096	PDMDEV_ASSERT_DEVINS(pDevIns);
3097	PVM pVM = pDevIns->Internal.s.pVMR3;
3098	VM_ASSERT_EMT(pVM);
3099
3100	PPDMCRITSECT pCritSect = PDMR3CritSectGetNop(pVM);
3101	LogFlow(("pdmR3DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n",
3102	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
3103	return pCritSect;
3104	}
3105
3106
3107	/** @interface_method_impl{PDMDEVHLPR3,pfnSetDeviceCritSect} */
3108	static DECLCALLBACK(int) pdmR3DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
3109	{
3110	/*
3111	* Validate input.
3112	*
3113	* Note! We only allow the automatically created default critical section
3114	* to be replaced by this API.
3115	*/
3116	PDMDEV_ASSERT_DEVINS(pDevIns);
3117	AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
3118	LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
3119	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
3120	AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
3121	PVM pVM = pDevIns->Internal.s.pVMR3;
3122
3123	VM_ASSERT_EMT(pVM);
3124	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
3125
3126	AssertReturn(pDevIns->pCritSectRoR3, VERR_PDM_DEV_IPE_1);
3127	AssertReturn(pDevIns->pCritSectRoR3->s.fAutomaticDefaultCritsect, VERR_WRONG_ORDER);
3128	AssertReturn(!pDevIns->pCritSectRoR3->s.fUsedByTimerOrSimilar, VERR_WRONG_ORDER);
3129	AssertReturn(pDevIns->pCritSectRoR3 != pCritSect, VERR_INVALID_PARAMETER);
3130
3131	/*
3132	* Replace the critical section and destroy the automatic default section.
3133	*/
3134	PPDMCRITSECT pOldCritSect = pDevIns->pCritSectRoR3;
3135	pDevIns->pCritSectRoR3 = pCritSect;
3136	pDevIns->Internal.s.fIntFlags \|= PDMDEVINSINT_FLAGS_CHANGED_CRITSECT;
3137
3138	Assert(RT_BOOL(pDevIns->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_R0_ENABLED) == pDevIns->fR0Enabled);
3139	if ( (pDevIns->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_R0_ENABLED)
3140	&& !(pDevIns->Internal.s.pDevR3->pReg->fFlags & PDM_DEVREG_FLAGS_NEW_STYLE))
3141	{
3142	PDMDEVICECOMPATSETCRITSECTREQ Req;
3143	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3144	Req.Hdr.cbReq = sizeof(Req);
3145	Req.idxR0Device = pDevIns->Internal.s.idxR0Device;
3146	Req.pDevInsR3 = pDevIns;
3147	Req.pCritSectR3 = pCritSect;
3148	int rc = VMMR3CallR0(pVM, VMMR0_DO_PDM_DEVICE_COMPAT_SET_CRITSECT, 0, &Req.Hdr);
3149	AssertLogRelRCReturn(rc, rc);
3150	}
3151
3152	PDMR3CritSectDelete(pVM, pOldCritSect);
3153	Assert((uintptr_t)pOldCritSect - (uintptr_t)pDevIns < pDevIns->cbRing3);
3154
3155	LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3156	return VINF_SUCCESS;
3157	}
3158
3159
3160	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectYield} */
3161	static DECLCALLBACK(bool) pdmR3DevHlp_CritSectYield(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
3162	{
3163	PDMDEV_ASSERT_DEVINS(pDevIns);
3164	return PDMR3CritSectYield(pDevIns->Internal.s.pVMR3, pCritSect);
3165	}
3166
3167
3168	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectEnter} */
3169	static DECLCALLBACK(int) pdmR3DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
3170	{
3171	PDMDEV_ASSERT_DEVINS(pDevIns);
3172	return PDMCritSectEnter(pDevIns->Internal.s.pVMR3, pCritSect, rcBusy);
3173	}
3174
3175
3176	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectEnterDebug} */
3177	static DECLCALLBACK(int) pdmR3DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
3178	{
3179	PDMDEV_ASSERT_DEVINS(pDevIns);
3180	return PDMCritSectEnterDebug(pDevIns->Internal.s.pVMR3, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
3181	}
3182
3183
3184	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectTryEnter} */
3185	static DECLCALLBACK(int) pdmR3DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
3186	{
3187	PDMDEV_ASSERT_DEVINS(pDevIns);
3188	return PDMCritSectTryEnter(pDevIns->Internal.s.pVMR3, pCritSect);
3189	}
3190
3191
3192	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectTryEnterDebug} */
3193	static DECLCALLBACK(int) pdmR3DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
3194	{
3195	PDMDEV_ASSERT_DEVINS(pDevIns);
3196	return PDMCritSectTryEnterDebug(pDevIns->Internal.s.pVMR3, pCritSect, uId, RT_SRC_POS_ARGS);
3197	}
3198
3199
3200	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectLeave} */
3201	static DECLCALLBACK(int) pdmR3DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
3202	{
3203	PDMDEV_ASSERT_DEVINS(pDevIns);
3204	return PDMCritSectLeave(pDevIns->Internal.s.pVMR3, pCritSect);
3205	}
3206
3207
3208	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectIsOwner} */
3209	static DECLCALLBACK(bool) pdmR3DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
3210	{
3211	PDMDEV_ASSERT_DEVINS(pDevIns);
3212	return PDMCritSectIsOwner(pDevIns->Internal.s.pVMR3, pCritSect);
3213	}
3214
3215
3216	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectIsInitialized} */
3217	static DECLCALLBACK(bool) pdmR3DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
3218	{
3219	PDMDEV_ASSERT_DEVINS(pDevIns);
3220	RT_NOREF(pDevIns);
3221	return PDMCritSectIsInitialized(pCritSect);
3222	}
3223
3224
3225	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectHasWaiters} */
3226	static DECLCALLBACK(bool) pdmR3DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
3227	{
3228	PDMDEV_ASSERT_DEVINS(pDevIns);
3229	return PDMCritSectHasWaiters(pDevIns->Internal.s.pVMR3, pCritSect);
3230	}
3231
3232
3233	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetRecursion} */
3234	static DECLCALLBACK(uint32_t) pdmR3DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
3235	{
3236	PDMDEV_ASSERT_DEVINS(pDevIns);
3237	RT_NOREF(pDevIns);
3238	return PDMCritSectGetRecursion(pCritSect);
3239	}
3240
3241
3242	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectScheduleExitEvent} */
3243	static DECLCALLBACK(int) pdmR3DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
3244	SUPSEMEVENT hEventToSignal)
3245	{
3246	PDMDEV_ASSERT_DEVINS(pDevIns);
3247	RT_NOREF(pDevIns);
3248	return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
3249	}
3250
3251
3252	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectDelete} */
3253	static DECLCALLBACK(int) pdmR3DevHlp_CritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
3254	{
3255	PDMDEV_ASSERT_DEVINS(pDevIns);
3256	return PDMR3CritSectDelete(pDevIns->Internal.s.pVMR3, pCritSect);
3257	}
3258
3259
3260	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwInit} */
3261	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
3262	const char *pszNameFmt, va_list va)
3263	{
3264	PDMDEV_ASSERT_DEVINS(pDevIns);
3265	LogFlow(("pdmR3DevHlp_CritSectRwInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n",
3266	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt));
3267
3268	PVM pVM = pDevIns->Internal.s.pVMR3;
3269	VM_ASSERT_EMT(pVM);
3270	int rc = pdmR3CritSectRwInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
3271
3272	LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3273	return rc;
3274	}
3275
3276
3277	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwDelete} */
3278	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3279	{
3280	PDMDEV_ASSERT_DEVINS(pDevIns);
3281	return PDMR3CritSectRwDelete(pDevIns->Internal.s.pVMR3, pCritSect);
3282	}
3283
3284
3285	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwEnterShared} */
3286	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
3287	{
3288	PDMDEV_ASSERT_DEVINS(pDevIns);
3289	return PDMCritSectRwEnterShared(pDevIns->Internal.s.pVMR3, pCritSect, rcBusy);
3290	}
3291
3292
3293	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwEnterSharedDebug} */
3294	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy,
3295	RTHCUINTPTR uId, RT_SRC_POS_DECL)
3296	{
3297	PDMDEV_ASSERT_DEVINS(pDevIns);
3298	return PDMCritSectRwEnterSharedDebug(pDevIns->Internal.s.pVMR3, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
3299	}
3300
3301
3302	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwTryEnterShared} */
3303	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3304	{
3305	PDMDEV_ASSERT_DEVINS(pDevIns);
3306	return PDMCritSectRwTryEnterShared(pDevIns->Internal.s.pVMR3, pCritSect);
3307	}
3308
3309
3310	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwTryEnterSharedDebug} */
3311	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect,
3312	RTHCUINTPTR uId, RT_SRC_POS_DECL)
3313	{
3314	PDMDEV_ASSERT_DEVINS(pDevIns);
3315	return PDMCritSectRwTryEnterSharedDebug(pDevIns->Internal.s.pVMR3, pCritSect, uId, RT_SRC_POS_ARGS);
3316	}
3317
3318
3319	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwLeaveShared} */
3320	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3321	{
3322	PDMDEV_ASSERT_DEVINS(pDevIns);
3323	return PDMCritSectRwLeaveShared(pDevIns->Internal.s.pVMR3, pCritSect);
3324	}
3325
3326
3327	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwEnterExcl} */
3328	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
3329	{
3330	PDMDEV_ASSERT_DEVINS(pDevIns);
3331	return PDMCritSectRwEnterExcl(pDevIns->Internal.s.pVMR3, pCritSect, rcBusy);
3332	}
3333
3334
3335	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwEnterExclDebug} */
3336	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy,
3337	RTHCUINTPTR uId, RT_SRC_POS_DECL)
3338	{
3339	PDMDEV_ASSERT_DEVINS(pDevIns);
3340	return PDMCritSectRwEnterExclDebug(pDevIns->Internal.s.pVMR3, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
3341	}
3342
3343
3344	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwTryEnterExcl} */
3345	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3346	{
3347	PDMDEV_ASSERT_DEVINS(pDevIns);
3348	return PDMCritSectRwTryEnterExcl(pDevIns->Internal.s.pVMR3, pCritSect);
3349	}
3350
3351
3352	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwTryEnterExclDebug} */
3353	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect,
3354	RTHCUINTPTR uId, RT_SRC_POS_DECL)
3355	{
3356	PDMDEV_ASSERT_DEVINS(pDevIns);
3357	return PDMCritSectRwTryEnterExclDebug(pDevIns->Internal.s.pVMR3, pCritSect, uId, RT_SRC_POS_ARGS);
3358	}
3359
3360
3361	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwLeaveExcl} */
3362	static DECLCALLBACK(int) pdmR3DevHlp_CritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3363	{
3364	PDMDEV_ASSERT_DEVINS(pDevIns);
3365	return PDMCritSectRwLeaveExcl(pDevIns->Internal.s.pVMR3, pCritSect);
3366	}
3367
3368
3369	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwIsWriteOwner} */
3370	static DECLCALLBACK(bool) pdmR3DevHlp_CritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3371	{
3372	PDMDEV_ASSERT_DEVINS(pDevIns);
3373	return PDMCritSectRwIsWriteOwner(pDevIns->Internal.s.pVMR3, pCritSect);
3374	}
3375
3376
3377	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwIsReadOwner} */
3378	static DECLCALLBACK(bool) pdmR3DevHlp_CritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
3379	{
3380	PDMDEV_ASSERT_DEVINS(pDevIns);
3381	return PDMCritSectRwIsReadOwner(pDevIns->Internal.s.pVMR3, pCritSect, fWannaHear);
3382	}
3383
3384
3385	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwGetWriteRecursion} */
3386	static DECLCALLBACK(uint32_t) pdmR3DevHlp_CritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3387	{
3388	PDMDEV_ASSERT_DEVINS(pDevIns);
3389	RT_NOREF(pDevIns);
3390	return PDMCritSectRwGetWriteRecursion(pCritSect);
3391	}
3392
3393
3394	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwGetWriterReadRecursion} */
3395	static DECLCALLBACK(uint32_t) pdmR3DevHlp_CritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3396	{
3397	PDMDEV_ASSERT_DEVINS(pDevIns);
3398	RT_NOREF(pDevIns);
3399	return PDMCritSectRwGetWriterReadRecursion(pCritSect);
3400	}
3401
3402
3403	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwGetReadCount} */
3404	static DECLCALLBACK(uint32_t) pdmR3DevHlp_CritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3405	{
3406	PDMDEV_ASSERT_DEVINS(pDevIns);
3407	RT_NOREF(pDevIns);
3408	return PDMCritSectRwGetReadCount(pCritSect);
3409	}
3410
3411
3412	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectRwIsInitialized} */
3413	static DECLCALLBACK(bool) pdmR3DevHlp_CritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
3414	{
3415	PDMDEV_ASSERT_DEVINS(pDevIns);
3416	RT_NOREF(pDevIns);
3417	return PDMCritSectRwIsInitialized(pCritSect);
3418	}
3419
3420
3421	/** @interface_method_impl{PDMDEVHLPR3,pfnThreadCreate} */
3422	static DECLCALLBACK(int) pdmR3DevHlp_ThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3423	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
3424	{
3425	PDMDEV_ASSERT_DEVINS(pDevIns);
3426	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3427	LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n",
3428	pDevIns->pReg->szName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName));
3429
3430	int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
3431
3432	LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pReg->szName, pDevIns->iInstance,
3433	rc, *ppThread));
3434	return rc;
3435	}
3436
3437
3438	/** @interface_method_impl{PDMDEVHLPR3,pfnSetAsyncNotification} */
3439	static DECLCALLBACK(int) pdmR3DevHlp_SetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
3440	{
3441	PDMDEV_ASSERT_DEVINS(pDevIns);
3442	VM_ASSERT_EMT0(pDevIns->Internal.s.pVMR3);
3443	LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: pfnAsyncNotify=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pfnAsyncNotify));
3444
3445	int rc = VINF_SUCCESS;
3446	AssertStmt(pfnAsyncNotify, rc = VERR_INVALID_PARAMETER);
3447	AssertStmt(!pDevIns->Internal.s.pfnAsyncNotify, rc = VERR_WRONG_ORDER);
3448	AssertStmt(pDevIns->Internal.s.fIntFlags & (PDMDEVINSINT_FLAGS_SUSPENDED \| PDMDEVINSINT_FLAGS_RESET), rc = VERR_WRONG_ORDER);
3449	VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
3450	AssertStmt( enmVMState == VMSTATE_SUSPENDING
3451	\|\| enmVMState == VMSTATE_SUSPENDING_EXT_LS
3452	\|\| enmVMState == VMSTATE_SUSPENDING_LS
3453	\|\| enmVMState == VMSTATE_RESETTING
3454	\|\| enmVMState == VMSTATE_RESETTING_LS
3455	\|\| enmVMState == VMSTATE_POWERING_OFF
3456	\|\| enmVMState == VMSTATE_POWERING_OFF_LS,
3457	rc = VERR_INVALID_STATE);
3458
3459	if (RT_SUCCESS(rc))
3460	pDevIns->Internal.s.pfnAsyncNotify = pfnAsyncNotify;
3461
3462	LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3463	return rc;
3464	}
3465
3466
3467	/** @interface_method_impl{PDMDEVHLPR3,pfnAsyncNotificationCompleted} */
3468	static DECLCALLBACK(void) pdmR3DevHlp_AsyncNotificationCompleted(PPDMDEVINS pDevIns)
3469	{
3470	PDMDEV_ASSERT_DEVINS(pDevIns);
3471	PVM pVM = pDevIns->Internal.s.pVMR3;
3472
3473	VMSTATE enmVMState = VMR3GetState(pVM);
3474	if ( enmVMState == VMSTATE_SUSPENDING
3475	\|\| enmVMState == VMSTATE_SUSPENDING_EXT_LS
3476	\|\| enmVMState == VMSTATE_SUSPENDING_LS
3477	\|\| enmVMState == VMSTATE_RESETTING
3478	\|\| enmVMState == VMSTATE_RESETTING_LS
3479	\|\| enmVMState == VMSTATE_POWERING_OFF
3480	\|\| enmVMState == VMSTATE_POWERING_OFF_LS)
3481	{
3482	LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3483	VMR3AsyncPdmNotificationWakeupU(pVM->pUVM);
3484	}
3485	else
3486	LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d: enmVMState=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, enmVMState));
3487	}
3488
3489
3490	/** @interface_method_impl{PDMDEVHLPR3,pfnRTCRegister} */
3491	static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
3492	{
3493	PDMDEV_ASSERT_DEVINS(pDevIns);
3494	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3495	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n",
3496	pDevIns->pReg->szName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite,
3497	pRtcReg->pfnWrite, ppRtcHlp));
3498
3499	/*
3500	* Validate input.
3501	*/
3502	if (pRtcReg->u32Version != PDM_RTCREG_VERSION)
3503	{
3504	AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version,
3505	PDM_RTCREG_VERSION));
3506	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n",
3507	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3508	return VERR_INVALID_PARAMETER;
3509	}
3510	if ( !pRtcReg->pfnWrite
3511	\|\| !pRtcReg->pfnRead)
3512	{
3513	Assert(pRtcReg->pfnWrite);
3514	Assert(pRtcReg->pfnRead);
3515	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3516	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3517	return VERR_INVALID_PARAMETER;
3518	}
3519
3520	if (!ppRtcHlp)
3521	{
3522	Assert(ppRtcHlp);
3523	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n",
3524	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3525	return VERR_INVALID_PARAMETER;
3526	}
3527
3528	/*
3529	* Only one DMA device.
3530	*/
3531	PVM const pVM = pDevIns->Internal.s.pVMR3;
3532	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
3533
3534	int rc = VINF_SUCCESS;
3535	if (!pVM->pdm.s.pRtc)
3536	{
3537	/*
3538	* Allocate and initialize pci bus structure.
3539	*/
3540	PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc));
3541	if (pRtc)
3542	{
3543	pRtc->pDevIns = pDevIns;
3544	pRtc->Reg = *pRtcReg;
3545	pVM->pdm.s.pRtc = pRtc;
3546
3547	/* set the helper pointer. */
3548	*ppRtcHlp = &g_pdmR3DevRtcHlp;
3549	Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n",
3550	pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3551	}
3552	else
3553	rc = VERR_NO_MEMORY;
3554	}
3555	else
3556	{
3557	AssertMsgFailed(("Only one RTC device is supported!\n"));
3558	rc = VERR_ALREADY_EXISTS;
3559	}
3560
3561	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
3562	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
3563	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3564	return rc;
3565	}
3566
3567
3568	/** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */
3569	static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
3570	{
3571	PDMDEV_ASSERT_DEVINS(pDevIns);
3572	PVM pVM = pDevIns->Internal.s.pVMR3;
3573	VM_ASSERT_EMT(pVM);
3574	LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n",
3575	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser));
3576	int rc = VINF_SUCCESS;
3577	PPDMDMAC const pDmac = pVM->pdm.s.pDmac;
3578	if (pDmac)
3579	pDmac->Reg.pfnRegister(pDmac->pDevIns, uChannel, pDevIns, pfnTransferHandler, pvUser);
3580	else
3581	{
3582	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
3583	rc = VERR_PDM_NO_DMAC_INSTANCE;
3584	}
3585	LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n",
3586	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3587	return rc;
3588	}
3589
3590
3591	/** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */
3592	static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
3593	{
3594	PDMDEV_ASSERT_DEVINS(pDevIns);
3595	PVM pVM = pDevIns->Internal.s.pVMR3;
3596	VM_ASSERT_EMT(pVM);
3597	LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n",
3598	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead));
3599	int rc = VINF_SUCCESS;
3600	PPDMDMAC const pDmac = pVM->pdm.s.pDmac;
3601	if (pDmac)
3602	{
3603	uint32_t cb = pDmac->Reg.pfnReadMemory(pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
3604	if (pcbRead)
3605	*pcbRead = cb;
3606	}
3607	else
3608	{
3609	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
3610	rc = VERR_PDM_NO_DMAC_INSTANCE;
3611	}
3612	LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n",
3613	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3614	return rc;
3615	}
3616
3617
3618	/** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */
3619	static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
3620	{
3621	PDMDEV_ASSERT_DEVINS(pDevIns);
3622	PVM pVM = pDevIns->Internal.s.pVMR3;
3623	VM_ASSERT_EMT(pVM);
3624	LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n",
3625	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten));
3626	int rc = VINF_SUCCESS;
3627	PPDMDMAC const pDmac = pVM->pdm.s.pDmac;
3628	if (pDmac)
3629	{
3630	uint32_t cb = pDmac->Reg.pfnWriteMemory(pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
3631	if (pcbWritten)
3632	*pcbWritten = cb;
3633	}
3634	else
3635	{
3636	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
3637	rc = VERR_PDM_NO_DMAC_INSTANCE;
3638	}
3639	LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n",
3640	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3641	return rc;
3642	}
3643
3644
3645	/** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */
3646	static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
3647	{
3648	PDMDEV_ASSERT_DEVINS(pDevIns);
3649	PVM pVM = pDevIns->Internal.s.pVMR3;
3650	VM_ASSERT_EMT(pVM);
3651	LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n",
3652	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, uLevel));
3653	int rc = VINF_SUCCESS;
3654	PPDMDMAC const pDmac = pVM->pdm.s.pDmac;
3655	if (pDmac)
3656	pDmac->Reg.pfnSetDREQ(pDmac->pDevIns, uChannel, uLevel);
3657	else
3658	{
3659	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
3660	rc = VERR_PDM_NO_DMAC_INSTANCE;
3661	}
3662	LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n",
3663	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3664	return rc;
3665	}
3666
3667	/** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */
3668	static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
3669	{
3670	PDMDEV_ASSERT_DEVINS(pDevIns);
3671	PVM pVM = pDevIns->Internal.s.pVMR3;
3672	VM_ASSERT_EMT(pVM);
3673	LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n",
3674	pDevIns->pReg->szName, pDevIns->iInstance, uChannel));
3675	uint8_t u8Mode;
3676	PPDMDMAC const pDmac = pVM->pdm.s.pDmac;
3677	if (pDmac)
3678	u8Mode = pDmac->Reg.pfnGetChannelMode(pDmac->pDevIns, uChannel);
3679	else
3680	{
3681	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
3682	u8Mode = 3 << 2 /* illegal mode type */;
3683	}
3684	LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n",
3685	pDevIns->pReg->szName, pDevIns->iInstance, u8Mode));
3686	return u8Mode;
3687	}
3688
3689	/** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */
3690	static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns)
3691	{
3692	PDMDEV_ASSERT_DEVINS(pDevIns);
3693	PVM pVM = pDevIns->Internal.s.pVMR3;
3694	VM_ASSERT_EMT(pVM);
3695	LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n",
3696	pDevIns->pReg->szName, pDevIns->iInstance, VM_FF_IS_SET(pVM, VM_FF_PDM_DMA)));
3697
3698	AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
3699	VM_FF_SET(pVM, VM_FF_PDM_DMA);
3700	VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM);
3701	}
3702
3703
3704	/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */
3705	static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
3706	{
3707	PDMDEV_ASSERT_DEVINS(pDevIns);
3708	PVM pVM = pDevIns->Internal.s.pVMR3;
3709	VM_ASSERT_EMT(pVM);
3710
3711	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n",
3712	pDevIns->pReg->szName, pDevIns->iInstance, iReg, u8Value));
3713	int rc;
3714	PPDMRTC const pRtc = pVM->pdm.s.pRtc;
3715	if (pRtc)
3716	{
3717	PPDMDEVINS const pDevInsRtc = pRtc->pDevIns;
3718	rc = PDMCritSectEnter(pVM, pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
3719	if (RT_SUCCESS(rc))
3720	{
3721	rc = pRtc->Reg.pfnWrite(pDevInsRtc, iReg, u8Value);
3722	PDMCritSectLeave(pVM, pDevInsRtc->pCritSectRoR3);
3723	}
3724	}
3725	else
3726	rc = VERR_PDM_NO_RTC_INSTANCE;
3727
3728	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
3729	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3730	return rc;
3731	}
3732
3733
3734	/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */
3735	static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
3736	{
3737	PDMDEV_ASSERT_DEVINS(pDevIns);
3738	PVM pVM = pDevIns->Internal.s.pVMR3;
3739	VM_ASSERT_EMT(pVM);
3740
3741	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n",
3742	pDevIns->pReg->szName, pDevIns->iInstance, iReg, pu8Value));
3743	int rc;
3744	PPDMRTC const pRtc = pVM->pdm.s.pRtc;
3745	if (pRtc)
3746	{
3747	PPDMDEVINS const pDevInsRtc = pRtc->pDevIns;
3748	rc = PDMCritSectEnter(pVM, pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
3749	if (RT_SUCCESS(rc))
3750	{
3751	rc = pRtc->Reg.pfnRead(pDevInsRtc, iReg, pu8Value);
3752	PDMCritSectLeave(pVM, pDevInsRtc->pCritSectRoR3);
3753	}
3754	}
3755	else
3756	rc = VERR_PDM_NO_RTC_INSTANCE;
3757
3758	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
3759	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3760	return rc;
3761	}
3762
3763
3764	/** @interface_method_impl{PDMDEVHLPR3,pfnAssertEMT} */
3765	static DECLCALLBACK(bool) pdmR3DevHlp_AssertEMT(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction)
3766	{
3767	PDMDEV_ASSERT_DEVINS(pDevIns);
3768	if (VM_IS_EMT(pDevIns->Internal.s.pVMR3))
3769	return true;
3770
3771	char szMsg[100];
3772	RTStrPrintf(szMsg, sizeof(szMsg), "AssertEMT '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
3773	RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
3774	AssertBreakpoint();
3775	return false;
3776	}
3777
3778
3779	/** @interface_method_impl{PDMDEVHLPR3,pfnAssertOther} */
3780	static DECLCALLBACK(bool) pdmR3DevHlp_AssertOther(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction)
3781	{
3782	PDMDEV_ASSERT_DEVINS(pDevIns);
3783	if (!VM_IS_EMT(pDevIns->Internal.s.pVMR3))
3784	return true;
3785
3786	char szMsg[100];
3787	RTStrPrintf(szMsg, sizeof(szMsg), "AssertOther '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
3788	RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
3789	AssertBreakpoint();
3790	return false;
3791	}
3792
3793
3794	/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetRCInterfaceSymbols} */
3795	static DECLCALLBACK(int) pdmR3DevHlp_LdrGetRCInterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3796	const char pszSymPrefix, const char pszSymList)
3797	{
3798	PDMDEV_ASSERT_DEVINS(pDevIns);
3799	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3800	LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
3801	pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
3802
3803	int rc;
3804	if ( strncmp(pszSymPrefix, "dev", 3) == 0
3805	&& RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
3806	{
3807	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
3808	rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
3809	pvInterface, cbInterface,
3810	pDevIns->pReg->pszRCMod, pDevIns->Internal.s.pDevR3->pszRCSearchPath,
3811	pszSymPrefix, pszSymList,
3812	false /fRing0OrRC/);
3813	else
3814	{
3815	AssertMsgFailed(("Not a raw-mode enabled driver\n"));
3816	rc = VERR_PERMISSION_DENIED;
3817	}
3818	}
3819	else
3820	{
3821	AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
3822	pszSymPrefix, pDevIns->pReg->szName));
3823	rc = VERR_INVALID_NAME;
3824	}
3825
3826	LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
3827	pDevIns->iInstance, rc));
3828	return rc;
3829	}
3830
3831
3832	/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetR0InterfaceSymbols} */
3833	static DECLCALLBACK(int) pdmR3DevHlp_LdrGetR0InterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3834	const char pszSymPrefix, const char pszSymList)
3835	{
3836	PDMDEV_ASSERT_DEVINS(pDevIns);
3837	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3838	LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
3839	pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
3840
3841	int rc;
3842	if ( strncmp(pszSymPrefix, "dev", 3) == 0
3843	&& RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
3844	{
3845	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
3846	rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
3847	pvInterface, cbInterface,
3848	pDevIns->pReg->pszR0Mod, pDevIns->Internal.s.pDevR3->pszR0SearchPath,
3849	pszSymPrefix, pszSymList,
3850	true /fRing0OrRC/);
3851	else
3852	{
3853	AssertMsgFailed(("Not a ring-0 enabled driver\n"));
3854	rc = VERR_PERMISSION_DENIED;
3855	}
3856	}
3857	else
3858	{
3859	AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
3860	pszSymPrefix, pDevIns->pReg->szName));
3861	rc = VERR_INVALID_NAME;
3862	}
3863
3864	LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
3865	pDevIns->iInstance, rc));
3866	return rc;
3867	}
3868
3869
3870	/** @interface_method_impl{PDMDEVHLPR3,pfnCallR0} */
3871	static DECLCALLBACK(int) pdmR3DevHlp_CallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
3872	{
3873	PDMDEV_ASSERT_DEVINS(pDevIns);
3874	PVM pVM = pDevIns->Internal.s.pVMR3;
3875	PVMCPU pVCpu = VMMGetCpu(pVM);
3876	AssertReturn(pVCpu, VERR_VM_THREAD_IS_EMT);
3877	LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: uOperation=%#x u64Arg=%#RX64\n",
3878	pDevIns->pReg->szName, pDevIns->iInstance, uOperation, u64Arg));
3879
3880	/*
3881	* Resolve the ring-0 entry point. There is not need to remember this like
3882	* we do for drivers since this is mainly for construction time hacks and
3883	* other things that aren't performance critical.
3884	*/
3885	int rc;
3886	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
3887	{
3888	/*
3889	* Make the ring-0 call.
3890	*/
3891	PDMDEVICEGENCALLREQ Req;
3892	RT_ZERO(Req.Params);
3893	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3894	Req.Hdr.cbReq = sizeof(Req);
3895	Req.pDevInsR3 = pDevIns;
3896	Req.idxR0Device = pDevIns->Internal.s.idxR0Device;
3897	Req.enmCall = PDMDEVICEGENCALL_REQUEST;
3898	Req.Params.Req.uReq = uOperation;
3899	Req.Params.Req.uArg = u64Arg;
3900	rc = VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_PDM_DEVICE_GEN_CALL, 0, &Req.Hdr);
3901	}
3902	else
3903	rc = VERR_ACCESS_DENIED;
3904	LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
3905	pDevIns->iInstance, rc));
3906	return rc;
3907	}
3908
3909
3910	/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetSuspendReason} */
3911	static DECLCALLBACK(VMSUSPENDREASON) pdmR3DevHlp_VMGetSuspendReason(PPDMDEVINS pDevIns)
3912	{
3913	PDMDEV_ASSERT_DEVINS(pDevIns);
3914	PVM pVM = pDevIns->Internal.s.pVMR3;
3915	VM_ASSERT_EMT(pVM);
3916	VMSUSPENDREASON enmReason = VMR3GetSuspendReason(pVM->pUVM);
3917	LogFlow(("pdmR3DevHlp_VMGetSuspendReason: caller='%s'/%d: returns %d\n",
3918	pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
3919	return enmReason;
3920	}
3921
3922
3923	/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetResumeReason} */
3924	static DECLCALLBACK(VMRESUMEREASON) pdmR3DevHlp_VMGetResumeReason(PPDMDEVINS pDevIns)
3925	{
3926	PDMDEV_ASSERT_DEVINS(pDevIns);
3927	PVM pVM = pDevIns->Internal.s.pVMR3;
3928	VM_ASSERT_EMT(pVM);
3929	VMRESUMEREASON enmReason = VMR3GetResumeReason(pVM->pUVM);
3930	LogFlow(("pdmR3DevHlp_VMGetResumeReason: caller='%s'/%d: returns %d\n",
3931	pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
3932	return enmReason;
3933	}
3934
3935
3936	/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
3937	static DECLCALLBACK(PUVM) pdmR3DevHlp_GetUVM(PPDMDEVINS pDevIns)
3938	{
3939	PDMDEV_ASSERT_DEVINS(pDevIns);
3940	LogFlow(("pdmR3DevHlp_GetUVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
3941	return pDevIns->Internal.s.pVMR3->pUVM;
3942	}
3943
3944
3945	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
3946	static DECLCALLBACK(PVM) pdmR3DevHlp_GetVM(PPDMDEVINS pDevIns)
3947	{
3948	PDMDEV_ASSERT_DEVINS(pDevIns);
3949	LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
3950	return pDevIns->Internal.s.pVMR3;
3951	}
3952
3953
3954	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
3955	static DECLCALLBACK(PVMCPU) pdmR3DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
3956	{
3957	PDMDEV_ASSERT_DEVINS(pDevIns);
3958	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3959	LogFlow(("pdmR3DevHlp_GetVMCPU: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, VMMGetCpuId(pDevIns->Internal.s.pVMR3)));
3960	return VMMGetCpu(pDevIns->Internal.s.pVMR3);
3961	}
3962
3963
3964	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
3965	static DECLCALLBACK(VMCPUID) pdmR3DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
3966	{
3967	PDMDEV_ASSERT_DEVINS(pDevIns);
3968	VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR3);
3969	LogFlow(("pdmR3DevHlp_GetCurrentCpuId: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, idCpu));
3970	return idCpu;
3971	}
3972
3973
3974	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */
3975	static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3976	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
3977	{
3978	PDMDEV_ASSERT_DEVINS(pDevIns);
3979	PVM pVM = pDevIns->Internal.s.pVMR3;
3980	VM_ASSERT_EMT(pVM);
3981	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
3982	".pfnInterceptConfigAccesses=%p, pfnConfigRead=%p, pfnConfigWrite=%p, .pfnSetIrqR3=%p, .u32EndVersion=%#x} ppPciHlpR3=%p piBus=%p\n",
3983	pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
3984	pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnInterceptConfigAccesses, pPciBusReg->pfnConfigRead,
3985	pPciBusReg->pfnConfigWrite, pPciBusReg->pfnSetIrqR3, pPciBusReg->u32EndVersion, ppPciHlp, piBus));
3986
3987	/*
3988	* Validate the structure and output parameters.
3989	*/
3990	AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGR3_VERSION,
3991	("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGR3_VERSION),
3992	VERR_INVALID_PARAMETER);
3993	AssertPtrReturn(pPciBusReg->pfnRegisterR3, VERR_INVALID_PARAMETER);
3994	AssertPtrNullReturn(pPciBusReg->pfnRegisterMsiR3, VERR_INVALID_POINTER);
3995	AssertPtrReturn(pPciBusReg->pfnIORegionRegisterR3, VERR_INVALID_POINTER);
3996	AssertPtrReturn(pPciBusReg->pfnInterceptConfigAccesses, VERR_INVALID_POINTER);
3997	AssertPtrReturn(pPciBusReg->pfnConfigWrite, VERR_INVALID_POINTER);
3998	AssertPtrReturn(pPciBusReg->pfnConfigRead, VERR_INVALID_POINTER);
3999	AssertPtrReturn(pPciBusReg->pfnSetIrqR3, VERR_INVALID_POINTER);
4000	AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGR3_VERSION,
4001	("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGR3_VERSION),
4002	VERR_INVALID_PARAMETER);
4003	AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
4004	AssertPtrNullReturn(piBus, VERR_INVALID_POINTER);
4005	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
4006
4007	/* Take the core lock exclusively just to be safe. */
4008	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4009
4010	/*
4011	* Find free PCI bus entry.
4012	*/
4013	unsigned iBus = 0;
4014	for (iBus = 0; iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses); iBus++)
4015	if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
4016	break;
4017	AssertLogRelMsgReturnStmt(iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
4018	("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)),
4019	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4020	VERR_OUT_OF_RESOURCES);
4021	PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
4022
4023	/*
4024	* Init the R3 bits.
4025	*/
4026	pPciBus->iBus = iBus;
4027	pPciBus->pDevInsR3 = pDevIns;
4028	pPciBus->pfnRegister = pPciBusReg->pfnRegisterR3;
4029	pPciBus->pfnRegisterMsi = pPciBusReg->pfnRegisterMsiR3;
4030	pPciBus->pfnIORegionRegister = pPciBusReg->pfnIORegionRegisterR3;
4031	pPciBus->pfnInterceptConfigAccesses = pPciBusReg->pfnInterceptConfigAccesses;
4032	pPciBus->pfnConfigRead = pPciBusReg->pfnConfigRead;
4033	pPciBus->pfnConfigWrite = pPciBusReg->pfnConfigWrite;
4034	pPciBus->pfnSetIrqR3 = pPciBusReg->pfnSetIrqR3;
4035
4036	Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
4037
4038	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4039
4040	/* set the helper pointer and return. */
4041	*ppPciHlp = &g_pdmR3DevPciHlp;
4042	if (piBus)
4043	*piBus = iBus;
4044	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc *piBus=%u\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS, iBus));
4045	return VINF_SUCCESS;
4046	}
4047
4048
4049	/** @interface_method_impl{PDMDEVHLPR3,pfnIommuRegister} */
4050	static DECLCALLBACK(int) pdmR3DevHlp_IommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4051	uint32_t *pidxIommu)
4052	{
4053	PDMDEV_ASSERT_DEVINS(pDevIns);
4054	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4055	LogFlow(("pdmR3DevHlp_IommuRegister: caller='%s'/%d: pIommuReg=%p:{.u32Version=%#x, .u32TheEnd=%#x } ppIommuHlp=%p\n",
4056	pDevIns->pReg->szName, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
4057	PVM pVM = pDevIns->Internal.s.pVMR3;
4058
4059	/*
4060	* Validate input.
4061	*/
4062	AssertMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGR3_VERSION,
4063	("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIommuReg->u32Version, PDM_IOMMUREGR3_VERSION),
4064	VERR_INVALID_PARAMETER);
4065	AssertPtrReturn(pIommuReg->pfnMemAccess, VERR_INVALID_POINTER);
4066	AssertPtrReturn(pIommuReg->pfnMemBulkAccess, VERR_INVALID_POINTER);
4067	AssertPtrReturn(pIommuReg->pfnMsiRemap, VERR_INVALID_POINTER);
4068	AssertMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGR3_VERSION,
4069	("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIommuReg->u32TheEnd, PDM_IOMMUREGR3_VERSION),
4070	VERR_INVALID_PARAMETER);
4071	AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
4072
4073	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
4074	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4075
4076	/* Take the core lock exclusively just to be safe. */
4077	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4078
4079	/*
4080	* Find free IOMMU slot.
4081	* The IOMMU at the root complex is the one at 0.
4082	*/
4083	unsigned idxIommu = 0;
4084	#if 0
4085	for (idxIommu = 0; idxIommu < RT_ELEMENTS(pVM->pdm.s.aIommus); idxIommu++)
4086	if (!pVM->pdm.s.aIommus[idxIommu].pDevInsR3)
4087	break;
4088	AssertLogRelMsgReturnStmt(idxIommu < RT_ELEMENTS(pVM->pdm.s.aIommus),
4089	("Too many IOMMUs. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aIommus)),
4090	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4091	VERR_OUT_OF_RESOURCES);
4092	#else
4093	/* Currently we support only a single IOMMU. */
4094	AssertMsgReturnStmt(!pVM->pdm.s.aIommus[idxIommu].pDevInsR3,
4095	("%s/%u: Only one IOMMU device is supported!\n", pDevIns->pReg->szName, pDevIns->iInstance),
4096	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4097	VERR_ALREADY_EXISTS);
4098	#endif
4099	PPDMIOMMUR3 pIommu = &pVM->pdm.s.aIommus[idxIommu];
4100
4101	/*
4102	* Init the R3 bits.
4103	*/
4104	pIommu->idxIommu = idxIommu;
4105	pIommu->pDevInsR3 = pDevIns;
4106	pIommu->pfnMemAccess = pIommuReg->pfnMemAccess;
4107	pIommu->pfnMemBulkAccess = pIommuReg->pfnMemBulkAccess;
4108	pIommu->pfnMsiRemap = pIommuReg->pfnMsiRemap;
4109	Log(("PDM: Registered IOMMU device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
4110
4111	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4112
4113	/* Set the helper pointer and return. */
4114	*ppIommuHlp = &g_pdmR3DevIommuHlp;
4115	if (pidxIommu)
4116	*pidxIommu = idxIommu;
4117	LogFlow(("pdmR3DevHlp_IommuRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
4118	return VINF_SUCCESS;
4119	}
4120
4121
4122
4123	/** @interface_method_impl{PDMDEVHLPR3,pfnPICRegister} */
4124	static DECLCALLBACK(int) pdmR3DevHlp_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
4125	{
4126	PDMDEV_ASSERT_DEVINS(pDevIns);
4127	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4128	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
4129	pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
4130	PVM pVM = pDevIns->Internal.s.pVMR3;
4131
4132	/*
4133	* Validate input.
4134	*/
4135	AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
4136	("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
4137	VERR_INVALID_PARAMETER);
4138	AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
4139	AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
4140	AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
4141	("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
4142	VERR_INVALID_PARAMETER);
4143	AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
4144
4145	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
4146	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4147
4148	/* Take the core lock exclusively just to be safe. */
4149	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4150
4151	/*
4152	* Only one PIC device.
4153	*/
4154	AssertMsgReturnStmt(pVM->pdm.s.Pic.pDevInsR3 == NULL,
4155	("%s/%d: Only one PIC!\n", pDevIns->pReg->szName, pDevIns->iInstance),
4156	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4157	VERR_ALREADY_EXISTS);
4158
4159	/*
4160	* Take down the callbacks and instance.
4161	*/
4162	pVM->pdm.s.Pic.pDevInsR3 = pDevIns;
4163	pVM->pdm.s.Pic.pfnSetIrqR3 = pPicReg->pfnSetIrq;
4164	pVM->pdm.s.Pic.pfnGetInterruptR3 = pPicReg->pfnGetInterrupt;
4165	Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
4166
4167	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4168
4169	/* set the helper pointer and return. */
4170	*ppPicHlp = &g_pdmR3DevPicHlp;
4171	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
4172	return VINF_SUCCESS;
4173	}
4174
4175
4176	/** @interface_method_impl{PDMDEVHLPR3,pfnApicRegister} */
4177	static DECLCALLBACK(int) pdmR3DevHlp_ApicRegister(PPDMDEVINS pDevIns)
4178	{
4179	PDMDEV_ASSERT_DEVINS(pDevIns);
4180
4181	/*
4182	* Validate caller context.
4183	*/
4184	PVM pVM = pDevIns->Internal.s.pVMR3;
4185	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
4186	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4187
4188	/* Take the core lock exclusively just to be safe. */
4189	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4190
4191	/*
4192	* Only one APIC device. On SMP we have single logical device covering all LAPICs,
4193	* as they need to communicate and share state easily.
4194	*/
4195	AssertMsgReturnStmt(pVM->pdm.s.Apic.pDevInsR3 == NULL,
4196	("%s/%u: Only one APIC device is supported!\n", pDevIns->pReg->szName, pDevIns->iInstance),
4197	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4198	VERR_ALREADY_EXISTS);
4199
4200	/*
4201	* Set the ring-3 and raw-mode bits, leave the ring-0 to ring-0 setup.
4202	*/
4203	pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
4204	#ifdef VBOX_WITH_RAW_MODE_KEEP
4205	pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4206	Assert(pVM->pdm.s.Apic.pDevInsRC \|\| !VM_IS_RAW_MODE_ENABLED(pVM));
4207	#endif
4208
4209	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4210
4211	LogFlow(("pdmR3DevHlp_ApicRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
4212	return VINF_SUCCESS;
4213	}
4214
4215
4216	/** @interface_method_impl{PDMDEVHLPR3,pfnIoApicRegister} */
4217	static DECLCALLBACK(int) pdmR3DevHlp_IoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
4218	{
4219	PDMDEV_ASSERT_DEVINS(pDevIns);
4220	LogFlow(("pdmR3DevHlp_IoApicRegister: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
4221	pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
4222	PVM pVM = pDevIns->Internal.s.pVMR3;
4223
4224	/*
4225	* Validate input.
4226	*/
4227	AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
4228	("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
4229	VERR_VERSION_MISMATCH);
4230	AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
4231	AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
4232	AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
4233	AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
4234	("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
4235	VERR_VERSION_MISMATCH);
4236	AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
4237	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
4238	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4239
4240	/* Take the core lock exclusively just to be safe. */
4241	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4242
4243	/*
4244	* The I/O APIC requires the APIC to be present (hacks++).
4245	* If the I/O APIC does GC stuff so must the APIC.
4246	*/
4247	AssertMsgReturnStmt(pVM->pdm.s.Apic.pDevInsR3 != NULL,
4248	("Configuration error / Init order error! No APIC!\n"),
4249	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4250	VERR_WRONG_ORDER);
4251
4252	/*
4253	* Only one I/O APIC device.
4254	*/
4255	AssertMsgReturnStmt(pVM->pdm.s.IoApic.pDevInsR3 == NULL,
4256	("Only one IOAPIC device is supported! (caller %s/%d)\n", pDevIns->pReg->szName, pDevIns->iInstance),
4257	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4258	VERR_ALREADY_EXISTS);
4259
4260	/*
4261	* Initialize the R3 bits.
4262	*/
4263	pVM->pdm.s.IoApic.pDevInsR3 = pDevIns;
4264	pVM->pdm.s.IoApic.pfnSetIrqR3 = pIoApicReg->pfnSetIrq;
4265	pVM->pdm.s.IoApic.pfnSendMsiR3 = pIoApicReg->pfnSendMsi;
4266	pVM->pdm.s.IoApic.pfnSetEoiR3 = pIoApicReg->pfnSetEoi;
4267	Log(("PDM: Registered I/O APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
4268
4269	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4270
4271	/* set the helper pointer and return. */
4272	*ppIoApicHlp = &g_pdmR3DevIoApicHlp;
4273	LogFlow(("pdmR3DevHlp_IoApicRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
4274	return VINF_SUCCESS;
4275	}
4276
4277
4278	/** @interface_method_impl{PDMDEVHLPR3,pfnHpetRegister} */
4279	static DECLCALLBACK(int) pdmR3DevHlp_HpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
4280	{
4281	PDMDEV_ASSERT_DEVINS(pDevIns);
4282	LogFlow(("pdmR3DevHlp_HpetRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
4283	PVM pVM = pDevIns->Internal.s.pVMR3;
4284
4285	/*
4286	* Validate input.
4287	*/
4288	AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
4289	("%s/%u: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
4290	VERR_VERSION_MISMATCH);
4291	AssertPtrReturn(ppHpetHlpR3, VERR_INVALID_POINTER);
4292	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
4293	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4294
4295	/*
4296	* Only one HPET device.
4297	*/
4298	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4299
4300	AssertMsgReturnStmt(pVM->pdm.s.pHpet == NULL,
4301	("Only one HPET device is supported! (caller %s/%d)\n", pDevIns->pReg->szName, pDevIns->iInstance),
4302	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
4303	VERR_ALREADY_EXISTS);
4304
4305	/*
4306	* Do the job (what there is of it).
4307	*/
4308	pVM->pdm.s.pHpet = pDevIns;
4309
4310	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4311
4312	*ppHpetHlpR3 = &g_pdmR3DevHpetHlp;
4313
4314	LogFlow(("pdmR3DevHlp_HpetRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
4315	return VINF_SUCCESS;
4316	}
4317
4318
4319	/** @interface_method_impl{PDMDEVHLPR3,pfnPciRawRegister} */
4320	static DECLCALLBACK(int) pdmR3DevHlp_PciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
4321	{
4322	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
4323	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4324	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
4325
4326	/*
4327	* Validate input.
4328	*/
4329	if (pPciRawReg->u32Version != PDM_PCIRAWREG_VERSION)
4330	{
4331	AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciRawReg->u32Version, PDM_PCIRAWREG_VERSION));
4332	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4333	return VERR_INVALID_PARAMETER;
4334	}
4335
4336	if (!ppPciRawHlpR3)
4337	{
4338	Assert(ppPciRawHlpR3);
4339	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (ppPciRawHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4340	return VERR_INVALID_PARAMETER;
4341	}
4342
4343	/* set the helper pointer and return. */
4344	*ppPciRawHlpR3 = &g_pdmR3DevPciRawHlp;
4345	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
4346	return VINF_SUCCESS;
4347	}
4348
4349
4350	/** @interface_method_impl{PDMDEVHLPR3,pfnDMACRegister} */
4351	static DECLCALLBACK(int) pdmR3DevHlp_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
4352	{
4353	PDMDEV_ASSERT_DEVINS(pDevIns);
4354	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4355	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: pDmacReg=%p:{.u32Version=%#x, .pfnRun=%p, .pfnRegister=%p, .pfnReadMemory=%p, .pfnWriteMemory=%p, .pfnSetDREQ=%p, .pfnGetChannelMode=%p} ppDmacHlp=%p\n",
4356	pDevIns->pReg->szName, pDevIns->iInstance, pDmacReg, pDmacReg->u32Version, pDmacReg->pfnRun, pDmacReg->pfnRegister,
4357	pDmacReg->pfnReadMemory, pDmacReg->pfnWriteMemory, pDmacReg->pfnSetDREQ, pDmacReg->pfnGetChannelMode, ppDmacHlp));
4358
4359	/*
4360	* Validate input.
4361	*/
4362	if (pDmacReg->u32Version != PDM_DMACREG_VERSION)
4363	{
4364	AssertMsgFailed(("u32Version=%#x expected %#x\n", pDmacReg->u32Version,
4365	PDM_DMACREG_VERSION));
4366	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (version)\n",
4367	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4368	return VERR_INVALID_PARAMETER;
4369	}
4370	if ( !pDmacReg->pfnRun
4371	\|\| !pDmacReg->pfnRegister
4372	\|\| !pDmacReg->pfnReadMemory
4373	\|\| !pDmacReg->pfnWriteMemory
4374	\|\| !pDmacReg->pfnSetDREQ
4375	\|\| !pDmacReg->pfnGetChannelMode)
4376	{
4377	Assert(pDmacReg->pfnRun);
4378	Assert(pDmacReg->pfnRegister);
4379	Assert(pDmacReg->pfnReadMemory);
4380	Assert(pDmacReg->pfnWriteMemory);
4381	Assert(pDmacReg->pfnSetDREQ);
4382	Assert(pDmacReg->pfnGetChannelMode);
4383	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
4384	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4385	return VERR_INVALID_PARAMETER;
4386	}
4387
4388	if (!ppDmacHlp)
4389	{
4390	Assert(ppDmacHlp);
4391	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (ppDmacHlp)\n",
4392	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4393	return VERR_INVALID_PARAMETER;
4394	}
4395
4396	/*
4397	* Only one DMA device.
4398	*/
4399	PVM const pVM = pDevIns->Internal.s.pVMR3;
4400	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4401
4402	int rc = VINF_SUCCESS;
4403	if (!pVM->pdm.s.pDmac)
4404	{
4405
4406	/*
4407	* Allocate and initialize pci bus structure.
4408	*/
4409	PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pDmac));
4410	if (pDmac)
4411	{
4412	pDmac->pDevIns = pDevIns;
4413	pDmac->Reg = *pDmacReg;
4414	pVM->pdm.s.pDmac = pDmac;
4415
4416	/* set the helper pointer. */
4417	*ppDmacHlp = &g_pdmR3DevDmacHlp;
4418	Log(("PDM: Registered DMAC device '%s'/%d pDevIns=%p\n",
4419	pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
4420	}
4421	else
4422	rc = VERR_NO_MEMORY;
4423	}
4424	else
4425	{
4426	AssertMsgFailed(("Only one DMA device is supported!\n"));
4427	rc = VERR_ALREADY_EXISTS;
4428	}
4429
4430	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4431	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
4432	pDevIns->pReg->szName, pDevIns->iInstance, rc));
4433	return rc;
4434	}
4435
4436
4437	/**
4438	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
4439	*/
4440	static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
4441	{
4442	PDMDEV_ASSERT_DEVINS(pDevIns);
4443	PVM pVM = pDevIns->Internal.s.pVMR3;
4444	VM_ASSERT_EMT(pVM);
4445	LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: GCPhys=%RGp pvHeap=%p cbHeap=%#x\n",
4446	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvHeap, cbHeap));
4447
4448	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4449	if (pVM->pdm.s.pvVMMDevHeap == NULL)
4450	{
4451	pVM->pdm.s.pvVMMDevHeap = pvHeap;
4452	pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
4453	pVM->pdm.s.cbVMMDevHeap = cbHeap;
4454	pVM->pdm.s.cbVMMDevHeapLeft = cbHeap;
4455	}
4456	else
4457	{
4458	Assert(pVM->pdm.s.pvVMMDevHeap == pvHeap);
4459	Assert(pVM->pdm.s.cbVMMDevHeap == cbHeap);
4460	Assert(pVM->pdm.s.GCPhysVMMDevHeap != GCPhys \|\| GCPhys == NIL_RTGCPHYS);
4461	if (pVM->pdm.s.GCPhysVMMDevHeap != GCPhys)
4462	{
4463	pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
4464	PFNPDMVMMDEVHEAPNOTIFY const pfnVMMDevHeapNotify = pVM->pdm.s.pfnVMMDevHeapNotify;
4465	if (pfnVMMDevHeapNotify)
4466	pfnVMMDevHeapNotify(pVM, pvHeap, GCPhys);
4467	}
4468	}
4469	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4470
4471	LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: returns %Rrc\n",
4472	pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
4473	return VINF_SUCCESS;
4474	}
4475
4476
4477	/**
4478	* @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister}
4479	*/
4480	static DECLCALLBACK(int) pdmR3DevHlp_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
4481	{
4482	PDMDEV_ASSERT_DEVINS(pDevIns);
4483	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4484	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: pFWReg=%p:{.u32Version=%#x, .pfnIsHardReset=%p, .u32TheEnd=%#x} ppFwHlp=%p\n",
4485	pDevIns->pReg->szName, pDevIns->iInstance, pFwReg, pFwReg->u32Version, pFwReg->pfnIsHardReset, pFwReg->u32TheEnd, ppFwHlp));
4486
4487	/*
4488	* Validate input.
4489	*/
4490	if (pFwReg->u32Version != PDM_FWREG_VERSION)
4491	{
4492	AssertMsgFailed(("u32Version=%#x expected %#x\n", pFwReg->u32Version, PDM_FWREG_VERSION));
4493	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (version)\n",
4494	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4495	return VERR_INVALID_PARAMETER;
4496	}
4497	if (!pFwReg->pfnIsHardReset)
4498	{
4499	Assert(pFwReg->pfnIsHardReset);
4500	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
4501	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4502	return VERR_INVALID_PARAMETER;
4503	}
4504
4505	if (!ppFwHlp)
4506	{
4507	Assert(ppFwHlp);
4508	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (ppFwHlp)\n",
4509	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
4510	return VERR_INVALID_PARAMETER;
4511	}
4512
4513	/*
4514	* Only one firmware registration.
4515	*/
4516	PVM const pVM = pDevIns->Internal.s.pVMR3;
4517	RTCritSectRwEnterExcl(&pVM->pdm.s.CoreListCritSectRw);
4518
4519	int rc = VINF_SUCCESS;
4520	if (!pVM->pdm.s.pFirmware)
4521	{
4522	/*
4523	* Allocate and initialize pci bus structure.
4524	*/
4525	PPDMFW pFirmware = (PPDMFW)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pFirmware));
4526	if (pFirmware)
4527	{
4528	pFirmware->pDevIns = pDevIns;
4529	pFirmware->Reg = *pFwReg;
4530	pVM->pdm.s.pFirmware = pFirmware;
4531
4532	/* set the helper pointer. */
4533	*ppFwHlp = &g_pdmR3DevFirmwareHlp;
4534	Log(("PDM: Registered firmware device '%s'/%d pDevIns=%p\n",
4535	pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
4536	}
4537	else
4538	rc = VERR_NO_MEMORY;
4539	}
4540	else
4541	{
4542	AssertMsgFailed(("Only one firmware device is supported!\n"));
4543	rc = VERR_ALREADY_EXISTS;
4544	}
4545
4546	RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
4547	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc\n",
4548	pDevIns->pReg->szName, pDevIns->iInstance, rc));
4549	return rc;
4550	}
4551
4552
4553	/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
4554	static DECLCALLBACK(int) pdmR3DevHlp_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
4555	{
4556	PDMDEV_ASSERT_DEVINS(pDevIns);
4557	PVM pVM = pDevIns->Internal.s.pVMR3;
4558	VM_ASSERT_EMT(pVM);
4559	LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: fFlags=%#x VM_FF_RESET %d -> 1\n",
4560	pDevIns->pReg->szName, pDevIns->iInstance, fFlags, VM_FF_IS_SET(pVM, VM_FF_RESET)));
4561
4562	/*
4563	* We postpone this operation because we're likely to be inside a I/O instruction
4564	* and the EIP will be updated when we return.
4565	* We still return VINF_EM_RESET to break out of any execution loops and force FF evaluation.
4566	*/
4567	bool fHaltOnReset;
4568	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
4569	if (RT_SUCCESS(rc) && fHaltOnReset)
4570	{
4571	Log(("pdmR3DevHlp_VMReset: Halt On Reset!\n"));
4572	rc = VINF_EM_HALT;
4573	}
4574	else
4575	{
4576	pVM->pdm.s.fResetFlags = fFlags;
4577	VM_FF_SET(pVM, VM_FF_RESET);
4578	rc = VINF_EM_RESET;
4579	}
4580
4581	LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4582	return rc;
4583	}
4584
4585
4586	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
4587	static DECLCALLBACK(int) pdmR3DevHlp_VMSuspend(PPDMDEVINS pDevIns)
4588	{
4589	int rc;
4590	PDMDEV_ASSERT_DEVINS(pDevIns);
4591	PVM pVM = pDevIns->Internal.s.pVMR3;
4592	VM_ASSERT_EMT(pVM);
4593	LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d:\n",
4594	pDevIns->pReg->szName, pDevIns->iInstance));
4595
4596	/** @todo Always take the SMP path - fewer code paths. */
4597	if (pVM->cCpus > 1)
4598	{
4599	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
4600	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3Suspend, 2, pVM->pUVM, VMSUSPENDREASON_VM);
4601	AssertRC(rc);
4602	rc = VINF_EM_SUSPEND;
4603	}
4604	else
4605	rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
4606
4607	LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4608	return rc;
4609	}
4610
4611
4612	/**
4613	* Worker for pdmR3DevHlp_VMSuspendSaveAndPowerOff that is invoked via a queued
4614	* EMT request to avoid deadlocks.
4615	*
4616	* @returns VBox status code fit for scheduling.
4617	* @param pVM The cross context VM structure.
4618	* @param pDevIns The device that triggered this action.
4619	*/
4620	static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker(PVM pVM, PPDMDEVINS pDevIns)
4621	{
4622	/*
4623	* Suspend the VM first then do the saving.
4624	*/
4625	int rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
4626	if (RT_SUCCESS(rc))
4627	{
4628	PUVM pUVM = pVM->pUVM;
4629	rc = pUVM->pVmm2UserMethods->pfnSaveState(pVM->pUVM->pVmm2UserMethods, pUVM);
4630
4631	/*
4632	* On success, power off the VM, on failure we'll leave it suspended.
4633	*/
4634	if (RT_SUCCESS(rc))
4635	{
4636	rc = VMR3PowerOff(pVM->pUVM);
4637	if (RT_FAILURE(rc))
4638	LogRel(("%s/SSP: VMR3PowerOff failed: %Rrc\n", pDevIns->pReg->szName, rc));
4639	}
4640	else
4641	LogRel(("%s/SSP: pfnSaveState failed: %Rrc\n", pDevIns->pReg->szName, rc));
4642	}
4643	else
4644	LogRel(("%s/SSP: Suspend failed: %Rrc\n", pDevIns->pReg->szName, rc));
4645	return rc;
4646	}
4647
4648
4649	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
4650	static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
4651	{
4652	PDMDEV_ASSERT_DEVINS(pDevIns);
4653	PVM pVM = pDevIns->Internal.s.pVMR3;
4654	VM_ASSERT_EMT(pVM);
4655	LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d:\n",
4656	pDevIns->pReg->szName, pDevIns->iInstance));
4657
4658	int rc;
4659	if ( pVM->pUVM->pVmm2UserMethods
4660	&& pVM->pUVM->pVmm2UserMethods->pfnSaveState)
4661	{
4662	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker, 2, pVM, pDevIns);
4663	if (RT_SUCCESS(rc))
4664	{
4665	LogRel(("%s: Suspending, Saving and Powering Off the VM\n", pDevIns->pReg->szName));
4666	rc = VINF_EM_SUSPEND;
4667	}
4668	}
4669	else
4670	rc = VERR_NOT_SUPPORTED;
4671
4672	LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4673	return rc;
4674	}
4675
4676
4677	/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
4678	static DECLCALLBACK(int) pdmR3DevHlp_VMPowerOff(PPDMDEVINS pDevIns)
4679	{
4680	int rc;
4681	PDMDEV_ASSERT_DEVINS(pDevIns);
4682	PVM pVM = pDevIns->Internal.s.pVMR3;
4683	VM_ASSERT_EMT(pVM);
4684	LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d:\n",
4685	pDevIns->pReg->szName, pDevIns->iInstance));
4686
4687	/** @todo Always take the SMP path - fewer code paths. */
4688	if (pVM->cCpus > 1)
4689	{
4690	/* We might be holding locks here and could cause a deadlock since
4691	VMR3PowerOff rendezvous with the other CPUs. */
4692	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3PowerOff, 1, pVM->pUVM);
4693	AssertRC(rc);
4694	/* Set the VCPU state to stopped here as well to make sure no
4695	inconsistency with the EM state occurs. */
4696	VMCPU_SET_STATE(VMMGetCpu(pVM), VMCPUSTATE_STOPPED);
4697	rc = VINF_EM_OFF;
4698	}
4699	else
4700	rc = VMR3PowerOff(pVM->pUVM);
4701
4702	LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4703	return rc;
4704	}
4705
4706
4707	/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
4708	static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
4709	{
4710	PDMDEV_ASSERT_DEVINS(pDevIns);
4711	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4712
4713	bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3));
4714
4715	LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pReg->szName, pDevIns->iInstance, fRc));
4716	return fRc;
4717	}
4718
4719
4720	/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
4721	static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable)
4722	{
4723	PDMDEV_ASSERT_DEVINS(pDevIns);
4724	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4725	LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, fEnable));
4726	#ifdef VBOX_VMM_TARGET_ARMV8
4727	AssertReleaseFailed();
4728	RT_NOREF(pDevIns, fEnable);
4729	#else
4730	PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable);
4731	#endif
4732	}
4733
4734
4735	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
4736	static DECLCALLBACK(void) pdmR3DevHlp_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
4737	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
4738	{
4739	PDMDEV_ASSERT_DEVINS(pDevIns);
4740	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4741
4742	LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: iLeaf=%d pEax=%p pEbx=%p pEcx=%p pEdx=%p\n",
4743	pDevIns->pReg->szName, pDevIns->iInstance, iLeaf, pEax, pEbx, pEcx, pEdx));
4744	AssertPtr(pEax); AssertPtr(pEbx); AssertPtr(pEcx); AssertPtr(pEdx);
4745
4746	#ifdef VBOX_VMM_TARGET_ARMV8
4747	RT_NOREF(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
4748	AssertReleaseFailed();
4749	#else
4750	CPUMGetGuestCpuId(VMMGetCpu(pDevIns->Internal.s.pVMR3), iLeaf, 0 /iSubLeaf/, -1 /f64BitMode/, pEax, pEbx, pEcx, pEdx);
4751	#endif
4752
4753	LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - pEax=%#x pEbx=%#x pEcx=%#x pEdx=%#x\n",
4754	pDevIns->pReg->szName, pDevIns->iInstance, pEax, pEbx, pEcx, pEdx));
4755	}
4756
4757
4758	/** @interface_method_impl{PDMDEVHLPR3,pfnGetMainExecutionEngine} */
4759	static DECLCALLBACK(uint8_t) pdmR3DevHlp_GetMainExecutionEngine(PPDMDEVINS pDevIns)
4760	{
4761	PDMDEV_ASSERT_DEVINS(pDevIns);
4762	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
4763	LogFlow(("pdmR3DevHlp_GetMainExecutionEngine: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
4764	return pDevIns->Internal.s.pVMR3->bMainExecutionEngine;
4765	}
4766
4767
4768	/** @interface_method_impl{PDMDEVHLPR3,pfnVMMRegisterPatchMemory} */
4769	static DECLCALLBACK(int) pdmR3DevHlp_VMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
4770	{
4771	PDMDEV_ASSERT_DEVINS(pDevIns);
4772
4773	LogFlow(("pdmR3DevHlp_VMMRegisterPatchMemory: caller='%s'/%d: GCPtrPatchMem=%RGv cbPatchMem=%RU32\n",
4774	pDevIns->pReg->szName, pDevIns->iInstance, GCPtrPatchMem, cbPatchMem));
4775
4776	int rc = VMMR3RegisterPatchMemory(pDevIns->Internal.s.pVMR3, GCPtrPatchMem, cbPatchMem);
4777
4778	LogFlow(("pdmR3DevHlp_VMMRegisterPatchMemory: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4779	return rc;
4780	}
4781
4782
4783	/** @interface_method_impl{PDMDEVHLPR3,pfnVMMDeregisterPatchMemory} */
4784	static DECLCALLBACK(int) pdmR3DevHlp_VMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
4785	{
4786	PDMDEV_ASSERT_DEVINS(pDevIns);
4787
4788	LogFlow(("pdmR3DevHlp_VMMDeregisterPatchMemory: caller='%s'/%d: GCPtrPatchMem=%RGv cbPatchMem=%RU32\n",
4789	pDevIns->pReg->szName, pDevIns->iInstance, GCPtrPatchMem, cbPatchMem));
4790
4791	int rc = VMMR3DeregisterPatchMemory(pDevIns->Internal.s.pVMR3, GCPtrPatchMem, cbPatchMem);
4792
4793	LogFlow(("pdmR3DevHlp_VMMDeregisterPatchMemory: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4794	return rc;
4795	}
4796
4797
4798	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleRegister} */
4799	static DECLCALLBACK(int) pdmR3DevHlp_SharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4800	RTGCPTR GCBaseAddr, uint32_t cbModule,
4801	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
4802	{
4803	PDMDEV_ASSERT_DEVINS(pDevIns);
4804
4805	LogFlow(("pdmR3DevHlp_SharedModuleRegister: caller='%s'/%d: enmGuestOS=%u pszModuleName=%p:{%s} pszVersion=%p:{%s} GCBaseAddr=%RGv cbModule=%#x cRegions=%u paRegions=%p\n",
4806	pDevIns->pReg->szName, pDevIns->iInstance, enmGuestOS, pszModuleName, pszModuleName, pszVersion, pszVersion, GCBaseAddr, cbModule, cRegions, paRegions));
4807
4808	#ifdef VBOX_WITH_PAGE_SHARING
4809	int rc = PGMR3SharedModuleRegister(pDevIns->Internal.s.pVMR3, enmGuestOS, pszModuleName, pszVersion,
4810	GCBaseAddr, cbModule, cRegions, paRegions);
4811	#else
4812	RT_NOREF(pDevIns, enmGuestOS, pszModuleName, pszVersion, GCBaseAddr, cbModule, cRegions, paRegions);
4813	int rc = VERR_NOT_SUPPORTED;
4814	#endif
4815
4816	LogFlow(("pdmR3DevHlp_SharedModuleRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4817	return rc;
4818	}
4819
4820
4821	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleUnregister} */
4822	static DECLCALLBACK(int) pdmR3DevHlp_SharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
4823	RTGCPTR GCBaseAddr, uint32_t cbModule)
4824	{
4825	PDMDEV_ASSERT_DEVINS(pDevIns);
4826
4827	LogFlow(("pdmR3DevHlp_SharedModuleUnregister: caller='%s'/%d: pszModuleName=%p:{%s} pszVersion=%p:{%s} GCBaseAddr=%RGv cbModule=%#x\n",
4828	pDevIns->pReg->szName, pDevIns->iInstance, pszModuleName, pszModuleName, pszVersion, pszVersion, GCBaseAddr, cbModule));
4829
4830	#ifdef VBOX_WITH_PAGE_SHARING
4831	int rc = PGMR3SharedModuleUnregister(pDevIns->Internal.s.pVMR3, pszModuleName, pszVersion, GCBaseAddr, cbModule);
4832	#else
4833	RT_NOREF(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
4834	int rc = VERR_NOT_SUPPORTED;
4835	#endif
4836
4837	LogFlow(("pdmR3DevHlp_SharedModuleUnregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4838	return rc;
4839	}
4840
4841
4842	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleGetPageState} */
4843	static DECLCALLBACK(int) pdmR3DevHlp_SharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags)
4844	{
4845	PDMDEV_ASSERT_DEVINS(pDevIns);
4846
4847	LogFlow(("pdmR3DevHlp_SharedModuleGetPageState: caller='%s'/%d: GCPtrPage=%RGv pfShared=%p pfPageFlags=%p\n",
4848	pDevIns->pReg->szName, pDevIns->iInstance, GCPtrPage, pfShared, pfPageFlags));
4849
4850	#if defined(VBOX_WITH_PAGE_SHARING) && defined(DEBUG)
4851	int rc = PGMR3SharedModuleGetPageState(pDevIns->Internal.s.pVMR3, GCPtrPage, pfShared, pfPageFlags);
4852	#else
4853	RT_NOREF(pDevIns, GCPtrPage, pfShared, pfPageFlags);
4854	int rc = VERR_NOT_IMPLEMENTED;
4855	#endif
4856
4857	LogFlow(("pdmR3DevHlp_SharedModuleGetPageState: caller='%s'/%d: returns %Rrc pfShared=%RTbool pfPageFlags=%#RX64\n",
4858	pDevIns->pReg->szName, pDevIns->iInstance, rc, pfShared, pfPageFlags));
4859	return rc;
4860	}
4861
4862
4863	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleCheckAll} */
4864	static DECLCALLBACK(int) pdmR3DevHlp_SharedModuleCheckAll(PPDMDEVINS pDevIns)
4865	{
4866	PDMDEV_ASSERT_DEVINS(pDevIns);
4867
4868	LogFlow(("pdmR3DevHlp_SharedModuleCheckAll: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
4869
4870	#ifdef VBOX_WITH_PAGE_SHARING
4871	int rc = PGMR3SharedModuleCheckAll(pDevIns->Internal.s.pVMR3);
4872	#else
4873	RT_NOREF(pDevIns);
4874	int rc = VERR_NOT_SUPPORTED;
4875	#endif
4876
4877	LogFlow(("pdmR3DevHlp_SharedModuleCheckAll: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4878	return rc;
4879	}
4880
4881
4882	/** @interface_method_impl{PDMDEVHLPR3,pfnQueryLun} */
4883	static DECLCALLBACK(int) pdmR3DevHlp_QueryLun(PPDMDEVINS pDevIns, const char *pszDevice,
4884	unsigned iInstance, unsigned iLun, PPDMIBASE *ppBase)
4885	{
4886	PDMDEV_ASSERT_DEVINS(pDevIns);
4887
4888	LogFlow(("pdmR3DevHlp_QueryLun: caller='%s'/%d: pszDevice=%p:{%s} iInstance=%u iLun=%u ppBase=%p\n",
4889	pDevIns->pReg->szName, pDevIns->iInstance, pszDevice, pszDevice, iInstance, iLun, ppBase));
4890
4891	int rc = PDMR3QueryLun(pDevIns->Internal.s.pVMR3->pUVM, pszDevice, iInstance, iLun, ppBase);
4892
4893	LogFlow(("pdmR3DevHlp_QueryLun: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4894	return rc;
4895	}
4896
4897
4898	/** @interface_method_impl{PDMDEVHLPR3,pfnGIMDeviceRegister} */
4899	static DECLCALLBACK(void) pdmR3DevHlp_GIMDeviceRegister(PPDMDEVINS pDevIns, PGIMDEBUG pDbg)
4900	{
4901	PDMDEV_ASSERT_DEVINS(pDevIns);
4902
4903	LogFlow(("pdmR3DevHlp_GIMDeviceRegister: caller='%s'/%d: pDbg=%p\n",
4904	pDevIns->pReg->szName, pDevIns->iInstance, pDbg));
4905
4906	GIMR3GimDeviceRegister(pDevIns->Internal.s.pVMR3, pDevIns, pDbg);
4907
4908	LogFlow(("pdmR3DevHlp_GIMDeviceRegister: caller='%s'/%d: returns\n", pDevIns->pReg->szName, pDevIns->iInstance));
4909	}
4910
4911
4912	/** @interface_method_impl{PDMDEVHLPR3,pfnGIMGetDebugSetup} */
4913	static DECLCALLBACK(int) pdmR3DevHlp_GIMGetDebugSetup(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup)
4914	{
4915	PDMDEV_ASSERT_DEVINS(pDevIns);
4916
4917	LogFlow(("pdmR3DevHlp_GIMGetDebugSetup: caller='%s'/%d: pDbgSetup=%p\n",
4918	pDevIns->pReg->szName, pDevIns->iInstance, pDbgSetup));
4919
4920	int rc = GIMR3GetDebugSetup(pDevIns->Internal.s.pVMR3, pDbgSetup);
4921
4922	LogFlow(("pdmR3DevHlp_GIMGetDebugSetup: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
4923	return rc;
4924	}
4925
4926
4927	/** @interface_method_impl{PDMDEVHLPR3,pfnGIMGetMmio2Regions} */
4928	static DECLCALLBACK(PGIMMMIO2REGION) pdmR3DevHlp_GIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
4929	{
4930	PDMDEV_ASSERT_DEVINS(pDevIns);
4931
4932	LogFlow(("pdmR3DevHlp_GIMGetMmio2Regions: caller='%s'/%d: pcRegions=%p\n",
4933	pDevIns->pReg->szName, pDevIns->iInstance, pcRegions));
4934
4935	PGIMMMIO2REGION pRegion = GIMGetMmio2Regions(pDevIns->Internal.s.pVMR3, pcRegions);
4936
4937	LogFlow(("pdmR3DevHlp_GIMGetMmio2Regions: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRegion));
4938	return pRegion;
4939	}
4940
4941
4942	/**
4943	* The device helper structure for trusted devices.
4944	*/
4945	const PDMDEVHLPR3 g_pdmR3DevHlpTrusted =
4946	{
4947	PDM_DEVHLPR3_VERSION,
4948	pdmR3DevHlp_IoPortCreateEx,
4949	pdmR3DevHlp_IoPortMap,
4950	pdmR3DevHlp_IoPortUnmap,
4951	pdmR3DevHlp_IoPortGetMappingAddress,
4952	pdmR3DevHlp_IoPortRead,
4953	pdmR3DevHlp_IoPortWrite,
4954	pdmR3DevHlp_MmioCreateEx,
4955	pdmR3DevHlp_MmioMap,
4956	pdmR3DevHlp_MmioUnmap,
4957	pdmR3DevHlp_MmioReduce,
4958	pdmR3DevHlp_MmioGetMappingAddress,
4959	pdmR3DevHlp_Mmio2Create,
4960	pdmR3DevHlp_Mmio2Destroy,
4961	pdmR3DevHlp_Mmio2Map,
4962	pdmR3DevHlp_Mmio2Unmap,
4963	pdmR3DevHlp_Mmio2Reduce,
4964	pdmR3DevHlp_Mmio2GetMappingAddress,
4965	pdmR3DevHlp_Mmio2QueryAndResetDirtyBitmap,
4966	pdmR3DevHlp_Mmio2ControlDirtyPageTracking,
4967	pdmR3DevHlp_Mmio2ChangeRegionNo,
4968	pdmR3DevHlp_MmioMapMmio2Page,
4969	pdmR3DevHlp_MmioResetRegion,
4970	pdmR3DevHlp_ROMRegister,
4971	pdmR3DevHlp_ROMProtectShadow,
4972	pdmR3DevHlp_SSMRegister,
4973	pdmR3DevHlp_SSMRegisterLegacy,
4974	SSMR3PutStruct,
4975	SSMR3PutStructEx,
4976	SSMR3PutBool,
4977	SSMR3PutU8,
4978	SSMR3PutS8,
4979	SSMR3PutU16,
4980	SSMR3PutS16,
4981	SSMR3PutU32,
4982	SSMR3PutS32,
4983	SSMR3PutU64,
4984	SSMR3PutS64,
4985	SSMR3PutU128,
4986	SSMR3PutS128,
4987	SSMR3PutUInt,
4988	SSMR3PutSInt,
4989	SSMR3PutGCUInt,
4990	SSMR3PutGCUIntReg,
4991	SSMR3PutGCPhys32,
4992	SSMR3PutGCPhys64,
4993	SSMR3PutGCPhys,
4994	SSMR3PutGCPtr,
4995	SSMR3PutGCUIntPtr,
4996	SSMR3PutRCPtr,
4997	SSMR3PutIOPort,
4998	SSMR3PutSel,
4999	SSMR3PutMem,
5000	SSMR3PutStrZ,
5001	SSMR3GetStruct,
5002	SSMR3GetStructEx,
5003	SSMR3GetBool,
5004	SSMR3GetBoolV,
5005	SSMR3GetU8,
5006	SSMR3GetU8V,
5007	SSMR3GetS8,
5008	SSMR3GetS8V,
5009	SSMR3GetU16,
5010	SSMR3GetU16V,
5011	SSMR3GetS16,
5012	SSMR3GetS16V,
5013	SSMR3GetU32,
5014	SSMR3GetU32V,
5015	SSMR3GetS32,
5016	SSMR3GetS32V,
5017	SSMR3GetU64,
5018	SSMR3GetU64V,
5019	SSMR3GetS64,
5020	SSMR3GetS64V,
5021	SSMR3GetU128,
5022	SSMR3GetU128V,
5023	SSMR3GetS128,
5024	SSMR3GetS128V,
5025	SSMR3GetGCPhys32,
5026	SSMR3GetGCPhys32V,
5027	SSMR3GetGCPhys64,
5028	SSMR3GetGCPhys64V,
5029	SSMR3GetGCPhys,
5030	SSMR3GetGCPhysV,
5031	SSMR3GetUInt,
5032	SSMR3GetSInt,
5033	SSMR3GetGCUInt,
5034	SSMR3GetGCUIntReg,
5035	SSMR3GetGCPtr,
5036	SSMR3GetGCUIntPtr,
5037	SSMR3GetRCPtr,
5038	SSMR3GetIOPort,
5039	SSMR3GetSel,
5040	SSMR3GetMem,
5041	SSMR3GetStrZ,
5042	SSMR3GetStrZEx,
5043	SSMR3Skip,
5044	SSMR3SkipToEndOfUnit,
5045	SSMR3SetLoadError,
5046	SSMR3SetLoadErrorV,
5047	SSMR3SetCfgError,
5048	SSMR3SetCfgErrorV,
5049	SSMR3HandleGetStatus,
5050	SSMR3HandleGetAfter,
5051	SSMR3HandleIsLiveSave,
5052	SSMR3HandleMaxDowntime,
5053	SSMR3HandleHostBits,
5054	SSMR3HandleRevision,
5055	SSMR3HandleVersion,
5056	SSMR3HandleHostOSAndArch,
5057	pdmR3DevHlp_TimerCreate,
5058	pdmR3DevHlp_TimerFromMicro,
5059	pdmR3DevHlp_TimerFromMilli,
5060	pdmR3DevHlp_TimerFromNano,
5061	pdmR3DevHlp_TimerGet,
5062	pdmR3DevHlp_TimerGetFreq,
5063	pdmR3DevHlp_TimerGetNano,
5064	pdmR3DevHlp_TimerIsActive,
5065	pdmR3DevHlp_TimerIsLockOwner,
5066	pdmR3DevHlp_TimerLockClock,
5067	pdmR3DevHlp_TimerLockClock2,
5068	pdmR3DevHlp_TimerSet,
5069	pdmR3DevHlp_TimerSetFrequencyHint,
5070	pdmR3DevHlp_TimerSetMicro,
5071	pdmR3DevHlp_TimerSetMillies,
5072	pdmR3DevHlp_TimerSetNano,
5073	pdmR3DevHlp_TimerSetRelative,
5074	pdmR3DevHlp_TimerStop,
5075	pdmR3DevHlp_TimerUnlockClock,
5076	pdmR3DevHlp_TimerUnlockClock2,
5077	pdmR3DevHlp_TimerSetCritSect,
5078	pdmR3DevHlp_TimerSave,
5079	pdmR3DevHlp_TimerLoad,
5080	pdmR3DevHlp_TimerDestroy,
5081	TMR3TimerSkip,
5082	pdmR3DevHlp_TMUtcNow,
5083	CFGMR3Exists,
5084	CFGMR3QueryType,
5085	CFGMR3QuerySize,
5086	CFGMR3QueryInteger,
5087	CFGMR3QueryIntegerDef,
5088	CFGMR3QueryString,
5089	CFGMR3QueryStringDef,
5090	CFGMR3QueryPassword,
5091	CFGMR3QueryPasswordDef,
5092	CFGMR3QueryBytes,
5093	CFGMR3QueryU64,
5094	CFGMR3QueryU64Def,
5095	CFGMR3QueryS64,
5096	CFGMR3QueryS64Def,
5097	CFGMR3QueryU32,
5098	CFGMR3QueryU32Def,
5099	CFGMR3QueryS32,
5100	CFGMR3QueryS32Def,
5101	CFGMR3QueryU16,
5102	CFGMR3QueryU16Def,
5103	CFGMR3QueryS16,
5104	CFGMR3QueryS16Def,
5105	CFGMR3QueryU8,
5106	CFGMR3QueryU8Def,
5107	CFGMR3QueryS8,
5108	CFGMR3QueryS8Def,
5109	CFGMR3QueryBool,
5110	CFGMR3QueryBoolDef,
5111	CFGMR3QueryPort,
5112	CFGMR3QueryPortDef,
5113	CFGMR3QueryUInt,
5114	CFGMR3QueryUIntDef,
5115	CFGMR3QuerySInt,
5116	CFGMR3QuerySIntDef,
5117	CFGMR3QueryGCPtr,
5118	CFGMR3QueryGCPtrDef,
5119	CFGMR3QueryGCPtrU,
5120	CFGMR3QueryGCPtrUDef,
5121	CFGMR3QueryGCPtrS,
5122	CFGMR3QueryGCPtrSDef,
5123	CFGMR3QueryStringAlloc,
5124	CFGMR3QueryStringAllocDef,
5125	CFGMR3GetParent,
5126	CFGMR3GetChild,
5127	CFGMR3GetChildF,
5128	CFGMR3GetChildFV,
5129	CFGMR3GetFirstChild,
5130	CFGMR3GetNextChild,
5131	CFGMR3GetName,
5132	CFGMR3GetNameLen,
5133	CFGMR3AreChildrenValid,
5134	CFGMR3GetFirstValue,
5135	CFGMR3GetNextValue,
5136	CFGMR3GetValueName,
5137	CFGMR3GetValueNameLen,
5138	CFGMR3GetValueType,
5139	CFGMR3AreValuesValid,
5140	CFGMR3ValidateConfig,
5141	pdmR3DevHlp_PhysRead,
5142	pdmR3DevHlp_PhysWrite,
5143	pdmR3DevHlp_PhysGCPhys2CCPtr,
5144	pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
5145	pdmR3DevHlp_PhysReleasePageMappingLock,
5146	pdmR3DevHlp_PhysReadGCVirt,
5147	pdmR3DevHlp_PhysWriteGCVirt,
5148	pdmR3DevHlp_PhysGCPtr2GCPhys,
5149	pdmR3DevHlp_PhysIsGCPhysNormal,
5150	pdmR3DevHlp_PhysChangeMemBalloon,
5151	pdmR3DevHlp_MMHeapAlloc,
5152	pdmR3DevHlp_MMHeapAllocZ,
5153	pdmR3DevHlp_MMHeapAPrintfV,
5154	pdmR3DevHlp_MMHeapFree,
5155	pdmR3DevHlp_MMPhysGetRamSize,
5156	pdmR3DevHlp_MMPhysGetRamSizeBelow4GB,
5157	pdmR3DevHlp_MMPhysGetRamSizeAbove4GB,
5158	pdmR3DevHlp_VMState,
5159	pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
5160	pdmR3DevHlp_VMSetErrorV,
5161	pdmR3DevHlp_VMSetRuntimeErrorV,
5162	pdmR3DevHlp_VMWaitForDeviceReady,
5163	pdmR3DevHlp_VMNotifyCpuDeviceReady,
5164	pdmR3DevHlp_VMReqCallNoWaitV,
5165	pdmR3DevHlp_VMReqPriorityCallWaitV,
5166	pdmR3DevHlp_DBGFStopV,
5167	pdmR3DevHlp_DBGFInfoRegister,
5168	pdmR3DevHlp_DBGFInfoRegisterArgv,
5169	pdmR3DevHlp_DBGFRegRegister,
5170	pdmR3DevHlp_DBGFTraceBuf,
5171	pdmR3DevHlp_DBGFReportBugCheck,
5172	pdmR3DevHlp_DBGFCoreWrite,
5173	pdmR3DevHlp_DBGFInfoLogHlp,
5174	pdmR3DevHlp_DBGFRegNmQueryU64,
5175	pdmR3DevHlp_DBGFRegPrintfV,
5176	pdmR3DevHlp_STAMRegister,
5177	pdmR3DevHlp_STAMRegisterV,
5178	pdmR3DevHlp_PCIRegister,
5179	pdmR3DevHlp_PCIRegisterMsi,
5180	pdmR3DevHlp_PCIIORegionRegister,
5181	pdmR3DevHlp_PCIInterceptConfigAccesses,
5182	pdmR3DevHlp_PCIConfigWrite,
5183	pdmR3DevHlp_PCIConfigRead,
5184	pdmR3DevHlp_PCIPhysRead,
5185	pdmR3DevHlp_PCIPhysWrite,
5186	pdmR3DevHlp_PCIPhysGCPhys2CCPtr,
5187	pdmR3DevHlp_PCIPhysGCPhys2CCPtrReadOnly,
5188	pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtr,
5189	pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtrReadOnly,
5190	pdmR3DevHlp_PCISetIrq,
5191	pdmR3DevHlp_PCISetIrqNoWait,
5192	pdmR3DevHlp_ISASetIrq,
5193	pdmR3DevHlp_ISASetIrqNoWait,
5194	pdmR3DevHlp_DriverAttach,
5195	pdmR3DevHlp_DriverDetach,
5196	pdmR3DevHlp_DriverReconfigure,
5197	pdmR3DevHlp_QueueCreate,
5198	pdmR3DevHlp_QueueAlloc,
5199	pdmR3DevHlp_QueueInsert,
5200	pdmR3DevHlp_QueueFlushIfNecessary,
5201	pdmR3DevHlp_TaskCreate,
5202	pdmR3DevHlp_TaskTrigger,
5203	pdmR3DevHlp_SUPSemEventCreate,
5204	pdmR3DevHlp_SUPSemEventClose,
5205	pdmR3DevHlp_SUPSemEventSignal,
5206	pdmR3DevHlp_SUPSemEventWaitNoResume,
5207	pdmR3DevHlp_SUPSemEventWaitNsAbsIntr,
5208	pdmR3DevHlp_SUPSemEventWaitNsRelIntr,
5209	pdmR3DevHlp_SUPSemEventGetResolution,
5210	pdmR3DevHlp_SUPSemEventMultiCreate,
5211	pdmR3DevHlp_SUPSemEventMultiClose,
5212	pdmR3DevHlp_SUPSemEventMultiSignal,
5213	pdmR3DevHlp_SUPSemEventMultiReset,
5214	pdmR3DevHlp_SUPSemEventMultiWaitNoResume,
5215	pdmR3DevHlp_SUPSemEventMultiWaitNsAbsIntr,
5216	pdmR3DevHlp_SUPSemEventMultiWaitNsRelIntr,
5217	pdmR3DevHlp_SUPSemEventMultiGetResolution,
5218	pdmR3DevHlp_CritSectInit,
5219	pdmR3DevHlp_CritSectGetNop,
5220	pdmR3DevHlp_SetDeviceCritSect,
5221	pdmR3DevHlp_CritSectYield,
5222	pdmR3DevHlp_CritSectEnter,
5223	pdmR3DevHlp_CritSectEnterDebug,
5224	pdmR3DevHlp_CritSectTryEnter,
5225	pdmR3DevHlp_CritSectTryEnterDebug,
5226	pdmR3DevHlp_CritSectLeave,
5227	pdmR3DevHlp_CritSectIsOwner,
5228	pdmR3DevHlp_CritSectIsInitialized,
5229	pdmR3DevHlp_CritSectHasWaiters,
5230	pdmR3DevHlp_CritSectGetRecursion,
5231	pdmR3DevHlp_CritSectScheduleExitEvent,
5232	pdmR3DevHlp_CritSectDelete,
5233	pdmR3DevHlp_CritSectRwInit,
5234	pdmR3DevHlp_CritSectRwDelete,
5235	pdmR3DevHlp_CritSectRwEnterShared,
5236	pdmR3DevHlp_CritSectRwEnterSharedDebug,
5237	pdmR3DevHlp_CritSectRwTryEnterShared,
5238	pdmR3DevHlp_CritSectRwTryEnterSharedDebug,
5239	pdmR3DevHlp_CritSectRwLeaveShared,
5240	pdmR3DevHlp_CritSectRwEnterExcl,
5241	pdmR3DevHlp_CritSectRwEnterExclDebug,
5242	pdmR3DevHlp_CritSectRwTryEnterExcl,
5243	pdmR3DevHlp_CritSectRwTryEnterExclDebug,
5244	pdmR3DevHlp_CritSectRwLeaveExcl,
5245	pdmR3DevHlp_CritSectRwIsWriteOwner,
5246	pdmR3DevHlp_CritSectRwIsReadOwner,
5247	pdmR3DevHlp_CritSectRwGetWriteRecursion,
5248	pdmR3DevHlp_CritSectRwGetWriterReadRecursion,
5249	pdmR3DevHlp_CritSectRwGetReadCount,
5250	pdmR3DevHlp_CritSectRwIsInitialized,
5251	pdmR3DevHlp_ThreadCreate,
5252	PDMR3ThreadDestroy,
5253	PDMR3ThreadIAmSuspending,
5254	PDMR3ThreadIAmRunning,
5255	PDMR3ThreadSleep,
5256	PDMR3ThreadSuspend,
5257	PDMR3ThreadResume,
5258	pdmR3DevHlp_SetAsyncNotification,
5259	pdmR3DevHlp_AsyncNotificationCompleted,
5260	pdmR3DevHlp_RTCRegister,
5261	pdmR3DevHlp_PCIBusRegister,
5262	pdmR3DevHlp_IommuRegister,
5263	pdmR3DevHlp_PICRegister,
5264	pdmR3DevHlp_ApicRegister,
5265	pdmR3DevHlp_IoApicRegister,
5266	pdmR3DevHlp_HpetRegister,
5267	pdmR3DevHlp_PciRawRegister,
5268	pdmR3DevHlp_DMACRegister,
5269	pdmR3DevHlp_DMARegister,
5270	pdmR3DevHlp_DMAReadMemory,
5271	pdmR3DevHlp_DMAWriteMemory,
5272	pdmR3DevHlp_DMASetDREQ,
5273	pdmR3DevHlp_DMAGetChannelMode,
5274	pdmR3DevHlp_DMASchedule,
5275	pdmR3DevHlp_CMOSWrite,
5276	pdmR3DevHlp_CMOSRead,
5277	pdmR3DevHlp_AssertEMT,
5278	pdmR3DevHlp_AssertOther,
5279	pdmR3DevHlp_LdrGetRCInterfaceSymbols,
5280	pdmR3DevHlp_LdrGetR0InterfaceSymbols,
5281	pdmR3DevHlp_CallR0,
5282	pdmR3DevHlp_VMGetSuspendReason,
5283	pdmR3DevHlp_VMGetResumeReason,
5284	pdmR3DevHlp_PhysBulkGCPhys2CCPtr,
5285	pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly,
5286	pdmR3DevHlp_PhysBulkReleasePageMappingLocks,
5287	pdmR3DevHlp_CpuGetGuestArch,
5288	pdmR3DevHlp_CpuGetGuestMicroarch,
5289	pdmR3DevHlp_CpuGetGuestAddrWidths,
5290	pdmR3DevHlp_CpuGetGuestScalableBusFrequency,
5291	pdmR3DevHlp_STAMDeregisterByPrefix,
5292	0,
5293	0,
5294	0,
5295	0,
5296	0,
5297	0,
5298	0,
5299	0,
5300	0,
5301	pdmR3DevHlp_GetUVM,
5302	pdmR3DevHlp_GetVM,
5303	pdmR3DevHlp_GetVMCPU,
5304	pdmR3DevHlp_GetCurrentCpuId,
5305	pdmR3DevHlp_RegisterVMMDevHeap,
5306	pdmR3DevHlp_FirmwareRegister,
5307	pdmR3DevHlp_VMReset,
5308	pdmR3DevHlp_VMSuspend,
5309	pdmR3DevHlp_VMSuspendSaveAndPowerOff,
5310	pdmR3DevHlp_VMPowerOff,
5311	pdmR3DevHlp_A20IsEnabled,
5312	pdmR3DevHlp_A20Set,
5313	pdmR3DevHlp_GetCpuId,
5314	pdmR3DevHlp_GetMainExecutionEngine,
5315	pdmR3DevHlp_TMTimeVirtGet,
5316	pdmR3DevHlp_TMTimeVirtGetFreq,
5317	pdmR3DevHlp_TMTimeVirtGetNano,
5318	pdmR3DevHlp_TMCpuTicksPerSecond,
5319	pdmR3DevHlp_GetSupDrvSession,
5320	pdmR3DevHlp_QueryGenericUserObject,
5321	pdmR3DevHlp_PGMHandlerPhysicalTypeRegister,
5322	pdmR3DevHlp_PGMHandlerPhysicalRegister,
5323	pdmR3DevHlp_PGMHandlerPhysicalDeregister,
5324	pdmR3DevHlp_PGMHandlerPhysicalPageTempOff,
5325	pdmR3DevHlp_PGMHandlerPhysicalReset,
5326	pdmR3DevHlp_VMMRegisterPatchMemory,
5327	pdmR3DevHlp_VMMDeregisterPatchMemory,
5328	pdmR3DevHlp_SharedModuleRegister,
5329	pdmR3DevHlp_SharedModuleUnregister,
5330	pdmR3DevHlp_SharedModuleGetPageState,
5331	pdmR3DevHlp_SharedModuleCheckAll,
5332	pdmR3DevHlp_QueryLun,
5333	pdmR3DevHlp_GIMDeviceRegister,
5334	pdmR3DevHlp_GIMGetDebugSetup,
5335	pdmR3DevHlp_GIMGetMmio2Regions,
5336	PDM_DEVHLPR3_VERSION /* the end */
5337	};
5338
5339
5340	#ifdef VBOX_WITH_DBGF_TRACING
5341	/**
5342	* The device helper structure for trusted devices - tracing variant.
5343	*/
5344	const PDMDEVHLPR3 g_pdmR3DevHlpTracing =
5345	{
5346	PDM_DEVHLPR3_VERSION,
5347	pdmR3DevHlpTracing_IoPortCreateEx,
5348	pdmR3DevHlpTracing_IoPortMap,
5349	pdmR3DevHlpTracing_IoPortUnmap,
5350	pdmR3DevHlp_IoPortGetMappingAddress,
5351	pdmR3DevHlp_IoPortRead, /** @todo Needs tracing variants for ARM now. */
5352	pdmR3DevHlp_IoPortWrite, /** @todo Needs tracing variants for ARM now. */
5353	pdmR3DevHlpTracing_MmioCreateEx,
5354	pdmR3DevHlpTracing_MmioMap,
5355	pdmR3DevHlpTracing_MmioUnmap,
5356	pdmR3DevHlp_MmioReduce,
5357	pdmR3DevHlp_MmioGetMappingAddress,
5358	pdmR3DevHlp_Mmio2Create,
5359	pdmR3DevHlp_Mmio2Destroy,
5360	pdmR3DevHlp_Mmio2Map,
5361	pdmR3DevHlp_Mmio2Unmap,
5362	pdmR3DevHlp_Mmio2Reduce,
5363	pdmR3DevHlp_Mmio2GetMappingAddress,
5364	pdmR3DevHlp_Mmio2QueryAndResetDirtyBitmap,
5365	pdmR3DevHlp_Mmio2ControlDirtyPageTracking,
5366	pdmR3DevHlp_Mmio2ChangeRegionNo,
5367	pdmR3DevHlp_MmioMapMmio2Page,
5368	pdmR3DevHlp_MmioResetRegion,
5369	pdmR3DevHlp_ROMRegister,
5370	pdmR3DevHlp_ROMProtectShadow,
5371	pdmR3DevHlp_SSMRegister,
5372	pdmR3DevHlp_SSMRegisterLegacy,
5373	SSMR3PutStruct,
5374	SSMR3PutStructEx,
5375	SSMR3PutBool,
5376	SSMR3PutU8,
5377	SSMR3PutS8,
5378	SSMR3PutU16,
5379	SSMR3PutS16,
5380	SSMR3PutU32,
5381	SSMR3PutS32,
5382	SSMR3PutU64,
5383	SSMR3PutS64,
5384	SSMR3PutU128,
5385	SSMR3PutS128,
5386	SSMR3PutUInt,
5387	SSMR3PutSInt,
5388	SSMR3PutGCUInt,
5389	SSMR3PutGCUIntReg,
5390	SSMR3PutGCPhys32,
5391	SSMR3PutGCPhys64,
5392	SSMR3PutGCPhys,
5393	SSMR3PutGCPtr,
5394	SSMR3PutGCUIntPtr,
5395	SSMR3PutRCPtr,
5396	SSMR3PutIOPort,
5397	SSMR3PutSel,
5398	SSMR3PutMem,
5399	SSMR3PutStrZ,
5400	SSMR3GetStruct,
5401	SSMR3GetStructEx,
5402	SSMR3GetBool,
5403	SSMR3GetBoolV,
5404	SSMR3GetU8,
5405	SSMR3GetU8V,
5406	SSMR3GetS8,
5407	SSMR3GetS8V,
5408	SSMR3GetU16,
5409	SSMR3GetU16V,
5410	SSMR3GetS16,
5411	SSMR3GetS16V,
5412	SSMR3GetU32,
5413	SSMR3GetU32V,
5414	SSMR3GetS32,
5415	SSMR3GetS32V,
5416	SSMR3GetU64,
5417	SSMR3GetU64V,
5418	SSMR3GetS64,
5419	SSMR3GetS64V,
5420	SSMR3GetU128,
5421	SSMR3GetU128V,
5422	SSMR3GetS128,
5423	SSMR3GetS128V,
5424	SSMR3GetGCPhys32,
5425	SSMR3GetGCPhys32V,
5426	SSMR3GetGCPhys64,
5427	SSMR3GetGCPhys64V,
5428	SSMR3GetGCPhys,
5429	SSMR3GetGCPhysV,
5430	SSMR3GetUInt,
5431	SSMR3GetSInt,
5432	SSMR3GetGCUInt,
5433	SSMR3GetGCUIntReg,
5434	SSMR3GetGCPtr,
5435	SSMR3GetGCUIntPtr,
5436	SSMR3GetRCPtr,
5437	SSMR3GetIOPort,
5438	SSMR3GetSel,
5439	SSMR3GetMem,
5440	SSMR3GetStrZ,
5441	SSMR3GetStrZEx,
5442	SSMR3Skip,
5443	SSMR3SkipToEndOfUnit,
5444	SSMR3SetLoadError,
5445	SSMR3SetLoadErrorV,
5446	SSMR3SetCfgError,
5447	SSMR3SetCfgErrorV,
5448	SSMR3HandleGetStatus,
5449	SSMR3HandleGetAfter,
5450	SSMR3HandleIsLiveSave,
5451	SSMR3HandleMaxDowntime,
5452	SSMR3HandleHostBits,
5453	SSMR3HandleRevision,
5454	SSMR3HandleVersion,
5455	SSMR3HandleHostOSAndArch,
5456	pdmR3DevHlp_TimerCreate,
5457	pdmR3DevHlp_TimerFromMicro,
5458	pdmR3DevHlp_TimerFromMilli,
5459	pdmR3DevHlp_TimerFromNano,
5460	pdmR3DevHlp_TimerGet,
5461	pdmR3DevHlp_TimerGetFreq,
5462	pdmR3DevHlp_TimerGetNano,
5463	pdmR3DevHlp_TimerIsActive,
5464	pdmR3DevHlp_TimerIsLockOwner,
5465	pdmR3DevHlp_TimerLockClock,
5466	pdmR3DevHlp_TimerLockClock2,
5467	pdmR3DevHlp_TimerSet,
5468	pdmR3DevHlp_TimerSetFrequencyHint,
5469	pdmR3DevHlp_TimerSetMicro,
5470	pdmR3DevHlp_TimerSetMillies,
5471	pdmR3DevHlp_TimerSetNano,
5472	pdmR3DevHlp_TimerSetRelative,
5473	pdmR3DevHlp_TimerStop,
5474	pdmR3DevHlp_TimerUnlockClock,
5475	pdmR3DevHlp_TimerUnlockClock2,
5476	pdmR3DevHlp_TimerSetCritSect,
5477	pdmR3DevHlp_TimerSave,
5478	pdmR3DevHlp_TimerLoad,
5479	pdmR3DevHlp_TimerDestroy,
5480	TMR3TimerSkip,
5481	pdmR3DevHlp_TMUtcNow,
5482	CFGMR3Exists,
5483	CFGMR3QueryType,
5484	CFGMR3QuerySize,
5485	CFGMR3QueryInteger,
5486	CFGMR3QueryIntegerDef,
5487	CFGMR3QueryString,
5488	CFGMR3QueryStringDef,
5489	CFGMR3QueryPassword,
5490	CFGMR3QueryPasswordDef,
5491	CFGMR3QueryBytes,
5492	CFGMR3QueryU64,
5493	CFGMR3QueryU64Def,
5494	CFGMR3QueryS64,
5495	CFGMR3QueryS64Def,
5496	CFGMR3QueryU32,
5497	CFGMR3QueryU32Def,
5498	CFGMR3QueryS32,
5499	CFGMR3QueryS32Def,
5500	CFGMR3QueryU16,
5501	CFGMR3QueryU16Def,
5502	CFGMR3QueryS16,
5503	CFGMR3QueryS16Def,
5504	CFGMR3QueryU8,
5505	CFGMR3QueryU8Def,
5506	CFGMR3QueryS8,
5507	CFGMR3QueryS8Def,
5508	CFGMR3QueryBool,
5509	CFGMR3QueryBoolDef,
5510	CFGMR3QueryPort,
5511	CFGMR3QueryPortDef,
5512	CFGMR3QueryUInt,
5513	CFGMR3QueryUIntDef,
5514	CFGMR3QuerySInt,
5515	CFGMR3QuerySIntDef,
5516	CFGMR3QueryGCPtr,
5517	CFGMR3QueryGCPtrDef,
5518	CFGMR3QueryGCPtrU,
5519	CFGMR3QueryGCPtrUDef,
5520	CFGMR3QueryGCPtrS,
5521	CFGMR3QueryGCPtrSDef,
5522	CFGMR3QueryStringAlloc,
5523	CFGMR3QueryStringAllocDef,
5524	CFGMR3GetParent,
5525	CFGMR3GetChild,
5526	CFGMR3GetChildF,
5527	CFGMR3GetChildFV,
5528	CFGMR3GetFirstChild,
5529	CFGMR3GetNextChild,
5530	CFGMR3GetName,
5531	CFGMR3GetNameLen,
5532	CFGMR3AreChildrenValid,
5533	CFGMR3GetFirstValue,
5534	CFGMR3GetNextValue,
5535	CFGMR3GetValueName,
5536	CFGMR3GetValueNameLen,
5537	CFGMR3GetValueType,
5538	CFGMR3AreValuesValid,
5539	CFGMR3ValidateConfig,
5540	pdmR3DevHlpTracing_PhysRead,
5541	pdmR3DevHlpTracing_PhysWrite,
5542	pdmR3DevHlp_PhysGCPhys2CCPtr,
5543	pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
5544	pdmR3DevHlp_PhysReleasePageMappingLock,
5545	pdmR3DevHlp_PhysReadGCVirt,
5546	pdmR3DevHlp_PhysWriteGCVirt,
5547	pdmR3DevHlp_PhysGCPtr2GCPhys,
5548	pdmR3DevHlp_PhysIsGCPhysNormal,
5549	pdmR3DevHlp_PhysChangeMemBalloon,
5550	pdmR3DevHlp_MMHeapAlloc,
5551	pdmR3DevHlp_MMHeapAllocZ,
5552	pdmR3DevHlp_MMHeapAPrintfV,
5553	pdmR3DevHlp_MMHeapFree,
5554	pdmR3DevHlp_MMPhysGetRamSize,
5555	pdmR3DevHlp_MMPhysGetRamSizeBelow4GB,
5556	pdmR3DevHlp_MMPhysGetRamSizeAbove4GB,
5557	pdmR3DevHlp_VMState,
5558	pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
5559	pdmR3DevHlp_VMSetErrorV,
5560	pdmR3DevHlp_VMSetRuntimeErrorV,
5561	pdmR3DevHlp_VMWaitForDeviceReady,
5562	pdmR3DevHlp_VMNotifyCpuDeviceReady,
5563	pdmR3DevHlp_VMReqCallNoWaitV,
5564	pdmR3DevHlp_VMReqPriorityCallWaitV,
5565	pdmR3DevHlp_DBGFStopV,
5566	pdmR3DevHlp_DBGFInfoRegister,
5567	pdmR3DevHlp_DBGFInfoRegisterArgv,
5568	pdmR3DevHlp_DBGFRegRegister,
5569	pdmR3DevHlp_DBGFTraceBuf,
5570	pdmR3DevHlp_DBGFReportBugCheck,
5571	pdmR3DevHlp_DBGFCoreWrite,
5572	pdmR3DevHlp_DBGFInfoLogHlp,
5573	pdmR3DevHlp_DBGFRegNmQueryU64,
5574	pdmR3DevHlp_DBGFRegPrintfV,
5575	pdmR3DevHlp_STAMRegister,
5576	pdmR3DevHlp_STAMRegisterV,
5577	pdmR3DevHlp_PCIRegister,
5578	pdmR3DevHlp_PCIRegisterMsi,
5579	pdmR3DevHlp_PCIIORegionRegister,
5580	pdmR3DevHlp_PCIInterceptConfigAccesses,
5581	pdmR3DevHlp_PCIConfigWrite,
5582	pdmR3DevHlp_PCIConfigRead,
5583	pdmR3DevHlpTracing_PCIPhysRead,
5584	pdmR3DevHlpTracing_PCIPhysWrite,
5585	pdmR3DevHlp_PCIPhysGCPhys2CCPtr,
5586	pdmR3DevHlp_PCIPhysGCPhys2CCPtrReadOnly,
5587	pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtr,
5588	pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtrReadOnly,
5589	pdmR3DevHlpTracing_PCISetIrq,
5590	pdmR3DevHlpTracing_PCISetIrqNoWait,
5591	pdmR3DevHlpTracing_ISASetIrq,
5592	pdmR3DevHlpTracing_ISASetIrqNoWait,
5593	pdmR3DevHlp_DriverAttach,
5594	pdmR3DevHlp_DriverDetach,
5595	pdmR3DevHlp_DriverReconfigure,
5596	pdmR3DevHlp_QueueCreate,
5597	pdmR3DevHlp_QueueAlloc,
5598	pdmR3DevHlp_QueueInsert,
5599	pdmR3DevHlp_QueueFlushIfNecessary,
5600	pdmR3DevHlp_TaskCreate,
5601	pdmR3DevHlp_TaskTrigger,
5602	pdmR3DevHlp_SUPSemEventCreate,
5603	pdmR3DevHlp_SUPSemEventClose,
5604	pdmR3DevHlp_SUPSemEventSignal,
5605	pdmR3DevHlp_SUPSemEventWaitNoResume,
5606	pdmR3DevHlp_SUPSemEventWaitNsAbsIntr,
5607	pdmR3DevHlp_SUPSemEventWaitNsRelIntr,
5608	pdmR3DevHlp_SUPSemEventGetResolution,
5609	pdmR3DevHlp_SUPSemEventMultiCreate,
5610	pdmR3DevHlp_SUPSemEventMultiClose,
5611	pdmR3DevHlp_SUPSemEventMultiSignal,
5612	pdmR3DevHlp_SUPSemEventMultiReset,
5613	pdmR3DevHlp_SUPSemEventMultiWaitNoResume,
5614	pdmR3DevHlp_SUPSemEventMultiWaitNsAbsIntr,
5615	pdmR3DevHlp_SUPSemEventMultiWaitNsRelIntr,
5616	pdmR3DevHlp_SUPSemEventMultiGetResolution,
5617	pdmR3DevHlp_CritSectInit,
5618	pdmR3DevHlp_CritSectGetNop,
5619	pdmR3DevHlp_SetDeviceCritSect,
5620	pdmR3DevHlp_CritSectYield,
5621	pdmR3DevHlp_CritSectEnter,
5622	pdmR3DevHlp_CritSectEnterDebug,
5623	pdmR3DevHlp_CritSectTryEnter,
5624	pdmR3DevHlp_CritSectTryEnterDebug,
5625	pdmR3DevHlp_CritSectLeave,
5626	pdmR3DevHlp_CritSectIsOwner,
5627	pdmR3DevHlp_CritSectIsInitialized,
5628	pdmR3DevHlp_CritSectHasWaiters,
5629	pdmR3DevHlp_CritSectGetRecursion,
5630	pdmR3DevHlp_CritSectScheduleExitEvent,
5631	pdmR3DevHlp_CritSectDelete,
5632	pdmR3DevHlp_CritSectRwInit,
5633	pdmR3DevHlp_CritSectRwDelete,
5634	pdmR3DevHlp_CritSectRwEnterShared,
5635	pdmR3DevHlp_CritSectRwEnterSharedDebug,
5636	pdmR3DevHlp_CritSectRwTryEnterShared,
5637	pdmR3DevHlp_CritSectRwTryEnterSharedDebug,
5638	pdmR3DevHlp_CritSectRwLeaveShared,
5639	pdmR3DevHlp_CritSectRwEnterExcl,
5640	pdmR3DevHlp_CritSectRwEnterExclDebug,
5641	pdmR3DevHlp_CritSectRwTryEnterExcl,
5642	pdmR3DevHlp_CritSectRwTryEnterExclDebug,
5643	pdmR3DevHlp_CritSectRwLeaveExcl,
5644	pdmR3DevHlp_CritSectRwIsWriteOwner,
5645	pdmR3DevHlp_CritSectRwIsReadOwner,
5646	pdmR3DevHlp_CritSectRwGetWriteRecursion,
5647	pdmR3DevHlp_CritSectRwGetWriterReadRecursion,
5648	pdmR3DevHlp_CritSectRwGetReadCount,
5649	pdmR3DevHlp_CritSectRwIsInitialized,
5650	pdmR3DevHlp_ThreadCreate,
5651	PDMR3ThreadDestroy,
5652	PDMR3ThreadIAmSuspending,
5653	PDMR3ThreadIAmRunning,
5654	PDMR3ThreadSleep,
5655	PDMR3ThreadSuspend,
5656	PDMR3ThreadResume,
5657	pdmR3DevHlp_SetAsyncNotification,
5658	pdmR3DevHlp_AsyncNotificationCompleted,
5659	pdmR3DevHlp_RTCRegister,
5660	pdmR3DevHlp_PCIBusRegister,
5661	pdmR3DevHlp_IommuRegister,
5662	pdmR3DevHlp_PICRegister,
5663	pdmR3DevHlp_ApicRegister,
5664	pdmR3DevHlp_IoApicRegister,
5665	pdmR3DevHlp_HpetRegister,
5666	pdmR3DevHlp_PciRawRegister,
5667	pdmR3DevHlp_DMACRegister,
5668	pdmR3DevHlp_DMARegister,
5669	pdmR3DevHlp_DMAReadMemory,
5670	pdmR3DevHlp_DMAWriteMemory,
5671	pdmR3DevHlp_DMASetDREQ,
5672	pdmR3DevHlp_DMAGetChannelMode,
5673	pdmR3DevHlp_DMASchedule,
5674	pdmR3DevHlp_CMOSWrite,
5675	pdmR3DevHlp_CMOSRead,
5676	pdmR3DevHlp_AssertEMT,
5677	pdmR3DevHlp_AssertOther,
5678	pdmR3DevHlp_LdrGetRCInterfaceSymbols,
5679	pdmR3DevHlp_LdrGetR0InterfaceSymbols,
5680	pdmR3DevHlp_CallR0,
5681	pdmR3DevHlp_VMGetSuspendReason,
5682	pdmR3DevHlp_VMGetResumeReason,
5683	pdmR3DevHlp_PhysBulkGCPhys2CCPtr,
5684	pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly,
5685	pdmR3DevHlp_PhysBulkReleasePageMappingLocks,
5686	pdmR3DevHlp_CpuGetGuestArch,
5687	pdmR3DevHlp_CpuGetGuestMicroarch,
5688	pdmR3DevHlp_CpuGetGuestAddrWidths,
5689	pdmR3DevHlp_CpuGetGuestScalableBusFrequency,
5690	pdmR3DevHlp_STAMDeregisterByPrefix,
5691	0,
5692	0,
5693	0,
5694	0,
5695	0,
5696	0,
5697	0,
5698	0,
5699	0,
5700	pdmR3DevHlp_GetUVM,
5701	pdmR3DevHlp_GetVM,
5702	pdmR3DevHlp_GetVMCPU,
5703	pdmR3DevHlp_GetCurrentCpuId,
5704	pdmR3DevHlp_RegisterVMMDevHeap,
5705	pdmR3DevHlp_FirmwareRegister,
5706	pdmR3DevHlp_VMReset,
5707	pdmR3DevHlp_VMSuspend,
5708	pdmR3DevHlp_VMSuspendSaveAndPowerOff,
5709	pdmR3DevHlp_VMPowerOff,
5710	pdmR3DevHlp_A20IsEnabled,
5711	pdmR3DevHlp_A20Set,
5712	pdmR3DevHlp_GetCpuId,
5713	pdmR3DevHlp_GetMainExecutionEngine,
5714	pdmR3DevHlp_TMTimeVirtGet,
5715	pdmR3DevHlp_TMTimeVirtGetFreq,
5716	pdmR3DevHlp_TMTimeVirtGetNano,
5717	pdmR3DevHlp_TMCpuTicksPerSecond,
5718	pdmR3DevHlp_GetSupDrvSession,
5719	pdmR3DevHlp_QueryGenericUserObject,
5720	pdmR3DevHlp_PGMHandlerPhysicalTypeRegister,
5721	pdmR3DevHlp_PGMHandlerPhysicalRegister,
5722	pdmR3DevHlp_PGMHandlerPhysicalDeregister,
5723	pdmR3DevHlp_PGMHandlerPhysicalPageTempOff,
5724	pdmR3DevHlp_PGMHandlerPhysicalReset,
5725	pdmR3DevHlp_VMMRegisterPatchMemory,
5726	pdmR3DevHlp_VMMDeregisterPatchMemory,
5727	pdmR3DevHlp_SharedModuleRegister,
5728	pdmR3DevHlp_SharedModuleUnregister,
5729	pdmR3DevHlp_SharedModuleGetPageState,
5730	pdmR3DevHlp_SharedModuleCheckAll,
5731	pdmR3DevHlp_QueryLun,
5732	pdmR3DevHlp_GIMDeviceRegister,
5733	pdmR3DevHlp_GIMGetDebugSetup,
5734	pdmR3DevHlp_GIMGetMmio2Regions,
5735	PDM_DEVHLPR3_VERSION /* the end */
5736	};
5737	#endif /* VBOX_WITH_DBGF_TRACING */
5738
5739
5740
5741
5742	/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
5743	static DECLCALLBACK(PUVM) pdmR3DevHlp_Untrusted_GetUVM(PPDMDEVINS pDevIns)
5744	{
5745	PDMDEV_ASSERT_DEVINS(pDevIns);
5746	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5747	return NULL;
5748	}
5749
5750
5751	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
5752	static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns)
5753	{
5754	PDMDEV_ASSERT_DEVINS(pDevIns);
5755	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5756	return NULL;
5757	}
5758
5759
5760	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
5761	static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns)
5762	{
5763	PDMDEV_ASSERT_DEVINS(pDevIns);
5764	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5765	return NULL;
5766	}
5767
5768
5769	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
5770	static DECLCALLBACK(VMCPUID) pdmR3DevHlp_Untrusted_GetCurrentCpuId(PPDMDEVINS pDevIns)
5771	{
5772	PDMDEV_ASSERT_DEVINS(pDevIns);
5773	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5774	return NIL_VMCPUID;
5775	}
5776
5777
5778	/** @interface_method_impl{PDMDEVHLPR3,pfnRegisterVMMDevHeap} */
5779	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
5780	RTR3PTR pvHeap, unsigned cbHeap)
5781	{
5782	PDMDEV_ASSERT_DEVINS(pDevIns);
5783	NOREF(GCPhys); NOREF(pvHeap); NOREF(cbHeap);
5784	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5785	return VERR_ACCESS_DENIED;
5786	}
5787
5788
5789	/** @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister} */
5790	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
5791	{
5792	PDMDEV_ASSERT_DEVINS(pDevIns);
5793	NOREF(pFwReg); NOREF(ppFwHlp);
5794	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5795	return VERR_ACCESS_DENIED;
5796	}
5797
5798
5799	/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
5800	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
5801	{
5802	PDMDEV_ASSERT_DEVINS(pDevIns); NOREF(fFlags);
5803	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5804	return VERR_ACCESS_DENIED;
5805	}
5806
5807
5808	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
5809	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns)
5810	{
5811	PDMDEV_ASSERT_DEVINS(pDevIns);
5812	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5813	return VERR_ACCESS_DENIED;
5814	}
5815
5816
5817	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
5818	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
5819	{
5820	PDMDEV_ASSERT_DEVINS(pDevIns);
5821	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5822	return VERR_ACCESS_DENIED;
5823	}
5824
5825
5826	/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
5827	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns)
5828	{
5829	PDMDEV_ASSERT_DEVINS(pDevIns);
5830	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5831	return VERR_ACCESS_DENIED;
5832	}
5833
5834
5835	/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
5836	static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns)
5837	{
5838	PDMDEV_ASSERT_DEVINS(pDevIns);
5839	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5840	return false;
5841	}
5842
5843
5844	/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
5845	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable)
5846	{
5847	PDMDEV_ASSERT_DEVINS(pDevIns);
5848	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5849	NOREF(fEnable);
5850	}
5851
5852
5853	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
5854	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
5855	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
5856	{
5857	PDMDEV_ASSERT_DEVINS(pDevIns);
5858	NOREF(iLeaf); NOREF(pEax); NOREF(pEbx); NOREF(pEcx); NOREF(pEdx);
5859	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5860	}
5861
5862
5863	/** @interface_method_impl{PDMDEVHLPR3,pfnGetMainExecutionEngine} */
5864	static DECLCALLBACK(uint8_t) pdmR3DevHlp_Untrusted_GetMainExecutionEngine(PPDMDEVINS pDevIns)
5865	{
5866	PDMDEV_ASSERT_DEVINS(pDevIns);
5867	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5868	return VM_EXEC_ENGINE_NOT_SET;
5869	}
5870
5871
5872	/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
5873	static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_Untrusted_GetSupDrvSession(PPDMDEVINS pDevIns)
5874	{
5875	PDMDEV_ASSERT_DEVINS(pDevIns);
5876	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5877	return (PSUPDRVSESSION)0;
5878	}
5879
5880
5881	/** @interface_method_impl{PDMDEVHLPR3,pfnQueryGenericUserObject} */
5882	static DECLCALLBACK(void *) pdmR3DevHlp_Untrusted_QueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
5883	{
5884	PDMDEV_ASSERT_DEVINS(pDevIns);
5885	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d %RTuuid\n",
5886	pDevIns->pReg->szName, pDevIns->iInstance, pUuid));
5887	return NULL;
5888	}
5889
5890
5891	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalTypeRegister} */
5892	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
5893	PFNPGMPHYSHANDLER pfnHandler,
5894	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
5895	{
5896	PDMDEV_ASSERT_DEVINS(pDevIns);
5897	RT_NOREF(pDevIns, enmKind, pfnHandler, pszDesc);
5898	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5899	pDevIns->pReg->szName, pDevIns->iInstance));
5900	*phType = NIL_PGMPHYSHANDLERTYPE;
5901	return VERR_ACCESS_DENIED;
5902	}
5903
5904
5905	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalRegister} */
5906	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
5907	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc)
5908	{
5909	PDMDEV_ASSERT_DEVINS(pDevIns);
5910	RT_NOREF(GCPhys, GCPhysLast, hType, pszDesc);
5911	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
5912	return VERR_ACCESS_DENIED;
5913	}
5914
5915
5916	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalDeregister} */
5917	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
5918	{
5919	PDMDEV_ASSERT_DEVINS(pDevIns);
5920	RT_NOREF(GCPhys);
5921	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5922	pDevIns->pReg->szName, pDevIns->iInstance));
5923	return VERR_ACCESS_DENIED;
5924	}
5925
5926
5927	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalPageTempOff} */
5928	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
5929	{
5930	PDMDEV_ASSERT_DEVINS(pDevIns);
5931	RT_NOREF(GCPhys, GCPhysPage);
5932	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5933	pDevIns->pReg->szName, pDevIns->iInstance));
5934	return VERR_ACCESS_DENIED;
5935	}
5936
5937
5938	/** @interface_method_impl{PDMDEVHLPR3,pfnPGMHandlerPhysicalReset} */
5939	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
5940	{
5941	PDMDEV_ASSERT_DEVINS(pDevIns);
5942	RT_NOREF(GCPhys);
5943	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5944	pDevIns->pReg->szName, pDevIns->iInstance));
5945	return VERR_ACCESS_DENIED;
5946	}
5947
5948
5949	/** @interface_method_impl{PDMDEVHLPR3,pfnVMMRegisterPatchMemory} */
5950	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
5951	{
5952	PDMDEV_ASSERT_DEVINS(pDevIns);
5953	RT_NOREF(GCPtrPatchMem, cbPatchMem);
5954	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5955	pDevIns->pReg->szName, pDevIns->iInstance));
5956	return VERR_ACCESS_DENIED;
5957	}
5958
5959
5960	/** @interface_method_impl{PDMDEVHLPR3,pfnVMMDeregisterPatchMemory} */
5961	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
5962	{
5963	PDMDEV_ASSERT_DEVINS(pDevIns);
5964	RT_NOREF(GCPtrPatchMem, cbPatchMem);
5965	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5966	pDevIns->pReg->szName, pDevIns->iInstance));
5967	return VERR_ACCESS_DENIED;
5968	}
5969
5970
5971	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleRegister} */
5972	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_SharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
5973	RTGCPTR GCBaseAddr, uint32_t cbModule,
5974	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
5975	{
5976	PDMDEV_ASSERT_DEVINS(pDevIns);
5977	RT_NOREF(enmGuestOS, pszModuleName, pszVersion, GCBaseAddr, cbModule, cRegions, paRegions);
5978	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5979	pDevIns->pReg->szName, pDevIns->iInstance));
5980	return VERR_ACCESS_DENIED;
5981	}
5982
5983
5984	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleUnregister} */
5985	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_SharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
5986	RTGCPTR GCBaseAddr, uint32_t cbModule)
5987	{
5988	PDMDEV_ASSERT_DEVINS(pDevIns);
5989	RT_NOREF(pszModuleName, pszVersion, GCBaseAddr, cbModule);
5990	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
5991	pDevIns->pReg->szName, pDevIns->iInstance));
5992	return VERR_ACCESS_DENIED;
5993	}
5994
5995
5996	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleGetPageState} */
5997	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_SharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags)
5998	{
5999	PDMDEV_ASSERT_DEVINS(pDevIns);
6000	RT_NOREF(GCPtrPage, pfShared, pfPageFlags);
6001	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
6002	pDevIns->pReg->szName, pDevIns->iInstance));
6003	return VERR_ACCESS_DENIED;
6004	}
6005
6006
6007	/** @interface_method_impl{PDMDEVHLPR3,pfnSharedModuleCheckAll} */
6008	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_SharedModuleCheckAll(PPDMDEVINS pDevIns)
6009	{
6010	PDMDEV_ASSERT_DEVINS(pDevIns);
6011	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
6012	pDevIns->pReg->szName, pDevIns->iInstance));
6013	return VERR_ACCESS_DENIED;
6014	}
6015
6016
6017	/** @interface_method_impl{PDMDEVHLPR3,pfnQueryLun} */
6018	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_QueryLun(PPDMDEVINS pDevIns, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMIBASE ppBase)
6019	{
6020	PDMDEV_ASSERT_DEVINS(pDevIns);
6021	RT_NOREF(pszDevice, iInstance, iLun, ppBase);
6022	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
6023	pDevIns->pReg->szName, pDevIns->iInstance));
6024	return VERR_ACCESS_DENIED;
6025	}
6026
6027
6028	/** @interface_method_impl{PDMDEVHLPR3,pfnGIMDeviceRegister} */
6029	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GIMDeviceRegister(PPDMDEVINS pDevIns, PGIMDEBUG pDbg)
6030	{
6031	PDMDEV_ASSERT_DEVINS(pDevIns);
6032	RT_NOREF(pDbg);
6033	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
6034	pDevIns->pReg->szName, pDevIns->iInstance));
6035	}
6036
6037
6038	/** @interface_method_impl{PDMDEVHLPR3,pfnGIMGetDebugSetup} */
6039	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_GIMGetDebugSetup(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup)
6040	{
6041	PDMDEV_ASSERT_DEVINS(pDevIns);
6042	RT_NOREF(pDbgSetup);
6043	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
6044	pDevIns->pReg->szName, pDevIns->iInstance));
6045	return VERR_ACCESS_DENIED;
6046	}
6047
6048
6049	/** @interface_method_impl{PDMDEVHLPR3,pfnGIMGetMmio2Regions} */
6050	static DECLCALLBACK(PGIMMMIO2REGION) pdmR3DevHlp_Untrusted_GIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
6051	{
6052	PDMDEV_ASSERT_DEVINS(pDevIns);
6053	RT_NOREF(pcRegions);
6054	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n",
6055	pDevIns->pReg->szName, pDevIns->iInstance));
6056	return NULL;
6057	}
6058
6059
6060	/**
6061	* The device helper structure for non-trusted devices.
6062	*/
6063	const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted =
6064	{
6065	PDM_DEVHLPR3_VERSION,
6066	pdmR3DevHlp_IoPortCreateEx,
6067	pdmR3DevHlp_IoPortMap,
6068	pdmR3DevHlp_IoPortUnmap,
6069	pdmR3DevHlp_IoPortGetMappingAddress,
6070	pdmR3DevHlp_IoPortRead,
6071	pdmR3DevHlp_IoPortWrite,
6072	pdmR3DevHlp_MmioCreateEx,
6073	pdmR3DevHlp_MmioMap,
6074	pdmR3DevHlp_MmioUnmap,
6075	pdmR3DevHlp_MmioReduce,
6076	pdmR3DevHlp_MmioGetMappingAddress,
6077	pdmR3DevHlp_Mmio2Create,
6078	pdmR3DevHlp_Mmio2Destroy,
6079	pdmR3DevHlp_Mmio2Map,
6080	pdmR3DevHlp_Mmio2Unmap,
6081	pdmR3DevHlp_Mmio2Reduce,
6082	pdmR3DevHlp_Mmio2GetMappingAddress,
6083	pdmR3DevHlp_Mmio2QueryAndResetDirtyBitmap,
6084	pdmR3DevHlp_Mmio2ControlDirtyPageTracking,
6085	pdmR3DevHlp_Mmio2ChangeRegionNo,
6086	pdmR3DevHlp_MmioMapMmio2Page,
6087	pdmR3DevHlp_MmioResetRegion,
6088	pdmR3DevHlp_ROMRegister,
6089	pdmR3DevHlp_ROMProtectShadow,
6090	pdmR3DevHlp_SSMRegister,
6091	pdmR3DevHlp_SSMRegisterLegacy,
6092	SSMR3PutStruct,
6093	SSMR3PutStructEx,
6094	SSMR3PutBool,
6095	SSMR3PutU8,
6096	SSMR3PutS8,
6097	SSMR3PutU16,
6098	SSMR3PutS16,
6099	SSMR3PutU32,
6100	SSMR3PutS32,
6101	SSMR3PutU64,
6102	SSMR3PutS64,
6103	SSMR3PutU128,
6104	SSMR3PutS128,
6105	SSMR3PutUInt,
6106	SSMR3PutSInt,
6107	SSMR3PutGCUInt,
6108	SSMR3PutGCUIntReg,
6109	SSMR3PutGCPhys32,
6110	SSMR3PutGCPhys64,
6111	SSMR3PutGCPhys,
6112	SSMR3PutGCPtr,
6113	SSMR3PutGCUIntPtr,
6114	SSMR3PutRCPtr,
6115	SSMR3PutIOPort,
6116	SSMR3PutSel,
6117	SSMR3PutMem,
6118	SSMR3PutStrZ,
6119	SSMR3GetStruct,
6120	SSMR3GetStructEx,
6121	SSMR3GetBool,
6122	SSMR3GetBoolV,
6123	SSMR3GetU8,
6124	SSMR3GetU8V,
6125	SSMR3GetS8,
6126	SSMR3GetS8V,
6127	SSMR3GetU16,
6128	SSMR3GetU16V,
6129	SSMR3GetS16,
6130	SSMR3GetS16V,
6131	SSMR3GetU32,
6132	SSMR3GetU32V,
6133	SSMR3GetS32,
6134	SSMR3GetS32V,
6135	SSMR3GetU64,
6136	SSMR3GetU64V,
6137	SSMR3GetS64,
6138	SSMR3GetS64V,
6139	SSMR3GetU128,
6140	SSMR3GetU128V,
6141	SSMR3GetS128,
6142	SSMR3GetS128V,
6143	SSMR3GetGCPhys32,
6144	SSMR3GetGCPhys32V,
6145	SSMR3GetGCPhys64,
6146	SSMR3GetGCPhys64V,
6147	SSMR3GetGCPhys,
6148	SSMR3GetGCPhysV,
6149	SSMR3GetUInt,
6150	SSMR3GetSInt,
6151	SSMR3GetGCUInt,
6152	SSMR3GetGCUIntReg,
6153	SSMR3GetGCPtr,
6154	SSMR3GetGCUIntPtr,
6155	SSMR3GetRCPtr,
6156	SSMR3GetIOPort,
6157	SSMR3GetSel,
6158	SSMR3GetMem,
6159	SSMR3GetStrZ,
6160	SSMR3GetStrZEx,
6161	SSMR3Skip,
6162	SSMR3SkipToEndOfUnit,
6163	SSMR3SetLoadError,
6164	SSMR3SetLoadErrorV,
6165	SSMR3SetCfgError,
6166	SSMR3SetCfgErrorV,
6167	SSMR3HandleGetStatus,
6168	SSMR3HandleGetAfter,
6169	SSMR3HandleIsLiveSave,
6170	SSMR3HandleMaxDowntime,
6171	SSMR3HandleHostBits,
6172	SSMR3HandleRevision,
6173	SSMR3HandleVersion,
6174	SSMR3HandleHostOSAndArch,
6175	pdmR3DevHlp_TimerCreate,
6176	pdmR3DevHlp_TimerFromMicro,
6177	pdmR3DevHlp_TimerFromMilli,
6178	pdmR3DevHlp_TimerFromNano,
6179	pdmR3DevHlp_TimerGet,
6180	pdmR3DevHlp_TimerGetFreq,
6181	pdmR3DevHlp_TimerGetNano,
6182	pdmR3DevHlp_TimerIsActive,
6183	pdmR3DevHlp_TimerIsLockOwner,
6184	pdmR3DevHlp_TimerLockClock,
6185	pdmR3DevHlp_TimerLockClock2,
6186	pdmR3DevHlp_TimerSet,
6187	pdmR3DevHlp_TimerSetFrequencyHint,
6188	pdmR3DevHlp_TimerSetMicro,
6189	pdmR3DevHlp_TimerSetMillies,
6190	pdmR3DevHlp_TimerSetNano,
6191	pdmR3DevHlp_TimerSetRelative,
6192	pdmR3DevHlp_TimerStop,
6193	pdmR3DevHlp_TimerUnlockClock,
6194	pdmR3DevHlp_TimerUnlockClock2,
6195	pdmR3DevHlp_TimerSetCritSect,
6196	pdmR3DevHlp_TimerSave,
6197	pdmR3DevHlp_TimerLoad,
6198	pdmR3DevHlp_TimerDestroy,
6199	TMR3TimerSkip,
6200	pdmR3DevHlp_TMUtcNow,
6201	CFGMR3Exists,
6202	CFGMR3QueryType,
6203	CFGMR3QuerySize,
6204	CFGMR3QueryInteger,
6205	CFGMR3QueryIntegerDef,
6206	CFGMR3QueryString,
6207	CFGMR3QueryStringDef,
6208	CFGMR3QueryPassword,
6209	CFGMR3QueryPasswordDef,
6210	CFGMR3QueryBytes,
6211	CFGMR3QueryU64,
6212	CFGMR3QueryU64Def,
6213	CFGMR3QueryS64,
6214	CFGMR3QueryS64Def,
6215	CFGMR3QueryU32,
6216	CFGMR3QueryU32Def,
6217	CFGMR3QueryS32,
6218	CFGMR3QueryS32Def,
6219	CFGMR3QueryU16,
6220	CFGMR3QueryU16Def,
6221	CFGMR3QueryS16,
6222	CFGMR3QueryS16Def,
6223	CFGMR3QueryU8,
6224	CFGMR3QueryU8Def,
6225	CFGMR3QueryS8,
6226	CFGMR3QueryS8Def,
6227	CFGMR3QueryBool,
6228	CFGMR3QueryBoolDef,
6229	CFGMR3QueryPort,
6230	CFGMR3QueryPortDef,
6231	CFGMR3QueryUInt,
6232	CFGMR3QueryUIntDef,
6233	CFGMR3QuerySInt,
6234	CFGMR3QuerySIntDef,
6235	CFGMR3QueryGCPtr,
6236	CFGMR3QueryGCPtrDef,
6237	CFGMR3QueryGCPtrU,
6238	CFGMR3QueryGCPtrUDef,
6239	CFGMR3QueryGCPtrS,
6240	CFGMR3QueryGCPtrSDef,
6241	CFGMR3QueryStringAlloc,
6242	CFGMR3QueryStringAllocDef,
6243	CFGMR3GetParent,
6244	CFGMR3GetChild,
6245	CFGMR3GetChildF,
6246	CFGMR3GetChildFV,
6247	CFGMR3GetFirstChild,
6248	CFGMR3GetNextChild,
6249	CFGMR3GetName,
6250	CFGMR3GetNameLen,
6251	CFGMR3AreChildrenValid,
6252	CFGMR3GetFirstValue,
6253	CFGMR3GetNextValue,
6254	CFGMR3GetValueName,
6255	CFGMR3GetValueNameLen,
6256	CFGMR3GetValueType,
6257	CFGMR3AreValuesValid,
6258	CFGMR3ValidateConfig,
6259	pdmR3DevHlp_PhysRead,
6260	pdmR3DevHlp_PhysWrite,
6261	pdmR3DevHlp_PhysGCPhys2CCPtr,
6262	pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
6263	pdmR3DevHlp_PhysReleasePageMappingLock,
6264	pdmR3DevHlp_PhysReadGCVirt,
6265	pdmR3DevHlp_PhysWriteGCVirt,
6266	pdmR3DevHlp_PhysGCPtr2GCPhys,
6267	pdmR3DevHlp_PhysIsGCPhysNormal,
6268	pdmR3DevHlp_PhysChangeMemBalloon,
6269	pdmR3DevHlp_MMHeapAlloc,
6270	pdmR3DevHlp_MMHeapAllocZ,
6271	pdmR3DevHlp_MMHeapAPrintfV,
6272	pdmR3DevHlp_MMHeapFree,
6273	pdmR3DevHlp_MMPhysGetRamSize,
6274	pdmR3DevHlp_MMPhysGetRamSizeBelow4GB,
6275	pdmR3DevHlp_MMPhysGetRamSizeAbove4GB,
6276	pdmR3DevHlp_VMState,
6277	pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
6278	pdmR3DevHlp_VMSetErrorV,
6279	pdmR3DevHlp_VMSetRuntimeErrorV,
6280	pdmR3DevHlp_VMWaitForDeviceReady,
6281	pdmR3DevHlp_VMNotifyCpuDeviceReady,
6282	pdmR3DevHlp_VMReqCallNoWaitV,
6283	pdmR3DevHlp_VMReqPriorityCallWaitV,
6284	pdmR3DevHlp_DBGFStopV,
6285	pdmR3DevHlp_DBGFInfoRegister,
6286	pdmR3DevHlp_DBGFInfoRegisterArgv,
6287	pdmR3DevHlp_DBGFRegRegister,
6288	pdmR3DevHlp_DBGFTraceBuf,
6289	pdmR3DevHlp_DBGFReportBugCheck,
6290	pdmR3DevHlp_DBGFCoreWrite,
6291	pdmR3DevHlp_DBGFInfoLogHlp,
6292	pdmR3DevHlp_DBGFRegNmQueryU64,
6293	pdmR3DevHlp_DBGFRegPrintfV,
6294	pdmR3DevHlp_STAMRegister,
6295	pdmR3DevHlp_STAMRegisterV,
6296	pdmR3DevHlp_PCIRegister,
6297	pdmR3DevHlp_PCIRegisterMsi,
6298	pdmR3DevHlp_PCIIORegionRegister,
6299	pdmR3DevHlp_PCIInterceptConfigAccesses,
6300	pdmR3DevHlp_PCIConfigWrite,
6301	pdmR3DevHlp_PCIConfigRead,
6302	pdmR3DevHlp_PCIPhysRead,
6303	pdmR3DevHlp_PCIPhysWrite,
6304	pdmR3DevHlp_PCIPhysGCPhys2CCPtr,
6305	pdmR3DevHlp_PCIPhysGCPhys2CCPtrReadOnly,
6306	pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtr,
6307	pdmR3DevHlp_PCIPhysBulkGCPhys2CCPtrReadOnly,
6308	pdmR3DevHlp_PCISetIrq,
6309	pdmR3DevHlp_PCISetIrqNoWait,
6310	pdmR3DevHlp_ISASetIrq,
6311	pdmR3DevHlp_ISASetIrqNoWait,
6312	pdmR3DevHlp_DriverAttach,
6313	pdmR3DevHlp_DriverDetach,
6314	pdmR3DevHlp_DriverReconfigure,
6315	pdmR3DevHlp_QueueCreate,
6316	pdmR3DevHlp_QueueAlloc,
6317	pdmR3DevHlp_QueueInsert,
6318	pdmR3DevHlp_QueueFlushIfNecessary,
6319	pdmR3DevHlp_TaskCreate,
6320	pdmR3DevHlp_TaskTrigger,
6321	pdmR3DevHlp_SUPSemEventCreate,
6322	pdmR3DevHlp_SUPSemEventClose,
6323	pdmR3DevHlp_SUPSemEventSignal,
6324	pdmR3DevHlp_SUPSemEventWaitNoResume,
6325	pdmR3DevHlp_SUPSemEventWaitNsAbsIntr,
6326	pdmR3DevHlp_SUPSemEventWaitNsRelIntr,
6327	pdmR3DevHlp_SUPSemEventGetResolution,
6328	pdmR3DevHlp_SUPSemEventMultiCreate,
6329	pdmR3DevHlp_SUPSemEventMultiClose,
6330	pdmR3DevHlp_SUPSemEventMultiSignal,
6331	pdmR3DevHlp_SUPSemEventMultiReset,
6332	pdmR3DevHlp_SUPSemEventMultiWaitNoResume,
6333	pdmR3DevHlp_SUPSemEventMultiWaitNsAbsIntr,
6334	pdmR3DevHlp_SUPSemEventMultiWaitNsRelIntr,
6335	pdmR3DevHlp_SUPSemEventMultiGetResolution,
6336	pdmR3DevHlp_CritSectInit,
6337	pdmR3DevHlp_CritSectGetNop,
6338	pdmR3DevHlp_SetDeviceCritSect,
6339	pdmR3DevHlp_CritSectYield,
6340	pdmR3DevHlp_CritSectEnter,
6341	pdmR3DevHlp_CritSectEnterDebug,
6342	pdmR3DevHlp_CritSectTryEnter,
6343	pdmR3DevHlp_CritSectTryEnterDebug,
6344	pdmR3DevHlp_CritSectLeave,
6345	pdmR3DevHlp_CritSectIsOwner,
6346	pdmR3DevHlp_CritSectIsInitialized,
6347	pdmR3DevHlp_CritSectHasWaiters,
6348	pdmR3DevHlp_CritSectGetRecursion,
6349	pdmR3DevHlp_CritSectScheduleExitEvent,
6350	pdmR3DevHlp_CritSectDelete,
6351	pdmR3DevHlp_CritSectRwInit,
6352	pdmR3DevHlp_CritSectRwDelete,
6353	pdmR3DevHlp_CritSectRwEnterShared,
6354	pdmR3DevHlp_CritSectRwEnterSharedDebug,
6355	pdmR3DevHlp_CritSectRwTryEnterShared,
6356	pdmR3DevHlp_CritSectRwTryEnterSharedDebug,
6357	pdmR3DevHlp_CritSectRwLeaveShared,
6358	pdmR3DevHlp_CritSectRwEnterExcl,
6359	pdmR3DevHlp_CritSectRwEnterExclDebug,
6360	pdmR3DevHlp_CritSectRwTryEnterExcl,
6361	pdmR3DevHlp_CritSectRwTryEnterExclDebug,
6362	pdmR3DevHlp_CritSectRwLeaveExcl,
6363	pdmR3DevHlp_CritSectRwIsWriteOwner,
6364	pdmR3DevHlp_CritSectRwIsReadOwner,
6365	pdmR3DevHlp_CritSectRwGetWriteRecursion,
6366	pdmR3DevHlp_CritSectRwGetWriterReadRecursion,
6367	pdmR3DevHlp_CritSectRwGetReadCount,
6368	pdmR3DevHlp_CritSectRwIsInitialized,
6369	pdmR3DevHlp_ThreadCreate,
6370	PDMR3ThreadDestroy,
6371	PDMR3ThreadIAmSuspending,
6372	PDMR3ThreadIAmRunning,
6373	PDMR3ThreadSleep,
6374	PDMR3ThreadSuspend,
6375	PDMR3ThreadResume,
6376	pdmR3DevHlp_SetAsyncNotification,
6377	pdmR3DevHlp_AsyncNotificationCompleted,
6378	pdmR3DevHlp_RTCRegister,
6379	pdmR3DevHlp_PCIBusRegister,
6380	pdmR3DevHlp_IommuRegister,
6381	pdmR3DevHlp_PICRegister,
6382	pdmR3DevHlp_ApicRegister,
6383	pdmR3DevHlp_IoApicRegister,
6384	pdmR3DevHlp_HpetRegister,
6385	pdmR3DevHlp_PciRawRegister,
6386	pdmR3DevHlp_DMACRegister,
6387	pdmR3DevHlp_DMARegister,
6388	pdmR3DevHlp_DMAReadMemory,
6389	pdmR3DevHlp_DMAWriteMemory,
6390	pdmR3DevHlp_DMASetDREQ,
6391	pdmR3DevHlp_DMAGetChannelMode,
6392	pdmR3DevHlp_DMASchedule,
6393	pdmR3DevHlp_CMOSWrite,
6394	pdmR3DevHlp_CMOSRead,
6395	pdmR3DevHlp_AssertEMT,
6396	pdmR3DevHlp_AssertOther,
6397	pdmR3DevHlp_LdrGetRCInterfaceSymbols,
6398	pdmR3DevHlp_LdrGetR0InterfaceSymbols,
6399	pdmR3DevHlp_CallR0,
6400	pdmR3DevHlp_VMGetSuspendReason,
6401	pdmR3DevHlp_VMGetResumeReason,
6402	pdmR3DevHlp_PhysBulkGCPhys2CCPtr,
6403	pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly,
6404	pdmR3DevHlp_PhysBulkReleasePageMappingLocks,
6405	pdmR3DevHlp_CpuGetGuestArch,
6406	pdmR3DevHlp_CpuGetGuestMicroarch,
6407	pdmR3DevHlp_CpuGetGuestAddrWidths,
6408	pdmR3DevHlp_CpuGetGuestScalableBusFrequency,
6409	pdmR3DevHlp_STAMDeregisterByPrefix,
6410	0,
6411	0,
6412	0,
6413	0,
6414	0,
6415	0,
6416	0,
6417	0,
6418	0,
6419	pdmR3DevHlp_Untrusted_GetUVM,
6420	pdmR3DevHlp_Untrusted_GetVM,
6421	pdmR3DevHlp_Untrusted_GetVMCPU,
6422	pdmR3DevHlp_Untrusted_GetCurrentCpuId,
6423	pdmR3DevHlp_Untrusted_RegisterVMMDevHeap,
6424	pdmR3DevHlp_Untrusted_FirmwareRegister,
6425	pdmR3DevHlp_Untrusted_VMReset,
6426	pdmR3DevHlp_Untrusted_VMSuspend,
6427	pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff,
6428	pdmR3DevHlp_Untrusted_VMPowerOff,
6429	pdmR3DevHlp_Untrusted_A20IsEnabled,
6430	pdmR3DevHlp_Untrusted_A20Set,
6431	pdmR3DevHlp_Untrusted_GetCpuId,
6432	pdmR3DevHlp_Untrusted_GetMainExecutionEngine,
6433	pdmR3DevHlp_TMTimeVirtGet,
6434	pdmR3DevHlp_TMTimeVirtGetFreq,
6435	pdmR3DevHlp_TMTimeVirtGetNano,
6436	pdmR3DevHlp_TMCpuTicksPerSecond,
6437	pdmR3DevHlp_Untrusted_GetSupDrvSession,
6438	pdmR3DevHlp_Untrusted_QueryGenericUserObject,
6439	pdmR3DevHlp_Untrusted_PGMHandlerPhysicalTypeRegister,
6440	pdmR3DevHlp_Untrusted_PGMHandlerPhysicalRegister,
6441	pdmR3DevHlp_Untrusted_PGMHandlerPhysicalDeregister,
6442	pdmR3DevHlp_Untrusted_PGMHandlerPhysicalPageTempOff,
6443	pdmR3DevHlp_Untrusted_PGMHandlerPhysicalReset,
6444	pdmR3DevHlp_Untrusted_VMMRegisterPatchMemory,
6445	pdmR3DevHlp_Untrusted_VMMDeregisterPatchMemory,
6446	pdmR3DevHlp_Untrusted_SharedModuleRegister,
6447	pdmR3DevHlp_Untrusted_SharedModuleUnregister,
6448	pdmR3DevHlp_Untrusted_SharedModuleGetPageState,
6449	pdmR3DevHlp_Untrusted_SharedModuleCheckAll,
6450	pdmR3DevHlp_Untrusted_QueryLun,
6451	pdmR3DevHlp_Untrusted_GIMDeviceRegister,
6452	pdmR3DevHlp_Untrusted_GIMGetDebugSetup,
6453	pdmR3DevHlp_Untrusted_GIMGetMmio2Regions,
6454	PDM_DEVHLPR3_VERSION /* the end */
6455	};
6456
6457
6458
6459	/**
6460	* Queue consumer callback for internal component.
6461	*
6462	* @returns Success indicator.
6463	* If false the item will not be removed and the flushing will stop.
6464	* @param pVM The cross context VM structure.
6465	* @param pItem The item to consume. Upon return this item will be freed.
6466	*/
6467	DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem)
6468	{
6469	PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)pItem;
6470	LogFlow(("pdmR3DevHlpQueueConsumer: enmOp=%d pDevIns=%p\n", pTask->enmOp, pTask->pDevInsR3));
6471	switch (pTask->enmOp)
6472	{
6473	case PDMDEVHLPTASKOP_ISA_SET_IRQ:
6474	PDMIsaSetIrq(pVM, pTask->u.IsaSetIrq.iIrq, pTask->u.IsaSetIrq.iLevel, pTask->u.IsaSetIrq.uTagSrc);
6475	break;
6476
6477	case PDMDEVHLPTASKOP_PCI_SET_IRQ:
6478	{
6479	/* Same as pdmR3DevHlp_PCISetIrq, except we've got a tag already. */
6480	PPDMDEVINSR3 pDevIns = pTask->pDevInsR3;
6481	PPDMPCIDEV pPciDev = pTask->u.PciSetIrq.idxPciDev < RT_ELEMENTS(pDevIns->apPciDevs)
6482	? pDevIns->apPciDevs[pTask->u.PciSetIrq.idxPciDev] : NULL;
6483	if (pPciDev)
6484	{
6485	size_t const idxBus = pPciDev->Int.s.idxPdmBus;
6486	AssertBreak(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses));
6487	PPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
6488
6489	pdmLock(pVM);
6490	pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, pTask->u.PciSetIrq.iIrq,
6491	pTask->u.PciSetIrq.iLevel, pTask->u.PciSetIrq.uTagSrc);
6492	pdmUnlock(pVM);
6493	}
6494	else
6495	AssertReleaseMsgFailed(("No PCI device given! (%#x)\n", pPciDev->Int.s.idxSubDev));
6496	break;
6497	}
6498
6499	case PDMDEVHLPTASKOP_IOAPIC_SET_IRQ:
6500	{
6501	PDMIoApicSetIrq(pVM, pTask->u.IoApicSetIrq.uBusDevFn, pTask->u.IoApicSetIrq.iIrq, pTask->u.IoApicSetIrq.iLevel,
6502	pTask->u.IoApicSetIrq.uTagSrc);
6503	break;
6504	}
6505
6506	case PDMDEVHLPTASKOP_IOAPIC_SEND_MSI:
6507	{
6508	PDMIoApicSendMsi(pVM, pTask->u.IoApicSendMsi.uBusDevFn, &pTask->u.IoApicSendMsi.Msi, pTask->u.IoApicSendMsi.uTagSrc);
6509	break;
6510	}
6511
6512	case PDMDEVHLPTASKOP_IOAPIC_SET_EOI:
6513	{
6514	PDMIoApicBroadcastEoi(pVM, pTask->u.IoApicSetEoi.uVector);
6515	break;
6516	}
6517
6518	default:
6519	AssertReleaseMsgFailed(("Invalid operation %d\n", pTask->enmOp));
6520	break;
6521	}
6522	return true;
6523	}
6524
6525	/** @} */
6526

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source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp@ 106022

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