VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp@ 44824

Last change on this file since 44824 was 44691, checked in by vboxsync, 12 years ago

Added a device helper for registering device registers with DBGF (breaks extpacks). Added IOREDTBLn subfields.

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  • Property svn:keywords set to Id Revision
File size: 148.9 KB
Line 
1/* $Id: PDMDevHlp.cpp 44691 2013-02-14 15:33:24Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/iom.h>
28#ifdef VBOX_WITH_REM
29# include <VBox/vmm/rem.h>
30#endif
31#include <VBox/vmm/dbgf.h>
32#include <VBox/vmm/vmapi.h>
33#include <VBox/vmm/vm.h>
34#include <VBox/vmm/uvm.h>
35#include <VBox/vmm/vmm.h>
36
37#include <VBox/version.h>
38#include <VBox/log.h>
39#include <VBox/err.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/ctype.h>
43#include <iprt/string.h>
44#include <iprt/thread.h>
45
46#include "dtrace/VBoxVMM.h"
47#include "PDMInline.h"
48
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53/** @def PDM_DEVHLP_DEADLOCK_DETECTION
54 * Define this to enable the deadlock detection when accessing physical memory.
55 */
56#if /*defined(DEBUG_bird) ||*/ defined(DOXYGEN_RUNNING)
57# define PDM_DEVHLP_DEADLOCK_DETECTION /**< @todo enable DevHlp deadlock detection! */
58#endif
59
60
61
62/**
63 * Wrapper around PDMR3LdrGetSymbolRCLazy.
64 */
65DECLINLINE(int) pdmR3DevGetSymbolRCLazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTRCPTR ppvValue)
66{
67 return PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3,
68 pDevIns->Internal.s.pDevR3->pReg->szRCMod,
69 pDevIns->Internal.s.pDevR3->pszRCSearchPath,
70 pszSymbol, ppvValue);
71}
72
73
74/**
75 * Wrapper around PDMR3LdrGetSymbolR0Lazy.
76 */
77DECLINLINE(int) pdmR3DevGetSymbolR0Lazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTR0PTR ppvValue)
78{
79 return PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3,
80 pDevIns->Internal.s.pDevR3->pReg->szR0Mod,
81 pDevIns->Internal.s.pDevR3->pszR0SearchPath,
82 pszSymbol, ppvValue);
83}
84
85
86/** @name R3 DevHlp
87 * @{
88 */
89
90
91/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegister} */
92static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
93 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
94{
95 PDMDEV_ASSERT_DEVINS(pDevIns);
96 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p p32_tszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
97 Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc, pszDesc));
98 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
99
100#if 0 /** @todo needs a real string cache for this */
101 if (pDevIns->iInstance > 0)
102 {
103 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
104 if (pszDesc2)
105 pszDesc = pszDesc2;
106 }
107#endif
108
109 int rc = IOMR3IOPortRegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser,
110 pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
111
112 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
113 return rc;
114}
115
116
117/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterRC} */
118static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
119 const char *pszOut, const char *pszIn,
120 const char *pszOutStr, const char *pszInStr, const char *pszDesc)
121{
122 PDMDEV_ASSERT_DEVINS(pDevIns);
123 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
124 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
125 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
126
127 /*
128 * Resolve the functions (one of the can be NULL).
129 */
130 int rc = VINF_SUCCESS;
131 if ( pDevIns->pReg->szRCMod[0]
132 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC))
133 {
134 RTRCPTR RCPtrIn = NIL_RTRCPTR;
135 if (pszIn)
136 {
137 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszIn, &RCPtrIn);
138 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szRCMod, pszIn));
139 }
140 RTRCPTR RCPtrOut = NIL_RTRCPTR;
141 if (pszOut && RT_SUCCESS(rc))
142 {
143 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOut, &RCPtrOut);
144 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szRCMod, pszOut));
145 }
146 RTRCPTR RCPtrInStr = NIL_RTRCPTR;
147 if (pszInStr && RT_SUCCESS(rc))
148 {
149 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszInStr, &RCPtrInStr);
150 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szRCMod, pszInStr));
151 }
152 RTRCPTR RCPtrOutStr = NIL_RTRCPTR;
153 if (pszOutStr && RT_SUCCESS(rc))
154 {
155 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOutStr, &RCPtrOutStr);
156 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szRCMod, pszOutStr));
157 }
158
159 if (RT_SUCCESS(rc))
160 {
161#if 0 /** @todo needs a real string cache for this */
162 if (pDevIns->iInstance > 0)
163 {
164 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
165 if (pszDesc2)
166 pszDesc = pszDesc2;
167 }
168#endif
169
170 rc = IOMR3IOPortRegisterRC(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, RCPtrOut, RCPtrIn, RCPtrOutStr, RCPtrInStr, pszDesc);
171 }
172 }
173 else
174 {
175 AssertMsgFailed(("No GC module for this driver!\n"));
176 rc = VERR_INVALID_PARAMETER;
177 }
178
179 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
180 return rc;
181}
182
183
184/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterR0} */
185static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
186 const char *pszOut, const char *pszIn,
187 const char *pszOutStr, const char *pszInStr, const char *pszDesc)
188{
189 PDMDEV_ASSERT_DEVINS(pDevIns);
190 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
191 LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
192 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
193
194 /*
195 * Resolve the functions (one of the can be NULL).
196 */
197 int rc = VINF_SUCCESS;
198 if ( pDevIns->pReg->szR0Mod[0]
199 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
200 {
201 R0PTRTYPE(PFNIOMIOPORTIN) pfnR0PtrIn = 0;
202 if (pszIn)
203 {
204 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszIn, &pfnR0PtrIn);
205 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szR0Mod, pszIn));
206 }
207 R0PTRTYPE(PFNIOMIOPORTOUT) pfnR0PtrOut = 0;
208 if (pszOut && RT_SUCCESS(rc))
209 {
210 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOut, &pfnR0PtrOut);
211 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szR0Mod, pszOut));
212 }
213 R0PTRTYPE(PFNIOMIOPORTINSTRING) pfnR0PtrInStr = 0;
214 if (pszInStr && RT_SUCCESS(rc))
215 {
216 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszInStr, &pfnR0PtrInStr);
217 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szR0Mod, pszInStr));
218 }
219 R0PTRTYPE(PFNIOMIOPORTOUTSTRING) pfnR0PtrOutStr = 0;
220 if (pszOutStr && RT_SUCCESS(rc))
221 {
222 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOutStr, &pfnR0PtrOutStr);
223 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szR0Mod, pszOutStr));
224 }
225
226 if (RT_SUCCESS(rc))
227 {
228#if 0 /** @todo needs a real string cache for this */
229 if (pDevIns->iInstance > 0)
230 {
231 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
232 if (pszDesc2)
233 pszDesc = pszDesc2;
234 }
235#endif
236
237 rc = IOMR3IOPortRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnR0PtrOut, pfnR0PtrIn, pfnR0PtrOutStr, pfnR0PtrInStr, pszDesc);
238 }
239 }
240 else
241 {
242 AssertMsgFailed(("No R0 module for this driver!\n"));
243 rc = VERR_INVALID_PARAMETER;
244 }
245
246 LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
247 return rc;
248}
249
250
251/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortDeregister} */
252static DECLCALLBACK(int) pdmR3DevHlp_IOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts)
253{
254 PDMDEV_ASSERT_DEVINS(pDevIns);
255 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
256 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: Port=%#x cPorts=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance,
257 Port, cPorts));
258
259 int rc = IOMR3IOPortDeregister(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts);
260
261 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
262 return rc;
263}
264
265
266/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegister} */
267static DECLCALLBACK(int) pdmR3DevHlp_MMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, RTHCPTR pvUser,
268 PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
269 uint32_t fFlags, const char *pszDesc)
270{
271 PDMDEV_ASSERT_DEVINS(pDevIns);
272 PVM pVM = pDevIns->Internal.s.pVMR3;
273 VM_ASSERT_EMT(pVM);
274 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p fFlags=%#x pszDesc=%p:{%s}\n",
275 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc, fFlags, pszDesc));
276
277 if (pDevIns->iInstance > 0)
278 {
279 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
280 if (pszDesc2)
281 pszDesc = pszDesc2;
282 }
283
284 int rc = IOMR3MmioRegisterR3(pVM, pDevIns, GCPhysStart, cbRange, pvUser,
285 pfnWrite, pfnRead, pfnFill, fFlags, pszDesc);
286
287 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
288 return rc;
289}
290
291
292/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterRC} */
293static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, RTRCPTR pvUser,
294 const char *pszWrite, const char *pszRead, const char *pszFill)
295{
296 PDMDEV_ASSERT_DEVINS(pDevIns);
297 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
298 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
299 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
300
301
302 /*
303 * Resolve the functions.
304 * Not all function have to present, leave it to IOM to enforce this.
305 */
306 int rc = VINF_SUCCESS;
307 if ( pDevIns->pReg->szRCMod[0]
308 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC))
309 {
310 RTRCPTR RCPtrWrite = NIL_RTRCPTR;
311 if (pszWrite)
312 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszWrite, &RCPtrWrite);
313
314 RTRCPTR RCPtrRead = NIL_RTRCPTR;
315 int rc2 = VINF_SUCCESS;
316 if (pszRead)
317 rc2 = pdmR3DevGetSymbolRCLazy(pDevIns, pszRead, &RCPtrRead);
318
319 RTRCPTR RCPtrFill = NIL_RTRCPTR;
320 int rc3 = VINF_SUCCESS;
321 if (pszFill)
322 rc3 = pdmR3DevGetSymbolRCLazy(pDevIns, pszFill, &RCPtrFill);
323
324 if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
325 rc = IOMR3MmioRegisterRC(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, RCPtrWrite, RCPtrRead, RCPtrFill);
326 else
327 {
328 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szRCMod, pszWrite));
329 AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szRCMod, pszRead));
330 AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szRCMod, pszFill));
331 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
332 rc = rc2;
333 if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
334 rc = rc3;
335 }
336 }
337 else
338 {
339 AssertMsgFailed(("No GC module for this driver!\n"));
340 rc = VERR_INVALID_PARAMETER;
341 }
342
343 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
344 return rc;
345}
346
347/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterR0} */
348static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, RTR0PTR pvUser,
349 const char *pszWrite, const char *pszRead, const char *pszFill)
350{
351 PDMDEV_ASSERT_DEVINS(pDevIns);
352 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
353 LogFlow(("pdmR3DevHlp_MMIORegisterHC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
354 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
355
356 /*
357 * Resolve the functions.
358 * Not all function have to present, leave it to IOM to enforce this.
359 */
360 int rc = VINF_SUCCESS;
361 if ( pDevIns->pReg->szR0Mod[0]
362 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
363 {
364 R0PTRTYPE(PFNIOMMMIOWRITE) pfnR0PtrWrite = 0;
365 if (pszWrite)
366 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszWrite, &pfnR0PtrWrite);
367 R0PTRTYPE(PFNIOMMMIOREAD) pfnR0PtrRead = 0;
368 int rc2 = VINF_SUCCESS;
369 if (pszRead)
370 rc2 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszRead, &pfnR0PtrRead);
371 R0PTRTYPE(PFNIOMMMIOFILL) pfnR0PtrFill = 0;
372 int rc3 = VINF_SUCCESS;
373 if (pszFill)
374 rc3 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszFill, &pfnR0PtrFill);
375 if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
376 rc = IOMR3MmioRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, pfnR0PtrWrite, pfnR0PtrRead, pfnR0PtrFill);
377 else
378 {
379 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szR0Mod, pszWrite));
380 AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szR0Mod, pszRead));
381 AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szR0Mod, pszFill));
382 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
383 rc = rc2;
384 if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
385 rc = rc3;
386 }
387 }
388 else
389 {
390 AssertMsgFailed(("No R0 module for this driver!\n"));
391 rc = VERR_INVALID_PARAMETER;
392 }
393
394 LogFlow(("pdmR3DevHlp_MMIORegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
395 return rc;
396}
397
398
399/** @interface_method_impl{PDMDEVHLPR3,pfnMMIODeregister} */
400static DECLCALLBACK(int) pdmR3DevHlp_MMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange)
401{
402 PDMDEV_ASSERT_DEVINS(pDevIns);
403 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
404 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x\n",
405 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange));
406
407 int rc = IOMR3MmioDeregister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange);
408
409 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
410 return rc;
411}
412
413
414/**
415 * @copydoc PDMDEVHLPR3::pfnMMIO2Register
416 */
417static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
418{
419 PDMDEV_ASSERT_DEVINS(pDevIns);
420 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
421 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: iRegion=%#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n",
422 pDevIns->pReg->szName, pDevIns->iInstance, iRegion, cb, fFlags, ppv, pszDesc, pszDesc));
423
424/** @todo PGMR3PhysMMIO2Register mangles the description, move it here and
425 * use a real string cache. */
426 int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, cb, fFlags, ppv, pszDesc);
427
428 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
429 return rc;
430}
431
432
433/**
434 * @copydoc PDMDEVHLPR3::pfnMMIO2Deregister
435 */
436static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion)
437{
438 PDMDEV_ASSERT_DEVINS(pDevIns);
439 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
440 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: iRegion=%#x\n",
441 pDevIns->pReg->szName, pDevIns->iInstance, iRegion));
442
443 AssertReturn(iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
444
445 int rc = PGMR3PhysMMIO2Deregister(pDevIns->Internal.s.pVMR3, pDevIns, iRegion);
446
447 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
448 return rc;
449}
450
451
452/**
453 * @copydoc PDMDEVHLPR3::pfnMMIO2Map
454 */
455static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
456{
457 PDMDEV_ASSERT_DEVINS(pDevIns);
458 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
459 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: iRegion=%#x GCPhys=%#RGp\n",
460 pDevIns->pReg->szName, pDevIns->iInstance, iRegion, GCPhys));
461
462 int rc = PGMR3PhysMMIO2Map(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys);
463
464 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
465 return rc;
466}
467
468
469/**
470 * @copydoc PDMDEVHLPR3::pfnMMIO2Unmap
471 */
472static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
473{
474 PDMDEV_ASSERT_DEVINS(pDevIns);
475 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
476 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: iRegion=%#x GCPhys=%#RGp\n",
477 pDevIns->pReg->szName, pDevIns->iInstance, iRegion, GCPhys));
478
479 int rc = PGMR3PhysMMIO2Unmap(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys);
480
481 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
482 return rc;
483}
484
485
486/**
487 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
488 */
489static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
490 const char *pszDesc, PRTRCPTR pRCPtr)
491{
492 PDMDEV_ASSERT_DEVINS(pDevIns);
493 PVM pVM = pDevIns->Internal.s.pVMR3;
494 VM_ASSERT_EMT(pVM);
495 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n",
496 pDevIns->pReg->szName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pRCPtr));
497
498 if (pDevIns->iInstance > 0)
499 {
500 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
501 if (pszDesc2)
502 pszDesc = pszDesc2;
503 }
504
505 int rc = MMR3HyperMapMMIO2(pVM, pDevIns, iRegion, off, cb, pszDesc, pRCPtr);
506
507 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc *pRCPtr=%RRv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pRCPtr));
508 return rc;
509}
510
511
512/**
513 * @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
514 */
515static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
516 const char *pszDesc, PRTR0PTR pR0Ptr)
517{
518 PDMDEV_ASSERT_DEVINS(pDevIns);
519 PVM pVM = pDevIns->Internal.s.pVMR3;
520 VM_ASSERT_EMT(pVM);
521 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pR0Ptr=%p\n",
522 pDevIns->pReg->szName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pR0Ptr));
523
524 if (pDevIns->iInstance > 0)
525 {
526 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
527 if (pszDesc2)
528 pszDesc = pszDesc2;
529 }
530
531 int rc = PGMR3PhysMMIO2MapKernel(pVM, pDevIns, iRegion, off, cb, pszDesc, pR0Ptr);
532
533 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: returns %Rrc *pR0Ptr=%RHv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pR0Ptr));
534 return rc;
535}
536
537
538/** @interface_method_impl{PDMDEVHLPR3,pfnROMRegister} */
539static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
540 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc)
541{
542 PDMDEV_ASSERT_DEVINS(pDevIns);
543 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
544 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvBinary=%p cbBinary=%#x fFlags=%#RX32 pszDesc=%p:{%s}\n",
545 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc, pszDesc));
546
547/** @todo can we mangle pszDesc? */
548 int rc = PGMR3PhysRomRegister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
549
550 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
551 return rc;
552}
553
554
555/** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */
556static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
557{
558 PDMDEV_ASSERT_DEVINS(pDevIns);
559 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n",
560 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt));
561
562 int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt);
563
564 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
565 return rc;
566}
567
568
569/** @interface_method_impl{PDMDEVHLPR3,pfnSSMRegister} */
570static DECLCALLBACK(int) pdmR3DevHlp_SSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
571 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
572 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
573 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
574{
575 PDMDEV_ASSERT_DEVINS(pDevIns);
576 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
577 LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: uVersion=#x cbGuess=%#x pszBefore=%p:{%s}\n"
578 " pfnLivePrep=%p pfnLiveExec=%p pfnLiveVote=%p pfnSavePrep=%p pfnSaveExec=%p pfnSaveDone=%p pszLoadPrep=%p pfnLoadExec=%p pfnLoadDone=%p\n",
579 pDevIns->pReg->szName, pDevIns->iInstance, uVersion, cbGuess, pszBefore, pszBefore,
580 pfnLivePrep, pfnLiveExec, pfnLiveVote,
581 pfnSavePrep, pfnSaveExec, pfnSaveDone,
582 pfnLoadPrep, pfnLoadExec, pfnLoadDone));
583
584 int rc = SSMR3RegisterDevice(pDevIns->Internal.s.pVMR3, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance,
585 uVersion, cbGuess, pszBefore,
586 pfnLivePrep, pfnLiveExec, pfnLiveVote,
587 pfnSavePrep, pfnSaveExec, pfnSaveDone,
588 pfnLoadPrep, pfnLoadExec, pfnLoadDone);
589
590 LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
591 return rc;
592}
593
594
595/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimerCreate} */
596static DECLCALLBACK(int) pdmR3DevHlp_TMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser, uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
597{
598 PDMDEV_ASSERT_DEVINS(pDevIns);
599 PVM pVM = pDevIns->Internal.s.pVMR3;
600 VM_ASSERT_EMT(pVM);
601 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: enmClock=%d pfnCallback=%p pvUser=%p fFlags=%#x pszDesc=%p:{%s} ppTimer=%p\n",
602 pDevIns->pReg->szName, pDevIns->iInstance, enmClock, pfnCallback, pvUser, fFlags, pszDesc, pszDesc, ppTimer));
603
604 if (pDevIns->iInstance > 0) /** @todo use a string cache here later. */
605 {
606 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
607 if (pszDesc2)
608 pszDesc = pszDesc2;
609 }
610
611 int rc = TMR3TimerCreateDevice(pVM, pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
612
613 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
614 return rc;
615}
616
617
618/** @interface_method_impl{PDMDEVHLPR3,pfnTMUtcNow} */
619static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_TMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
620{
621 PDMDEV_ASSERT_DEVINS(pDevIns);
622 LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: pTime=%p\n",
623 pDevIns->pReg->szName, pDevIns->iInstance, pTime));
624
625 pTime = TMR3UtcNow(pDevIns->Internal.s.pVMR3, pTime);
626
627 LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, RTTimeSpecGetNano(pTime)));
628 return pTime;
629}
630
631
632/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGet} */
633static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
634{
635 PDMDEV_ASSERT_DEVINS(pDevIns);
636 LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'\n",
637 pDevIns->pReg->szName, pDevIns->iInstance));
638
639 uint64_t u64Time = TMVirtualSyncGet(pDevIns->Internal.s.pVMR3);
640
641 LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Time));
642 return u64Time;
643}
644
645
646/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetFreq} */
647static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
648{
649 PDMDEV_ASSERT_DEVINS(pDevIns);
650 LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'\n",
651 pDevIns->pReg->szName, pDevIns->iInstance));
652
653 uint64_t u64Freq = TMVirtualGetFreq(pDevIns->Internal.s.pVMR3);
654
655 LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Freq));
656 return u64Freq;
657}
658
659
660/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetNano} */
661static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
662{
663 PDMDEV_ASSERT_DEVINS(pDevIns);
664 LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'\n",
665 pDevIns->pReg->szName, pDevIns->iInstance));
666
667 uint64_t u64Time = TMVirtualGet(pDevIns->Internal.s.pVMR3);
668 uint64_t u64Nano = TMVirtualToNano(pDevIns->Internal.s.pVMR3, u64Time);
669
670 LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Nano));
671 return u64Nano;
672}
673
674
675/** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */
676static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
677{
678 PDMDEV_ASSERT_DEVINS(pDevIns);
679 PVM pVM = pDevIns->Internal.s.pVMR3;
680 LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
681 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
682
683#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
684 if (!VM_IS_EMT(pVM))
685 {
686 char szNames[128];
687 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
688 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
689 }
690#endif
691
692 int rc;
693 if (VM_IS_EMT(pVM))
694 rc = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead);
695 else
696 rc = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead);
697
698 Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
699 return rc;
700}
701
702
703/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */
704static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
705{
706 PDMDEV_ASSERT_DEVINS(pDevIns);
707 PVM pVM = pDevIns->Internal.s.pVMR3;
708 LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
709 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
710
711#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
712 if (!VM_IS_EMT(pVM))
713 {
714 char szNames[128];
715 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
716 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
717 }
718#endif
719
720 int rc;
721 if (VM_IS_EMT(pVM))
722 rc = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite);
723 else
724 rc = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite, pDevIns->pReg->szName);
725
726 Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
727 return rc;
728}
729
730
731/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */
732static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
733{
734 PDMDEV_ASSERT_DEVINS(pDevIns);
735 PVM pVM = pDevIns->Internal.s.pVMR3;
736 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
737 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
738 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
739
740#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
741 if (!VM_IS_EMT(pVM))
742 {
743 char szNames[128];
744 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
745 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
746 }
747#endif
748
749 int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock);
750
751 Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
752 return rc;
753}
754
755
756/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */
757static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)
758{
759 PDMDEV_ASSERT_DEVINS(pDevIns);
760 PVM pVM = pDevIns->Internal.s.pVMR3;
761 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
762 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
763 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
764
765#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
766 if (!VM_IS_EMT(pVM))
767 {
768 char szNames[128];
769 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
770 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
771 }
772#endif
773
774 int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock);
775
776 Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
777 return rc;
778}
779
780
781/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */
782static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
783{
784 PDMDEV_ASSERT_DEVINS(pDevIns);
785 PVM pVM = pDevIns->Internal.s.pVMR3;
786 LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n",
787 pDevIns->pReg->szName, pDevIns->iInstance, pLock));
788
789 PGMPhysReleasePageMappingLock(pVM, pLock);
790
791 Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
792}
793
794
795/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */
796static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
797{
798 PDMDEV_ASSERT_DEVINS(pDevIns);
799 PVM pVM = pDevIns->Internal.s.pVMR3;
800 VM_ASSERT_EMT(pVM);
801 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n",
802 pDevIns->pReg->szName, pDevIns->iInstance, pvDst, GCVirtSrc, cb));
803
804 PVMCPU pVCpu = VMMGetCpu(pVM);
805 if (!pVCpu)
806 return VERR_ACCESS_DENIED;
807#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
808 /** @todo SMP. */
809#endif
810
811 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb);
812
813 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
814
815 return rc;
816}
817
818
819/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */
820static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
821{
822 PDMDEV_ASSERT_DEVINS(pDevIns);
823 PVM pVM = pDevIns->Internal.s.pVMR3;
824 VM_ASSERT_EMT(pVM);
825 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n",
826 pDevIns->pReg->szName, pDevIns->iInstance, GCVirtDst, pvSrc, cb));
827
828 PVMCPU pVCpu = VMMGetCpu(pVM);
829 if (!pVCpu)
830 return VERR_ACCESS_DENIED;
831#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
832 /** @todo SMP. */
833#endif
834
835 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb);
836
837 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
838
839 return rc;
840}
841
842
843/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPtr2GCPhys} */
844static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
845{
846 PDMDEV_ASSERT_DEVINS(pDevIns);
847 PVM pVM = pDevIns->Internal.s.pVMR3;
848 VM_ASSERT_EMT(pVM);
849 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n",
850 pDevIns->pReg->szName, pDevIns->iInstance, GCPtr, pGCPhys));
851
852 PVMCPU pVCpu = VMMGetCpu(pVM);
853 if (!pVCpu)
854 return VERR_ACCESS_DENIED;
855#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
856 /** @todo SMP. */
857#endif
858
859 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys);
860
861 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc *pGCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pGCPhys));
862
863 return rc;
864}
865
866
867/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAlloc} */
868static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
869{
870 PDMDEV_ASSERT_DEVINS(pDevIns);
871 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
872
873 void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
874
875 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
876 return pv;
877}
878
879
880/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAllocZ} */
881static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
882{
883 PDMDEV_ASSERT_DEVINS(pDevIns);
884 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
885
886 void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
887
888 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
889 return pv;
890}
891
892
893/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapFree} */
894static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv)
895{
896 PDMDEV_ASSERT_DEVINS(pDevIns);
897 LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
898
899 MMR3HeapFree(pv);
900
901 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
902}
903
904
905/** @interface_method_impl{PDMDEVHLPR3,pfnVMState} */
906static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns)
907{
908 PDMDEV_ASSERT_DEVINS(pDevIns);
909
910 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
911
912 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pReg->szName, pDevIns->iInstance,
913 enmVMState, VMR3GetStateName(enmVMState)));
914 return enmVMState;
915}
916
917
918/** @interface_method_impl{PDMDEVHLPR3,pfnVMTeleportedAndNotFullyResumedYet} */
919static DECLCALLBACK(bool) pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
920{
921 PDMDEV_ASSERT_DEVINS(pDevIns);
922
923 bool fRc = VMR3TeleportedAndNotFullyResumedYet(pDevIns->Internal.s.pVMR3);
924
925 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance,
926 fRc));
927 return fRc;
928}
929
930
931/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetError} */
932static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
933{
934 PDMDEV_ASSERT_DEVINS(pDevIns);
935 va_list args;
936 va_start(args, pszFormat);
937 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
938 va_end(args);
939 return rc;
940}
941
942
943/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetErrorV} */
944static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
945{
946 PDMDEV_ASSERT_DEVINS(pDevIns);
947 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
948 return rc;
949}
950
951
952/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeError} */
953static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
954{
955 PDMDEV_ASSERT_DEVINS(pDevIns);
956 va_list args;
957 va_start(args, pszFormat);
958 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, args);
959 va_end(args);
960 return rc;
961}
962
963
964/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeErrorV} */
965static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
966{
967 PDMDEV_ASSERT_DEVINS(pDevIns);
968 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va);
969 return rc;
970}
971
972
973/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFStopV} */
974static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction, const char *pszFormat, va_list args)
975{
976 PDMDEV_ASSERT_DEVINS(pDevIns);
977#ifdef LOG_ENABLED
978 va_list va2;
979 va_copy(va2, args);
980 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n",
981 pDevIns->pReg->szName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2));
982 va_end(va2);
983#endif
984
985 PVM pVM = pDevIns->Internal.s.pVMR3;
986 VM_ASSERT_EMT(pVM);
987 int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args);
988 if (rc == VERR_DBGF_NOT_ATTACHED)
989 rc = VINF_SUCCESS;
990
991 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
992 return rc;
993}
994
995
996/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegister} */
997static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)
998{
999 PDMDEV_ASSERT_DEVINS(pDevIns);
1000 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",
1001 pDevIns->pReg->szName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));
1002
1003 PVM pVM = pDevIns->Internal.s.pVMR3;
1004 VM_ASSERT_EMT(pVM);
1005 int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns);
1006
1007 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1008 return rc;
1009}
1010
1011
1012/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFRegRegister} */
1013static DECLCALLBACK(int) pdmR3DevHlp_DBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
1014{
1015 PDMDEV_ASSERT_DEVINS(pDevIns);
1016 LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: paRegisters=%p\n",
1017 pDevIns->pReg->szName, pDevIns->iInstance, paRegisters));
1018
1019 PVM pVM = pDevIns->Internal.s.pVMR3;
1020 VM_ASSERT_EMT(pVM);
1021 int rc = DBGFR3RegRegisterDevice(pVM, paRegisters, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance);
1022
1023 LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1024 return rc;
1025}
1026
1027
1028/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFTraceBuf} */
1029static DECLCALLBACK(RTTRACEBUF) pdmR3DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1030{
1031 PDMDEV_ASSERT_DEVINS(pDevIns);
1032 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR3->hTraceBufR3;
1033 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, hTraceBuf));
1034 return hTraceBuf;
1035}
1036
1037
1038/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegister} */
1039static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc)
1040{
1041 PDMDEV_ASSERT_DEVINS(pDevIns);
1042 PVM pVM = pDevIns->Internal.s.pVMR3;
1043 VM_ASSERT_EMT(pVM);
1044
1045 STAM_REG(pVM, pvSample, enmType, pszName, enmUnit, pszDesc);
1046 NOREF(pVM);
1047}
1048
1049
1050
1051/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterF} */
1052static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1053 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, ...)
1054{
1055 PDMDEV_ASSERT_DEVINS(pDevIns);
1056 PVM pVM = pDevIns->Internal.s.pVMR3;
1057 VM_ASSERT_EMT(pVM);
1058
1059 va_list args;
1060 va_start(args, pszName);
1061 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1062 va_end(args);
1063 AssertRC(rc);
1064
1065 NOREF(pVM);
1066}
1067
1068
1069/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterV} */
1070static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1071 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, va_list args)
1072{
1073 PDMDEV_ASSERT_DEVINS(pDevIns);
1074 PVM pVM = pDevIns->Internal.s.pVMR3;
1075 VM_ASSERT_EMT(pVM);
1076
1077 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1078 AssertRC(rc);
1079
1080 NOREF(pVM);
1081}
1082
1083
1084/** @interface_method_impl{PDMDEVHLPR3,pfnPCIDevPhysRead} */
1085static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
1086{
1087 PDMDEV_ASSERT_DEVINS(pDevIns);
1088 return PDMDevHlpPCIDevPhysRead(pDevIns->Internal.s.pPciDeviceR3, GCPhys, pvBuf, cbRead);
1089}
1090
1091
1092/** @interface_method_impl{PDMDEVHLPR3,pfnPCIDevPhysWrite} */
1093static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
1094{
1095 PDMDEV_ASSERT_DEVINS(pDevIns);
1096 return PDMDevHlpPCIDevPhysWrite(pDevIns->Internal.s.pPciDeviceR3, GCPhys, pvBuf, cbWrite);
1097}
1098
1099
1100/** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegister} */
1101static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev)
1102{
1103 PDMDEV_ASSERT_DEVINS(pDevIns);
1104 PVM pVM = pDevIns->Internal.s.pVMR3;
1105 VM_ASSERT_EMT(pVM);
1106 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: pPciDev=%p:{.config={%#.256Rhxs}\n",
1107 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->config));
1108
1109 /*
1110 * Validate input.
1111 */
1112 if (!pPciDev)
1113 {
1114 Assert(pPciDev);
1115 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (pPciDev)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1116 return VERR_INVALID_PARAMETER;
1117 }
1118 if (!pPciDev->config[0] && !pPciDev->config[1])
1119 {
1120 Assert(pPciDev->config[0] || pPciDev->config[1]);
1121 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (vendor)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1122 return VERR_INVALID_PARAMETER;
1123 }
1124 if (pDevIns->Internal.s.pPciDeviceR3)
1125 {
1126 /** @todo the PCI device vs. PDM device designed is a bit flawed if we have to
1127 * support a PDM device with multiple PCI devices. This might become a problem
1128 * when upgrading the chipset for instance because of multiple functions in some
1129 * devices...
1130 */
1131 AssertMsgFailed(("Only one PCI device per device is currently implemented!\n"));
1132 return VERR_PDM_ONE_PCI_FUNCTION_PER_DEVICE;
1133 }
1134
1135 /*
1136 * Choose the PCI bus for the device.
1137 *
1138 * This is simple. If the device was configured for a particular bus, the PCIBusNo
1139 * configuration value will be set. If not the default bus is 0.
1140 */
1141 int rc;
1142 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3;
1143 if (!pBus)
1144 {
1145 uint8_t u8Bus;
1146 rc = CFGMR3QueryU8Def(pDevIns->Internal.s.pCfgHandle, "PCIBusNo", &u8Bus, 0);
1147 AssertLogRelMsgRCReturn(rc, ("Configuration error: PCIBusNo query failed with rc=%Rrc (%s/%d)\n",
1148 rc, pDevIns->pReg->szName, pDevIns->iInstance), rc);
1149 AssertLogRelMsgReturn(u8Bus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
1150 ("Configuration error: PCIBusNo=%d, max is %d. (%s/%d)\n", u8Bus,
1151 RT_ELEMENTS(pVM->pdm.s.aPciBuses), pDevIns->pReg->szName, pDevIns->iInstance),
1152 VERR_PDM_NO_PCI_BUS);
1153 pBus = pDevIns->Internal.s.pPciBusR3 = &pVM->pdm.s.aPciBuses[u8Bus];
1154 }
1155 if (pBus->pDevInsR3)
1156 {
1157 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1158 pDevIns->Internal.s.pPciBusR0 = MMHyperR3ToR0(pVM, pDevIns->Internal.s.pPciBusR3);
1159 else
1160 pDevIns->Internal.s.pPciBusR0 = NIL_RTR0PTR;
1161
1162 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1163 pDevIns->Internal.s.pPciBusRC = MMHyperR3ToRC(pVM, pDevIns->Internal.s.pPciBusR3);
1164 else
1165 pDevIns->Internal.s.pPciBusRC = NIL_RTRCPTR;
1166
1167 /*
1168 * Check the configuration for PCI device and function assignment.
1169 */
1170 int iDev = -1;
1171 uint8_t u8Device;
1172 rc = CFGMR3QueryU8(pDevIns->Internal.s.pCfgHandle, "PCIDeviceNo", &u8Device);
1173 if (RT_SUCCESS(rc))
1174 {
1175 AssertMsgReturn(u8Device <= 31,
1176 ("Configuration error: PCIDeviceNo=%d, max is 31. (%s/%d)\n",
1177 u8Device, pDevIns->pReg->szName, pDevIns->iInstance),
1178 VERR_PDM_BAD_PCI_CONFIG);
1179
1180 uint8_t u8Function;
1181 rc = CFGMR3QueryU8(pDevIns->Internal.s.pCfgHandle, "PCIFunctionNo", &u8Function);
1182 AssertMsgRCReturn(rc, ("Configuration error: PCIDeviceNo, but PCIFunctionNo query failed with rc=%Rrc (%s/%d)\n",
1183 rc, pDevIns->pReg->szName, pDevIns->iInstance),
1184 rc);
1185 AssertMsgReturn(u8Function <= 7,
1186 ("Configuration error: PCIFunctionNo=%d, max is 7. (%s/%d)\n",
1187 u8Function, pDevIns->pReg->szName, pDevIns->iInstance),
1188 VERR_PDM_BAD_PCI_CONFIG);
1189
1190 iDev = (u8Device << 3) | u8Function;
1191 }
1192 else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
1193 {
1194 AssertMsgFailed(("Configuration error: PCIDeviceNo query failed with rc=%Rrc (%s/%d)\n",
1195 rc, pDevIns->pReg->szName, pDevIns->iInstance));
1196 return rc;
1197 }
1198
1199 /*
1200 * Call the pci bus device to do the actual registration.
1201 */
1202 pdmLock(pVM);
1203 rc = pBus->pfnRegisterR3(pBus->pDevInsR3, pPciDev, pDevIns->pReg->szName, iDev);
1204 pdmUnlock(pVM);
1205 if (RT_SUCCESS(rc))
1206 {
1207 pPciDev->pDevIns = pDevIns;
1208
1209 pDevIns->Internal.s.pPciDeviceR3 = pPciDev;
1210 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1211 pDevIns->Internal.s.pPciDeviceR0 = MMHyperR3ToR0(pVM, pPciDev);
1212 else
1213 pDevIns->Internal.s.pPciDeviceR0 = NIL_RTR0PTR;
1214
1215 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1216 pDevIns->Internal.s.pPciDeviceRC = MMHyperR3ToRC(pVM, pPciDev);
1217 else
1218 pDevIns->Internal.s.pPciDeviceRC = NIL_RTRCPTR;
1219
1220 Log(("PDM: Registered device '%s'/%d as PCI device %d on bus %d\n",
1221 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->devfn, pDevIns->Internal.s.pPciBusR3->iBus));
1222 }
1223 }
1224 else
1225 {
1226 AssertLogRelMsgFailed(("Configuration error: No PCI bus available. This could be related to init order too!\n"));
1227 rc = VERR_PDM_NO_PCI_BUS;
1228 }
1229
1230 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1231 return rc;
1232}
1233
1234
1235/** @interface_method_impl{PDMDEVHLPR3,pfnPCIIORegionRegister} */
1236static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1237{
1238 PDMDEV_ASSERT_DEVINS(pDevIns);
1239 PVM pVM = pDevIns->Internal.s.pVMR3;
1240 VM_ASSERT_EMT(pVM);
1241 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: iRegion=%d cbRegion=%#x enmType=%d pfnCallback=%p\n",
1242 pDevIns->pReg->szName, pDevIns->iInstance, iRegion, cbRegion, enmType, pfnCallback));
1243
1244 /*
1245 * Validate input.
1246 */
1247 if (iRegion < 0 || iRegion >= PCI_NUM_REGIONS)
1248 {
1249 Assert(iRegion >= 0 && iRegion < PCI_NUM_REGIONS);
1250 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (iRegion)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1251 return VERR_INVALID_PARAMETER;
1252 }
1253 switch ((int)enmType)
1254 {
1255 case PCI_ADDRESS_SPACE_IO:
1256 /*
1257 * Sanity check: don't allow to register more than 32K of the PCI I/O space.
1258 */
1259 AssertMsgReturn(cbRegion <= _32K,
1260 ("caller='%s'/%d: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cbRegion),
1261 VERR_INVALID_PARAMETER);
1262 break;
1263
1264 case PCI_ADDRESS_SPACE_MEM:
1265 case PCI_ADDRESS_SPACE_MEM_PREFETCH:
1266 case PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_BAR64:
1267 case PCI_ADDRESS_SPACE_MEM_PREFETCH | PCI_ADDRESS_SPACE_BAR64:
1268 /*
1269 * Sanity check: don't allow to register more than 512MB of the PCI MMIO space for
1270 * now. If this limit is increased beyond 2GB, adapt the aligned check below as well!
1271 */
1272 AssertMsgReturn(cbRegion <= 512 * _1M,
1273 ("caller='%s'/%d: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cbRegion),
1274 VERR_INVALID_PARAMETER);
1275 break;
1276 default:
1277 AssertMsgFailed(("enmType=%#x is unknown\n", enmType));
1278 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (enmType)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1279 return VERR_INVALID_PARAMETER;
1280 }
1281 if (!pfnCallback)
1282 {
1283 Assert(pfnCallback);
1284 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (callback)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1285 return VERR_INVALID_PARAMETER;
1286 }
1287 AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1288
1289 /*
1290 * Must have a PCI device registered!
1291 */
1292 int rc;
1293 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
1294 if (pPciDev)
1295 {
1296 /*
1297 * We're currently restricted to page aligned MMIO regions.
1298 */
1299 if ( ((enmType & ~(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_MEM_PREFETCH)) == PCI_ADDRESS_SPACE_MEM)
1300 && cbRegion != RT_ALIGN_32(cbRegion, PAGE_SIZE))
1301 {
1302 Log(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: aligning cbRegion %#x -> %#x\n",
1303 pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, RT_ALIGN_32(cbRegion, PAGE_SIZE)));
1304 cbRegion = RT_ALIGN_32(cbRegion, PAGE_SIZE);
1305 }
1306
1307 /*
1308 * For registering PCI MMIO memory or PCI I/O memory, the size of the region must be a power of 2!
1309 */
1310 int iLastSet = ASMBitLastSetU32(cbRegion);
1311 Assert(iLastSet > 0);
1312 uint32_t cbRegionAligned = RT_BIT_32(iLastSet - 1);
1313 if (cbRegion > cbRegionAligned)
1314 cbRegion = cbRegionAligned * 2; /* round up */
1315
1316 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3;
1317 Assert(pBus);
1318 pdmLock(pVM);
1319 rc = pBus->pfnIORegionRegisterR3(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
1320 pdmUnlock(pVM);
1321 }
1322 else
1323 {
1324 AssertMsgFailed(("No PCI device registered!\n"));
1325 rc = VERR_PDM_NOT_PCI_DEVICE;
1326 }
1327
1328 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1329 return rc;
1330}
1331
1332
1333/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetConfigCallbacks} */
1334static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1335 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1336{
1337 PDMDEV_ASSERT_DEVINS(pDevIns);
1338 PVM pVM = pDevIns->Internal.s.pVMR3;
1339 VM_ASSERT_EMT(pVM);
1340 LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n",
1341 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld));
1342
1343 /*
1344 * Validate input and resolve defaults.
1345 */
1346 AssertPtr(pfnRead);
1347 AssertPtr(pfnWrite);
1348 AssertPtrNull(ppfnReadOld);
1349 AssertPtrNull(ppfnWriteOld);
1350 AssertPtrNull(pPciDev);
1351
1352 if (!pPciDev)
1353 pPciDev = pDevIns->Internal.s.pPciDeviceR3;
1354 AssertReleaseMsg(pPciDev, ("You must register your device first!\n"));
1355 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3;
1356 AssertRelease(pBus);
1357 AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1358
1359 /*
1360 * Do the job.
1361 */
1362 pdmLock(pVM);
1363 pBus->pfnSetConfigCallbacksR3(pBus->pDevInsR3, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
1364 pdmUnlock(pVM);
1365
1366 LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1367}
1368
1369
1370/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrq} */
1371static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1372{
1373 PDMDEV_ASSERT_DEVINS(pDevIns);
1374 LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
1375
1376 /*
1377 * Validate input.
1378 */
1379 Assert(iIrq == 0);
1380 Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1381
1382 /*
1383 * Must have a PCI device registered!
1384 */
1385 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
1386 if (pPciDev)
1387 {
1388 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; /** @todo the bus should be associated with the PCI device not the PDM device. */
1389 Assert(pBus);
1390 PVM pVM = pDevIns->Internal.s.pVMR3;
1391
1392 pdmLock(pVM);
1393 uint32_t uTagSrc;
1394 if (iLevel & PDM_IRQ_LEVEL_HIGH)
1395 {
1396 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1397 if (iLevel == PDM_IRQ_LEVEL_HIGH)
1398 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1399 else
1400 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1401 }
1402 else
1403 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1404
1405 pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, iIrq, iLevel, uTagSrc);
1406
1407 if (iLevel == PDM_IRQ_LEVEL_LOW)
1408 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1409 pdmUnlock(pVM);
1410 }
1411 else
1412 AssertReleaseMsgFailed(("No PCI device registered!\n"));
1413
1414 LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1415}
1416
1417
1418/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrqNoWait} */
1419static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1420{
1421 pdmR3DevHlp_PCISetIrq(pDevIns, iIrq, iLevel);
1422}
1423
1424
1425/** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegisterMsi} */
1426static DECLCALLBACK(int) pdmR3DevHlp_PCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
1427{
1428 PDMDEV_ASSERT_DEVINS(pDevIns);
1429 LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: %d MSI vectors %d MSI-X vectors\n", pDevIns->pReg->szName, pDevIns->iInstance, pMsiReg->cMsiVectors,pMsiReg->cMsixVectors ));
1430 int rc = VINF_SUCCESS;
1431
1432 /*
1433 * Must have a PCI device registered!
1434 */
1435 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
1436 if (pPciDev)
1437 {
1438 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; /** @todo the bus should be associated with the PCI device not the PDM device. */
1439 Assert(pBus);
1440
1441 PVM pVM = pDevIns->Internal.s.pVMR3;
1442 pdmLock(pVM);
1443 if (pBus->pfnRegisterMsiR3)
1444 rc = pBus->pfnRegisterMsiR3(pBus->pDevInsR3, pPciDev, pMsiReg);
1445 else
1446 rc = VERR_NOT_IMPLEMENTED;
1447 pdmUnlock(pVM);
1448 }
1449 else
1450 AssertReleaseMsgFailed(("No PCI device registered!\n"));
1451
1452 LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1453 return rc;
1454}
1455
1456/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrq} */
1457static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1458{
1459 PDMDEV_ASSERT_DEVINS(pDevIns);
1460 LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
1461
1462 /*
1463 * Validate input.
1464 */
1465 Assert(iIrq < 16);
1466 Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1467
1468 PVM pVM = pDevIns->Internal.s.pVMR3;
1469
1470 /*
1471 * Do the job.
1472 */
1473 pdmLock(pVM);
1474 uint32_t uTagSrc;
1475 if (iLevel & PDM_IRQ_LEVEL_HIGH)
1476 {
1477 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1478 if (iLevel == PDM_IRQ_LEVEL_HIGH)
1479 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1480 else
1481 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1482 }
1483 else
1484 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1485
1486 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
1487
1488 if (iLevel == PDM_IRQ_LEVEL_LOW)
1489 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1490 pdmUnlock(pVM);
1491
1492 LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1493}
1494
1495
1496/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrqNoWait} */
1497static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1498{
1499 pdmR3DevHlp_ISASetIrq(pDevIns, iIrq, iLevel);
1500}
1501
1502
1503/** @interface_method_impl{PDMDEVHLPR3,pfnDriverAttach} */
1504static DECLCALLBACK(int) pdmR3DevHlp_DriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc)
1505{
1506 PDMDEV_ASSERT_DEVINS(pDevIns);
1507 PVM pVM = pDevIns->Internal.s.pVMR3;
1508 VM_ASSERT_EMT(pVM);
1509 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: iLun=%d pBaseInterface=%p ppBaseInterface=%p pszDesc=%p:{%s}\n",
1510 pDevIns->pReg->szName, pDevIns->iInstance, iLun, pBaseInterface, ppBaseInterface, pszDesc, pszDesc));
1511
1512 /*
1513 * Lookup the LUN, it might already be registered.
1514 */
1515 PPDMLUN pLunPrev = NULL;
1516 PPDMLUN pLun = pDevIns->Internal.s.pLunsR3;
1517 for (; pLun; pLunPrev = pLun, pLun = pLun->pNext)
1518 if (pLun->iLun == iLun)
1519 break;
1520
1521 /*
1522 * Create the LUN if if wasn't found, else check if driver is already attached to it.
1523 */
1524 if (!pLun)
1525 {
1526 if ( !pBaseInterface
1527 || !pszDesc
1528 || !*pszDesc)
1529 {
1530 Assert(pBaseInterface);
1531 Assert(pszDesc || *pszDesc);
1532 return VERR_INVALID_PARAMETER;
1533 }
1534
1535 pLun = (PPDMLUN)MMR3HeapAlloc(pVM, MM_TAG_PDM_LUN, sizeof(*pLun));
1536 if (!pLun)
1537 return VERR_NO_MEMORY;
1538
1539 pLun->iLun = iLun;
1540 pLun->pNext = pLunPrev ? pLunPrev->pNext : NULL;
1541 pLun->pTop = NULL;
1542 pLun->pBottom = NULL;
1543 pLun->pDevIns = pDevIns;
1544 pLun->pUsbIns = NULL;
1545 pLun->pszDesc = pszDesc;
1546 pLun->pBase = pBaseInterface;
1547 if (!pLunPrev)
1548 pDevIns->Internal.s.pLunsR3 = pLun;
1549 else
1550 pLunPrev->pNext = pLun;
1551 Log(("pdmR3DevHlp_DriverAttach: Registered LUN#%d '%s' with device '%s'/%d.\n",
1552 iLun, pszDesc, pDevIns->pReg->szName, pDevIns->iInstance));
1553 }
1554 else if (pLun->pTop)
1555 {
1556 AssertMsgFailed(("Already attached! The device should keep track of such things!\n"));
1557 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_DRIVER_ALREADY_ATTACHED));
1558 return VERR_PDM_DRIVER_ALREADY_ATTACHED;
1559 }
1560 Assert(pLun->pBase == pBaseInterface);
1561
1562
1563 /*
1564 * Get the attached driver configuration.
1565 */
1566 int rc;
1567 PCFGMNODE pNode = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "LUN#%u", iLun);
1568 if (pNode)
1569 rc = pdmR3DrvInstantiate(pVM, pNode, pBaseInterface, NULL /*pDrvAbove*/, pLun, ppBaseInterface);
1570 else
1571 rc = VERR_PDM_NO_ATTACHED_DRIVER;
1572
1573
1574 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1575 return rc;
1576}
1577
1578
1579/** @interface_method_impl{PDMDEVHLPR3,pfnQueueCreate} */
1580static DECLCALLBACK(int) pdmR3DevHlp_QueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
1581 PFNPDMQUEUEDEV pfnCallback, bool fGCEnabled, const char *pszName, PPDMQUEUE *ppQueue)
1582{
1583 PDMDEV_ASSERT_DEVINS(pDevIns);
1584 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fGCEnabled=%RTbool pszName=%p:{%s} ppQueue=%p\n",
1585 pDevIns->pReg->szName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, pszName, pszName, ppQueue));
1586
1587 PVM pVM = pDevIns->Internal.s.pVMR3;
1588 VM_ASSERT_EMT(pVM);
1589
1590 if (pDevIns->iInstance > 0)
1591 {
1592 pszName = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s_%u", pszName, pDevIns->iInstance);
1593 AssertLogRelReturn(pszName, VERR_NO_MEMORY);
1594 }
1595
1596 int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, pszName, ppQueue);
1597
1598 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: returns %Rrc *ppQueue=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppQueue));
1599 return rc;
1600}
1601
1602
1603/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectInit} */
1604static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1605 const char *pszNameFmt, va_list va)
1606{
1607 PDMDEV_ASSERT_DEVINS(pDevIns);
1608 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n",
1609 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt));
1610
1611 PVM pVM = pDevIns->Internal.s.pVMR3;
1612 VM_ASSERT_EMT(pVM);
1613 int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
1614
1615 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1616 return rc;
1617}
1618
1619
1620/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNop} */
1621static DECLCALLBACK(PPDMCRITSECT) pdmR3DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
1622{
1623 PDMDEV_ASSERT_DEVINS(pDevIns);
1624 PVM pVM = pDevIns->Internal.s.pVMR3;
1625 VM_ASSERT_EMT(pVM);
1626
1627 PPDMCRITSECT pCritSect = PDMR3CritSectGetNop(pVM);
1628 LogFlow(("pdmR3DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n",
1629 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
1630 return pCritSect;
1631}
1632
1633
1634/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopR0} */
1635static DECLCALLBACK(R0PTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopR0(PPDMDEVINS pDevIns)
1636{
1637 PDMDEV_ASSERT_DEVINS(pDevIns);
1638 PVM pVM = pDevIns->Internal.s.pVMR3;
1639 VM_ASSERT_EMT(pVM);
1640
1641 R0PTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopR0(pVM);
1642 LogFlow(("pdmR3DevHlp_CritSectGetNopR0: caller='%s'/%d: return %RHv\n",
1643 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
1644 return pCritSect;
1645}
1646
1647
1648/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopRC} */
1649static DECLCALLBACK(RCPTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopRC(PPDMDEVINS pDevIns)
1650{
1651 PDMDEV_ASSERT_DEVINS(pDevIns);
1652 PVM pVM = pDevIns->Internal.s.pVMR3;
1653 VM_ASSERT_EMT(pVM);
1654
1655 RCPTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopRC(pVM);
1656 LogFlow(("pdmR3DevHlp_CritSectGetNopRC: caller='%s'/%d: return %RRv\n",
1657 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
1658 return pCritSect;
1659}
1660
1661
1662/** @interface_method_impl{PDMDEVHLPR3,pfnSetDeviceCritSect} */
1663static DECLCALLBACK(int) pdmR3DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
1664{
1665 /*
1666 * Validate input.
1667 *
1668 * Note! We only allow the automatically created default critical section
1669 * to be replaced by this API.
1670 */
1671 PDMDEV_ASSERT_DEVINS(pDevIns);
1672 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
1673 LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
1674 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
1675 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
1676 PVM pVM = pDevIns->Internal.s.pVMR3;
1677 AssertReturn(pCritSect->s.pVMR3 == pVM, VERR_INVALID_PARAMETER);
1678
1679 VM_ASSERT_EMT(pVM);
1680 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1681
1682 AssertReturn(pDevIns->pCritSectRoR3, VERR_PDM_DEV_IPE_1);
1683 AssertReturn(pDevIns->pCritSectRoR3->s.fAutomaticDefaultCritsect, VERR_WRONG_ORDER);
1684 AssertReturn(!pDevIns->pCritSectRoR3->s.fUsedByTimerOrSimilar, VERR_WRONG_ORDER);
1685 AssertReturn(pDevIns->pCritSectRoR3 != pCritSect, VERR_INVALID_PARAMETER);
1686
1687 /*
1688 * Replace the critical section and destroy the automatic default section.
1689 */
1690 PPDMCRITSECT pOldCritSect = pDevIns->pCritSectRoR3;
1691 pDevIns->pCritSectRoR3 = pCritSect;
1692 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1693 pDevIns->pCritSectRoR0 = MMHyperCCToR0(pVM, pDevIns->pCritSectRoR3);
1694 else
1695 Assert(pDevIns->pCritSectRoR0 == NIL_RTRCPTR);
1696
1697 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1698 pDevIns->pCritSectRoRC = MMHyperCCToRC(pVM, pDevIns->pCritSectRoR3);
1699 else
1700 Assert(pDevIns->pCritSectRoRC == NIL_RTRCPTR);
1701
1702 PDMR3CritSectDelete(pOldCritSect);
1703 if (pDevIns->pReg->fFlags & (PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0))
1704 MMHyperFree(pVM, pOldCritSect);
1705 else
1706 MMR3HeapFree(pOldCritSect);
1707
1708 LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1709 return VINF_SUCCESS;
1710}
1711
1712
1713/** @interface_method_impl{PDMDEVHLPR3,pfnThreadCreate} */
1714static DECLCALLBACK(int) pdmR3DevHlp_ThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1715 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
1716{
1717 PDMDEV_ASSERT_DEVINS(pDevIns);
1718 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1719 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n",
1720 pDevIns->pReg->szName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName));
1721
1722 int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
1723
1724 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pReg->szName, pDevIns->iInstance,
1725 rc, *ppThread));
1726 return rc;
1727}
1728
1729
1730/** @interface_method_impl{PDMDEVHLPR3,pfnSetAsyncNotification} */
1731static DECLCALLBACK(int) pdmR3DevHlp_SetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
1732{
1733 PDMDEV_ASSERT_DEVINS(pDevIns);
1734 VM_ASSERT_EMT0(pDevIns->Internal.s.pVMR3);
1735 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: pfnAsyncNotify=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pfnAsyncNotify));
1736
1737 int rc = VINF_SUCCESS;
1738 AssertStmt(pfnAsyncNotify, rc = VERR_INVALID_PARAMETER);
1739 AssertStmt(!pDevIns->Internal.s.pfnAsyncNotify, rc = VERR_WRONG_ORDER);
1740 AssertStmt(pDevIns->Internal.s.fIntFlags & (PDMDEVINSINT_FLAGS_SUSPENDED | PDMDEVINSINT_FLAGS_RESET), rc = VERR_WRONG_ORDER);
1741 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
1742 AssertStmt( enmVMState == VMSTATE_SUSPENDING
1743 || enmVMState == VMSTATE_SUSPENDING_EXT_LS
1744 || enmVMState == VMSTATE_SUSPENDING_LS
1745 || enmVMState == VMSTATE_RESETTING
1746 || enmVMState == VMSTATE_RESETTING_LS
1747 || enmVMState == VMSTATE_POWERING_OFF
1748 || enmVMState == VMSTATE_POWERING_OFF_LS,
1749 rc = VERR_INVALID_STATE);
1750
1751 if (RT_SUCCESS(rc))
1752 pDevIns->Internal.s.pfnAsyncNotify = pfnAsyncNotify;
1753
1754 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1755 return rc;
1756}
1757
1758
1759/** @interface_method_impl{PDMDEVHLPR3,pfnAsyncNotificationCompleted} */
1760static DECLCALLBACK(void) pdmR3DevHlp_AsyncNotificationCompleted(PPDMDEVINS pDevIns)
1761{
1762 PDMDEV_ASSERT_DEVINS(pDevIns);
1763 PVM pVM = pDevIns->Internal.s.pVMR3;
1764
1765 VMSTATE enmVMState = VMR3GetState(pVM);
1766 if ( enmVMState == VMSTATE_SUSPENDING
1767 || enmVMState == VMSTATE_SUSPENDING_EXT_LS
1768 || enmVMState == VMSTATE_SUSPENDING_LS
1769 || enmVMState == VMSTATE_RESETTING
1770 || enmVMState == VMSTATE_RESETTING_LS
1771 || enmVMState == VMSTATE_POWERING_OFF
1772 || enmVMState == VMSTATE_POWERING_OFF_LS)
1773 {
1774 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1775 VMR3AsyncPdmNotificationWakeupU(pVM->pUVM);
1776 }
1777 else
1778 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d: enmVMState=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, enmVMState));
1779}
1780
1781
1782/** @interface_method_impl{PDMDEVHLPR3,pfnRTCRegister} */
1783static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
1784{
1785 PDMDEV_ASSERT_DEVINS(pDevIns);
1786 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1787 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n",
1788 pDevIns->pReg->szName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite,
1789 pRtcReg->pfnWrite, ppRtcHlp));
1790
1791 /*
1792 * Validate input.
1793 */
1794 if (pRtcReg->u32Version != PDM_RTCREG_VERSION)
1795 {
1796 AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version,
1797 PDM_RTCREG_VERSION));
1798 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n",
1799 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1800 return VERR_INVALID_PARAMETER;
1801 }
1802 if ( !pRtcReg->pfnWrite
1803 || !pRtcReg->pfnRead)
1804 {
1805 Assert(pRtcReg->pfnWrite);
1806 Assert(pRtcReg->pfnRead);
1807 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
1808 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1809 return VERR_INVALID_PARAMETER;
1810 }
1811
1812 if (!ppRtcHlp)
1813 {
1814 Assert(ppRtcHlp);
1815 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n",
1816 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1817 return VERR_INVALID_PARAMETER;
1818 }
1819
1820 /*
1821 * Only one DMA device.
1822 */
1823 PVM pVM = pDevIns->Internal.s.pVMR3;
1824 if (pVM->pdm.s.pRtc)
1825 {
1826 AssertMsgFailed(("Only one RTC device is supported!\n"));
1827 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
1828 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1829 return VERR_INVALID_PARAMETER;
1830 }
1831
1832 /*
1833 * Allocate and initialize pci bus structure.
1834 */
1835 int rc = VINF_SUCCESS;
1836 PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc));
1837 if (pRtc)
1838 {
1839 pRtc->pDevIns = pDevIns;
1840 pRtc->Reg = *pRtcReg;
1841 pVM->pdm.s.pRtc = pRtc;
1842
1843 /* set the helper pointer. */
1844 *ppRtcHlp = &g_pdmR3DevRtcHlp;
1845 Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n",
1846 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1847 }
1848 else
1849 rc = VERR_NO_MEMORY;
1850
1851 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
1852 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1853 return rc;
1854}
1855
1856
1857/** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */
1858static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
1859{
1860 PDMDEV_ASSERT_DEVINS(pDevIns);
1861 PVM pVM = pDevIns->Internal.s.pVMR3;
1862 VM_ASSERT_EMT(pVM);
1863 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n",
1864 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser));
1865 int rc = VINF_SUCCESS;
1866 if (pVM->pdm.s.pDmac)
1867 pVM->pdm.s.pDmac->Reg.pfnRegister(pVM->pdm.s.pDmac->pDevIns, uChannel, pfnTransferHandler, pvUser);
1868 else
1869 {
1870 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
1871 rc = VERR_PDM_NO_DMAC_INSTANCE;
1872 }
1873 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n",
1874 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1875 return rc;
1876}
1877
1878
1879/** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */
1880static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)
1881{
1882 PDMDEV_ASSERT_DEVINS(pDevIns);
1883 PVM pVM = pDevIns->Internal.s.pVMR3;
1884 VM_ASSERT_EMT(pVM);
1885 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n",
1886 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead));
1887 int rc = VINF_SUCCESS;
1888 if (pVM->pdm.s.pDmac)
1889 {
1890 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnReadMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
1891 if (pcbRead)
1892 *pcbRead = cb;
1893 }
1894 else
1895 {
1896 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
1897 rc = VERR_PDM_NO_DMAC_INSTANCE;
1898 }
1899 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n",
1900 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1901 return rc;
1902}
1903
1904
1905/** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */
1906static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)
1907{
1908 PDMDEV_ASSERT_DEVINS(pDevIns);
1909 PVM pVM = pDevIns->Internal.s.pVMR3;
1910 VM_ASSERT_EMT(pVM);
1911 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n",
1912 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten));
1913 int rc = VINF_SUCCESS;
1914 if (pVM->pdm.s.pDmac)
1915 {
1916 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnWriteMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
1917 if (pcbWritten)
1918 *pcbWritten = cb;
1919 }
1920 else
1921 {
1922 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
1923 rc = VERR_PDM_NO_DMAC_INSTANCE;
1924 }
1925 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n",
1926 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1927 return rc;
1928}
1929
1930
1931/** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */
1932static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
1933{
1934 PDMDEV_ASSERT_DEVINS(pDevIns);
1935 PVM pVM = pDevIns->Internal.s.pVMR3;
1936 VM_ASSERT_EMT(pVM);
1937 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n",
1938 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, uLevel));
1939 int rc = VINF_SUCCESS;
1940 if (pVM->pdm.s.pDmac)
1941 pVM->pdm.s.pDmac->Reg.pfnSetDREQ(pVM->pdm.s.pDmac->pDevIns, uChannel, uLevel);
1942 else
1943 {
1944 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
1945 rc = VERR_PDM_NO_DMAC_INSTANCE;
1946 }
1947 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n",
1948 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1949 return rc;
1950}
1951
1952/** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */
1953static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
1954{
1955 PDMDEV_ASSERT_DEVINS(pDevIns);
1956 PVM pVM = pDevIns->Internal.s.pVMR3;
1957 VM_ASSERT_EMT(pVM);
1958 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n",
1959 pDevIns->pReg->szName, pDevIns->iInstance, uChannel));
1960 uint8_t u8Mode;
1961 if (pVM->pdm.s.pDmac)
1962 u8Mode = pVM->pdm.s.pDmac->Reg.pfnGetChannelMode(pVM->pdm.s.pDmac->pDevIns, uChannel);
1963 else
1964 {
1965 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
1966 u8Mode = 3 << 2 /* illegal mode type */;
1967 }
1968 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n",
1969 pDevIns->pReg->szName, pDevIns->iInstance, u8Mode));
1970 return u8Mode;
1971}
1972
1973/** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */
1974static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns)
1975{
1976 PDMDEV_ASSERT_DEVINS(pDevIns);
1977 PVM pVM = pDevIns->Internal.s.pVMR3;
1978 VM_ASSERT_EMT(pVM);
1979 LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n",
1980 pDevIns->pReg->szName, pDevIns->iInstance, VM_FF_ISSET(pVM, VM_FF_PDM_DMA)));
1981
1982 AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
1983 VM_FF_SET(pVM, VM_FF_PDM_DMA);
1984#ifdef VBOX_WITH_REM
1985 REMR3NotifyDmaPending(pVM);
1986#endif
1987 VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM);
1988}
1989
1990
1991/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */
1992static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
1993{
1994 PDMDEV_ASSERT_DEVINS(pDevIns);
1995 PVM pVM = pDevIns->Internal.s.pVMR3;
1996 VM_ASSERT_EMT(pVM);
1997
1998 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n",
1999 pDevIns->pReg->szName, pDevIns->iInstance, iReg, u8Value));
2000 int rc;
2001 if (pVM->pdm.s.pRtc)
2002 {
2003 PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2004 rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2005 if (RT_SUCCESS(rc))
2006 {
2007 rc = pVM->pdm.s.pRtc->Reg.pfnWrite(pDevInsRtc, iReg, u8Value);
2008 PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2009 }
2010 }
2011 else
2012 rc = VERR_PDM_NO_RTC_INSTANCE;
2013
2014 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2015 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2016 return rc;
2017}
2018
2019
2020/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */
2021static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
2022{
2023 PDMDEV_ASSERT_DEVINS(pDevIns);
2024 PVM pVM = pDevIns->Internal.s.pVMR3;
2025 VM_ASSERT_EMT(pVM);
2026
2027 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n",
2028 pDevIns->pReg->szName, pDevIns->iInstance, iReg, pu8Value));
2029 int rc;
2030 if (pVM->pdm.s.pRtc)
2031 {
2032 PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2033 rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2034 if (RT_SUCCESS(rc))
2035 {
2036 rc = pVM->pdm.s.pRtc->Reg.pfnRead(pDevInsRtc, iReg, pu8Value);
2037 PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2038 }
2039 }
2040 else
2041 rc = VERR_PDM_NO_RTC_INSTANCE;
2042
2043 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2044 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2045 return rc;
2046}
2047
2048
2049/** @interface_method_impl{PDMDEVHLPR3,pfnAssertEMT} */
2050static DECLCALLBACK(bool) pdmR3DevHlp_AssertEMT(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction)
2051{
2052 PDMDEV_ASSERT_DEVINS(pDevIns);
2053 if (VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2054 return true;
2055
2056 char szMsg[100];
2057 RTStrPrintf(szMsg, sizeof(szMsg), "AssertEMT '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2058 RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2059 AssertBreakpoint();
2060 return false;
2061}
2062
2063
2064/** @interface_method_impl{PDMDEVHLPR3,pfnAssertOther} */
2065static DECLCALLBACK(bool) pdmR3DevHlp_AssertOther(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction)
2066{
2067 PDMDEV_ASSERT_DEVINS(pDevIns);
2068 if (!VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2069 return true;
2070
2071 char szMsg[100];
2072 RTStrPrintf(szMsg, sizeof(szMsg), "AssertOther '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2073 RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2074 AssertBreakpoint();
2075 return false;
2076}
2077
2078
2079/** @interface_method_impl{PDMDEVHLP,pfnLdrGetRCInterfaceSymbols} */
2080static DECLCALLBACK(int) pdmR3DevHlp_LdrGetRCInterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2081 const char *pszSymPrefix, const char *pszSymList)
2082{
2083 PDMDEV_ASSERT_DEVINS(pDevIns);
2084 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2085 LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2086 pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2087
2088 int rc;
2089 if ( strncmp(pszSymPrefix, "dev", 3) == 0
2090 && RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2091 {
2092 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
2093 rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2094 pvInterface, cbInterface,
2095 pDevIns->pReg->szRCMod, pDevIns->Internal.s.pDevR3->pszRCSearchPath,
2096 pszSymPrefix, pszSymList,
2097 false /*fRing0OrRC*/);
2098 else
2099 {
2100 AssertMsgFailed(("Not a raw-mode enabled driver\n"));
2101 rc = VERR_PERMISSION_DENIED;
2102 }
2103 }
2104 else
2105 {
2106 AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2107 pszSymPrefix, pDevIns->pReg->szName));
2108 rc = VERR_INVALID_NAME;
2109 }
2110
2111 LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2112 pDevIns->iInstance, rc));
2113 return rc;
2114}
2115
2116
2117/** @interface_method_impl{PDMDEVHLP,pfnLdrGetR0InterfaceSymbols} */
2118static DECLCALLBACK(int) pdmR3DevHlp_LdrGetR0InterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2119 const char *pszSymPrefix, const char *pszSymList)
2120{
2121 PDMDEV_ASSERT_DEVINS(pDevIns);
2122 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2123 LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2124 pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2125
2126 int rc;
2127 if ( strncmp(pszSymPrefix, "dev", 3) == 0
2128 && RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2129 {
2130 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2131 rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2132 pvInterface, cbInterface,
2133 pDevIns->pReg->szR0Mod, pDevIns->Internal.s.pDevR3->pszR0SearchPath,
2134 pszSymPrefix, pszSymList,
2135 true /*fRing0OrRC*/);
2136 else
2137 {
2138 AssertMsgFailed(("Not a ring-0 enabled driver\n"));
2139 rc = VERR_PERMISSION_DENIED;
2140 }
2141 }
2142 else
2143 {
2144 AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2145 pszSymPrefix, pDevIns->pReg->szName));
2146 rc = VERR_INVALID_NAME;
2147 }
2148
2149 LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2150 pDevIns->iInstance, rc));
2151 return rc;
2152}
2153
2154
2155/** @interface_method_impl{PDMDEVHLP,pfnCallR0} */
2156static DECLCALLBACK(int) pdmR3DevHlp_CallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
2157{
2158 PDMDEV_ASSERT_DEVINS(pDevIns);
2159 PVM pVM = pDevIns->Internal.s.pVMR3;
2160 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2161 LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: uOperation=%#x u64Arg=%#RX64\n",
2162 pDevIns->pReg->szName, pDevIns->iInstance, uOperation, u64Arg));
2163
2164 /*
2165 * Resolve the ring-0 entry point. There is not need to remember this like
2166 * we do for drivers since this is mainly for construction time hacks and
2167 * other things that aren't performance critical.
2168 */
2169 int rc;
2170 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2171 {
2172 char szSymbol[ sizeof("devR0") + sizeof(pDevIns->pReg->szName) + sizeof("ReqHandler")];
2173 strcat(strcat(strcpy(szSymbol, "devR0"), pDevIns->pReg->szName), "ReqHandler");
2174 szSymbol[sizeof("devR0") - 1] = RT_C_TO_UPPER(szSymbol[sizeof("devR0") - 1]);
2175
2176 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
2177 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, szSymbol, &pfnReqHandlerR0);
2178 if (RT_SUCCESS(rc))
2179 {
2180 /*
2181 * Make the ring-0 call.
2182 */
2183 PDMDEVICECALLREQHANDLERREQ Req;
2184 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2185 Req.Hdr.cbReq = sizeof(Req);
2186 Req.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2187 Req.pfnReqHandlerR0 = pfnReqHandlerR0;
2188 Req.uOperation = uOperation;
2189 Req.u32Alignment = 0;
2190 Req.u64Arg = u64Arg;
2191 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_PDM_DEVICE_CALL_REQ_HANDLER, 0, &Req.Hdr);
2192 }
2193 else
2194 pfnReqHandlerR0 = NIL_RTR0PTR;
2195 }
2196 else
2197 rc = VERR_ACCESS_DENIED;
2198 LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2199 pDevIns->iInstance, rc));
2200 return rc;
2201}
2202
2203
2204/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
2205static DECLCALLBACK(PUVM) pdmR3DevHlp_GetUVM(PPDMDEVINS pDevIns)
2206{
2207 PDMDEV_ASSERT_DEVINS(pDevIns);
2208 LogFlow(("pdmR3DevHlp_GetUVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2209 return pDevIns->Internal.s.pVMR3->pUVM;
2210}
2211
2212
2213/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
2214static DECLCALLBACK(PVM) pdmR3DevHlp_GetVM(PPDMDEVINS pDevIns)
2215{
2216 PDMDEV_ASSERT_DEVINS(pDevIns);
2217 LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2218 return pDevIns->Internal.s.pVMR3;
2219}
2220
2221
2222/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
2223static DECLCALLBACK(PVMCPU) pdmR3DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
2224{
2225 PDMDEV_ASSERT_DEVINS(pDevIns);
2226 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2227 LogFlow(("pdmR3DevHlp_GetVMCPU: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, VMMGetCpuId(pDevIns->Internal.s.pVMR3)));
2228 return VMMGetCpu(pDevIns->Internal.s.pVMR3);
2229}
2230
2231
2232/** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */
2233static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3)
2234{
2235 PDMDEV_ASSERT_DEVINS(pDevIns);
2236 PVM pVM = pDevIns->Internal.s.pVMR3;
2237 VM_ASSERT_EMT(pVM);
2238 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
2239 ".pfnSetIrqR3=%p, .pfnFakePCIBIOSR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p\n",
2240 pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
2241 pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pfnFakePCIBIOSR3,
2242 pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3));
2243
2244 /*
2245 * Validate the structure.
2246 */
2247 if (pPciBusReg->u32Version != PDM_PCIBUSREG_VERSION)
2248 {
2249 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREG_VERSION));
2250 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2251 return VERR_INVALID_PARAMETER;
2252 }
2253 if ( !pPciBusReg->pfnRegisterR3
2254 || !pPciBusReg->pfnIORegionRegisterR3
2255 || !pPciBusReg->pfnSetIrqR3
2256 || (!pPciBusReg->pfnFakePCIBIOSR3 && !pVM->pdm.s.aPciBuses[0].pDevInsR3)) /* Only the first bus needs to do the BIOS work. */
2257 {
2258 Assert(pPciBusReg->pfnRegisterR3);
2259 Assert(pPciBusReg->pfnIORegionRegisterR3);
2260 Assert(pPciBusReg->pfnSetIrqR3);
2261 Assert(pPciBusReg->pfnFakePCIBIOSR3);
2262 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2263 return VERR_INVALID_PARAMETER;
2264 }
2265 if ( pPciBusReg->pszSetIrqRC
2266 && !VALID_PTR(pPciBusReg->pszSetIrqRC))
2267 {
2268 Assert(VALID_PTR(pPciBusReg->pszSetIrqRC));
2269 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2270 return VERR_INVALID_PARAMETER;
2271 }
2272 if ( pPciBusReg->pszSetIrqR0
2273 && !VALID_PTR(pPciBusReg->pszSetIrqR0))
2274 {
2275 Assert(VALID_PTR(pPciBusReg->pszSetIrqR0));
2276 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2277 return VERR_INVALID_PARAMETER;
2278 }
2279 if (!ppPciHlpR3)
2280 {
2281 Assert(ppPciHlpR3);
2282 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (ppPciHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2283 return VERR_INVALID_PARAMETER;
2284 }
2285
2286 /*
2287 * Find free PCI bus entry.
2288 */
2289 unsigned iBus = 0;
2290 for (iBus = 0; iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses); iBus++)
2291 if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
2292 break;
2293 if (iBus >= RT_ELEMENTS(pVM->pdm.s.aPciBuses))
2294 {
2295 AssertMsgFailed(("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)));
2296 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (pci bus)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2297 return VERR_INVALID_PARAMETER;
2298 }
2299 PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
2300
2301 /*
2302 * Resolve and init the RC bits.
2303 */
2304 if (pPciBusReg->pszSetIrqRC)
2305 {
2306 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPciBusReg->pszSetIrqRC, &pPciBus->pfnSetIrqRC);
2307 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPciBusReg->pszSetIrqRC, rc));
2308 if (RT_FAILURE(rc))
2309 {
2310 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2311 return rc;
2312 }
2313 pPciBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2314 }
2315 else
2316 {
2317 pPciBus->pfnSetIrqRC = 0;
2318 pPciBus->pDevInsRC = 0;
2319 }
2320
2321 /*
2322 * Resolve and init the R0 bits.
2323 */
2324 if (pPciBusReg->pszSetIrqR0)
2325 {
2326 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPciBusReg->pszSetIrqR0, &pPciBus->pfnSetIrqR0);
2327 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPciBusReg->pszSetIrqR0, rc));
2328 if (RT_FAILURE(rc))
2329 {
2330 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2331 return rc;
2332 }
2333 pPciBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2334 }
2335 else
2336 {
2337 pPciBus->pfnSetIrqR0 = 0;
2338 pPciBus->pDevInsR0 = 0;
2339 }
2340
2341 /*
2342 * Init the R3 bits.
2343 */
2344 pPciBus->iBus = iBus;
2345 pPciBus->pDevInsR3 = pDevIns;
2346 pPciBus->pfnRegisterR3 = pPciBusReg->pfnRegisterR3;
2347 pPciBus->pfnRegisterMsiR3 = pPciBusReg->pfnRegisterMsiR3;
2348 pPciBus->pfnIORegionRegisterR3 = pPciBusReg->pfnIORegionRegisterR3;
2349 pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
2350 pPciBus->pfnSetIrqR3 = pPciBusReg->pfnSetIrqR3;
2351 pPciBus->pfnFakePCIBIOSR3 = pPciBusReg->pfnFakePCIBIOSR3;
2352
2353 Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2354
2355 /* set the helper pointer and return. */
2356 *ppPciHlpR3 = &g_pdmR3DevPciHlp;
2357 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2358 return VINF_SUCCESS;
2359}
2360
2361
2362/** @interface_method_impl{PDMDEVHLPR3,pfnPICRegister} */
2363static DECLCALLBACK(int) pdmR3DevHlp_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
2364{
2365 PDMDEV_ASSERT_DEVINS(pDevIns);
2366 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2367 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pfnGetInterruptR3=%p, .pszGetIrqRC=%p:{%s}, .pszGetInterruptRC=%p:{%s}, .pszGetIrqR0=%p:{%s}, .pszGetInterruptR0=%p:{%s} } ppPicHlpR3=%p\n",
2368 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrqR3, pPicReg->pfnGetInterruptR3,
2369 pPicReg->pszSetIrqRC, pPicReg->pszSetIrqRC, pPicReg->pszGetInterruptRC, pPicReg->pszGetInterruptRC,
2370 pPicReg->pszSetIrqR0, pPicReg->pszSetIrqR0, pPicReg->pszGetInterruptR0, pPicReg->pszGetInterruptR0,
2371 ppPicHlpR3));
2372
2373 /*
2374 * Validate input.
2375 */
2376 if (pPicReg->u32Version != PDM_PICREG_VERSION)
2377 {
2378 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPicReg->u32Version, PDM_PICREG_VERSION));
2379 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2380 return VERR_INVALID_PARAMETER;
2381 }
2382 if ( !pPicReg->pfnSetIrqR3
2383 || !pPicReg->pfnGetInterruptR3)
2384 {
2385 Assert(pPicReg->pfnSetIrqR3);
2386 Assert(pPicReg->pfnGetInterruptR3);
2387 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2388 return VERR_INVALID_PARAMETER;
2389 }
2390 if ( ( pPicReg->pszSetIrqRC
2391 || pPicReg->pszGetInterruptRC)
2392 && ( !VALID_PTR(pPicReg->pszSetIrqRC)
2393 || !VALID_PTR(pPicReg->pszGetInterruptRC))
2394 )
2395 {
2396 Assert(VALID_PTR(pPicReg->pszSetIrqRC));
2397 Assert(VALID_PTR(pPicReg->pszGetInterruptRC));
2398 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2399 return VERR_INVALID_PARAMETER;
2400 }
2401 if ( pPicReg->pszSetIrqRC
2402 && !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC))
2403 {
2404 Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC);
2405 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2406 return VERR_INVALID_PARAMETER;
2407 }
2408 if ( pPicReg->pszSetIrqR0
2409 && !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
2410 {
2411 Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0);
2412 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R0 flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2413 return VERR_INVALID_PARAMETER;
2414 }
2415 if (!ppPicHlpR3)
2416 {
2417 Assert(ppPicHlpR3);
2418 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (ppPicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2419 return VERR_INVALID_PARAMETER;
2420 }
2421
2422 /*
2423 * Only one PIC device.
2424 */
2425 PVM pVM = pDevIns->Internal.s.pVMR3;
2426 if (pVM->pdm.s.Pic.pDevInsR3)
2427 {
2428 AssertMsgFailed(("Only one pic device is supported!\n"));
2429 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2430 return VERR_INVALID_PARAMETER;
2431 }
2432
2433 /*
2434 * RC stuff.
2435 */
2436 if (pPicReg->pszSetIrqRC)
2437 {
2438 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszSetIrqRC, &pVM->pdm.s.Pic.pfnSetIrqRC);
2439 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszSetIrqRC, rc));
2440 if (RT_SUCCESS(rc))
2441 {
2442 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszGetInterruptRC, &pVM->pdm.s.Pic.pfnGetInterruptRC);
2443 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszGetInterruptRC, rc));
2444 }
2445 if (RT_FAILURE(rc))
2446 {
2447 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2448 return rc;
2449 }
2450 pVM->pdm.s.Pic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2451 }
2452 else
2453 {
2454 pVM->pdm.s.Pic.pDevInsRC = 0;
2455 pVM->pdm.s.Pic.pfnSetIrqRC = 0;
2456 pVM->pdm.s.Pic.pfnGetInterruptRC = 0;
2457 }
2458
2459 /*
2460 * R0 stuff.
2461 */
2462 if (pPicReg->pszSetIrqR0)
2463 {
2464 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszSetIrqR0, &pVM->pdm.s.Pic.pfnSetIrqR0);
2465 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszSetIrqR0, rc));
2466 if (RT_SUCCESS(rc))
2467 {
2468 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszGetInterruptR0, &pVM->pdm.s.Pic.pfnGetInterruptR0);
2469 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszGetInterruptR0, rc));
2470 }
2471 if (RT_FAILURE(rc))
2472 {
2473 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2474 return rc;
2475 }
2476 pVM->pdm.s.Pic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2477 Assert(pVM->pdm.s.Pic.pDevInsR0);
2478 }
2479 else
2480 {
2481 pVM->pdm.s.Pic.pfnSetIrqR0 = 0;
2482 pVM->pdm.s.Pic.pfnGetInterruptR0 = 0;
2483 pVM->pdm.s.Pic.pDevInsR0 = 0;
2484 }
2485
2486 /*
2487 * R3 stuff.
2488 */
2489 pVM->pdm.s.Pic.pDevInsR3 = pDevIns;
2490 pVM->pdm.s.Pic.pfnSetIrqR3 = pPicReg->pfnSetIrqR3;
2491 pVM->pdm.s.Pic.pfnGetInterruptR3 = pPicReg->pfnGetInterruptR3;
2492 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2493
2494 /* set the helper pointer and return. */
2495 *ppPicHlpR3 = &g_pdmR3DevPicHlp;
2496 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2497 return VINF_SUCCESS;
2498}
2499
2500
2501/** @interface_method_impl{PDMDEVHLPR3,pfnAPICRegister} */
2502static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg, PCPDMAPICHLPR3 *ppApicHlpR3)
2503{
2504 PDMDEV_ASSERT_DEVINS(pDevIns);
2505 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2506 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: pApicReg=%p:{.u32Version=%#x, .pfnGetInterruptR3=%p, .pfnSetBaseR3=%p, .pfnGetBaseR3=%p, "
2507 ".pfnSetTPRR3=%p, .pfnGetTPRR3=%p, .pfnWriteMSR3=%p, .pfnReadMSR3=%p, .pfnBusDeliverR3=%p, .pfnLocalInterruptR3=%p, pszGetInterruptRC=%p:{%s}, pszSetBaseRC=%p:{%s}, pszGetBaseRC=%p:{%s}, "
2508 ".pszSetTPRRC=%p:{%s}, .pszGetTPRRC=%p:{%s}, .pszWriteMSRRC=%p:{%s}, .pszReadMSRRC=%p:{%s}, .pszBusDeliverRC=%p:{%s}, .pszLocalInterruptRC=%p:{%s}} ppApicHlpR3=%p\n",
2509 pDevIns->pReg->szName, pDevIns->iInstance, pApicReg, pApicReg->u32Version, pApicReg->pfnGetInterruptR3, pApicReg->pfnSetBaseR3,
2510 pApicReg->pfnGetBaseR3, pApicReg->pfnSetTPRR3, pApicReg->pfnGetTPRR3, pApicReg->pfnWriteMSRR3, pApicReg->pfnReadMSRR3, pApicReg->pfnBusDeliverR3, pApicReg->pfnLocalInterruptR3, pApicReg->pszGetInterruptRC,
2511 pApicReg->pszGetInterruptRC, pApicReg->pszSetBaseRC, pApicReg->pszSetBaseRC, pApicReg->pszGetBaseRC, pApicReg->pszGetBaseRC,
2512 pApicReg->pszSetTPRRC, pApicReg->pszSetTPRRC, pApicReg->pszGetTPRRC, pApicReg->pszGetTPRRC, pApicReg->pszWriteMSRRC, pApicReg->pszWriteMSRRC, pApicReg->pszReadMSRRC, pApicReg->pszReadMSRRC, pApicReg->pszBusDeliverRC,
2513 pApicReg->pszBusDeliverRC, pApicReg->pszLocalInterruptRC, pApicReg->pszLocalInterruptRC, ppApicHlpR3));
2514
2515 /*
2516 * Validate input.
2517 */
2518 if (pApicReg->u32Version != PDM_APICREG_VERSION)
2519 {
2520 AssertMsgFailed(("u32Version=%#x expected %#x\n", pApicReg->u32Version, PDM_APICREG_VERSION));
2521 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2522 return VERR_INVALID_PARAMETER;
2523 }
2524 if ( !pApicReg->pfnGetInterruptR3
2525 || !pApicReg->pfnHasPendingIrqR3
2526 || !pApicReg->pfnSetBaseR3
2527 || !pApicReg->pfnGetBaseR3
2528 || !pApicReg->pfnSetTPRR3
2529 || !pApicReg->pfnGetTPRR3
2530 || !pApicReg->pfnWriteMSRR3
2531 || !pApicReg->pfnReadMSRR3
2532 || !pApicReg->pfnBusDeliverR3
2533 || !pApicReg->pfnLocalInterruptR3)
2534 {
2535 Assert(pApicReg->pfnGetInterruptR3);
2536 Assert(pApicReg->pfnHasPendingIrqR3);
2537 Assert(pApicReg->pfnSetBaseR3);
2538 Assert(pApicReg->pfnGetBaseR3);
2539 Assert(pApicReg->pfnSetTPRR3);
2540 Assert(pApicReg->pfnGetTPRR3);
2541 Assert(pApicReg->pfnWriteMSRR3);
2542 Assert(pApicReg->pfnReadMSRR3);
2543 Assert(pApicReg->pfnBusDeliverR3);
2544 Assert(pApicReg->pfnLocalInterruptR3);
2545 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2546 return VERR_INVALID_PARAMETER;
2547 }
2548 if ( ( pApicReg->pszGetInterruptRC
2549 || pApicReg->pszHasPendingIrqRC
2550 || pApicReg->pszSetBaseRC
2551 || pApicReg->pszGetBaseRC
2552 || pApicReg->pszSetTPRRC
2553 || pApicReg->pszGetTPRRC
2554 || pApicReg->pszWriteMSRRC
2555 || pApicReg->pszReadMSRRC
2556 || pApicReg->pszBusDeliverRC
2557 || pApicReg->pszLocalInterruptRC)
2558 && ( !VALID_PTR(pApicReg->pszGetInterruptRC)
2559 || !VALID_PTR(pApicReg->pszHasPendingIrqRC)
2560 || !VALID_PTR(pApicReg->pszSetBaseRC)
2561 || !VALID_PTR(pApicReg->pszGetBaseRC)
2562 || !VALID_PTR(pApicReg->pszSetTPRRC)
2563 || !VALID_PTR(pApicReg->pszGetTPRRC)
2564 || !VALID_PTR(pApicReg->pszWriteMSRRC)
2565 || !VALID_PTR(pApicReg->pszReadMSRRC)
2566 || !VALID_PTR(pApicReg->pszBusDeliverRC)
2567 || !VALID_PTR(pApicReg->pszLocalInterruptRC))
2568 )
2569 {
2570 Assert(VALID_PTR(pApicReg->pszGetInterruptRC));
2571 Assert(VALID_PTR(pApicReg->pszHasPendingIrqRC));
2572 Assert(VALID_PTR(pApicReg->pszSetBaseRC));
2573 Assert(VALID_PTR(pApicReg->pszGetBaseRC));
2574 Assert(VALID_PTR(pApicReg->pszSetTPRRC));
2575 Assert(VALID_PTR(pApicReg->pszGetTPRRC));
2576 Assert(VALID_PTR(pApicReg->pszReadMSRRC));
2577 Assert(VALID_PTR(pApicReg->pszWriteMSRRC));
2578 Assert(VALID_PTR(pApicReg->pszBusDeliverRC));
2579 Assert(VALID_PTR(pApicReg->pszLocalInterruptRC));
2580 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2581 return VERR_INVALID_PARAMETER;
2582 }
2583 if ( ( pApicReg->pszGetInterruptR0
2584 || pApicReg->pszHasPendingIrqR0
2585 || pApicReg->pszSetBaseR0
2586 || pApicReg->pszGetBaseR0
2587 || pApicReg->pszSetTPRR0
2588 || pApicReg->pszGetTPRR0
2589 || pApicReg->pszWriteMSRR0
2590 || pApicReg->pszReadMSRR0
2591 || pApicReg->pszBusDeliverR0
2592 || pApicReg->pszLocalInterruptR0)
2593 && ( !VALID_PTR(pApicReg->pszGetInterruptR0)
2594 || !VALID_PTR(pApicReg->pszHasPendingIrqR0)
2595 || !VALID_PTR(pApicReg->pszSetBaseR0)
2596 || !VALID_PTR(pApicReg->pszGetBaseR0)
2597 || !VALID_PTR(pApicReg->pszSetTPRR0)
2598 || !VALID_PTR(pApicReg->pszGetTPRR0)
2599 || !VALID_PTR(pApicReg->pszReadMSRR0)
2600 || !VALID_PTR(pApicReg->pszWriteMSRR0)
2601 || !VALID_PTR(pApicReg->pszBusDeliverR0)
2602 || !VALID_PTR(pApicReg->pszLocalInterruptR0))
2603 )
2604 {
2605 Assert(VALID_PTR(pApicReg->pszGetInterruptR0));
2606 Assert(VALID_PTR(pApicReg->pszHasPendingIrqR0));
2607 Assert(VALID_PTR(pApicReg->pszSetBaseR0));
2608 Assert(VALID_PTR(pApicReg->pszGetBaseR0));
2609 Assert(VALID_PTR(pApicReg->pszSetTPRR0));
2610 Assert(VALID_PTR(pApicReg->pszGetTPRR0));
2611 Assert(VALID_PTR(pApicReg->pszReadMSRR0));
2612 Assert(VALID_PTR(pApicReg->pszWriteMSRR0));
2613 Assert(VALID_PTR(pApicReg->pszBusDeliverR0));
2614 Assert(VALID_PTR(pApicReg->pszLocalInterruptR0));
2615 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R0 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2616 return VERR_INVALID_PARAMETER;
2617 }
2618 if (!ppApicHlpR3)
2619 {
2620 Assert(ppApicHlpR3);
2621 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2622 return VERR_INVALID_PARAMETER;
2623 }
2624
2625 /*
2626 * Only one APIC device. On SMP we have single logical device covering all LAPICs,
2627 * as they need to communicate and share state easily.
2628 */
2629 PVM pVM = pDevIns->Internal.s.pVMR3;
2630 if (pVM->pdm.s.Apic.pDevInsR3)
2631 {
2632 AssertMsgFailed(("Only one apic device is supported!\n"));
2633 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2634 return VERR_INVALID_PARAMETER;
2635 }
2636
2637 /*
2638 * Resolve & initialize the RC bits.
2639 */
2640 if (pApicReg->pszGetInterruptRC)
2641 {
2642 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetInterruptRC, &pVM->pdm.s.Apic.pfnGetInterruptRC);
2643 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetInterruptRC, rc));
2644 if (RT_SUCCESS(rc))
2645 {
2646 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszHasPendingIrqRC, &pVM->pdm.s.Apic.pfnHasPendingIrqRC);
2647 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszHasPendingIrqRC, rc));
2648 }
2649 if (RT_SUCCESS(rc))
2650 {
2651 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszSetBaseRC, &pVM->pdm.s.Apic.pfnSetBaseRC);
2652 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszSetBaseRC, rc));
2653 }
2654 if (RT_SUCCESS(rc))
2655 {
2656 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetBaseRC, &pVM->pdm.s.Apic.pfnGetBaseRC);
2657 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetBaseRC, rc));
2658 }
2659 if (RT_SUCCESS(rc))
2660 {
2661 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszSetTPRRC, &pVM->pdm.s.Apic.pfnSetTPRRC);
2662 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszSetTPRRC, rc));
2663 }
2664 if (RT_SUCCESS(rc))
2665 {
2666 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetTPRRC, &pVM->pdm.s.Apic.pfnGetTPRRC);
2667 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetTPRRC, rc));
2668 }
2669 if (RT_SUCCESS(rc))
2670 {
2671 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszWriteMSRRC, &pVM->pdm.s.Apic.pfnWriteMSRRC);
2672 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszWriteMSRRC, rc));
2673 }
2674 if (RT_SUCCESS(rc))
2675 {
2676 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszReadMSRRC, &pVM->pdm.s.Apic.pfnReadMSRRC);
2677 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszReadMSRRC, rc));
2678 }
2679 if (RT_SUCCESS(rc))
2680 {
2681 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszBusDeliverRC, &pVM->pdm.s.Apic.pfnBusDeliverRC);
2682 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszBusDeliverRC, rc));
2683 }
2684 if (RT_SUCCESS(rc))
2685 {
2686 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszLocalInterruptRC, &pVM->pdm.s.Apic.pfnLocalInterruptRC);
2687 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszLocalInterruptRC, rc));
2688 }
2689 if (RT_FAILURE(rc))
2690 {
2691 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2692 return rc;
2693 }
2694 pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2695 }
2696 else
2697 {
2698 pVM->pdm.s.Apic.pDevInsRC = 0;
2699 pVM->pdm.s.Apic.pfnGetInterruptRC = 0;
2700 pVM->pdm.s.Apic.pfnHasPendingIrqRC = 0;
2701 pVM->pdm.s.Apic.pfnSetBaseRC = 0;
2702 pVM->pdm.s.Apic.pfnGetBaseRC = 0;
2703 pVM->pdm.s.Apic.pfnSetTPRRC = 0;
2704 pVM->pdm.s.Apic.pfnGetTPRRC = 0;
2705 pVM->pdm.s.Apic.pfnWriteMSRRC = 0;
2706 pVM->pdm.s.Apic.pfnReadMSRRC = 0;
2707 pVM->pdm.s.Apic.pfnBusDeliverRC = 0;
2708 pVM->pdm.s.Apic.pfnLocalInterruptRC = 0;
2709 }
2710
2711 /*
2712 * Resolve & initialize the R0 bits.
2713 */
2714 if (pApicReg->pszGetInterruptR0)
2715 {
2716 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetInterruptR0, &pVM->pdm.s.Apic.pfnGetInterruptR0);
2717 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetInterruptR0, rc));
2718 if (RT_SUCCESS(rc))
2719 {
2720 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszHasPendingIrqR0, &pVM->pdm.s.Apic.pfnHasPendingIrqR0);
2721 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszHasPendingIrqR0, rc));
2722 }
2723 if (RT_SUCCESS(rc))
2724 {
2725 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszSetBaseR0, &pVM->pdm.s.Apic.pfnSetBaseR0);
2726 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszSetBaseR0, rc));
2727 }
2728 if (RT_SUCCESS(rc))
2729 {
2730 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetBaseR0, &pVM->pdm.s.Apic.pfnGetBaseR0);
2731 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetBaseR0, rc));
2732 }
2733 if (RT_SUCCESS(rc))
2734 {
2735 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszSetTPRR0, &pVM->pdm.s.Apic.pfnSetTPRR0);
2736 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszSetTPRR0, rc));
2737 }
2738 if (RT_SUCCESS(rc))
2739 {
2740 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetTPRR0, &pVM->pdm.s.Apic.pfnGetTPRR0);
2741 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetTPRR0, rc));
2742 }
2743 if (RT_SUCCESS(rc))
2744 {
2745 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszWriteMSRR0, &pVM->pdm.s.Apic.pfnWriteMSRR0);
2746 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszWriteMSRR0, rc));
2747 }
2748 if (RT_SUCCESS(rc))
2749 {
2750 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszReadMSRR0, &pVM->pdm.s.Apic.pfnReadMSRR0);
2751 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszReadMSRR0, rc));
2752 }
2753 if (RT_SUCCESS(rc))
2754 {
2755 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszBusDeliverR0, &pVM->pdm.s.Apic.pfnBusDeliverR0);
2756 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszBusDeliverR0, rc));
2757 }
2758 if (RT_SUCCESS(rc))
2759 {
2760 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszLocalInterruptR0, &pVM->pdm.s.Apic.pfnLocalInterruptR0);
2761 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszLocalInterruptR0, rc));
2762 }
2763 if (RT_FAILURE(rc))
2764 {
2765 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2766 return rc;
2767 }
2768 pVM->pdm.s.Apic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2769 Assert(pVM->pdm.s.Apic.pDevInsR0);
2770 }
2771 else
2772 {
2773 pVM->pdm.s.Apic.pfnGetInterruptR0 = 0;
2774 pVM->pdm.s.Apic.pfnHasPendingIrqR0 = 0;
2775 pVM->pdm.s.Apic.pfnSetBaseR0 = 0;
2776 pVM->pdm.s.Apic.pfnGetBaseR0 = 0;
2777 pVM->pdm.s.Apic.pfnSetTPRR0 = 0;
2778 pVM->pdm.s.Apic.pfnGetTPRR0 = 0;
2779 pVM->pdm.s.Apic.pfnWriteMSRR0 = 0;
2780 pVM->pdm.s.Apic.pfnReadMSRR0 = 0;
2781 pVM->pdm.s.Apic.pfnBusDeliverR0 = 0;
2782 pVM->pdm.s.Apic.pfnLocalInterruptR0 = 0;
2783 pVM->pdm.s.Apic.pDevInsR0 = 0;
2784 }
2785
2786 /*
2787 * Initialize the HC bits.
2788 */
2789 pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
2790 pVM->pdm.s.Apic.pfnGetInterruptR3 = pApicReg->pfnGetInterruptR3;
2791 pVM->pdm.s.Apic.pfnHasPendingIrqR3 = pApicReg->pfnHasPendingIrqR3;
2792 pVM->pdm.s.Apic.pfnSetBaseR3 = pApicReg->pfnSetBaseR3;
2793 pVM->pdm.s.Apic.pfnGetBaseR3 = pApicReg->pfnGetBaseR3;
2794 pVM->pdm.s.Apic.pfnSetTPRR3 = pApicReg->pfnSetTPRR3;
2795 pVM->pdm.s.Apic.pfnGetTPRR3 = pApicReg->pfnGetTPRR3;
2796 pVM->pdm.s.Apic.pfnWriteMSRR3 = pApicReg->pfnWriteMSRR3;
2797 pVM->pdm.s.Apic.pfnReadMSRR3 = pApicReg->pfnReadMSRR3;
2798 pVM->pdm.s.Apic.pfnBusDeliverR3 = pApicReg->pfnBusDeliverR3;
2799 pVM->pdm.s.Apic.pfnLocalInterruptR3 = pApicReg->pfnLocalInterruptR3;
2800 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2801
2802 /* set the helper pointer and return. */
2803 *ppApicHlpR3 = &g_pdmR3DevApicHlp;
2804 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2805 return VINF_SUCCESS;
2806}
2807
2808
2809/** @interface_method_impl{PDMDEVHLPR3,pfnIOAPICRegister} */
2810static DECLCALLBACK(int) pdmR3DevHlp_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
2811{
2812 PDMDEV_ASSERT_DEVINS(pDevIns);
2813 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2814 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppIoApicHlpR3=%p\n",
2815 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrqR3,
2816 pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqR0, pIoApicReg->pszSetIrqR0, ppIoApicHlpR3));
2817
2818 /*
2819 * Validate input.
2820 */
2821 if (pIoApicReg->u32Version != PDM_IOAPICREG_VERSION)
2822 {
2823 AssertMsgFailed(("u32Version=%#x expected %#x\n", pIoApicReg->u32Version, PDM_IOAPICREG_VERSION));
2824 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2825 return VERR_INVALID_PARAMETER;
2826 }
2827 if (!pIoApicReg->pfnSetIrqR3 || !pIoApicReg->pfnSendMsiR3)
2828 {
2829 Assert(pIoApicReg->pfnSetIrqR3);
2830 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2831 return VERR_INVALID_PARAMETER;
2832 }
2833 if ( pIoApicReg->pszSetIrqRC
2834 && !VALID_PTR(pIoApicReg->pszSetIrqRC))
2835 {
2836 Assert(VALID_PTR(pIoApicReg->pszSetIrqRC));
2837 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2838 return VERR_INVALID_PARAMETER;
2839 }
2840 if ( pIoApicReg->pszSendMsiRC
2841 && !VALID_PTR(pIoApicReg->pszSendMsiRC))
2842 {
2843 Assert(VALID_PTR(pIoApicReg->pszSendMsiRC));
2844 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2845 return VERR_INVALID_PARAMETER;
2846 }
2847 if ( pIoApicReg->pszSetIrqR0
2848 && !VALID_PTR(pIoApicReg->pszSetIrqR0))
2849 {
2850 Assert(VALID_PTR(pIoApicReg->pszSetIrqR0));
2851 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2852 return VERR_INVALID_PARAMETER;
2853 }
2854 if ( pIoApicReg->pszSendMsiR0
2855 && !VALID_PTR(pIoApicReg->pszSendMsiR0))
2856 {
2857 Assert(VALID_PTR(pIoApicReg->pszSendMsiR0));
2858 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2859 return VERR_INVALID_PARAMETER;
2860 }
2861 if (!ppIoApicHlpR3)
2862 {
2863 Assert(ppIoApicHlpR3);
2864 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (ppApicHlp)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2865 return VERR_INVALID_PARAMETER;
2866 }
2867
2868 /*
2869 * The I/O APIC requires the APIC to be present (hacks++).
2870 * If the I/O APIC does GC stuff so must the APIC.
2871 */
2872 PVM pVM = pDevIns->Internal.s.pVMR3;
2873 if (!pVM->pdm.s.Apic.pDevInsR3)
2874 {
2875 AssertMsgFailed(("Configuration error / Init order error! No APIC!\n"));
2876 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2877 return VERR_INVALID_PARAMETER;
2878 }
2879 if ( pIoApicReg->pszSetIrqRC
2880 && !pVM->pdm.s.Apic.pDevInsRC)
2881 {
2882 AssertMsgFailed(("Configuration error! APIC doesn't do GC, I/O APIC does!\n"));
2883 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no GC APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2884 return VERR_INVALID_PARAMETER;
2885 }
2886
2887 /*
2888 * Only one I/O APIC device.
2889 */
2890 if (pVM->pdm.s.IoApic.pDevInsR3)
2891 {
2892 AssertMsgFailed(("Only one ioapic device is supported!\n"));
2893 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (only one)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2894 return VERR_INVALID_PARAMETER;
2895 }
2896
2897 /*
2898 * Resolve & initialize the GC bits.
2899 */
2900 if (pIoApicReg->pszSetIrqRC)
2901 {
2902 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetIrqRC, &pVM->pdm.s.IoApic.pfnSetIrqRC);
2903 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSetIrqRC, rc));
2904 if (RT_FAILURE(rc))
2905 {
2906 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2907 return rc;
2908 }
2909 pVM->pdm.s.IoApic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2910 }
2911 else
2912 {
2913 pVM->pdm.s.IoApic.pDevInsRC = 0;
2914 pVM->pdm.s.IoApic.pfnSetIrqRC = 0;
2915 }
2916
2917 if (pIoApicReg->pszSendMsiRC)
2918 {
2919 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetIrqRC, &pVM->pdm.s.IoApic.pfnSendMsiRC);
2920 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSendMsiRC, rc));
2921 if (RT_FAILURE(rc))
2922 {
2923 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2924 return rc;
2925 }
2926 }
2927 else
2928 {
2929 pVM->pdm.s.IoApic.pfnSendMsiRC = 0;
2930 }
2931
2932 /*
2933 * Resolve & initialize the R0 bits.
2934 */
2935 if (pIoApicReg->pszSetIrqR0)
2936 {
2937 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetIrqR0, &pVM->pdm.s.IoApic.pfnSetIrqR0);
2938 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSetIrqR0, rc));
2939 if (RT_FAILURE(rc))
2940 {
2941 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2942 return rc;
2943 }
2944 pVM->pdm.s.IoApic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2945 Assert(pVM->pdm.s.IoApic.pDevInsR0);
2946 }
2947 else
2948 {
2949 pVM->pdm.s.IoApic.pfnSetIrqR0 = 0;
2950 pVM->pdm.s.IoApic.pDevInsR0 = 0;
2951 }
2952
2953 if (pIoApicReg->pszSendMsiR0)
2954 {
2955 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetIrqR0, &pVM->pdm.s.IoApic.pfnSendMsiR0);
2956 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSendMsiR0, rc));
2957 if (RT_FAILURE(rc))
2958 {
2959 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2960 return rc;
2961 }
2962 }
2963 else
2964 {
2965 pVM->pdm.s.IoApic.pfnSendMsiR0 = 0;
2966 }
2967
2968
2969 /*
2970 * Initialize the R3 bits.
2971 */
2972 pVM->pdm.s.IoApic.pDevInsR3 = pDevIns;
2973 pVM->pdm.s.IoApic.pfnSetIrqR3 = pIoApicReg->pfnSetIrqR3;
2974 pVM->pdm.s.IoApic.pfnSendMsiR3 = pIoApicReg->pfnSendMsiR3;
2975 Log(("PDM: Registered I/O APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2976
2977 /* set the helper pointer and return. */
2978 *ppIoApicHlpR3 = &g_pdmR3DevIoApicHlp;
2979 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2980 return VINF_SUCCESS;
2981}
2982
2983
2984/** @interface_method_impl{PDMDEVHLPR3,pfnHPETRegister} */
2985static DECLCALLBACK(int) pdmR3DevHlp_HPETRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
2986{
2987 PDMDEV_ASSERT_DEVINS(pDevIns);
2988 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2989 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d:\n"));
2990
2991 /*
2992 * Validate input.
2993 */
2994 if (pHpetReg->u32Version != PDM_HPETREG_VERSION)
2995 {
2996 AssertMsgFailed(("u32Version=%#x expected %#x\n", pHpetReg->u32Version, PDM_HPETREG_VERSION));
2997 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2998 return VERR_INVALID_PARAMETER;
2999 }
3000
3001 if (!ppHpetHlpR3)
3002 {
3003 Assert(ppHpetHlpR3);
3004 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3005 return VERR_INVALID_PARAMETER;
3006 }
3007
3008 /* set the helper pointer and return. */
3009 *ppHpetHlpR3 = &g_pdmR3DevHpetHlp;
3010 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3011 return VINF_SUCCESS;
3012}
3013
3014
3015/** @interface_method_impl{PDMDEVHLPR3,pfnPciRawRegister} */
3016static DECLCALLBACK(int) pdmR3DevHlp_PciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
3017{
3018 PDMDEV_ASSERT_DEVINS(pDevIns);
3019 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3020 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d:\n"));
3021
3022 /*
3023 * Validate input.
3024 */
3025 if (pPciRawReg->u32Version != PDM_PCIRAWREG_VERSION)
3026 {
3027 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciRawReg->u32Version, PDM_PCIRAWREG_VERSION));
3028 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3029 return VERR_INVALID_PARAMETER;
3030 }
3031
3032 if (!ppPciRawHlpR3)
3033 {
3034 Assert(ppPciRawHlpR3);
3035 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3036 return VERR_INVALID_PARAMETER;
3037 }
3038
3039 /* set the helper pointer and return. */
3040 *ppPciRawHlpR3 = &g_pdmR3DevPciRawHlp;
3041 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3042 return VINF_SUCCESS;
3043}
3044
3045
3046/** @interface_method_impl{PDMDEVHLPR3,pfnDMACRegister} */
3047static DECLCALLBACK(int) pdmR3DevHlp_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
3048{
3049 PDMDEV_ASSERT_DEVINS(pDevIns);
3050 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3051 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: pDmacReg=%p:{.u32Version=%#x, .pfnRun=%p, .pfnRegister=%p, .pfnReadMemory=%p, .pfnWriteMemory=%p, .pfnSetDREQ=%p, .pfnGetChannelMode=%p} ppDmacHlp=%p\n",
3052 pDevIns->pReg->szName, pDevIns->iInstance, pDmacReg, pDmacReg->u32Version, pDmacReg->pfnRun, pDmacReg->pfnRegister,
3053 pDmacReg->pfnReadMemory, pDmacReg->pfnWriteMemory, pDmacReg->pfnSetDREQ, pDmacReg->pfnGetChannelMode, ppDmacHlp));
3054
3055 /*
3056 * Validate input.
3057 */
3058 if (pDmacReg->u32Version != PDM_DMACREG_VERSION)
3059 {
3060 AssertMsgFailed(("u32Version=%#x expected %#x\n", pDmacReg->u32Version,
3061 PDM_DMACREG_VERSION));
3062 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (version)\n",
3063 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3064 return VERR_INVALID_PARAMETER;
3065 }
3066 if ( !pDmacReg->pfnRun
3067 || !pDmacReg->pfnRegister
3068 || !pDmacReg->pfnReadMemory
3069 || !pDmacReg->pfnWriteMemory
3070 || !pDmacReg->pfnSetDREQ
3071 || !pDmacReg->pfnGetChannelMode)
3072 {
3073 Assert(pDmacReg->pfnRun);
3074 Assert(pDmacReg->pfnRegister);
3075 Assert(pDmacReg->pfnReadMemory);
3076 Assert(pDmacReg->pfnWriteMemory);
3077 Assert(pDmacReg->pfnSetDREQ);
3078 Assert(pDmacReg->pfnGetChannelMode);
3079 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3080 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3081 return VERR_INVALID_PARAMETER;
3082 }
3083
3084 if (!ppDmacHlp)
3085 {
3086 Assert(ppDmacHlp);
3087 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (ppDmacHlp)\n",
3088 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3089 return VERR_INVALID_PARAMETER;
3090 }
3091
3092 /*
3093 * Only one DMA device.
3094 */
3095 PVM pVM = pDevIns->Internal.s.pVMR3;
3096 if (pVM->pdm.s.pDmac)
3097 {
3098 AssertMsgFailed(("Only one DMA device is supported!\n"));
3099 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3100 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3101 return VERR_INVALID_PARAMETER;
3102 }
3103
3104 /*
3105 * Allocate and initialize pci bus structure.
3106 */
3107 int rc = VINF_SUCCESS;
3108 PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pDmac));
3109 if (pDmac)
3110 {
3111 pDmac->pDevIns = pDevIns;
3112 pDmac->Reg = *pDmacReg;
3113 pVM->pdm.s.pDmac = pDmac;
3114
3115 /* set the helper pointer. */
3116 *ppDmacHlp = &g_pdmR3DevDmacHlp;
3117 Log(("PDM: Registered DMAC device '%s'/%d pDevIns=%p\n",
3118 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3119 }
3120 else
3121 rc = VERR_NO_MEMORY;
3122
3123 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3124 pDevIns->pReg->szName, pDevIns->iInstance, rc));
3125 return rc;
3126}
3127
3128
3129/**
3130 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
3131 */
3132static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize)
3133{
3134 PDMDEV_ASSERT_DEVINS(pDevIns);
3135 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3136
3137 int rc = PDMR3VmmDevHeapRegister(pDevIns->Internal.s.pVMR3, GCPhys, pvHeap, cbSize);
3138 return rc;
3139}
3140
3141
3142/**
3143 * @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap
3144 */
3145static DECLCALLBACK(int) pdmR3DevHlp_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
3146{
3147 PDMDEV_ASSERT_DEVINS(pDevIns);
3148 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3149
3150 int rc = PDMR3VmmDevHeapUnregister(pDevIns->Internal.s.pVMR3, GCPhys);
3151 return rc;
3152}
3153
3154
3155/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
3156static DECLCALLBACK(int) pdmR3DevHlp_VMReset(PPDMDEVINS pDevIns)
3157{
3158 PDMDEV_ASSERT_DEVINS(pDevIns);
3159 PVM pVM = pDevIns->Internal.s.pVMR3;
3160 VM_ASSERT_EMT(pVM);
3161 LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: VM_FF_RESET %d -> 1\n",
3162 pDevIns->pReg->szName, pDevIns->iInstance, VM_FF_ISSET(pVM, VM_FF_RESET)));
3163
3164 /*
3165 * We postpone this operation because we're likely to be inside a I/O instruction
3166 * and the EIP will be updated when we return.
3167 * We still return VINF_EM_RESET to break out of any execution loops and force FF evaluation.
3168 */
3169 bool fHaltOnReset;
3170 int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
3171 if (RT_SUCCESS(rc) && fHaltOnReset)
3172 {
3173 Log(("pdmR3DevHlp_VMReset: Halt On Reset!\n"));
3174 rc = VINF_EM_HALT;
3175 }
3176 else
3177 {
3178 VM_FF_SET(pVM, VM_FF_RESET);
3179 rc = VINF_EM_RESET;
3180 }
3181
3182 LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3183 return rc;
3184}
3185
3186
3187/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
3188static DECLCALLBACK(int) pdmR3DevHlp_VMSuspend(PPDMDEVINS pDevIns)
3189{
3190 int rc;
3191 PDMDEV_ASSERT_DEVINS(pDevIns);
3192 PVM pVM = pDevIns->Internal.s.pVMR3;
3193 VM_ASSERT_EMT(pVM);
3194 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d:\n",
3195 pDevIns->pReg->szName, pDevIns->iInstance));
3196
3197 /** @todo Always take the SMP path - fewer code paths. */
3198 if (pVM->cCpus > 1)
3199 {
3200 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
3201 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3Suspend, 1, pVM->pUVM);
3202 AssertRC(rc);
3203 rc = VINF_EM_SUSPEND;
3204 }
3205 else
3206 rc = VMR3Suspend(pVM->pUVM);
3207
3208 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3209 return rc;
3210}
3211
3212
3213/**
3214 * Worker for pdmR3DevHlp_VMSuspendSaveAndPowerOff that is invoked via a queued
3215 * EMT request to avoid deadlocks.
3216 *
3217 * @returns VBox status code fit for scheduling.
3218 * @param pVM Pointer to the VM.
3219 * @param pDevIns The device that triggered this action.
3220 */
3221static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker(PVM pVM, PPDMDEVINS pDevIns)
3222{
3223 /*
3224 * Suspend the VM first then do the saving.
3225 */
3226 int rc = VMR3Suspend(pVM->pUVM);
3227 if (RT_SUCCESS(rc))
3228 {
3229 PUVM pUVM = pVM->pUVM;
3230 rc = pUVM->pVmm2UserMethods->pfnSaveState(pVM->pUVM->pVmm2UserMethods, pUVM);
3231
3232 /*
3233 * On success, power off the VM, on failure we'll leave it suspended.
3234 */
3235 if (RT_SUCCESS(rc))
3236 {
3237 rc = VMR3PowerOff(pVM->pUVM);
3238 if (RT_FAILURE(rc))
3239 LogRel(("%s/SSP: VMR3PowerOff failed: %Rrc\n", pDevIns->pReg->szName, rc));
3240 }
3241 else
3242 LogRel(("%s/SSP: pfnSaveState failed: %Rrc\n", pDevIns->pReg->szName, rc));
3243 }
3244 else
3245 LogRel(("%s/SSP: Suspend failed: %Rrc\n", pDevIns->pReg->szName, rc));
3246 return rc;
3247}
3248
3249
3250/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
3251static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
3252{
3253 PDMDEV_ASSERT_DEVINS(pDevIns);
3254 PVM pVM = pDevIns->Internal.s.pVMR3;
3255 VM_ASSERT_EMT(pVM);
3256 LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d:\n",
3257 pDevIns->pReg->szName, pDevIns->iInstance));
3258
3259 int rc;
3260 if ( pVM->pUVM->pVmm2UserMethods
3261 && pVM->pUVM->pVmm2UserMethods->pfnSaveState)
3262 {
3263 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker, 2, pVM, pDevIns);
3264 if (RT_SUCCESS(rc))
3265 {
3266 LogRel(("%s: Suspending, Saving and Powering Off the VM\n", pDevIns->pReg->szName));
3267 rc = VINF_EM_SUSPEND;
3268 }
3269 }
3270 else
3271 rc = VERR_NOT_SUPPORTED;
3272
3273 LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3274 return rc;
3275}
3276
3277
3278/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
3279static DECLCALLBACK(int) pdmR3DevHlp_VMPowerOff(PPDMDEVINS pDevIns)
3280{
3281 int rc;
3282 PDMDEV_ASSERT_DEVINS(pDevIns);
3283 PVM pVM = pDevIns->Internal.s.pVMR3;
3284 VM_ASSERT_EMT(pVM);
3285 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d:\n",
3286 pDevIns->pReg->szName, pDevIns->iInstance));
3287
3288 /** @todo Always take the SMP path - fewer code paths. */
3289 if (pVM->cCpus > 1)
3290 {
3291 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
3292 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3PowerOff, 1, pVM->pUVM);
3293 AssertRC(rc);
3294 /* Set the VCPU state to stopped here as well to make sure no
3295 * inconsistency with the EM state occurs.
3296 */
3297 VMCPU_SET_STATE(VMMGetCpu(pVM), VMCPUSTATE_STOPPED);
3298 rc = VINF_EM_OFF;
3299 }
3300 else
3301 rc = VMR3PowerOff(pVM->pUVM);
3302
3303 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3304 return rc;
3305}
3306
3307
3308/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
3309static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
3310{
3311 PDMDEV_ASSERT_DEVINS(pDevIns);
3312 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3313
3314 bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3));
3315
3316 LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pReg->szName, pDevIns->iInstance, fRc));
3317 return fRc;
3318}
3319
3320
3321/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
3322static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable)
3323{
3324 PDMDEV_ASSERT_DEVINS(pDevIns);
3325 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3326 LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, fEnable));
3327 PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable);
3328}
3329
3330
3331/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
3332static DECLCALLBACK(void) pdmR3DevHlp_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3333 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
3334{
3335 PDMDEV_ASSERT_DEVINS(pDevIns);
3336 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3337
3338 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: iLeaf=%d pEax=%p pEbx=%p pEcx=%p pEdx=%p\n",
3339 pDevIns->pReg->szName, pDevIns->iInstance, iLeaf, pEax, pEbx, pEcx, pEdx));
3340 AssertPtr(pEax); AssertPtr(pEbx); AssertPtr(pEcx); AssertPtr(pEdx);
3341
3342 CPUMGetGuestCpuId(VMMGetCpu(pDevIns->Internal.s.pVMR3), iLeaf, pEax, pEbx, pEcx, pEdx);
3343
3344 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - *pEax=%#x *pEbx=%#x *pEcx=%#x *pEdx=%#x\n",
3345 pDevIns->pReg->szName, pDevIns->iInstance, *pEax, *pEbx, *pEcx, *pEdx));
3346}
3347
3348
3349/**
3350 * The device helper structure for trusted devices.
3351 */
3352const PDMDEVHLPR3 g_pdmR3DevHlpTrusted =
3353{
3354 PDM_DEVHLPR3_VERSION,
3355 pdmR3DevHlp_IOPortRegister,
3356 pdmR3DevHlp_IOPortRegisterRC,
3357 pdmR3DevHlp_IOPortRegisterR0,
3358 pdmR3DevHlp_IOPortDeregister,
3359 pdmR3DevHlp_MMIORegister,
3360 pdmR3DevHlp_MMIORegisterRC,
3361 pdmR3DevHlp_MMIORegisterR0,
3362 pdmR3DevHlp_MMIODeregister,
3363 pdmR3DevHlp_MMIO2Register,
3364 pdmR3DevHlp_MMIO2Deregister,
3365 pdmR3DevHlp_MMIO2Map,
3366 pdmR3DevHlp_MMIO2Unmap,
3367 pdmR3DevHlp_MMHyperMapMMIO2,
3368 pdmR3DevHlp_MMIO2MapKernel,
3369 pdmR3DevHlp_ROMRegister,
3370 pdmR3DevHlp_ROMProtectShadow,
3371 pdmR3DevHlp_SSMRegister,
3372 pdmR3DevHlp_TMTimerCreate,
3373 pdmR3DevHlp_TMUtcNow,
3374 pdmR3DevHlp_PhysRead,
3375 pdmR3DevHlp_PhysWrite,
3376 pdmR3DevHlp_PhysGCPhys2CCPtr,
3377 pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
3378 pdmR3DevHlp_PhysReleasePageMappingLock,
3379 pdmR3DevHlp_PhysReadGCVirt,
3380 pdmR3DevHlp_PhysWriteGCVirt,
3381 pdmR3DevHlp_PhysGCPtr2GCPhys,
3382 pdmR3DevHlp_MMHeapAlloc,
3383 pdmR3DevHlp_MMHeapAllocZ,
3384 pdmR3DevHlp_MMHeapFree,
3385 pdmR3DevHlp_VMState,
3386 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
3387 pdmR3DevHlp_VMSetError,
3388 pdmR3DevHlp_VMSetErrorV,
3389 pdmR3DevHlp_VMSetRuntimeError,
3390 pdmR3DevHlp_VMSetRuntimeErrorV,
3391 pdmR3DevHlp_DBGFStopV,
3392 pdmR3DevHlp_DBGFInfoRegister,
3393 pdmR3DevHlp_DBGFRegRegister,
3394 pdmR3DevHlp_DBGFTraceBuf,
3395 pdmR3DevHlp_STAMRegister,
3396 pdmR3DevHlp_STAMRegisterF,
3397 pdmR3DevHlp_STAMRegisterV,
3398 pdmR3DevHlp_PCIPhysRead,
3399 pdmR3DevHlp_PCIPhysWrite,
3400 pdmR3DevHlp_PCIRegister,
3401 pdmR3DevHlp_PCIRegisterMsi,
3402 pdmR3DevHlp_PCIIORegionRegister,
3403 pdmR3DevHlp_PCISetConfigCallbacks,
3404 pdmR3DevHlp_PCISetIrq,
3405 pdmR3DevHlp_PCISetIrqNoWait,
3406 pdmR3DevHlp_ISASetIrq,
3407 pdmR3DevHlp_ISASetIrqNoWait,
3408 pdmR3DevHlp_DriverAttach,
3409 pdmR3DevHlp_QueueCreate,
3410 pdmR3DevHlp_CritSectInit,
3411 pdmR3DevHlp_CritSectGetNop,
3412 pdmR3DevHlp_CritSectGetNopR0,
3413 pdmR3DevHlp_CritSectGetNopRC,
3414 pdmR3DevHlp_SetDeviceCritSect,
3415 pdmR3DevHlp_ThreadCreate,
3416 pdmR3DevHlp_SetAsyncNotification,
3417 pdmR3DevHlp_AsyncNotificationCompleted,
3418 pdmR3DevHlp_RTCRegister,
3419 pdmR3DevHlp_PCIBusRegister,
3420 pdmR3DevHlp_PICRegister,
3421 pdmR3DevHlp_APICRegister,
3422 pdmR3DevHlp_IOAPICRegister,
3423 pdmR3DevHlp_HPETRegister,
3424 pdmR3DevHlp_PciRawRegister,
3425 pdmR3DevHlp_DMACRegister,
3426 pdmR3DevHlp_DMARegister,
3427 pdmR3DevHlp_DMAReadMemory,
3428 pdmR3DevHlp_DMAWriteMemory,
3429 pdmR3DevHlp_DMASetDREQ,
3430 pdmR3DevHlp_DMAGetChannelMode,
3431 pdmR3DevHlp_DMASchedule,
3432 pdmR3DevHlp_CMOSWrite,
3433 pdmR3DevHlp_CMOSRead,
3434 pdmR3DevHlp_AssertEMT,
3435 pdmR3DevHlp_AssertOther,
3436 pdmR3DevHlp_LdrGetRCInterfaceSymbols,
3437 pdmR3DevHlp_LdrGetR0InterfaceSymbols,
3438 pdmR3DevHlp_CallR0,
3439 0,
3440 0,
3441 0,
3442 0,
3443 0,
3444 0,
3445 0,
3446 0,
3447 0,
3448 pdmR3DevHlp_GetUVM,
3449 pdmR3DevHlp_GetVM,
3450 pdmR3DevHlp_GetVMCPU,
3451 pdmR3DevHlp_RegisterVMMDevHeap,
3452 pdmR3DevHlp_UnregisterVMMDevHeap,
3453 pdmR3DevHlp_VMReset,
3454 pdmR3DevHlp_VMSuspend,
3455 pdmR3DevHlp_VMSuspendSaveAndPowerOff,
3456 pdmR3DevHlp_VMPowerOff,
3457 pdmR3DevHlp_A20IsEnabled,
3458 pdmR3DevHlp_A20Set,
3459 pdmR3DevHlp_GetCpuId,
3460 pdmR3DevHlp_TMTimeVirtGet,
3461 pdmR3DevHlp_TMTimeVirtGetFreq,
3462 pdmR3DevHlp_TMTimeVirtGetNano,
3463 PDM_DEVHLPR3_VERSION /* the end */
3464};
3465
3466
3467
3468
3469/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
3470static DECLCALLBACK(PUVM) pdmR3DevHlp_Untrusted_GetUVM(PPDMDEVINS pDevIns)
3471{
3472 PDMDEV_ASSERT_DEVINS(pDevIns);
3473 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3474 return NULL;
3475}
3476
3477
3478/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
3479static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns)
3480{
3481 PDMDEV_ASSERT_DEVINS(pDevIns);
3482 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3483 return NULL;
3484}
3485
3486
3487/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
3488static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns)
3489{
3490 PDMDEV_ASSERT_DEVINS(pDevIns);
3491 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3492 return NULL;
3493}
3494
3495
3496/** @interface_method_impl{PDMDEVHLPR3,pfnRegisterVMMDevHeap} */
3497static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize)
3498{
3499 PDMDEV_ASSERT_DEVINS(pDevIns);
3500 NOREF(GCPhys); NOREF(pvHeap); NOREF(cbSize);
3501 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3502 return VERR_ACCESS_DENIED;
3503}
3504
3505
3506/** @interface_method_impl{PDMDEVHLPR3,pfnUnregisterVMMDevHeap} */
3507static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
3508{
3509 PDMDEV_ASSERT_DEVINS(pDevIns);
3510 NOREF(GCPhys);
3511 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3512 return VERR_ACCESS_DENIED;
3513}
3514
3515
3516/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
3517static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns)
3518{
3519 PDMDEV_ASSERT_DEVINS(pDevIns);
3520 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3521 return VERR_ACCESS_DENIED;
3522}
3523
3524
3525/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
3526static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns)
3527{
3528 PDMDEV_ASSERT_DEVINS(pDevIns);
3529 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3530 return VERR_ACCESS_DENIED;
3531}
3532
3533
3534/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
3535static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
3536{
3537 PDMDEV_ASSERT_DEVINS(pDevIns);
3538 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3539 return VERR_ACCESS_DENIED;
3540}
3541
3542
3543/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
3544static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns)
3545{
3546 PDMDEV_ASSERT_DEVINS(pDevIns);
3547 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3548 return VERR_ACCESS_DENIED;
3549}
3550
3551
3552/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
3553static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns)
3554{
3555 PDMDEV_ASSERT_DEVINS(pDevIns);
3556 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3557 return false;
3558}
3559
3560
3561/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
3562static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable)
3563{
3564 PDMDEV_ASSERT_DEVINS(pDevIns);
3565 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3566 NOREF(fEnable);
3567}
3568
3569
3570/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
3571static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3572 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
3573{
3574 PDMDEV_ASSERT_DEVINS(pDevIns);
3575 NOREF(iLeaf); NOREF(pEax); NOREF(pEbx); NOREF(pEcx); NOREF(pEdx);
3576 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3577}
3578
3579
3580/**
3581 * The device helper structure for non-trusted devices.
3582 */
3583const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted =
3584{
3585 PDM_DEVHLPR3_VERSION,
3586 pdmR3DevHlp_IOPortRegister,
3587 pdmR3DevHlp_IOPortRegisterRC,
3588 pdmR3DevHlp_IOPortRegisterR0,
3589 pdmR3DevHlp_IOPortDeregister,
3590 pdmR3DevHlp_MMIORegister,
3591 pdmR3DevHlp_MMIORegisterRC,
3592 pdmR3DevHlp_MMIORegisterR0,
3593 pdmR3DevHlp_MMIODeregister,
3594 pdmR3DevHlp_MMIO2Register,
3595 pdmR3DevHlp_MMIO2Deregister,
3596 pdmR3DevHlp_MMIO2Map,
3597 pdmR3DevHlp_MMIO2Unmap,
3598 pdmR3DevHlp_MMHyperMapMMIO2,
3599 pdmR3DevHlp_MMIO2MapKernel,
3600 pdmR3DevHlp_ROMRegister,
3601 pdmR3DevHlp_ROMProtectShadow,
3602 pdmR3DevHlp_SSMRegister,
3603 pdmR3DevHlp_TMTimerCreate,
3604 pdmR3DevHlp_TMUtcNow,
3605 pdmR3DevHlp_PhysRead,
3606 pdmR3DevHlp_PhysWrite,
3607 pdmR3DevHlp_PhysGCPhys2CCPtr,
3608 pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
3609 pdmR3DevHlp_PhysReleasePageMappingLock,
3610 pdmR3DevHlp_PhysReadGCVirt,
3611 pdmR3DevHlp_PhysWriteGCVirt,
3612 pdmR3DevHlp_PhysGCPtr2GCPhys,
3613 pdmR3DevHlp_MMHeapAlloc,
3614 pdmR3DevHlp_MMHeapAllocZ,
3615 pdmR3DevHlp_MMHeapFree,
3616 pdmR3DevHlp_VMState,
3617 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
3618 pdmR3DevHlp_VMSetError,
3619 pdmR3DevHlp_VMSetErrorV,
3620 pdmR3DevHlp_VMSetRuntimeError,
3621 pdmR3DevHlp_VMSetRuntimeErrorV,
3622 pdmR3DevHlp_DBGFStopV,
3623 pdmR3DevHlp_DBGFInfoRegister,
3624 pdmR3DevHlp_DBGFRegRegister,
3625 pdmR3DevHlp_DBGFTraceBuf,
3626 pdmR3DevHlp_STAMRegister,
3627 pdmR3DevHlp_STAMRegisterF,
3628 pdmR3DevHlp_STAMRegisterV,
3629 pdmR3DevHlp_PCIPhysRead,
3630 pdmR3DevHlp_PCIPhysWrite,
3631 pdmR3DevHlp_PCIRegister,
3632 pdmR3DevHlp_PCIRegisterMsi,
3633 pdmR3DevHlp_PCIIORegionRegister,
3634 pdmR3DevHlp_PCISetConfigCallbacks,
3635 pdmR3DevHlp_PCISetIrq,
3636 pdmR3DevHlp_PCISetIrqNoWait,
3637 pdmR3DevHlp_ISASetIrq,
3638 pdmR3DevHlp_ISASetIrqNoWait,
3639 pdmR3DevHlp_DriverAttach,
3640 pdmR3DevHlp_QueueCreate,
3641 pdmR3DevHlp_CritSectInit,
3642 pdmR3DevHlp_CritSectGetNop,
3643 pdmR3DevHlp_CritSectGetNopR0,
3644 pdmR3DevHlp_CritSectGetNopRC,
3645 pdmR3DevHlp_SetDeviceCritSect,
3646 pdmR3DevHlp_ThreadCreate,
3647 pdmR3DevHlp_SetAsyncNotification,
3648 pdmR3DevHlp_AsyncNotificationCompleted,
3649 pdmR3DevHlp_RTCRegister,
3650 pdmR3DevHlp_PCIBusRegister,
3651 pdmR3DevHlp_PICRegister,
3652 pdmR3DevHlp_APICRegister,
3653 pdmR3DevHlp_IOAPICRegister,
3654 pdmR3DevHlp_HPETRegister,
3655 pdmR3DevHlp_PciRawRegister,
3656 pdmR3DevHlp_DMACRegister,
3657 pdmR3DevHlp_DMARegister,
3658 pdmR3DevHlp_DMAReadMemory,
3659 pdmR3DevHlp_DMAWriteMemory,
3660 pdmR3DevHlp_DMASetDREQ,
3661 pdmR3DevHlp_DMAGetChannelMode,
3662 pdmR3DevHlp_DMASchedule,
3663 pdmR3DevHlp_CMOSWrite,
3664 pdmR3DevHlp_CMOSRead,
3665 pdmR3DevHlp_AssertEMT,
3666 pdmR3DevHlp_AssertOther,
3667 pdmR3DevHlp_LdrGetRCInterfaceSymbols,
3668 pdmR3DevHlp_LdrGetR0InterfaceSymbols,
3669 pdmR3DevHlp_CallR0,
3670 0,
3671 0,
3672 0,
3673 0,
3674 0,
3675 0,
3676 0,
3677 0,
3678 0,
3679 pdmR3DevHlp_Untrusted_GetUVM,
3680 pdmR3DevHlp_Untrusted_GetVM,
3681 pdmR3DevHlp_Untrusted_GetVMCPU,
3682 pdmR3DevHlp_Untrusted_RegisterVMMDevHeap,
3683 pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap,
3684 pdmR3DevHlp_Untrusted_VMReset,
3685 pdmR3DevHlp_Untrusted_VMSuspend,
3686 pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff,
3687 pdmR3DevHlp_Untrusted_VMPowerOff,
3688 pdmR3DevHlp_Untrusted_A20IsEnabled,
3689 pdmR3DevHlp_Untrusted_A20Set,
3690 pdmR3DevHlp_Untrusted_GetCpuId,
3691 pdmR3DevHlp_TMTimeVirtGet,
3692 pdmR3DevHlp_TMTimeVirtGetFreq,
3693 pdmR3DevHlp_TMTimeVirtGetNano,
3694 PDM_DEVHLPR3_VERSION /* the end */
3695};
3696
3697
3698
3699/**
3700 * Queue consumer callback for internal component.
3701 *
3702 * @returns Success indicator.
3703 * If false the item will not be removed and the flushing will stop.
3704 * @param pVM Pointer to the VM.
3705 * @param pItem The item to consume. Upon return this item will be freed.
3706 */
3707DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem)
3708{
3709 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)pItem;
3710 LogFlow(("pdmR3DevHlpQueueConsumer: enmOp=%d pDevIns=%p\n", pTask->enmOp, pTask->pDevInsR3));
3711 switch (pTask->enmOp)
3712 {
3713 case PDMDEVHLPTASKOP_ISA_SET_IRQ:
3714 PDMIsaSetIrq(pVM, pTask->u.SetIRQ.iIrq, pTask->u.SetIRQ.iLevel, pTask->u.SetIRQ.uTagSrc);
3715 break;
3716
3717 case PDMDEVHLPTASKOP_PCI_SET_IRQ:
3718 {
3719 /* Same as pdmR3DevHlp_PCISetIrq, except we've got a tag already. */
3720 PPDMDEVINS pDevIns = pTask->pDevInsR3;
3721 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
3722 if (pPciDev)
3723 {
3724 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; /** @todo the bus should be associated with the PCI device not the PDM device. */
3725 Assert(pBus);
3726
3727 pdmLock(pVM);
3728 pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, pTask->u.SetIRQ.iIrq,
3729 pTask->u.SetIRQ.iLevel, pTask->u.SetIRQ.uTagSrc);
3730 pdmUnlock(pVM);
3731 }
3732 else
3733 AssertReleaseMsgFailed(("No PCI device registered!\n"));
3734 break;
3735 }
3736
3737 case PDMDEVHLPTASKOP_IOAPIC_SET_IRQ:
3738 PDMIoApicSetIrq(pVM, pTask->u.SetIRQ.iIrq, pTask->u.SetIRQ.iLevel, pTask->u.SetIRQ.uTagSrc);
3739 break;
3740
3741 default:
3742 AssertReleaseMsgFailed(("Invalid operation %d\n", pTask->enmOp));
3743 break;
3744 }
3745 return true;
3746}
3747
3748/** @} */
3749
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