NEMR3Native-linux.cpp@ 93115

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1	/* $Id: NEMR3Native-linux.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 Linux backend.
4	*/
5
6	/*
7	* Copyright (C) 2021-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_NEM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/nem.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/em.h>
27	#include <VBox/vmm/apic.h>
28	#include <VBox/vmm/pdm.h>
29	#include <VBox/vmm/trpm.h>
30	#include "NEMInternal.h"
31	#include <VBox/vmm/vmcc.h>
32
33	#include <iprt/alloca.h>
34	#include <iprt/string.h>
35	#include <iprt/system.h>
36	#include <iprt/x86.h>
37
38	#include <errno.h>
39	#include <unistd.h>
40	#include <sys/ioctl.h>
41	#include <sys/fcntl.h>
42	#include <sys/mman.h>
43	#include <linux/kvm.h>
44
45	/*
46	* Supply stuff missing from the kvm.h on the build box.
47	*/
48	#ifndef KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON /* since 5.4 */
49	# define KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON 4
50	#endif
51
52
53
54	/**
55	* Worker for nemR3NativeInit that gets the hypervisor capabilities.
56	*
57	* @returns VBox status code.
58	* @param pVM The cross context VM structure.
59	* @param pErrInfo Where to always return error info.
60	*/
61	static int nemR3LnxInitCheckCapabilities(PVM pVM, PRTERRINFO pErrInfo)
62	{
63	AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
64
65	/*
66	* Capabilities.
67	*/
68	static const struct
69	{
70	const char *pszName;
71	int iCap;
72	uint32_t offNem : 24;
73	uint32_t cbNem : 3;
74	uint32_t fReqNonZero : 1;
75	uint32_t uReserved : 4;
76	} s_aCaps[] =
77	{
78	#define CAP_ENTRY__L(a_Define) { #a_Define, a_Define, UINT32_C(0x00ffffff), 0, 0, 0 }
79	#define CAP_ENTRY__S(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 0, 0 }
80	#define CAP_ENTRY_MS(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 1, 0 }
81	#define CAP_ENTRY__U(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 0, 0 }
82	#define CAP_ENTRY_ML(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 1, 0 }
83
84	CAP_ENTRY__L(KVM_CAP_IRQCHIP), /* 0 */
85	CAP_ENTRY_ML(KVM_CAP_HLT),
86	CAP_ENTRY__L(KVM_CAP_MMU_SHADOW_CACHE_CONTROL),
87	CAP_ENTRY_ML(KVM_CAP_USER_MEMORY),
88	CAP_ENTRY__L(KVM_CAP_SET_TSS_ADDR),
89	CAP_ENTRY__U(5),
90	CAP_ENTRY__L(KVM_CAP_VAPIC),
91	CAP_ENTRY__L(KVM_CAP_EXT_CPUID),
92	CAP_ENTRY__L(KVM_CAP_CLOCKSOURCE),
93	CAP_ENTRY__L(KVM_CAP_NR_VCPUS),
94	CAP_ENTRY_MS(KVM_CAP_NR_MEMSLOTS, cMaxMemSlots), /* 10 */
95	CAP_ENTRY__L(KVM_CAP_PIT),
96	CAP_ENTRY__L(KVM_CAP_NOP_IO_DELAY),
97	CAP_ENTRY__L(KVM_CAP_PV_MMU),
98	CAP_ENTRY__L(KVM_CAP_MP_STATE),
99	CAP_ENTRY__L(KVM_CAP_COALESCED_MMIO),
100	CAP_ENTRY__L(KVM_CAP_SYNC_MMU),
101	CAP_ENTRY__U(17),
102	CAP_ENTRY__L(KVM_CAP_IOMMU),
103	CAP_ENTRY__U(19), /* Buggy KVM_CAP_JOIN_MEMORY_REGIONS? */
104	CAP_ENTRY__U(20), /* Mon-working KVM_CAP_DESTROY_MEMORY_REGION? */
105	CAP_ENTRY__L(KVM_CAP_DESTROY_MEMORY_REGION_WORKS), /* 21 */
106	CAP_ENTRY__L(KVM_CAP_USER_NMI),
107	#ifdef __KVM_HAVE_GUEST_DEBUG
108	CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG),
109	#endif
110	#ifdef __KVM_HAVE_PIT
111	CAP_ENTRY__L(KVM_CAP_REINJECT_CONTROL),
112	#endif
113	CAP_ENTRY__L(KVM_CAP_IRQ_ROUTING),
114	CAP_ENTRY__L(KVM_CAP_IRQ_INJECT_STATUS),
115	CAP_ENTRY__U(27),
116	CAP_ENTRY__U(28),
117	CAP_ENTRY__L(KVM_CAP_ASSIGN_DEV_IRQ),
118	CAP_ENTRY__L(KVM_CAP_JOIN_MEMORY_REGIONS_WORKS), /* 30 */
119	#ifdef __KVM_HAVE_MCE
120	CAP_ENTRY__L(KVM_CAP_MCE),
121	#endif
122	CAP_ENTRY__L(KVM_CAP_IRQFD),
123	#ifdef __KVM_HAVE_PIT
124	CAP_ENTRY__L(KVM_CAP_PIT2),
125	#endif
126	CAP_ENTRY__L(KVM_CAP_SET_BOOT_CPU_ID),
127	#ifdef __KVM_HAVE_PIT_STATE2
128	CAP_ENTRY__L(KVM_CAP_PIT_STATE2),
129	#endif
130	CAP_ENTRY__L(KVM_CAP_IOEVENTFD),
131	CAP_ENTRY__L(KVM_CAP_SET_IDENTITY_MAP_ADDR),
132	#ifdef __KVM_HAVE_XEN_HVM
133	CAP_ENTRY__L(KVM_CAP_XEN_HVM),
134	#endif
135	CAP_ENTRY_ML(KVM_CAP_ADJUST_CLOCK),
136	CAP_ENTRY__L(KVM_CAP_INTERNAL_ERROR_DATA), /* 40 */
137	#ifdef __KVM_HAVE_VCPU_EVENTS
138	CAP_ENTRY_ML(KVM_CAP_VCPU_EVENTS),
139	#else
140	CAP_ENTRY_MU(41),
141	#endif
142	CAP_ENTRY__L(KVM_CAP_S390_PSW),
143	CAP_ENTRY__L(KVM_CAP_PPC_SEGSTATE),
144	CAP_ENTRY__L(KVM_CAP_HYPERV),
145	CAP_ENTRY__L(KVM_CAP_HYPERV_VAPIC),
146	CAP_ENTRY__L(KVM_CAP_HYPERV_SPIN),
147	CAP_ENTRY__L(KVM_CAP_PCI_SEGMENT),
148	CAP_ENTRY__L(KVM_CAP_PPC_PAIRED_SINGLES),
149	CAP_ENTRY__L(KVM_CAP_INTR_SHADOW),
150	#ifdef __KVM_HAVE_DEBUGREGS
151	CAP_ENTRY__L(KVM_CAP_DEBUGREGS), /* 50 */
152	#endif
153	CAP_ENTRY__S(KVM_CAP_X86_ROBUST_SINGLESTEP, fRobustSingleStep),
154	CAP_ENTRY__L(KVM_CAP_PPC_OSI),
155	CAP_ENTRY__L(KVM_CAP_PPC_UNSET_IRQ),
156	CAP_ENTRY__L(KVM_CAP_ENABLE_CAP),
157	#ifdef __KVM_HAVE_XSAVE
158	CAP_ENTRY_ML(KVM_CAP_XSAVE),
159	#else
160	CAP_ENTRY_MU(55),
161	#endif
162	#ifdef __KVM_HAVE_XCRS
163	CAP_ENTRY_ML(KVM_CAP_XCRS),
164	#else
165	CAP_ENTRY_MU(56),
166	#endif
167	CAP_ENTRY__L(KVM_CAP_PPC_GET_PVINFO),
168	CAP_ENTRY__L(KVM_CAP_PPC_IRQ_LEVEL),
169	CAP_ENTRY__L(KVM_CAP_ASYNC_PF),
170	CAP_ENTRY__L(KVM_CAP_TSC_CONTROL), /* 60 */
171	CAP_ENTRY__L(KVM_CAP_GET_TSC_KHZ),
172	CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_SREGS),
173	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE),
174	CAP_ENTRY__L(KVM_CAP_PPC_SMT),
175	CAP_ENTRY__L(KVM_CAP_PPC_RMA),
176	CAP_ENTRY__L(KVM_CAP_MAX_VCPUS),
177	CAP_ENTRY__L(KVM_CAP_PPC_HIOR),
178	CAP_ENTRY__L(KVM_CAP_PPC_PAPR),
179	CAP_ENTRY__L(KVM_CAP_SW_TLB),
180	CAP_ENTRY__L(KVM_CAP_ONE_REG), /* 70 */
181	CAP_ENTRY__L(KVM_CAP_S390_GMAP),
182	CAP_ENTRY__L(KVM_CAP_TSC_DEADLINE_TIMER),
183	CAP_ENTRY__L(KVM_CAP_S390_UCONTROL),
184	CAP_ENTRY__L(KVM_CAP_SYNC_REGS),
185	CAP_ENTRY__L(KVM_CAP_PCI_2_3),
186	CAP_ENTRY__L(KVM_CAP_KVMCLOCK_CTRL),
187	CAP_ENTRY__L(KVM_CAP_SIGNAL_MSI),
188	CAP_ENTRY__L(KVM_CAP_PPC_GET_SMMU_INFO),
189	CAP_ENTRY__L(KVM_CAP_S390_COW),
190	CAP_ENTRY__L(KVM_CAP_PPC_ALLOC_HTAB), /* 80 */
191	CAP_ENTRY__L(KVM_CAP_READONLY_MEM),
192	CAP_ENTRY__L(KVM_CAP_IRQFD_RESAMPLE),
193	CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_WATCHDOG),
194	CAP_ENTRY__L(KVM_CAP_PPC_HTAB_FD),
195	CAP_ENTRY__L(KVM_CAP_S390_CSS_SUPPORT),
196	CAP_ENTRY__L(KVM_CAP_PPC_EPR),
197	CAP_ENTRY__L(KVM_CAP_ARM_PSCI),
198	CAP_ENTRY__L(KVM_CAP_ARM_SET_DEVICE_ADDR),
199	CAP_ENTRY__L(KVM_CAP_DEVICE_CTRL),
200	CAP_ENTRY__L(KVM_CAP_IRQ_MPIC), /* 90 */
201	CAP_ENTRY__L(KVM_CAP_PPC_RTAS),
202	CAP_ENTRY__L(KVM_CAP_IRQ_XICS),
203	CAP_ENTRY__L(KVM_CAP_ARM_EL1_32BIT),
204	CAP_ENTRY__L(KVM_CAP_SPAPR_MULTITCE),
205	CAP_ENTRY__L(KVM_CAP_EXT_EMUL_CPUID),
206	CAP_ENTRY__L(KVM_CAP_HYPERV_TIME),
207	CAP_ENTRY__L(KVM_CAP_IOAPIC_POLARITY_IGNORED),
208	CAP_ENTRY__L(KVM_CAP_ENABLE_CAP_VM),
209	CAP_ENTRY__L(KVM_CAP_S390_IRQCHIP),
210	CAP_ENTRY__L(KVM_CAP_IOEVENTFD_NO_LENGTH), /* 100 */
211	CAP_ENTRY__L(KVM_CAP_VM_ATTRIBUTES),
212	CAP_ENTRY__L(KVM_CAP_ARM_PSCI_0_2),
213	CAP_ENTRY__L(KVM_CAP_PPC_FIXUP_HCALL),
214	CAP_ENTRY__L(KVM_CAP_PPC_ENABLE_HCALL),
215	CAP_ENTRY__L(KVM_CAP_CHECK_EXTENSION_VM),
216	CAP_ENTRY__L(KVM_CAP_S390_USER_SIGP),
217	CAP_ENTRY__L(KVM_CAP_S390_VECTOR_REGISTERS),
218	CAP_ENTRY__L(KVM_CAP_S390_MEM_OP),
219	CAP_ENTRY__L(KVM_CAP_S390_USER_STSI),
220	CAP_ENTRY__L(KVM_CAP_S390_SKEYS), /* 110 */
221	CAP_ENTRY__L(KVM_CAP_MIPS_FPU),
222	CAP_ENTRY__L(KVM_CAP_MIPS_MSA),
223	CAP_ENTRY__L(KVM_CAP_S390_INJECT_IRQ),
224	CAP_ENTRY__L(KVM_CAP_S390_IRQ_STATE),
225	CAP_ENTRY__L(KVM_CAP_PPC_HWRNG),
226	CAP_ENTRY__L(KVM_CAP_DISABLE_QUIRKS),
227	CAP_ENTRY__L(KVM_CAP_X86_SMM),
228	CAP_ENTRY__L(KVM_CAP_MULTI_ADDRESS_SPACE),
229	CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_BPS),
230	CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_WPS), /* 120 */
231	CAP_ENTRY__L(KVM_CAP_SPLIT_IRQCHIP),
232	CAP_ENTRY__L(KVM_CAP_IOEVENTFD_ANY_LENGTH),
233	CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC),
234	CAP_ENTRY__L(KVM_CAP_S390_RI),
235	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_64),
236	CAP_ENTRY__L(KVM_CAP_ARM_PMU_V3),
237	CAP_ENTRY__L(KVM_CAP_VCPU_ATTRIBUTES),
238	CAP_ENTRY__L(KVM_CAP_MAX_VCPU_ID),
239	CAP_ENTRY__L(KVM_CAP_X2APIC_API),
240	CAP_ENTRY__L(KVM_CAP_S390_USER_INSTR0), /* 130 */
241	CAP_ENTRY__L(KVM_CAP_MSI_DEVID),
242	CAP_ENTRY__L(KVM_CAP_PPC_HTM),
243	CAP_ENTRY__L(KVM_CAP_SPAPR_RESIZE_HPT),
244	CAP_ENTRY__L(KVM_CAP_PPC_MMU_RADIX),
245	CAP_ENTRY__L(KVM_CAP_PPC_MMU_HASH_V3),
246	CAP_ENTRY__L(KVM_CAP_IMMEDIATE_EXIT),
247	CAP_ENTRY__L(KVM_CAP_MIPS_VZ),
248	CAP_ENTRY__L(KVM_CAP_MIPS_TE),
249	CAP_ENTRY__L(KVM_CAP_MIPS_64BIT),
250	CAP_ENTRY__L(KVM_CAP_S390_GS), /* 140 */
251	CAP_ENTRY__L(KVM_CAP_S390_AIS),
252	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_VFIO),
253	CAP_ENTRY__L(KVM_CAP_X86_DISABLE_EXITS),
254	CAP_ENTRY__L(KVM_CAP_ARM_USER_IRQ),
255	CAP_ENTRY__L(KVM_CAP_S390_CMMA_MIGRATION),
256	CAP_ENTRY__L(KVM_CAP_PPC_FWNMI),
257	CAP_ENTRY__L(KVM_CAP_PPC_SMT_POSSIBLE),
258	CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC2),
259	CAP_ENTRY__L(KVM_CAP_HYPERV_VP_INDEX),
260	CAP_ENTRY__L(KVM_CAP_S390_AIS_MIGRATION), /* 150 */
261	CAP_ENTRY__L(KVM_CAP_PPC_GET_CPU_CHAR),
262	CAP_ENTRY__L(KVM_CAP_S390_BPB),
263	CAP_ENTRY__L(KVM_CAP_GET_MSR_FEATURES),
264	CAP_ENTRY__L(KVM_CAP_HYPERV_EVENTFD),
265	CAP_ENTRY__L(KVM_CAP_HYPERV_TLBFLUSH),
266	CAP_ENTRY__L(KVM_CAP_S390_HPAGE_1M),
267	CAP_ENTRY__L(KVM_CAP_NESTED_STATE),
268	CAP_ENTRY__L(KVM_CAP_ARM_INJECT_SERROR_ESR),
269	CAP_ENTRY__L(KVM_CAP_MSR_PLATFORM_INFO),
270	CAP_ENTRY__L(KVM_CAP_PPC_NESTED_HV), /* 160 */
271	CAP_ENTRY__L(KVM_CAP_HYPERV_SEND_IPI),
272	CAP_ENTRY__L(KVM_CAP_COALESCED_PIO),
273	CAP_ENTRY__L(KVM_CAP_HYPERV_ENLIGHTENED_VMCS),
274	CAP_ENTRY__L(KVM_CAP_EXCEPTION_PAYLOAD),
275	CAP_ENTRY__L(KVM_CAP_ARM_VM_IPA_SIZE),
276	CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT),
277	CAP_ENTRY__L(KVM_CAP_HYPERV_CPUID),
278	CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2),
279	CAP_ENTRY__L(KVM_CAP_PPC_IRQ_XIVE),
280	CAP_ENTRY__L(KVM_CAP_ARM_SVE), /* 170 */
281	CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_ADDRESS),
282	CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_GENERIC),
283	CAP_ENTRY__L(KVM_CAP_PMU_EVENT_FILTER),
284	CAP_ENTRY__L(KVM_CAP_ARM_IRQ_LINE_LAYOUT_2),
285	CAP_ENTRY__L(KVM_CAP_HYPERV_DIRECT_TLBFLUSH),
286	CAP_ENTRY__L(KVM_CAP_PPC_GUEST_DEBUG_SSTEP),
287	CAP_ENTRY__L(KVM_CAP_ARM_NISV_TO_USER),
288	CAP_ENTRY__L(KVM_CAP_ARM_INJECT_EXT_DABT),
289	CAP_ENTRY__L(KVM_CAP_S390_VCPU_RESETS),
290	CAP_ENTRY__L(KVM_CAP_S390_PROTECTED), /* 180 */
291	CAP_ENTRY__L(KVM_CAP_PPC_SECURE_GUEST),
292	CAP_ENTRY__L(KVM_CAP_HALT_POLL),
293	CAP_ENTRY__L(KVM_CAP_ASYNC_PF_INT),
294	CAP_ENTRY__L(KVM_CAP_LAST_CPU),
295	CAP_ENTRY__L(KVM_CAP_SMALLER_MAXPHYADDR),
296	CAP_ENTRY__L(KVM_CAP_S390_DIAG318),
297	CAP_ENTRY__L(KVM_CAP_STEAL_TIME),
298	CAP_ENTRY_ML(KVM_CAP_X86_USER_SPACE_MSR), /* (since 5.10) */
299	CAP_ENTRY_ML(KVM_CAP_X86_MSR_FILTER),
300	CAP_ENTRY__L(KVM_CAP_ENFORCE_PV_FEATURE_CPUID), /* 190 */
301	CAP_ENTRY__L(KVM_CAP_SYS_HYPERV_CPUID),
302	CAP_ENTRY__L(KVM_CAP_DIRTY_LOG_RING),
303	CAP_ENTRY__L(KVM_CAP_X86_BUS_LOCK_EXIT),
304	CAP_ENTRY__L(KVM_CAP_PPC_DAWR1),
305	CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG2),
306	CAP_ENTRY__L(KVM_CAP_SGX_ATTRIBUTE),
307	CAP_ENTRY__L(KVM_CAP_VM_COPY_ENC_CONTEXT_FROM),
308	CAP_ENTRY__L(KVM_CAP_PTP_KVM),
309	CAP_ENTRY__U(199),
310	CAP_ENTRY__U(200),
311	CAP_ENTRY__U(201),
312	CAP_ENTRY__U(202),
313	CAP_ENTRY__U(203),
314	CAP_ENTRY__U(204),
315	CAP_ENTRY__U(205),
316	CAP_ENTRY__U(206),
317	CAP_ENTRY__U(207),
318	CAP_ENTRY__U(208),
319	CAP_ENTRY__U(209),
320	CAP_ENTRY__U(210),
321	CAP_ENTRY__U(211),
322	CAP_ENTRY__U(212),
323	CAP_ENTRY__U(213),
324	CAP_ENTRY__U(214),
325	CAP_ENTRY__U(215),
326	CAP_ENTRY__U(216),
327	};
328
329	LogRel(("NEM: KVM capabilities (system):\n"));
330	int rcRet = VINF_SUCCESS;
331	for (unsigned i = 0; i < RT_ELEMENTS(s_aCaps); i++)
332	{
333	int rc = ioctl(pVM->nem.s.fdVm, KVM_CHECK_EXTENSION, s_aCaps[i].iCap);
334	if (rc >= 10)
335	LogRel(("NEM: %36s: %#x (%d)\n", s_aCaps[i].pszName, rc, rc));
336	else if (rc >= 0)
337	LogRel(("NEM: %36s: %d\n", s_aCaps[i].pszName, rc));
338	else
339	LogRel(("NEM: %s failed: %d/%d\n", s_aCaps[i].pszName, rc, errno));
340	switch (s_aCaps[i].cbNem)
341	{
342	case 0:
343	break;
344	case 1:
345	{
346	uint8_t puValue = (uint8_t )&pVM->nem.padding[s_aCaps[i].offNem];
347	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
348	*puValue = (uint8_t)rc;
349	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
350	break;
351	}
352	case 2:
353	{
354	uint16_t puValue = (uint16_t )&pVM->nem.padding[s_aCaps[i].offNem];
355	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
356	*puValue = (uint16_t)rc;
357	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
358	break;
359	}
360	case 4:
361	{
362	uint32_t puValue = (uint32_t )&pVM->nem.padding[s_aCaps[i].offNem];
363	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
364	*puValue = (uint32_t)rc;
365	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
366	break;
367	}
368	default:
369	rcRet = RTErrInfoSetF(pErrInfo, VERR_NEM_IPE_0, "s_aCaps[%u] is bad: cbNem=%#x - %s",
370	i, s_aCaps[i].pszName, s_aCaps[i].cbNem);
371	AssertFailedReturn(rcRet);
372	}
373
374	/*
375	* Is a require non-zero entry zero or failing?
376	*/
377	if (s_aCaps[i].fReqNonZero && rc <= 0)
378	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE,
379	"Required capability '%s' is missing!", s_aCaps[i].pszName);
380	}
381
382	/*
383	* Get per VCpu KVM_RUN MMAP area size.
384	*/
385	int rc = ioctl(pVM->nem.s.fdKvm, KVM_GET_VCPU_MMAP_SIZE, 0UL);
386	if ((unsigned)rc < _64M)
387	{
388	pVM->nem.s.cbVCpuMmap = (uint32_t)rc;
389	LogRel(("NEM: %36s: %#x (%d)\n", "KVM_GET_VCPU_MMAP_SIZE", rc, rc));
390	}
391	else if (rc < 0)
392	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE, "KVM_GET_VCPU_MMAP_SIZE failed: %d", errno);
393	else
394	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_INIT_FAILED, "Odd KVM_GET_VCPU_MMAP_SIZE value: %#x (%d)", rc, rc);
395
396	/*
397	* Init the slot ID bitmap.
398	*/
399	ASMBitSet(&pVM->nem.s.bmSlotIds[0], 0); /* don't use slot 0 */
400	if (pVM->nem.s.cMaxMemSlots < _32K)
401	ASMBitSetRange(&pVM->nem.s.bmSlotIds[0], pVM->nem.s.cMaxMemSlots, _32K);
402	ASMBitSet(&pVM->nem.s.bmSlotIds[0], _32K - 1); /* don't use the last slot */
403
404	return rcRet;
405	}
406
407
408	/**
409	* Does the early setup of a KVM VM.
410	*
411	* @returns VBox status code.
412	* @param pVM The cross context VM structure.
413	* @param pErrInfo Where to always return error info.
414	*/
415	static int nemR3LnxInitSetupVm(PVM pVM, PRTERRINFO pErrInfo)
416	{
417	AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
418
419	/*
420	* Enable user space MSRs and let us check everything KVM cannot handle.
421	* We will set up filtering later when ring-3 init has completed.
422	*/
423	struct kvm_enable_cap CapEn =
424	{
425	KVM_CAP_X86_USER_SPACE_MSR, 0,
426	{ KVM_MSR_EXIT_REASON_FILTER \| KVM_MSR_EXIT_REASON_UNKNOWN \| KVM_MSR_EXIT_REASON_INVAL, 0, 0, 0}
427	};
428	int rcLnx = ioctl(pVM->nem.s.fdVm, KVM_ENABLE_CAP, &CapEn);
429	if (rcLnx == -1)
430	return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "Failed to enable KVM_CAP_X86_USER_SPACE_MSR failed: %u", errno);
431
432	/*
433	* Create the VCpus.
434	*/
435	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
436	{
437	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
438
439	/* Create it. */
440	pVCpu->nem.s.fdVCpu = ioctl(pVM->nem.s.fdVm, KVM_CREATE_VCPU, (unsigned long)idCpu);
441	if (pVCpu->nem.s.fdVCpu < 0)
442	return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VCPU failed for VCpu #%u: %d", idCpu, errno);
443
444	/* Map the KVM_RUN area. */
445	pVCpu->nem.s.pRun = (struct kvm_run *)mmap(NULL, pVM->nem.s.cbVCpuMmap, PROT_READ \| PROT_WRITE, MAP_SHARED,
446	pVCpu->nem.s.fdVCpu, 0 /offset/);
447	if ((void *)pVCpu->nem.s.pRun == MAP_FAILED)
448	return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "mmap failed for VCpu #%u: %d", idCpu, errno);
449
450	/* We want all x86 registers and events on each exit. */
451	pVCpu->nem.s.pRun->kvm_valid_regs = KVM_SYNC_X86_REGS \| KVM_SYNC_X86_SREGS \| KVM_SYNC_X86_EVENTS;
452	}
453	return VINF_SUCCESS;
454	}
455
456
457	/** @callback_method_impl{FNVMMEMTRENDEZVOUS} */
458	static DECLCALLBACK(VBOXSTRICTRC) nemR3LnxFixThreadPoke(PVM pVM, PVMCPU pVCpu, void *pvUser)
459	{
460	RT_NOREF(pVM, pvUser);
461	int rc = RTThreadControlPokeSignal(pVCpu->hThread, true /fEnable/);
462	AssertLogRelRC(rc);
463	return VINF_SUCCESS;
464	}
465
466
467	/**
468	* Try initialize the native API.
469	*
470	* This may only do part of the job, more can be done in
471	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
472	*
473	* @returns VBox status code.
474	* @param pVM The cross context VM structure.
475	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
476	* the latter we'll fail if we cannot initialize.
477	* @param fForced Whether the HMForced flag is set and we should
478	* fail if we cannot initialize.
479	*/
480	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
481	{
482	RT_NOREF(pVM, fFallback, fForced);
483	/*
484	* Some state init.
485	*/
486	pVM->nem.s.fdKvm = -1;
487	pVM->nem.s.fdVm = -1;
488	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
489	{
490	PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
491	pNemCpu->fdVCpu = -1;
492	}
493
494	/*
495	* Error state.
496	* The error message will be non-empty on failure and 'rc' will be set too.
497	*/
498	RTERRINFOSTATIC ErrInfo;
499	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
500
501	/*
502	* Open kvm subsystem so we can issue system ioctls.
503	*/
504	int rc;
505	int fdKvm = open("/dev/kvm", O_RDWR \| O_CLOEXEC);
506	if (fdKvm >= 0)
507	{
508	pVM->nem.s.fdKvm = fdKvm;
509
510	/*
511	* Create an empty VM since it is recommended we check capabilities on
512	* the VM rather than the system descriptor.
513	*/
514	int fdVm = ioctl(fdKvm, KVM_CREATE_VM, 0UL /* Type must be zero on x86 */);
515	if (fdVm >= 0)
516	{
517	pVM->nem.s.fdVm = fdVm;
518
519	/*
520	* Check capabilities.
521	*/
522	rc = nemR3LnxInitCheckCapabilities(pVM, pErrInfo);
523	if (RT_SUCCESS(rc))
524	{
525	/*
526	* Set up the VM (more on this later).
527	*/
528	rc = nemR3LnxInitSetupVm(pVM, pErrInfo);
529	if (RT_SUCCESS(rc))
530	{
531	/*
532	* Set ourselves as the execution engine and make config adjustments.
533	*/
534	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
535	Log(("NEM: Marked active!\n"));
536	PGMR3EnableNemMode(pVM);
537
538	/*
539	* Register release statistics
540	*/
541	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
542	{
543	PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
544	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnDemand, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of on-demand state imports", "/NEM/CPU%u/ImportOnDemand", idCpu);
545	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturn, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of state imports on loop return", "/NEM/CPU%u/ImportOnReturn", idCpu);
546	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturnSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped state imports on loop return", "/NEM/CPU%u/ImportOnReturnSkipped", idCpu);
547	STAMR3RegisterF(pVM, &pNemCpu->StatImportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when importing from KVM", "/NEM/CPU%u/ImportPendingInterrupt", idCpu);
548	STAMR3RegisterF(pVM, &pNemCpu->StatExportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when exporting to KVM", "/NEM/CPU%u/ExportPendingInterrupt", idCpu);
549	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn", idCpu);
550	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn1Loop, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-01-loop", idCpu);
551	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn2Loops, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-02-loops", idCpu);
552	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn3Loops, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-03-loops", idCpu);
553	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn4PlusLoops, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-04-to-7-loops", idCpu);
554	STAMR3RegisterF(pVM, &pNemCpu->StatQueryCpuTick, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSC queries", "/NEM/CPU%u/QueryCpuTick", idCpu);
555	STAMR3RegisterF(pVM, &pNemCpu->StatExitTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "All exits", "/NEM/CPU%u/Exit", idCpu);
556	STAMR3RegisterF(pVM, &pNemCpu->StatExitIo, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IO", "/NEM/CPU%u/Exit/Io", idCpu);
557	STAMR3RegisterF(pVM, &pNemCpu->StatExitMmio, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_MMIO", "/NEM/CPU%u/Exit/Mmio", idCpu);
558	STAMR3RegisterF(pVM, &pNemCpu->StatExitSetTpr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_SET_TRP", "/NEM/CPU%u/Exit/SetTpr", idCpu);
559	STAMR3RegisterF(pVM, &pNemCpu->StatExitTprAccess, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_TPR_ACCESS", "/NEM/CPU%u/Exit/TprAccess", idCpu);
560	STAMR3RegisterF(pVM, &pNemCpu->StatExitRdMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_RDMSR", "/NEM/CPU%u/Exit/RdMsr", idCpu);
561	STAMR3RegisterF(pVM, &pNemCpu->StatExitWrMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_WRMSR", "/NEM/CPU%u/Exit/WrMsr", idCpu);
562	STAMR3RegisterF(pVM, &pNemCpu->StatExitIrqWindowOpen, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IRQ_WINDOWS_OPEN", "/NEM/CPU%u/Exit/IrqWindowOpen", idCpu);
563	STAMR3RegisterF(pVM, &pNemCpu->StatExitHalt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HLT", "/NEM/CPU%u/Exit/Hlt", idCpu);
564	STAMR3RegisterF(pVM, &pNemCpu->StatExitIntr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTR", "/NEM/CPU%u/Exit/Intr", idCpu);
565	STAMR3RegisterF(pVM, &pNemCpu->StatExitHypercall, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HYPERCALL", "/NEM/CPU%u/Exit/Hypercall", idCpu);
566	STAMR3RegisterF(pVM, &pNemCpu->StatExitDebug, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_DEBUG", "/NEM/CPU%u/Exit/Debug", idCpu);
567	STAMR3RegisterF(pVM, &pNemCpu->StatExitBusLock, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_BUS_LOCK", "/NEM/CPU%u/Exit/BusLock", idCpu);
568	STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorEmulation, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/EMULATION", "/NEM/CPU%u/Exit/InternalErrorEmulation", idCpu);
569	STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorFatal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/*", "/NEM/CPU%u/Exit/InternalErrorFatal", idCpu);
570	}
571
572	/*
573	* Success.
574	*/
575	return VINF_SUCCESS;
576	}
577
578	/*
579	* Bail out.
580	*/
581	}
582	close(fdVm);
583	pVM->nem.s.fdVm = -1;
584	}
585	else
586	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VM failed: %u", errno);
587	close(fdKvm);
588	pVM->nem.s.fdKvm = -1;
589	}
590	else if (errno == EACCES)
591	rc = RTErrInfoSet(pErrInfo, VERR_ACCESS_DENIED, "Do not have access to open /dev/kvm for reading & writing.");
592	else if (errno == ENOENT)
593	rc = RTErrInfoSet(pErrInfo, VERR_NOT_SUPPORTED, "KVM is not availble (/dev/kvm does not exist)");
594	else
595	rc = RTErrInfoSetF(pErrInfo, RTErrConvertFromErrno(errno), "Failed to open '/dev/kvm': %u", errno);
596
597	/*
598	* We only fail if in forced mode, otherwise just log the complaint and return.
599	*/
600	Assert(RTErrInfoIsSet(pErrInfo));
601	if ( (fForced \|\| !fFallback)
602	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
603	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
604	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
605	return VINF_SUCCESS;
606	}
607
608
609	/**
610	* This is called after CPUMR3Init is done.
611	*
612	* @returns VBox status code.
613	* @param pVM The VM handle..
614	*/
615	int nemR3NativeInitAfterCPUM(PVM pVM)
616	{
617	/*
618	* Validate sanity.
619	*/
620	AssertReturn(pVM->nem.s.fdKvm >= 0, VERR_WRONG_ORDER);
621	AssertReturn(pVM->nem.s.fdVm >= 0, VERR_WRONG_ORDER);
622	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
623
624	/** @todo */
625
626	return VINF_SUCCESS;
627	}
628
629
630	/**
631	* Update the CPUID leaves for a VCPU.
632	*
633	* The KVM_SET_CPUID2 call replaces any previous leaves, so we have to redo
634	* everything when there really just are single bit changes. That said, it
635	* looks like KVM update the XCR/XSAVE related stuff as well as the APIC enabled
636	* bit(s), so it should suffice if we do this at startup, I hope.
637	*/
638	static int nemR3LnxUpdateCpuIdsLeaves(PVM pVM, PVMCPU pVCpu)
639	{
640	uint32_t cLeaves = 0;
641	PCCPUMCPUIDLEAF const paLeaves = CPUMR3CpuIdGetPtr(pVM, &cLeaves);
642	struct kvm_cpuid2 pReq = (struct kvm_cpuid2 )alloca(RT_UOFFSETOF_DYN(struct kvm_cpuid2, entries[cLeaves + 2]));
643
644	pReq->nent = cLeaves;
645	pReq->padding = 0;
646
647	for (uint32_t i = 0; i < cLeaves; i++)
648	{
649	CPUMGetGuestCpuId(pVCpu, paLeaves[i].uLeaf, paLeaves[i].uSubLeaf,
650	&pReq->entries[i].eax,
651	&pReq->entries[i].ebx,
652	&pReq->entries[i].ecx,
653	&pReq->entries[i].edx);
654	pReq->entries[i].function = paLeaves[i].uLeaf;
655	pReq->entries[i].index = paLeaves[i].uSubLeaf;
656	pReq->entries[i].flags = !paLeaves[i].fSubLeafMask ? 0 : KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
657	pReq->entries[i].padding[0] = 0;
658	pReq->entries[i].padding[1] = 0;
659	pReq->entries[i].padding[2] = 0;
660	}
661
662	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_CPUID2, pReq);
663	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d cLeaves=%#x\n", rcLnx, errno, cLeaves), RTErrConvertFromErrno(errno));
664
665	return VINF_SUCCESS;
666	}
667
668
669	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
670	{
671	/*
672	* Make RTThreadPoke work again (disabled for avoiding unnecessary
673	* critical section issues in ring-0).
674	*/
675	if (enmWhat == VMINITCOMPLETED_RING3)
676	VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE, nemR3LnxFixThreadPoke, NULL);
677
678	/*
679	* Configure CPUIDs after ring-3 init has been done.
680	*/
681	if (enmWhat == VMINITCOMPLETED_RING3)
682	{
683	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
684	{
685	int rc = nemR3LnxUpdateCpuIdsLeaves(pVM, pVM->apCpusR3[idCpu]);
686	AssertRCReturn(rc, rc);
687	}
688	}
689
690	/*
691	* Configure MSRs after ring-3 init is done.
692	*
693	* We only need to tell KVM which MSRs it can handle, as we already
694	* requested KVM_MSR_EXIT_REASON_FILTER, KVM_MSR_EXIT_REASON_UNKNOWN
695	* and KVM_MSR_EXIT_REASON_INVAL in nemR3LnxInitSetupVm, and here we
696	* will use KVM_MSR_FILTER_DEFAULT_DENY. So, all MSRs w/o a 1 in the
697	* bitmaps should be deferred to ring-3.
698	*/
699	if (enmWhat == VMINITCOMPLETED_RING3)
700	{
701	struct kvm_msr_filter MsrFilters = {0}; /* Structure with a couple of implicit paddings on 64-bit systems. */
702	MsrFilters.flags = KVM_MSR_FILTER_DEFAULT_DENY;
703
704	unsigned iRange = 0;
705	#define MSR_RANGE_BEGIN(a_uBase, a_uEnd, a_fFlags) \
706	AssertCompile(0x3000 <= KVM_MSR_FILTER_MAX_BITMAP_SIZE * 8); \
707	uint64_t RT_CONCAT(bm, a_uBase)[0x3000 / 64] = {0}; \
708	do { \
709	uint64_t * const pbm = RT_CONCAT(bm, a_uBase); \
710	uint32_t const uBase = UINT32_C(a_uBase); \
711	uint32_t const cMsrs = UINT32_C(a_uEnd) - UINT32_C(a_uBase); \
712	MsrFilters.ranges[iRange].base = UINT32_C(a_uBase); \
713	MsrFilters.ranges[iRange].nmsrs = cMsrs; \
714	MsrFilters.ranges[iRange].flags = (a_fFlags); \
715	MsrFilters.ranges[iRange].bitmap = (uint8_t *)&RT_CONCAT(bm, a_uBase)[0]
716	#define MSR_RANGE_ADD(a_Msr) \
717	do { Assert((uint32_t)(a_Msr) - uBase < cMsrs); ASMBitSet(pbm, (uint32_t)(a_Msr) - uBase); } while (0)
718	#define MSR_RANGE_END(a_cMinMsrs) \
719	/* optimize the range size before closing: */ \
720	uint32_t cBitmap = cMsrs / 64; \
721	while (cBitmap > ((a_cMinMsrs) + 63 / 64) && pbm[cBitmap - 1] == 0) \
722	cBitmap -= 1; \
723	MsrFilters.ranges[iRange].nmsrs = cBitmap * 64; \
724	iRange++; \
725	} while (0)
726
727	/* 1st Intel range: 0000_0000 to 0000_3000. */
728	MSR_RANGE_BEGIN(0x00000000, 0x00003000, KVM_MSR_FILTER_READ \| KVM_MSR_FILTER_WRITE);
729	MSR_RANGE_ADD(MSR_IA32_TSC);
730	MSR_RANGE_ADD(MSR_IA32_SYSENTER_CS);
731	MSR_RANGE_ADD(MSR_IA32_SYSENTER_ESP);
732	MSR_RANGE_ADD(MSR_IA32_SYSENTER_EIP);
733	MSR_RANGE_ADD(MSR_IA32_CR_PAT);
734	/** @todo more? */
735	MSR_RANGE_END(64);
736
737	/* 1st AMD range: c000_0000 to c000_3000 */
738	MSR_RANGE_BEGIN(0xc0000000, 0xc0003000, KVM_MSR_FILTER_READ \| KVM_MSR_FILTER_WRITE);
739	MSR_RANGE_ADD(MSR_K6_EFER);
740	MSR_RANGE_ADD(MSR_K6_STAR);
741	MSR_RANGE_ADD(MSR_K8_GS_BASE);
742	MSR_RANGE_ADD(MSR_K8_KERNEL_GS_BASE);
743	MSR_RANGE_ADD(MSR_K8_LSTAR);
744	MSR_RANGE_ADD(MSR_K8_CSTAR);
745	MSR_RANGE_ADD(MSR_K8_SF_MASK);
746	MSR_RANGE_ADD(MSR_K8_TSC_AUX);
747	/** @todo add more? */
748	MSR_RANGE_END(64);
749
750	/** @todo Specify other ranges too? Like hyper-V and KVM to make sure we get
751	* the MSR requests instead of KVM. */
752
753	int rcLnx = ioctl(pVM->nem.s.fdVm, KVM_X86_SET_MSR_FILTER, &MsrFilters);
754	if (rcLnx == -1)
755	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
756	"Failed to enable KVM_X86_SET_MSR_FILTER failed: %u", errno);
757	}
758
759	return VINF_SUCCESS;
760	}
761
762
763	int nemR3NativeTerm(PVM pVM)
764	{
765	/*
766	* Per-cpu data
767	*/
768	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
769	{
770	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
771
772	if (pVCpu->nem.s.fdVCpu != -1)
773	{
774	close(pVCpu->nem.s.fdVCpu);
775	pVCpu->nem.s.fdVCpu = -1;
776	}
777	if (pVCpu->nem.s.pRun)
778	{
779	munmap(pVCpu->nem.s.pRun, pVM->nem.s.cbVCpuMmap);
780	pVCpu->nem.s.pRun = NULL;
781	}
782	}
783
784	/*
785	* Global data.
786	*/
787	if (pVM->nem.s.fdVm != -1)
788	{
789	close(pVM->nem.s.fdVm);
790	pVM->nem.s.fdVm = -1;
791	}
792
793	if (pVM->nem.s.fdKvm != -1)
794	{
795	close(pVM->nem.s.fdKvm);
796	pVM->nem.s.fdKvm = -1;
797	}
798	return VINF_SUCCESS;
799	}
800
801
802	/**
803	* VM reset notification.
804	*
805	* @param pVM The cross context VM structure.
806	*/
807	void nemR3NativeReset(PVM pVM)
808	{
809	RT_NOREF(pVM);
810	}
811
812
813	/**
814	* Reset CPU due to INIT IPI or hot (un)plugging.
815	*
816	* @param pVCpu The cross context virtual CPU structure of the CPU being
817	* reset.
818	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
819	*/
820	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
821	{
822	RT_NOREF(pVCpu, fInitIpi);
823	}
824
825
826	/*********************************************************************************************************************************
827	* Memory management *
828	*********************************************************************************************************************************/
829
830
831	/**
832	* Allocates a memory slot ID.
833	*
834	* @returns Slot ID on success, UINT16_MAX on failure.
835	*/
836	static uint16_t nemR3LnxMemSlotIdAlloc(PVM pVM)
837	{
838	/* Use the hint first. */
839	uint16_t idHint = pVM->nem.s.idPrevSlot;
840	if (idHint < _32K - 1)
841	{
842	int32_t idx = ASMBitNextClear(&pVM->nem.s.bmSlotIds, _32K, idHint);
843	Assert(idx < _32K);
844	if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
845	return pVM->nem.s.idPrevSlot = (uint16_t)idx;
846	}
847
848	/*
849	* Search the whole map from the start.
850	*/
851	int32_t idx = ASMBitFirstClear(&pVM->nem.s.bmSlotIds, _32K);
852	Assert(idx < _32K);
853	if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
854	return pVM->nem.s.idPrevSlot = (uint16_t)idx;
855
856	Assert(idx < 0 /shouldn't trigger unless there is a race /);
857	return UINT16_MAX; /* caller is expected to assert. */
858	}
859
860
861	/**
862	* Frees a memory slot ID
863	*/
864	static void nemR3LnxMemSlotIdFree(PVM pVM, uint16_t idSlot)
865	{
866	if (RT_LIKELY(idSlot < _32K && ASMAtomicBitTestAndClear(&pVM->nem.s.bmSlotIds, idSlot)))
867	{ /likely/ }
868	else
869	AssertMsgFailed(("idSlot=%u (%#x)\n", idSlot, idSlot));
870	}
871
872
873
874	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
875	uint8_t pu2State, uint32_t puNemRange)
876	{
877	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
878	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
879
880	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p pu2State=%p (%d) puNemRange=%p (%d) - idSlot=%#x\n",
881	GCPhys, cb, pvR3, pu2State, pu2State, puNemRange, *puNemRange, idSlot));
882
883	struct kvm_userspace_memory_region Region;
884	Region.slot = idSlot;
885	Region.flags = 0;
886	Region.guest_phys_addr = GCPhys;
887	Region.memory_size = cb;
888	Region.userspace_addr = (uintptr_t)pvR3;
889
890	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
891	if (rc == 0)
892	{
893	*pu2State = 0;
894	*puNemRange = idSlot;
895	return VINF_SUCCESS;
896	}
897
898	LogRel(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p, idSlot=%#x failed: %u/%u\n", GCPhys, cb, pvR3, idSlot, rc, errno));
899	nemR3LnxMemSlotIdFree(pVM, idSlot);
900	return VERR_NEM_MAP_PAGES_FAILED;
901	}
902
903
904	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
905	{
906	RT_NOREF(pVM);
907	return true;
908	}
909
910
911	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
912	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
913	{
914	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d) puNemRange=%p (%#x)\n",
915	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, pu2State, puNemRange, puNemRange ? puNemRange : UINT32_MAX));
916	RT_NOREF(pvRam);
917
918	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
919	{
920	/** @todo implement splitting and whatnot of ranges if we want to be 100%
921	* conforming (just modify RAM registrations in MM.cpp to test). */
922	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
923	VERR_NEM_MAP_PAGES_FAILED);
924	}
925
926	/*
927	* Register MMIO2.
928	*/
929	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
930	{
931	AssertReturn(pvMmio2, VERR_NEM_MAP_PAGES_FAILED);
932	AssertReturn(puNemRange, VERR_NEM_MAP_PAGES_FAILED);
933
934	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
935	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
936
937	struct kvm_userspace_memory_region Region;
938	Region.slot = idSlot;
939	Region.flags = fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES ? KVM_MEM_LOG_DIRTY_PAGES : 0;
940	Region.guest_phys_addr = GCPhys;
941	Region.memory_size = cb;
942	Region.userspace_addr = (uintptr_t)pvMmio2;
943
944	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
945	if (rc == 0)
946	{
947	*pu2State = 0;
948	*puNemRange = idSlot;
949	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvMmio2=%p - idSlot=%#x\n",
950	GCPhys, cb, fFlags, pvMmio2, idSlot));
951	return VINF_SUCCESS;
952	}
953
954	nemR3LnxMemSlotIdFree(pVM, idSlot);
955	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
956	GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
957	VERR_NEM_MAP_PAGES_FAILED);
958	}
959
960	/* MMIO, don't care. */
961	*pu2State = 0;
962	*puNemRange = UINT32_MAX;
963	return VINF_SUCCESS;
964	}
965
966
967	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
968	void pvRam, void pvMmio2, uint32_t *puNemRange)
969	{
970	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
971	return VINF_SUCCESS;
972	}
973
974
975	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
976	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
977	{
978	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p puNemRange=%p (%#x)\n",
979	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
980	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
981
982	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
983	{
984	/** @todo implement splitting and whatnot of ranges if we want to be 100%
985	* conforming (just modify RAM registrations in MM.cpp to test). */
986	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
987	VERR_NEM_UNMAP_PAGES_FAILED);
988	}
989
990	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
991	{
992	uint32_t const idSlot = *puNemRange;
993	AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
994	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
995
996	struct kvm_userspace_memory_region Region;
997	Region.slot = idSlot;
998	Region.flags = 0;
999	Region.guest_phys_addr = GCPhys;
1000	Region.memory_size = 0; /* this deregisters it. */
1001	Region.userspace_addr = (uintptr_t)pvMmio2;
1002
1003	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
1004	if (rc == 0)
1005	{
1006	if (pu2State)
1007	*pu2State = 0;
1008	*puNemRange = UINT32_MAX;
1009	nemR3LnxMemSlotIdFree(pVM, idSlot);
1010	return VINF_SUCCESS;
1011	}
1012
1013	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
1014	GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
1015	VERR_NEM_UNMAP_PAGES_FAILED);
1016	}
1017
1018	if (pu2State)
1019	*pu2State = UINT8_MAX;
1020	return VINF_SUCCESS;
1021	}
1022
1023
1024	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
1025	void *pvBitmap, size_t cbBitmap)
1026	{
1027	AssertReturn(uNemRange > 0 && uNemRange < _32K, VERR_NEM_IPE_4);
1028	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, uNemRange), VERR_NEM_IPE_4);
1029
1030	RT_NOREF(GCPhys, cbBitmap);
1031
1032	struct kvm_dirty_log DirtyLog;
1033	DirtyLog.slot = uNemRange;
1034	DirtyLog.padding1 = 0;
1035	DirtyLog.dirty_bitmap = pvBitmap;
1036
1037	int rc = ioctl(pVM->nem.s.fdVm, KVM_GET_DIRTY_LOG, &DirtyLog);
1038	AssertLogRelMsgReturn(rc == 0, ("%RGp LB %RGp idSlot=%#x failed: %u/%u\n", GCPhys, cb, uNemRange, errno, rc),
1039	VERR_NEM_QUERY_DIRTY_BITMAP_FAILED);
1040
1041	return VINF_SUCCESS;
1042	}
1043
1044
1045	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
1046	uint8_t pu2State, uint32_t puNemRange)
1047	{
1048	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
1049	*pu2State = UINT8_MAX;
1050
1051	/* Don't support puttint ROM where there is already RAM. For
1052	now just shuffle the registrations till it works... */
1053	AssertLogRelMsgReturn(!(fFlags & NEM_NOTIFY_PHYS_ROM_F_REPLACE), ("%RGp LB %RGp fFlags=%#x\n", GCPhys, cb, fFlags),
1054	VERR_NEM_MAP_PAGES_FAILED);
1055
1056	/** @todo figure out how to do shadow ROMs. */
1057
1058	/*
1059	* We only allocate a slot number here in case we need to use it to
1060	* fend of physical handler fun.
1061	*/
1062	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
1063	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
1064
1065	*pu2State = 0;
1066	*puNemRange = idSlot;
1067	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
1068	GCPhys, cb, fFlags, pvPages, idSlot));
1069	RT_NOREF(GCPhys, cb, fFlags, pvPages);
1070	return VINF_SUCCESS;
1071	}
1072
1073
1074	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
1075	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
1076	{
1077	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
1078	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
1079
1080	AssertPtrReturn(pvPages, VERR_NEM_IPE_5);
1081
1082	uint32_t const idSlot = *puNemRange;
1083	AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
1084	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
1085
1086	*pu2State = UINT8_MAX;
1087
1088	/*
1089	* Do the actual setting of the user pages here now that we've
1090	* got a valid pvPages (typically isn't available during the early
1091	* notification, unless we're replacing RAM).
1092	*/
1093	struct kvm_userspace_memory_region Region;
1094	Region.slot = idSlot;
1095	Region.flags = 0;
1096	Region.guest_phys_addr = GCPhys;
1097	Region.memory_size = cb;
1098	Region.userspace_addr = (uintptr_t)pvPages;
1099
1100	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
1101	if (rc == 0)
1102	{
1103	*pu2State = 0;
1104	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
1105	GCPhys, cb, fFlags, pvPages, idSlot));
1106	return VINF_SUCCESS;
1107	}
1108	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvPages=%p, idSlot=%#x failed: %u/%u\n",
1109	GCPhys, cb, fFlags, pvPages, idSlot, errno, rc),
1110	VERR_NEM_MAP_PAGES_FAILED);
1111	}
1112
1113
1114	/**
1115	* Called when the A20 state changes.
1116	*
1117	* @param pVCpu The CPU the A20 state changed on.
1118	* @param fEnabled Whether it was enabled (true) or disabled.
1119	*/
1120	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
1121	{
1122	Log(("nemR3NativeNotifySetA20: fEnabled=%RTbool\n", fEnabled));
1123	Assert(VM_IS_NEM_ENABLED(pVCpu->CTX_SUFF(pVM)));
1124	RT_NOREF(pVCpu, fEnabled);
1125	}
1126
1127
1128	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1129	RTR3PTR pvMemR3, uint8_t *pu2State)
1130	{
1131	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
1132	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
1133
1134	*pu2State = UINT8_MAX;
1135	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
1136	}
1137
1138
1139	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
1140	{
1141	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
1142	RT_NOREF(pVM, enmKind, GCPhys, cb);
1143	}
1144
1145
1146	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
1147	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
1148	{
1149	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
1150	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
1151	RT_NOREF(pVM, enmKind, GCPhysOld, GCPhysNew, cb, fRestoreAsRAM);
1152	}
1153
1154
1155	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
1156	PGMPAGETYPE enmType, uint8_t *pu2State)
1157	{
1158	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1159	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1160	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
1161	return VINF_SUCCESS;
1162	}
1163
1164
1165	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
1166	PGMPAGETYPE enmType, uint8_t *pu2State)
1167	{
1168	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1169	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1170	Assert(VM_IS_NEM_ENABLED(pVM));
1171	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
1172
1173	}
1174
1175
1176	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
1177	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
1178	{
1179	Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp pvNewR3=%p fPageProt=%#x enmType=%d *pu2State=%d\n",
1180	GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, *pu2State));
1181	Assert(VM_IS_NEM_ENABLED(pVM));
1182	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
1183	}
1184
1185
1186	/*********************************************************************************************************************************
1187	* CPU State *
1188	*********************************************************************************************************************************/
1189
1190	/**
1191	* Worker that imports selected state from KVM.
1192	*/
1193	static int nemHCLnxImportState(PVMCPUCC pVCpu, uint64_t fWhat, PCPUMCTX pCtx, struct kvm_run *pRun)
1194	{
1195	fWhat &= pVCpu->cpum.GstCtx.fExtrn;
1196	if (!fWhat)
1197	return VINF_SUCCESS;
1198
1199	/*
1200	* Stuff that goes into kvm_run::s.regs.regs:
1201	*/
1202	if (fWhat & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK))
1203	{
1204	if (fWhat & CPUMCTX_EXTRN_RIP)
1205	pCtx->rip = pRun->s.regs.regs.rip;
1206	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1207	pCtx->rflags.u = pRun->s.regs.regs.rflags;
1208
1209	if (fWhat & CPUMCTX_EXTRN_RAX)
1210	pCtx->rax = pRun->s.regs.regs.rax;
1211	if (fWhat & CPUMCTX_EXTRN_RCX)
1212	pCtx->rcx = pRun->s.regs.regs.rcx;
1213	if (fWhat & CPUMCTX_EXTRN_RDX)
1214	pCtx->rdx = pRun->s.regs.regs.rdx;
1215	if (fWhat & CPUMCTX_EXTRN_RBX)
1216	pCtx->rbx = pRun->s.regs.regs.rbx;
1217	if (fWhat & CPUMCTX_EXTRN_RSP)
1218	pCtx->rsp = pRun->s.regs.regs.rsp;
1219	if (fWhat & CPUMCTX_EXTRN_RBP)
1220	pCtx->rbp = pRun->s.regs.regs.rbp;
1221	if (fWhat & CPUMCTX_EXTRN_RSI)
1222	pCtx->rsi = pRun->s.regs.regs.rsi;
1223	if (fWhat & CPUMCTX_EXTRN_RDI)
1224	pCtx->rdi = pRun->s.regs.regs.rdi;
1225	if (fWhat & CPUMCTX_EXTRN_R8_R15)
1226	{
1227	pCtx->r8 = pRun->s.regs.regs.r8;
1228	pCtx->r9 = pRun->s.regs.regs.r9;
1229	pCtx->r10 = pRun->s.regs.regs.r10;
1230	pCtx->r11 = pRun->s.regs.regs.r11;
1231	pCtx->r12 = pRun->s.regs.regs.r12;
1232	pCtx->r13 = pRun->s.regs.regs.r13;
1233	pCtx->r14 = pRun->s.regs.regs.r14;
1234	pCtx->r15 = pRun->s.regs.regs.r15;
1235	}
1236	}
1237
1238	/*
1239	* Stuff that goes into kvm_run::s.regs.sregs.
1240	*
1241	* Note! The apic_base can be ignored because we gets all MSR writes to it
1242	* and VBox always keeps the correct value.
1243	*/
1244	bool fMaybeChangedMode = false;
1245	bool fUpdateCr3 = false;
1246	if (fWhat & ( CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_TABLE_MASK \| CPUMCTX_EXTRN_CR_MASK
1247	\| CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_APIC_TPR))
1248	{
1249	/** @todo what about Attr.n.u4LimitHigh? */
1250	#define NEM_LNX_IMPORT_SEG(a_CtxSeg, a_KvmSeg) do { \
1251	(a_CtxSeg).u64Base = (a_KvmSeg).base; \
1252	(a_CtxSeg).u32Limit = (a_KvmSeg).limit; \
1253	(a_CtxSeg).ValidSel = (a_CtxSeg).Sel = (a_KvmSeg).selector; \
1254	(a_CtxSeg).Attr.n.u4Type = (a_KvmSeg).type; \
1255	(a_CtxSeg).Attr.n.u1DescType = (a_KvmSeg).s; \
1256	(a_CtxSeg).Attr.n.u2Dpl = (a_KvmSeg).dpl; \
1257	(a_CtxSeg).Attr.n.u1Present = (a_KvmSeg).present; \
1258	(a_CtxSeg).Attr.n.u1Available = (a_KvmSeg).avl; \
1259	(a_CtxSeg).Attr.n.u1Long = (a_KvmSeg).l; \
1260	(a_CtxSeg).Attr.n.u1DefBig = (a_KvmSeg).db; \
1261	(a_CtxSeg).Attr.n.u1Granularity = (a_KvmSeg).g; \
1262	(a_CtxSeg).Attr.n.u1Unusable = (a_KvmSeg).unusable; \
1263	(a_CtxSeg).fFlags = CPUMSELREG_FLAGS_VALID; \
1264	CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &(a_CtxSeg)); \
1265	} while (0)
1266
1267	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1268	{
1269	if (fWhat & CPUMCTX_EXTRN_ES)
1270	NEM_LNX_IMPORT_SEG(pCtx->es, pRun->s.regs.sregs.es);
1271	if (fWhat & CPUMCTX_EXTRN_CS)
1272	NEM_LNX_IMPORT_SEG(pCtx->cs, pRun->s.regs.sregs.cs);
1273	if (fWhat & CPUMCTX_EXTRN_SS)
1274	NEM_LNX_IMPORT_SEG(pCtx->ss, pRun->s.regs.sregs.ss);
1275	if (fWhat & CPUMCTX_EXTRN_DS)
1276	NEM_LNX_IMPORT_SEG(pCtx->ds, pRun->s.regs.sregs.ds);
1277	if (fWhat & CPUMCTX_EXTRN_FS)
1278	NEM_LNX_IMPORT_SEG(pCtx->fs, pRun->s.regs.sregs.fs);
1279	if (fWhat & CPUMCTX_EXTRN_GS)
1280	NEM_LNX_IMPORT_SEG(pCtx->gs, pRun->s.regs.sregs.gs);
1281	}
1282	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1283	{
1284	if (fWhat & CPUMCTX_EXTRN_GDTR)
1285	{
1286	pCtx->gdtr.pGdt = pRun->s.regs.sregs.gdt.base;
1287	pCtx->gdtr.cbGdt = pRun->s.regs.sregs.gdt.limit;
1288	}
1289	if (fWhat & CPUMCTX_EXTRN_IDTR)
1290	{
1291	pCtx->idtr.pIdt = pRun->s.regs.sregs.idt.base;
1292	pCtx->idtr.cbIdt = pRun->s.regs.sregs.idt.limit;
1293	}
1294	if (fWhat & CPUMCTX_EXTRN_LDTR)
1295	NEM_LNX_IMPORT_SEG(pCtx->ldtr, pRun->s.regs.sregs.ldt);
1296	if (fWhat & CPUMCTX_EXTRN_TR)
1297	NEM_LNX_IMPORT_SEG(pCtx->tr, pRun->s.regs.sregs.tr);
1298	}
1299	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1300	{
1301	if (fWhat & CPUMCTX_EXTRN_CR0)
1302	{
1303	if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1304	{
1305	CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1306	fMaybeChangedMode = true;
1307	}
1308	}
1309	if (fWhat & CPUMCTX_EXTRN_CR2)
1310	pCtx->cr2 = pRun->s.regs.sregs.cr2;
1311	if (fWhat & CPUMCTX_EXTRN_CR3)
1312	{
1313	if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1314	{
1315	CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1316	fUpdateCr3 = true;
1317	}
1318	}
1319	if (fWhat & CPUMCTX_EXTRN_CR4)
1320	{
1321	if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1322	{
1323	CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1324	fMaybeChangedMode = true;
1325	}
1326	}
1327	}
1328	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
1329	APICSetTpr(pVCpu, (uint8_t)pRun->s.regs.sregs.cr8 << 4);
1330	if (fWhat & CPUMCTX_EXTRN_EFER)
1331	{
1332	if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1333	{
1334	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1335	if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1336	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1337	pCtx->msrEFER = pRun->s.regs.sregs.efer;
1338	fMaybeChangedMode = true;
1339	}
1340	}
1341	#undef NEM_LNX_IMPORT_SEG
1342	}
1343
1344	/*
1345	* Debug registers.
1346	*/
1347	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
1348	{
1349	struct kvm_debugregs DbgRegs = {{0}};
1350	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1351	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1352
1353	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1354	{
1355	pCtx->dr[0] = DbgRegs.db[0];
1356	pCtx->dr[1] = DbgRegs.db[1];
1357	pCtx->dr[2] = DbgRegs.db[2];
1358	pCtx->dr[3] = DbgRegs.db[3];
1359	}
1360	if (fWhat & CPUMCTX_EXTRN_DR6)
1361	pCtx->dr[6] = DbgRegs.dr6;
1362	if (fWhat & CPUMCTX_EXTRN_DR7)
1363	pCtx->dr[7] = DbgRegs.dr7;
1364	}
1365
1366	/*
1367	* FPU, SSE, AVX, ++.
1368	*/
1369	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE \| CPUMCTX_EXTRN_XCRx))
1370	{
1371	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1372	{
1373	fWhat \|= CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE; /* we do all or nothing at all */
1374
1375	AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1376	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XSAVE, &pCtx->XState);
1377	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1378	}
1379
1380	if (fWhat & CPUMCTX_EXTRN_XCRx)
1381	{
1382	struct kvm_xcrs Xcrs =
1383	{ /.nr_xcrs = / 2,
1384	/.flags = / 0,
1385	/.xcrs= / {
1386	{ /.xcr =/ 0, /.reserved=/ 0, /.value=/ pCtx->aXcr[0] },
1387	{ /.xcr =/ 1, /.reserved=/ 0, /.value=/ pCtx->aXcr[1] },
1388	}
1389	};
1390
1391	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XCRS, &Xcrs);
1392	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1393
1394	pCtx->aXcr[0] = Xcrs.xcrs[0].value;
1395	pCtx->aXcr[1] = Xcrs.xcrs[1].value;
1396	}
1397	}
1398
1399	/*
1400	* MSRs.
1401	*/
1402	if (fWhat & ( CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS
1403	\| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
1404	{
1405	union
1406	{
1407	struct kvm_msrs Core;
1408	uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1409	} uBuf;
1410	uint64_t *pauDsts[32];
1411	uint32_t iMsr = 0;
1412	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1413
1414	#define ADD_MSR(a_Msr, a_uValue) do { \
1415	Assert(iMsr < 32); \
1416	uBuf.Core.entries[iMsr].index = (a_Msr); \
1417	uBuf.Core.entries[iMsr].reserved = 0; \
1418	uBuf.Core.entries[iMsr].data = UINT64_MAX; \
1419	pauDsts[iMsr] = &(a_uValue); \
1420	iMsr += 1; \
1421	} while (0)
1422
1423	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1424	ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1425	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1426	{
1427	ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1428	ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1429	ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1430	ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1431	}
1432	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1433	{
1434	ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1435	ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1436	ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1437	}
1438	if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
1439	ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1440	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1441	{
1442	ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1443	/** @todo What do we _have_ to add here?
1444	* We also have: Mttr, MiscEnable, FeatureControl. /
1445	}
1446
1447	uBuf.Core.pad = 0;
1448	uBuf.Core.nmsrs = iMsr;
1449	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MSRS, &uBuf);
1450	AssertMsgReturn(rc == (int)iMsr,
1451	("rc=%d iMsr=%d (->%#x) errno=%d\n",
1452	rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1453	VERR_NEM_IPE_3);
1454
1455	while (iMsr-- > 0)
1456	*pauDsts[iMsr] = uBuf.Core.entries[iMsr].data;
1457	#undef ADD_MSR
1458	}
1459
1460	/*
1461	* Interruptibility state and pending interrupts.
1462	*/
1463	if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1464	{
1465	fWhat \|= CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI; /* always do both, see export and interrupt FF handling */
1466
1467	struct kvm_vcpu_events KvmEvents = {0};
1468	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
1469	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1470
1471	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP)
1472	pVCpu->cpum.GstCtx.rip = pRun->s.regs.regs.rip;
1473
1474	if (KvmEvents.interrupt.shadow)
1475	EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
1476	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1477	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1478
1479	if (KvmEvents.nmi.masked)
1480	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1481	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1482	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
1483
1484	if (KvmEvents.interrupt.injected)
1485	{
1486	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportPendingInterrupt);
1487	TRPMAssertTrap(pVCpu, KvmEvents.interrupt.nr, !KvmEvents.interrupt.soft ? TRPM_HARDWARE_INT : TRPM_SOFTWARE_INT);
1488	}
1489
1490	Assert(KvmEvents.nmi.injected == 0);
1491	Assert(KvmEvents.nmi.pending == 0);
1492	}
1493
1494	/*
1495	* Update the external mask.
1496	*/
1497	pCtx->fExtrn &= ~fWhat;
1498	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1499	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1500	pVCpu->cpum.GstCtx.fExtrn = 0;
1501
1502	/*
1503	* We sometimes need to update PGM on the guest status.
1504	*/
1505	if (!fMaybeChangedMode && !fUpdateCr3)
1506	{ /* likely */ }
1507	else
1508	{
1509	/*
1510	* Make sure we got all the state PGM might need.
1511	*/
1512	Log7(("nemHCLnxImportState: fMaybeChangedMode=%d fUpdateCr3=%d fExtrnNeeded=%#RX64\n", fMaybeChangedMode, fUpdateCr3,
1513	pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER) ));
1514	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER))
1515	{
1516	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR0)
1517	{
1518	if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1519	{
1520	CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1521	fMaybeChangedMode = true;
1522	}
1523	}
1524	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR3)
1525	{
1526	if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1527	{
1528	CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1529	fUpdateCr3 = true;
1530	}
1531	}
1532	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR4)
1533	{
1534	if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1535	{
1536	CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1537	fMaybeChangedMode = true;
1538	}
1539	}
1540	if (fWhat & CPUMCTX_EXTRN_EFER)
1541	{
1542	if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1543	{
1544	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1545	if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1546	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1547	pCtx->msrEFER = pRun->s.regs.sregs.efer;
1548	fMaybeChangedMode = true;
1549	}
1550	}
1551
1552	pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER);
1553	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1554	pVCpu->cpum.GstCtx.fExtrn = 0;
1555	}
1556
1557	/*
1558	* Notify PGM about the changes.
1559	*/
1560	if (fMaybeChangedMode)
1561	{
1562	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4,
1563	pVCpu->cpum.GstCtx.msrEFER, false /fForce/);
1564	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1565	}
1566
1567	if (fUpdateCr3)
1568	{
1569	int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3);
1570	if (rc == VINF_SUCCESS)
1571	{ /* likely */ }
1572	else
1573	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1574	}
1575	}
1576
1577	return VINF_SUCCESS;
1578	}
1579
1580
1581	/**
1582	* Interface for importing state on demand (used by IEM).
1583	*
1584	* @returns VBox status code.
1585	* @param pVCpu The cross context CPU structure.
1586	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1587	*/
1588	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1589	{
1590	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
1591	return nemHCLnxImportState(pVCpu, fWhat, &pVCpu->cpum.GstCtx, pVCpu->nem.s.pRun);
1592	}
1593
1594
1595	/**
1596	* Exports state to KVM.
1597	*/
1598	static int nemHCLnxExportState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, struct kvm_run *pRun)
1599	{
1600	uint64_t const fExtrn = ~pCtx->fExtrn & CPUMCTX_EXTRN_ALL;
1601	Assert((~fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL);
1602
1603	/*
1604	* Stuff that goes into kvm_run::s.regs.regs:
1605	*/
1606	if (fExtrn & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK))
1607	{
1608	if (fExtrn & CPUMCTX_EXTRN_RIP)
1609	pRun->s.regs.regs.rip = pCtx->rip;
1610	if (fExtrn & CPUMCTX_EXTRN_RFLAGS)
1611	pRun->s.regs.regs.rflags = pCtx->rflags.u;
1612
1613	if (fExtrn & CPUMCTX_EXTRN_RAX)
1614	pRun->s.regs.regs.rax = pCtx->rax;
1615	if (fExtrn & CPUMCTX_EXTRN_RCX)
1616	pRun->s.regs.regs.rcx = pCtx->rcx;
1617	if (fExtrn & CPUMCTX_EXTRN_RDX)
1618	pRun->s.regs.regs.rdx = pCtx->rdx;
1619	if (fExtrn & CPUMCTX_EXTRN_RBX)
1620	pRun->s.regs.regs.rbx = pCtx->rbx;
1621	if (fExtrn & CPUMCTX_EXTRN_RSP)
1622	pRun->s.regs.regs.rsp = pCtx->rsp;
1623	if (fExtrn & CPUMCTX_EXTRN_RBP)
1624	pRun->s.regs.regs.rbp = pCtx->rbp;
1625	if (fExtrn & CPUMCTX_EXTRN_RSI)
1626	pRun->s.regs.regs.rsi = pCtx->rsi;
1627	if (fExtrn & CPUMCTX_EXTRN_RDI)
1628	pRun->s.regs.regs.rdi = pCtx->rdi;
1629	if (fExtrn & CPUMCTX_EXTRN_R8_R15)
1630	{
1631	pRun->s.regs.regs.r8 = pCtx->r8;
1632	pRun->s.regs.regs.r9 = pCtx->r9;
1633	pRun->s.regs.regs.r10 = pCtx->r10;
1634	pRun->s.regs.regs.r11 = pCtx->r11;
1635	pRun->s.regs.regs.r12 = pCtx->r12;
1636	pRun->s.regs.regs.r13 = pCtx->r13;
1637	pRun->s.regs.regs.r14 = pCtx->r14;
1638	pRun->s.regs.regs.r15 = pCtx->r15;
1639	}
1640	pRun->kvm_dirty_regs \|= KVM_SYNC_X86_REGS;
1641	}
1642
1643	/*
1644	* Stuff that goes into kvm_run::s.regs.sregs:
1645	*
1646	* The APIC base register updating is a little suboptimal... But at least
1647	* VBox always has the right base register value, so it's one directional.
1648	*/
1649	uint64_t const uApicBase = APICGetBaseMsrNoCheck(pVCpu);
1650	if ( (fExtrn & ( CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_TABLE_MASK \| CPUMCTX_EXTRN_CR_MASK
1651	\| CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_APIC_TPR))
1652	\|\| uApicBase != pVCpu->nem.s.uKvmApicBase)
1653	{
1654	if ((pVCpu->nem.s.uKvmApicBase ^ uApicBase) & MSR_IA32_APICBASE_EN)
1655	Log(("NEM/%u: APICBASE_EN changed %#010RX64 -> %#010RX64\n", pVCpu->idCpu, pVCpu->nem.s.uKvmApicBase, uApicBase));
1656	pRun->s.regs.sregs.apic_base = uApicBase;
1657	pVCpu->nem.s.uKvmApicBase = uApicBase;
1658
1659	if (fExtrn & CPUMCTX_EXTRN_APIC_TPR)
1660	pRun->s.regs.sregs.cr8 = CPUMGetGuestCR8(pVCpu);
1661
1662	#define NEM_LNX_EXPORT_SEG(a_KvmSeg, a_CtxSeg) do { \
1663	(a_KvmSeg).base = (a_CtxSeg).u64Base; \
1664	(a_KvmSeg).limit = (a_CtxSeg).u32Limit; \
1665	(a_KvmSeg).selector = (a_CtxSeg).Sel; \
1666	(a_KvmSeg).type = (a_CtxSeg).Attr.n.u4Type; \
1667	(a_KvmSeg).s = (a_CtxSeg).Attr.n.u1DescType; \
1668	(a_KvmSeg).dpl = (a_CtxSeg).Attr.n.u2Dpl; \
1669	(a_KvmSeg).present = (a_CtxSeg).Attr.n.u1Present; \
1670	(a_KvmSeg).avl = (a_CtxSeg).Attr.n.u1Available; \
1671	(a_KvmSeg).l = (a_CtxSeg).Attr.n.u1Long; \
1672	(a_KvmSeg).db = (a_CtxSeg).Attr.n.u1DefBig; \
1673	(a_KvmSeg).g = (a_CtxSeg).Attr.n.u1Granularity; \
1674	(a_KvmSeg).unusable = (a_CtxSeg).Attr.n.u1Unusable; \
1675	(a_KvmSeg).padding = 0; \
1676	} while (0)
1677
1678	if (fExtrn & CPUMCTX_EXTRN_SREG_MASK)
1679	{
1680	if (fExtrn & CPUMCTX_EXTRN_ES)
1681	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.es, pCtx->es);
1682	if (fExtrn & CPUMCTX_EXTRN_CS)
1683	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.cs, pCtx->cs);
1684	if (fExtrn & CPUMCTX_EXTRN_SS)
1685	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ss, pCtx->ss);
1686	if (fExtrn & CPUMCTX_EXTRN_DS)
1687	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ds, pCtx->ds);
1688	if (fExtrn & CPUMCTX_EXTRN_FS)
1689	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.fs, pCtx->fs);
1690	if (fExtrn & CPUMCTX_EXTRN_GS)
1691	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.gs, pCtx->gs);
1692	}
1693	if (fExtrn & CPUMCTX_EXTRN_TABLE_MASK)
1694	{
1695	if (fExtrn & CPUMCTX_EXTRN_GDTR)
1696	{
1697	pRun->s.regs.sregs.gdt.base = pCtx->gdtr.pGdt;
1698	pRun->s.regs.sregs.gdt.limit = pCtx->gdtr.cbGdt;
1699	pRun->s.regs.sregs.gdt.padding[0] = 0;
1700	pRun->s.regs.sregs.gdt.padding[1] = 0;
1701	pRun->s.regs.sregs.gdt.padding[2] = 0;
1702	}
1703	if (fExtrn & CPUMCTX_EXTRN_IDTR)
1704	{
1705	pRun->s.regs.sregs.idt.base = pCtx->idtr.pIdt;
1706	pRun->s.regs.sregs.idt.limit = pCtx->idtr.cbIdt;
1707	pRun->s.regs.sregs.idt.padding[0] = 0;
1708	pRun->s.regs.sregs.idt.padding[1] = 0;
1709	pRun->s.regs.sregs.idt.padding[2] = 0;
1710	}
1711	if (fExtrn & CPUMCTX_EXTRN_LDTR)
1712	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ldt, pCtx->ldtr);
1713	if (fExtrn & CPUMCTX_EXTRN_TR)
1714	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.tr, pCtx->tr);
1715	}
1716	if (fExtrn & CPUMCTX_EXTRN_CR_MASK)
1717	{
1718	if (fExtrn & CPUMCTX_EXTRN_CR0)
1719	pRun->s.regs.sregs.cr0 = pCtx->cr0;
1720	if (fExtrn & CPUMCTX_EXTRN_CR2)
1721	pRun->s.regs.sregs.cr2 = pCtx->cr2;
1722	if (fExtrn & CPUMCTX_EXTRN_CR3)
1723	pRun->s.regs.sregs.cr3 = pCtx->cr3;
1724	if (fExtrn & CPUMCTX_EXTRN_CR4)
1725	pRun->s.regs.sregs.cr4 = pCtx->cr4;
1726	}
1727	if (fExtrn & CPUMCTX_EXTRN_EFER)
1728	pRun->s.regs.sregs.efer = pCtx->msrEFER;
1729
1730	RT_ZERO(pRun->s.regs.sregs.interrupt_bitmap); /* this is an alternative interrupt injection interface */
1731
1732	pRun->kvm_dirty_regs \|= KVM_SYNC_X86_SREGS;
1733	}
1734
1735	/*
1736	* Debug registers.
1737	*/
1738	if (fExtrn & CPUMCTX_EXTRN_DR_MASK)
1739	{
1740	struct kvm_debugregs DbgRegs = {{0}};
1741
1742	if ((fExtrn & CPUMCTX_EXTRN_DR_MASK) != CPUMCTX_EXTRN_DR_MASK)
1743	{
1744	/* Partial debug state, we must get DbgRegs first so we can merge: */
1745	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1746	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1747	}
1748
1749	if (fExtrn & CPUMCTX_EXTRN_DR0_DR3)
1750	{
1751	DbgRegs.db[0] = pCtx->dr[0];
1752	DbgRegs.db[1] = pCtx->dr[1];
1753	DbgRegs.db[2] = pCtx->dr[2];
1754	DbgRegs.db[3] = pCtx->dr[3];
1755	}
1756	if (fExtrn & CPUMCTX_EXTRN_DR6)
1757	DbgRegs.dr6 = pCtx->dr[6];
1758	if (fExtrn & CPUMCTX_EXTRN_DR7)
1759	DbgRegs.dr7 = pCtx->dr[7];
1760
1761	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_DEBUGREGS, &DbgRegs);
1762	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1763	}
1764
1765	/*
1766	* FPU, SSE, AVX, ++.
1767	*/
1768	if (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE \| CPUMCTX_EXTRN_XCRx))
1769	{
1770	if (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1771	{
1772	/** @todo could IEM just grab state partial control in some situations? */
1773	Assert( (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1774	== (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE)); /* no partial states */
1775
1776	AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1777	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XSAVE, &pCtx->XState);
1778	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1779	}
1780
1781	if (fExtrn & CPUMCTX_EXTRN_XCRx)
1782	{
1783	struct kvm_xcrs Xcrs =
1784	{ /.nr_xcrs = / 2,
1785	/.flags = / 0,
1786	/.xcrs= / {
1787	{ /.xcr =/ 0, /.reserved=/ 0, /.value=/ pCtx->aXcr[0] },
1788	{ /.xcr =/ 1, /.reserved=/ 0, /.value=/ pCtx->aXcr[1] },
1789	}
1790	};
1791
1792	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XCRS, &Xcrs);
1793	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1794	}
1795	}
1796
1797	/*
1798	* MSRs.
1799	*/
1800	if (fExtrn & ( CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS
1801	\| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
1802	{
1803	union
1804	{
1805	struct kvm_msrs Core;
1806	uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1807	} uBuf;
1808	uint32_t iMsr = 0;
1809	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1810
1811	#define ADD_MSR(a_Msr, a_uValue) do { \
1812	Assert(iMsr < 32); \
1813	uBuf.Core.entries[iMsr].index = (a_Msr); \
1814	uBuf.Core.entries[iMsr].reserved = 0; \
1815	uBuf.Core.entries[iMsr].data = (a_uValue); \
1816	iMsr += 1; \
1817	} while (0)
1818
1819	if (fExtrn & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1820	ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1821	if (fExtrn & CPUMCTX_EXTRN_SYSCALL_MSRS)
1822	{
1823	ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1824	ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1825	ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1826	ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1827	}
1828	if (fExtrn & CPUMCTX_EXTRN_SYSENTER_MSRS)
1829	{
1830	ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1831	ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1832	ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1833	}
1834	if (fExtrn & CPUMCTX_EXTRN_TSC_AUX)
1835	ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1836	if (fExtrn & CPUMCTX_EXTRN_OTHER_MSRS)
1837	{
1838	ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1839	/** @todo What do we _have_ to add here?
1840	* We also have: Mttr, MiscEnable, FeatureControl. /
1841	}
1842
1843	uBuf.Core.pad = 0;
1844	uBuf.Core.nmsrs = iMsr;
1845	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_MSRS, &uBuf);
1846	AssertMsgReturn(rc == (int)iMsr,
1847	("rc=%d iMsr=%d (->%#x) errno=%d\n",
1848	rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1849	VERR_NEM_IPE_3);
1850	}
1851
1852	/*
1853	* Interruptibility state.
1854	*
1855	* Note! This I/O control function sets most fields passed in, so when
1856	* raising an interrupt, NMI, SMI or exception, this must be done
1857	* by the code doing the rasing or we'll overwrite it here.
1858	*/
1859	if (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1860	{
1861	Assert( (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1862	== (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI));
1863
1864	struct kvm_vcpu_events KvmEvents = {0};
1865
1866	KvmEvents.flags = KVM_VCPUEVENT_VALID_SHADOW;
1867	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1868	{
1869	if (pRun->s.regs.regs.rip == EMGetInhibitInterruptsPC(pVCpu))
1870	KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS \| KVM_X86_SHADOW_INT_STI;
1871	else
1872	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1873	}
1874
1875	/* No flag - this is updated unconditionally. */
1876	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1877	KvmEvents.nmi.masked = 1;
1878
1879	if (TRPMHasTrap(pVCpu))
1880	{
1881	TRPMEVENT enmType = TRPM_32BIT_HACK;
1882	uint8_t bTrapNo = 0;
1883	TRPMQueryTrap(pVCpu, &bTrapNo, &enmType);
1884	Log(("nemHCLnxExportState: Pending trap: bTrapNo=%#x enmType=%d\n", bTrapNo, enmType));
1885	if ( enmType == TRPM_HARDWARE_INT
1886	\|\| enmType == TRPM_SOFTWARE_INT)
1887	{
1888	KvmEvents.interrupt.soft = enmType == TRPM_SOFTWARE_INT;
1889	KvmEvents.interrupt.nr = bTrapNo;
1890	KvmEvents.interrupt.injected = 1;
1891	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExportPendingInterrupt);
1892	TRPMResetTrap(pVCpu);
1893	}
1894	else
1895	AssertFailed();
1896	}
1897
1898	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
1899	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1900	}
1901
1902	/*
1903	* KVM now owns all the state.
1904	*/
1905	pCtx->fExtrn = CPUMCTX_EXTRN_KEEPER_NEM \| CPUMCTX_EXTRN_ALL;
1906
1907	RT_NOREF(pVM);
1908	return VINF_SUCCESS;
1909	}
1910
1911
1912	/**
1913	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
1914	*
1915	* @returns VBox status code.
1916	* @param pVCpu The cross context CPU structure.
1917	* @param pcTicks Where to return the CPU tick count.
1918	* @param puAux Where to return the TSC_AUX register value.
1919	*/
1920	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
1921	{
1922	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
1923	// KVM_GET_CLOCK?
1924	RT_NOREF(pVCpu, pcTicks, puAux);
1925	return VINF_SUCCESS;
1926	}
1927
1928
1929	/**
1930	* Resumes CPU clock (TSC) on all virtual CPUs.
1931	*
1932	* This is called by TM when the VM is started, restored, resumed or similar.
1933	*
1934	* @returns VBox status code.
1935	* @param pVM The cross context VM structure.
1936	* @param pVCpu The cross context CPU structure of the calling EMT.
1937	* @param uPausedTscValue The TSC value at the time of pausing.
1938	*/
1939	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
1940	{
1941	// KVM_SET_CLOCK?
1942	RT_NOREF(pVM, pVCpu, uPausedTscValue);
1943	return VINF_SUCCESS;
1944	}
1945
1946
1947	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
1948	{
1949	RT_NOREF(pVM);
1950	return NEM_FEAT_F_NESTED_PAGING
1951	\| NEM_FEAT_F_FULL_GST_EXEC
1952	\| NEM_FEAT_F_XSAVE_XRSTOR;
1953	}
1954
1955
1956
1957	/*********************************************************************************************************************************
1958	* Execution *
1959	*********************************************************************************************************************************/
1960
1961
1962	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
1963	{
1964	/*
1965	* Only execute when the A20 gate is enabled as I cannot immediately
1966	* spot any A20 support in KVM.
1967	*/
1968	RT_NOREF(pVM);
1969	Assert(VM_IS_NEM_ENABLED(pVM));
1970	return PGMPhysIsA20Enabled(pVCpu);
1971	}
1972
1973
1974	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
1975	{
1976	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
1977	return false;
1978	}
1979
1980
1981	/**
1982	* Forced flag notification call from VMEmt.cpp.
1983	*
1984	* This is only called when pVCpu is in the VMCPUSTATE_STARTED_EXEC_NEM state.
1985	*
1986	* @param pVM The cross context VM structure.
1987	* @param pVCpu The cross context virtual CPU structure of the CPU
1988	* to be notified.
1989	* @param fFlags Notification flags, VMNOTIFYFF_FLAGS_XXX.
1990	*/
1991	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
1992	{
1993	int rc = RTThreadPoke(pVCpu->hThread);
1994	LogFlow(("nemR3NativeNotifyFF: #%u -> %Rrc\n", pVCpu->idCpu, rc));
1995	AssertRC(rc);
1996	RT_NOREF(pVM, fFlags);
1997	}
1998
1999
2000	/**
2001	* Deals with pending interrupt FFs prior to executing guest code.
2002	*/
2003	static VBOXSTRICTRC nemHCLnxHandleInterruptFF(PVM pVM, PVMCPU pVCpu, struct kvm_run *pRun)
2004	{
2005	RT_NOREF_PV(pVM);
2006
2007	/*
2008	* Do not doing anything if TRPM has something pending already as we can
2009	* only inject one event per KVM_RUN call. This can only happend if we
2010	* can directly from the loop in EM, so the inhibit bits must be internal.
2011	*/
2012	if (!TRPMHasTrap(pVCpu))
2013	{ /* semi likely */ }
2014	else
2015	{
2016	Assert(!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI)));
2017	Log8(("nemHCLnxHandleInterruptFF: TRPM has an pending event already\n"));
2018	return VINF_SUCCESS;
2019	}
2020
2021	/*
2022	* First update APIC. We ASSUME this won't need TPR/CR8.
2023	*/
2024	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2025	{
2026	APICUpdatePendingInterrupts(pVCpu);
2027	if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
2028	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2029	return VINF_SUCCESS;
2030	}
2031
2032	/*
2033	* We don't currently implement SMIs.
2034	*/
2035	AssertReturn(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI), VERR_NEM_IPE_0);
2036
2037	/*
2038	* In KVM the CPUMCTX_EXTRN_INHIBIT_INT and CPUMCTX_EXTRN_INHIBIT_NMI states
2039	* are tied together with interrupt and NMI delivery, so we must get and
2040	* synchronize these all in one go and set both CPUMCTX_EXTRN_INHIBIT_XXX flags.
2041	* If we don't we may lose the interrupt/NMI we marked pending here when the
2042	* state is exported again before execution.
2043	*/
2044	struct kvm_vcpu_events KvmEvents = {0};
2045	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
2046	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2047
2048	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP))
2049	pRun->s.regs.regs.rip = pVCpu->cpum.GstCtx.rip;
2050
2051	KvmEvents.flags \|= KVM_VCPUEVENT_VALID_SHADOW;
2052	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_INT))
2053	{
2054	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2055	KvmEvents.interrupt.shadow = 0;
2056	else if (EMGetInhibitInterruptsPC(pVCpu) == pRun->s.regs.regs.rip)
2057	KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS \| KVM_X86_SHADOW_INT_STI;
2058	else
2059	{
2060	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2061	KvmEvents.interrupt.shadow = 0;
2062	}
2063	}
2064	else if (KvmEvents.interrupt.shadow)
2065	EMSetInhibitInterruptsPC(pVCpu, pRun->s.regs.regs.rip);
2066	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2067	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2068
2069	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_NMI))
2070	KvmEvents.nmi.masked = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS) ? 1 : 0;
2071	else if (KvmEvents.nmi.masked)
2072	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2073	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2074	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2075
2076	/* KVM will own the INT + NMI inhibit state soon: */
2077	pVCpu->cpum.GstCtx.fExtrn = (pVCpu->cpum.GstCtx.fExtrn & ~CPUMCTX_EXTRN_KEEPER_MASK)
2078	\| CPUMCTX_EXTRN_KEEPER_NEM \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI;
2079
2080	/*
2081	* NMI? Try deliver it first.
2082	*/
2083	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))
2084	{
2085	#if 0
2086	int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_NMI, 0UL);
2087	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2088	#else
2089	KvmEvents.flags \|= KVM_VCPUEVENT_VALID_NMI_PENDING;
2090	KvmEvents.nmi.pending = 1;
2091	#endif
2092	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2093	Log8(("Queuing NMI on %u\n", pVCpu->idCpu));
2094	}
2095
2096	/*
2097	* APIC or PIC interrupt?
2098	*/
2099	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
2100	{
2101	if (pRun->s.regs.regs.rflags & X86_EFL_IF)
2102	{
2103	if (KvmEvents.interrupt.shadow == 0)
2104	{
2105	/*
2106	* If CR8 is in KVM, update the VBox copy so PDMGetInterrupt will
2107	* work correctly.
2108	*/
2109	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_APIC_TPR)
2110	APICSetTpr(pVCpu, (uint8_t)pRun->cr8 << 4);
2111
2112	uint8_t bInterrupt;
2113	int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
2114	if (RT_SUCCESS(rc))
2115	{
2116	Assert(KvmEvents.interrupt.injected == false);
2117	#if 0
2118	int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_INTERRUPT, (unsigned long)bInterrupt);
2119	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2120	#else
2121	KvmEvents.interrupt.nr = bInterrupt;
2122	KvmEvents.interrupt.soft = false;
2123	KvmEvents.interrupt.injected = true;
2124	#endif
2125	Log8(("Queuing interrupt %#x on %u: %04x:%08RX64 efl=%#x\n", bInterrupt, pVCpu->idCpu,
2126	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eflags));
2127	}
2128	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR) /** @todo this isn't extremely efficient if we get a lot of exits... */
2129	Log8(("VERR_APIC_INTR_MASKED_BY_TPR\n")); /* We'll get a TRP exit - no interrupt window needed. */
2130	else
2131	Log8(("PDMGetInterrupt failed -> %Rrc\n", rc));
2132	}
2133	else
2134	{
2135	pRun->request_interrupt_window = 1;
2136	Log8(("Interrupt window pending on %u (#2)\n", pVCpu->idCpu));
2137	}
2138	}
2139	else
2140	{
2141	pRun->request_interrupt_window = 1;
2142	Log8(("Interrupt window pending on %u (#1)\n", pVCpu->idCpu));
2143	}
2144	}
2145
2146	/*
2147	* Now, update the state.
2148	*/
2149	/** @todo skip when possible... */
2150	rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
2151	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2152
2153	return VINF_SUCCESS;
2154	}
2155
2156
2157	/**
2158	* Handles KVM_EXIT_INTERNAL_ERROR.
2159	*/
2160	static VBOXSTRICTRC nemR3LnxHandleInternalError(PVMCPU pVCpu, struct kvm_run *pRun)
2161	{
2162	Log(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%d) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror,
2163	pRun->internal.suberror, pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2164
2165	/*
2166	* Deal with each suberror, returning if we don't want IEM to handle it.
2167	*/
2168	switch (pRun->internal.suberror)
2169	{
2170	case KVM_INTERNAL_ERROR_EMULATION:
2171	{
2172	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_EMULATION),
2173	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2174	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorEmulation);
2175	break;
2176	}
2177
2178	case KVM_INTERNAL_ERROR_SIMUL_EX:
2179	case KVM_INTERNAL_ERROR_DELIVERY_EV:
2180	case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON:
2181	default:
2182	{
2183	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_FATAL),
2184	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2185	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorFatal);
2186	const char *pszName;
2187	switch (pRun->internal.suberror)
2188	{
2189	case KVM_INTERNAL_ERROR_EMULATION: pszName = "KVM_INTERNAL_ERROR_EMULATION"; break;
2190	case KVM_INTERNAL_ERROR_SIMUL_EX: pszName = "KVM_INTERNAL_ERROR_SIMUL_EX"; break;
2191	case KVM_INTERNAL_ERROR_DELIVERY_EV: pszName = "KVM_INTERNAL_ERROR_DELIVERY_EV"; break;
2192	case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON: pszName = "KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON"; break;
2193	default: pszName = "unknown"; break;
2194	}
2195	LogRel(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%s) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror, pszName,
2196	pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2197	return VERR_NEM_IPE_0;
2198	}
2199	}
2200
2201	/*
2202	* Execute instruction in IEM and try get on with it.
2203	*/
2204	Log2(("nemR3LnxHandleInternalError: Executing instruction at %04x:%08RX64 in IEM\n",
2205	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip));
2206	VBOXSTRICTRC rcStrict = nemHCLnxImportState(pVCpu,
2207	IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_INHIBIT_INT
2208	\| CPUMCTX_EXTRN_INHIBIT_NMI,
2209	&pVCpu->cpum.GstCtx, pRun);
2210	if (RT_SUCCESS(rcStrict))
2211	rcStrict = IEMExecOne(pVCpu);
2212	return rcStrict;
2213	}
2214
2215
2216	/**
2217	* Handles KVM_EXIT_IO.
2218	*/
2219	static VBOXSTRICTRC nemHCLnxHandleExitIo(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2220	{
2221	/*
2222	* Input validation.
2223	*/
2224	Assert(pRun->io.count > 0);
2225	Assert(pRun->io.size == 1 \|\| pRun->io.size == 2 \|\| pRun->io.size == 4);
2226	Assert(pRun->io.direction == KVM_EXIT_IO_IN \|\| pRun->io.direction == KVM_EXIT_IO_OUT);
2227	Assert(pRun->io.data_offset < pVM->nem.s.cbVCpuMmap);
2228	Assert(pRun->io.data_offset + pRun->io.size * pRun->io.count <= pVM->nem.s.cbVCpuMmap);
2229
2230	/*
2231	* We cannot easily act on the exit history here, because the I/O port
2232	* exit is stateful and the instruction will be completed in the next
2233	* KVM_RUN call. There seems no way to avoid this.
2234	*/
2235	EMHistoryAddExit(pVCpu,
2236	pRun->io.count == 1
2237	? ( pRun->io.direction == KVM_EXIT_IO_IN
2238	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)
2239	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE))
2240	: ( pRun->io.direction == KVM_EXIT_IO_IN
2241	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)
2242	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)),
2243	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2244
2245	/*
2246	* Do the requested job.
2247	*/
2248	VBOXSTRICTRC rcStrict;
2249	RTPTRUNION uPtrData;
2250	uPtrData.pu8 = (uint8_t *)pRun + pRun->io.data_offset;
2251	if (pRun->io.count == 1)
2252	{
2253	if (pRun->io.direction == KVM_EXIT_IO_IN)
2254	{
2255	uint32_t uValue = 0;
2256	rcStrict = IOMIOPortRead(pVM, pVCpu, pRun->io.port, &uValue, pRun->io.size);
2257	Log4(("IOExit/%u: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n",
2258	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2259	pRun->io.port, pRun->io.size, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
2260	if (IOM_SUCCESS(rcStrict))
2261	{
2262	if (pRun->io.size == 4)
2263	*uPtrData.pu32 = uValue;
2264	else if (pRun->io.size == 2)
2265	*uPtrData.pu16 = (uint16_t)uValue;
2266	else
2267	*uPtrData.pu8 = (uint8_t)uValue;
2268	}
2269	}
2270	else
2271	{
2272	uint32_t const uValue = pRun->io.size == 4 ? *uPtrData.pu32
2273	: pRun->io.size == 2 ? *uPtrData.pu16
2274	: *uPtrData.pu8;
2275	rcStrict = IOMIOPortWrite(pVM, pVCpu, pRun->io.port, uValue, pRun->io.size);
2276	Log4(("IOExit/%u: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
2277	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2278	pRun->io.port, uValue, pRun->io.size, VBOXSTRICTRC_VAL(rcStrict) ));
2279	}
2280	}
2281	else
2282	{
2283	uint32_t cTransfers = pRun->io.count;
2284	if (pRun->io.direction == KVM_EXIT_IO_IN)
2285	{
2286	rcStrict = IOMIOPortReadString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2287	Log4(("IOExit/%u: %04x:%08RX64: REP INS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2288	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2289	pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2290	}
2291	else
2292	{
2293	rcStrict = IOMIOPortWriteString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2294	Log4(("IOExit/%u: %04x:%08RX64: REP OUTS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2295	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2296	pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2297	}
2298	Assert(cTransfers == 0);
2299	}
2300	return rcStrict;
2301	}
2302
2303
2304	/**
2305	* Handles KVM_EXIT_MMIO.
2306	*/
2307	static VBOXSTRICTRC nemHCLnxHandleExitMmio(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2308	{
2309	/*
2310	* Input validation.
2311	*/
2312	Assert(pRun->mmio.len <= sizeof(pRun->mmio.data));
2313	Assert(pRun->mmio.is_write <= 1);
2314
2315	/*
2316	* We cannot easily act on the exit history here, because the MMIO port
2317	* exit is stateful and the instruction will be completed in the next
2318	* KVM_RUN call. There seems no way to circumvent this.
2319	*/
2320	EMHistoryAddExit(pVCpu,
2321	pRun->mmio.is_write
2322	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
2323	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
2324	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2325
2326	/*
2327	* Do the requested job.
2328	*/
2329	VBOXSTRICTRC rcStrict;
2330	if (pRun->mmio.is_write)
2331	{
2332	rcStrict = PGMPhysWrite(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2333	Log4(("MmioExit/%u: %04x:%08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
2334	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2335	pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2336	}
2337	else
2338	{
2339	rcStrict = PGMPhysRead(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2340	Log4(("MmioExit/%u: %04x:%08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
2341	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2342	pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2343	}
2344	return rcStrict;
2345	}
2346
2347
2348	/**
2349	* Handles KVM_EXIT_RDMSR
2350	*/
2351	static VBOXSTRICTRC nemHCLnxHandleExitRdMsr(PVMCPUCC pVCpu, struct kvm_run *pRun)
2352	{
2353	/*
2354	* Input validation.
2355	*/
2356	Assert( pRun->msr.reason == KVM_MSR_EXIT_REASON_INVAL
2357	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_UNKNOWN
2358	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
2359
2360	/*
2361	* We cannot easily act on the exit history here, because the MSR exit is
2362	* stateful and the instruction will be completed in the next KVM_RUN call.
2363	* There seems no way to circumvent this.
2364	*/
2365	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ),
2366	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2367
2368	/*
2369	* Do the requested job.
2370	*/
2371	uint64_t uValue = 0;
2372	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRun->msr.index, &uValue);
2373	pRun->msr.data = uValue;
2374	if (rcStrict != VERR_CPUM_RAISE_GP_0)
2375	{
2376	Log3(("MsrRead/%u: %04x:%08RX64: msr=%#010x (reason=%#x) -> %#RX64 rcStrict=%Rrc\n", pVCpu->idCpu,
2377	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.reason, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
2378	pRun->msr.error = 0;
2379	}
2380	else
2381	{
2382	Log3(("MsrRead/%u: %04x:%08RX64: msr=%#010x (reason%#x)-> %#RX64 rcStrict=#GP!\n", pVCpu->idCpu,
2383	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.reason, uValue));
2384	pRun->msr.error = 1;
2385	rcStrict = VINF_SUCCESS;
2386	}
2387	return rcStrict;
2388	}
2389
2390
2391	/**
2392	* Handles KVM_EXIT_WRMSR
2393	*/
2394	static VBOXSTRICTRC nemHCLnxHandleExitWrMsr(PVMCPUCC pVCpu, struct kvm_run *pRun)
2395	{
2396	/*
2397	* Input validation.
2398	*/
2399	Assert( pRun->msr.reason == KVM_MSR_EXIT_REASON_INVAL
2400	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_UNKNOWN
2401	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
2402
2403	/*
2404	* We cannot easily act on the exit history here, because the MSR exit is
2405	* stateful and the instruction will be completed in the next KVM_RUN call.
2406	* There seems no way to circumvent this.
2407	*/
2408	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
2409	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2410
2411	/*
2412	* Do the requested job.
2413	*/
2414	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRun->msr.index, pRun->msr.data);
2415	if (rcStrict != VERR_CPUM_RAISE_GP_0)
2416	{
2417	Log3(("MsrWrite/%u: %04x:%08RX64: msr=%#010x := %#RX64 (reason=%#x) -> rcStrict=%Rrc\n", pVCpu->idCpu,
2418	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.data, pRun->msr.reason, VBOXSTRICTRC_VAL(rcStrict) ));
2419	pRun->msr.error = 0;
2420	}
2421	else
2422	{
2423	Log3(("MsrWrite/%u: %04x:%08RX64: msr=%#010x := %#RX64 (reason%#x)-> rcStrict=#GP!\n", pVCpu->idCpu,
2424	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.data, pRun->msr.reason));
2425	pRun->msr.error = 1;
2426	rcStrict = VINF_SUCCESS;
2427	}
2428	return rcStrict;
2429	}
2430
2431
2432
2433	static VBOXSTRICTRC nemHCLnxHandleExit(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run pRun, bool pfStatefulExit)
2434	{
2435	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTotal);
2436	switch (pRun->exit_reason)
2437	{
2438	case KVM_EXIT_EXCEPTION:
2439	AssertFailed();
2440	break;
2441
2442	case KVM_EXIT_IO:
2443	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIo);
2444	*pfStatefulExit = true;
2445	return nemHCLnxHandleExitIo(pVM, pVCpu, pRun);
2446
2447	case KVM_EXIT_MMIO:
2448	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMmio);
2449	*pfStatefulExit = true;
2450	return nemHCLnxHandleExitMmio(pVM, pVCpu, pRun);
2451
2452	case KVM_EXIT_IRQ_WINDOW_OPEN:
2453	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW),
2454	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2455	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIrqWindowOpen);
2456	Log5(("IrqWinOpen/%u: %d\n", pVCpu->idCpu, pRun->request_interrupt_window));
2457	pRun->request_interrupt_window = 0;
2458	return VINF_SUCCESS;
2459
2460	case KVM_EXIT_SET_TPR:
2461	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitSetTpr);
2462	AssertFailed();
2463	break;
2464
2465	case KVM_EXIT_TPR_ACCESS:
2466	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTprAccess);
2467	AssertFailed();
2468	break;
2469
2470	case KVM_EXIT_X86_RDMSR:
2471	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitRdMsr);
2472	*pfStatefulExit = true;
2473	return nemHCLnxHandleExitRdMsr(pVCpu, pRun);
2474
2475	case KVM_EXIT_X86_WRMSR:
2476	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitWrMsr);
2477	*pfStatefulExit = true;
2478	return nemHCLnxHandleExitWrMsr(pVCpu, pRun);
2479
2480	case KVM_EXIT_HLT:
2481	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT),
2482	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2483	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
2484	Log5(("Halt/%u\n", pVCpu->idCpu));
2485	return VINF_EM_HALT;
2486
2487	case KVM_EXIT_INTR: /* EINTR */
2488	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERRUPTED),
2489	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2490	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIntr);
2491	Log5(("Intr/%u\n", pVCpu->idCpu));
2492	return VINF_SUCCESS;
2493
2494	case KVM_EXIT_HYPERCALL:
2495	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHypercall);
2496	AssertFailed();
2497	break;
2498
2499	case KVM_EXIT_DEBUG:
2500	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitDebug);
2501	AssertFailed();
2502	break;
2503
2504	case KVM_EXIT_SYSTEM_EVENT:
2505	AssertFailed();
2506	break;
2507	case KVM_EXIT_IOAPIC_EOI:
2508	AssertFailed();
2509	break;
2510	case KVM_EXIT_HYPERV:
2511	AssertFailed();
2512	break;
2513
2514	case KVM_EXIT_DIRTY_RING_FULL:
2515	AssertFailed();
2516	break;
2517	case KVM_EXIT_AP_RESET_HOLD:
2518	AssertFailed();
2519	break;
2520	case KVM_EXIT_X86_BUS_LOCK:
2521	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitBusLock);
2522	AssertFailed();
2523	break;
2524
2525
2526	case KVM_EXIT_SHUTDOWN:
2527	AssertFailed();
2528	break;
2529
2530	case KVM_EXIT_FAIL_ENTRY:
2531	LogRel(("NEM: KVM_EXIT_FAIL_ENTRY! hardware_entry_failure_reason=%#x cpu=%#x\n",
2532	pRun->fail_entry.hardware_entry_failure_reason, pRun->fail_entry.cpu));
2533	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_FAILED_ENTRY),
2534	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2535	return VERR_NEM_IPE_1;
2536
2537	case KVM_EXIT_INTERNAL_ERROR:
2538	/* we're counting sub-reasons inside the function. */
2539	return nemR3LnxHandleInternalError(pVCpu, pRun);
2540
2541	/*
2542	* Foreign and unknowns.
2543	*/
2544	case KVM_EXIT_NMI:
2545	AssertLogRelMsgFailedReturn(("KVM_EXIT_NMI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2546	case KVM_EXIT_EPR:
2547	AssertLogRelMsgFailedReturn(("KVM_EXIT_EPR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2548	case KVM_EXIT_WATCHDOG:
2549	AssertLogRelMsgFailedReturn(("KVM_EXIT_WATCHDOG on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2550	case KVM_EXIT_ARM_NISV:
2551	AssertLogRelMsgFailedReturn(("KVM_EXIT_ARM_NISV on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2552	case KVM_EXIT_S390_STSI:
2553	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_STSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2554	case KVM_EXIT_S390_TSCH:
2555	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_TSCH on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2556	case KVM_EXIT_OSI:
2557	AssertLogRelMsgFailedReturn(("KVM_EXIT_OSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2558	case KVM_EXIT_PAPR_HCALL:
2559	AssertLogRelMsgFailedReturn(("KVM_EXIT_PAPR_HCALL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2560	case KVM_EXIT_S390_UCONTROL:
2561	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_UCONTROL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2562	case KVM_EXIT_DCR:
2563	AssertLogRelMsgFailedReturn(("KVM_EXIT_DCR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2564	case KVM_EXIT_S390_SIEIC:
2565	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_SIEIC on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2566	case KVM_EXIT_S390_RESET:
2567	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_RESET on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2568	case KVM_EXIT_UNKNOWN:
2569	AssertLogRelMsgFailedReturn(("KVM_EXIT_UNKNOWN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2570	case KVM_EXIT_XEN:
2571	AssertLogRelMsgFailedReturn(("KVM_EXIT_XEN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2572	default:
2573	AssertLogRelMsgFailedReturn(("Unknown exit reason %u on VCpu #%u at %04x:%RX64!\n", pRun->exit_reason, pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2574	}
2575
2576	RT_NOREF(pVM, pVCpu, pRun);
2577	return VERR_NOT_IMPLEMENTED;
2578	}
2579
2580
2581	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2582	{
2583	/*
2584	* Try switch to NEM runloop state.
2585	*/
2586	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2587	{ /* likely */ }
2588	else
2589	{
2590	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2591	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2592	return VINF_SUCCESS;
2593	}
2594
2595	/*
2596	* The run loop.
2597	*/
2598	struct kvm_run * const pRun = pVCpu->nem.s.pRun;
2599	const bool fSingleStepping = DBGFIsStepping(pVCpu);
2600	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2601	bool fStatefulExit = false; /* For MMIO and IO exits. */
2602	for (unsigned iLoop = 0;; iLoop++)
2603	{
2604	/*
2605	* Pending interrupts or such? Need to check and deal with this prior
2606	* to the state syncing.
2607	*/
2608	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC
2609	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2610	{
2611	/* Try inject interrupt. */
2612	rcStrict = nemHCLnxHandleInterruptFF(pVM, pVCpu, pRun);
2613	if (rcStrict == VINF_SUCCESS)
2614	{ /* likely */ }
2615	else
2616	{
2617	LogFlow(("NEM/%u: breaking: nemHCLnxHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2618	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2619	break;
2620	}
2621	}
2622
2623	/*
2624	* Do not execute in KVM if the A20 isn't enabled.
2625	*/
2626	if (PGMPhysIsA20Enabled(pVCpu))
2627	{ /* likely */ }
2628	else
2629	{
2630	rcStrict = VINF_EM_RESCHEDULE_REM;
2631	LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));
2632	break;
2633	}
2634
2635	/*
2636	* Ensure KVM has the whole state.
2637	*/
2638	if ((pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL)
2639	{
2640	int rc2 = nemHCLnxExportState(pVM, pVCpu, &pVCpu->cpum.GstCtx, pRun);
2641	AssertRCReturn(rc2, rc2);
2642	}
2643
2644	/*
2645	* Poll timers and run for a bit.
2646	*
2647	* With the VID approach (ring-0 or ring-3) we can specify a timeout here,
2648	* so we take the time of the next timer event and uses that as a deadline.
2649	* The rounding heuristics are "tuned" so that rhel5 (1K timer) will boot fine.
2650	*/
2651	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2652	* the whole polling job when timers have changed... */
2653	uint64_t offDeltaIgnored;
2654	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2655	if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2656	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2657	{
2658	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2659	{
2660	LogFlow(("NEM/%u: Entry @ %04x:%08RX64 IF=%d EFL=%#RX64 SS:RSP=%04x:%08RX64 cr0=%RX64\n",
2661	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2662	!!(pRun->s.regs.regs.rflags & X86_EFL_IF), pRun->s.regs.regs.rflags,
2663	pRun->s.regs.sregs.ss.selector, pRun->s.regs.regs.rsp, pRun->s.regs.sregs.cr0));
2664	TMNotifyStartOfExecution(pVM, pVCpu);
2665
2666	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);
2667
2668	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2669	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2670
2671	#ifdef LOG_ENABLED
2672	if (LogIsFlowEnabled())
2673	{
2674	struct kvm_mp_state MpState = {UINT32_MAX};
2675	ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MP_STATE, &MpState);
2676	LogFlow(("NEM/%u: Exit @ %04x:%08RX64 IF=%d EFL=%#RX64 CR8=%#x Reason=%#x IrqReady=%d Flags=%#x %#lx\n", pVCpu->idCpu,
2677	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->if_flag,
2678	pRun->s.regs.regs.rflags, pRun->s.regs.sregs.cr8, pRun->exit_reason,
2679	pRun->ready_for_interrupt_injection, pRun->flags, MpState.mp_state));
2680	}
2681	#endif
2682	fStatefulExit = false;
2683	if (RT_LIKELY(rcLnx == 0 \|\| errno == EINTR))
2684	{
2685	/*
2686	* Deal with the exit.
2687	*/
2688	rcStrict = nemHCLnxHandleExit(pVM, pVCpu, pRun, &fStatefulExit);
2689	if (rcStrict == VINF_SUCCESS)
2690	{ /* hopefully likely */ }
2691	else
2692	{
2693	LogFlow(("NEM/%u: breaking: nemHCLnxHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2694	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2695	break;
2696	}
2697	}
2698	else
2699	{
2700	int rc2 = RTErrConvertFromErrno(errno);
2701	AssertLogRelMsgFailedReturn(("KVM_RUN failed: rcLnx=%d errno=%u rc=%Rrc\n", rcLnx, errno, rc2), rc2);
2702	}
2703
2704	/*
2705	* If no relevant FFs are pending, loop.
2706	*/
2707	if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2708	&& !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2709	{ /* likely */ }
2710	else
2711	{
2712
2713	/** @todo Try handle pending flags, not just return to EM loops. Take care
2714	* not to set important RCs here unless we've handled an exit. */
2715	LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",
2716	pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));
2717	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2718	break;
2719	}
2720	}
2721	else
2722	{
2723	LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2724	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2725	break;
2726	}
2727	}
2728	else
2729	{
2730	LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2731	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2732	break;
2733	}
2734	} /* the run loop */
2735
2736
2737	/*
2738	* If the last exit was stateful, commit the state we provided before
2739	* returning to the EM loop so we have a consistent state and can safely
2740	* be rescheduled and whatnot. This may require us to make multiple runs
2741	* for larger MMIO and I/O operations. Sigh^3.
2742	*
2743	* Note! There is no 'ing way to reset the kernel side completion callback
2744	* for these stateful i/o exits. Very annoying interface.
2745	*/
2746	/** @todo check how this works with string I/O and string MMIO. */
2747	if (fStatefulExit && RT_SUCCESS(rcStrict))
2748	{
2749	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn);
2750	uint32_t const uOrgExit = pRun->exit_reason;
2751	for (uint32_t i = 0; ; i++)
2752	{
2753	pRun->immediate_exit = 1;
2754	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);
2755	Log(("NEM/%u: Flushed stateful exit -> %d/%d exit_reason=%d\n", pVCpu->idCpu, rcLnx, errno, pRun->exit_reason));
2756	if (rcLnx == -1 && errno == EINTR)
2757	{
2758	switch (i)
2759	{
2760	case 0: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn1Loop); break;
2761	case 1: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn2Loops); break;
2762	case 2: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn3Loops); break;
2763	default: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn4PlusLoops); break;
2764	}
2765	break;
2766	}
2767	AssertLogRelMsgBreakStmt(rcLnx == 0 && pRun->exit_reason == uOrgExit,
2768	("rcLnx=%d errno=%d exit_reason=%d uOrgExit=%d\n", rcLnx, errno, pRun->exit_reason, uOrgExit),
2769	rcStrict = VERR_NEM_IPE_6);
2770	VBOXSTRICTRC rcStrict2 = nemHCLnxHandleExit(pVM, pVCpu, pRun, &fStatefulExit);
2771	if (rcStrict2 == VINF_SUCCESS \|\| rcStrict2 == rcStrict)
2772	{ /* likely */ }
2773	else if (RT_FAILURE(rcStrict2))
2774	{
2775	rcStrict = rcStrict2;
2776	break;
2777	}
2778	else
2779	{
2780	AssertLogRelMsgBreakStmt(rcStrict == VINF_SUCCESS,
2781	("rcStrict=%Rrc rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict), VBOXSTRICTRC_VAL(rcStrict2)),
2782	rcStrict = VERR_NEM_IPE_7);
2783	rcStrict = rcStrict2;
2784	}
2785	}
2786	pRun->immediate_exit = 0;
2787	}
2788
2789	/*
2790	* If the CPU is running, make sure to stop it before we try sync back the
2791	* state and return to EM. We don't sync back the whole state if we can help it.
2792	*/
2793	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2794	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2795
2796	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL)
2797	{
2798	/* Try anticipate what we might need. */
2799	uint64_t fImport = CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI /* Required for processing APIC,PIC,NMI & SMI FFs. */
2800	\| IEM_CPUMCTX_EXTRN_MUST_MASK /?/;
2801	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2802	\|\| RT_FAILURE(rcStrict))
2803	fImport = CPUMCTX_EXTRN_ALL;
2804	# ifdef IN_RING0 /* Ring-3 I/O port access optimizations: */
2805	else if ( rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
2806	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
2807	fImport = CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS;
2808	else if (rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
2809	fImport = CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS;
2810	# endif
2811	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_INTERRUPT_APIC
2812	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2813	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2814
2815	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2816	{
2817	int rc2 = nemHCLnxImportState(pVCpu, fImport, &pVCpu->cpum.GstCtx, pRun);
2818	if (RT_SUCCESS(rc2))
2819	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2820	else if (RT_SUCCESS(rcStrict))
2821	rcStrict = rc2;
2822	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2823	pVCpu->cpum.GstCtx.fExtrn = 0;
2824	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2825	}
2826	else
2827	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2828	}
2829	else
2830	{
2831	pVCpu->cpum.GstCtx.fExtrn = 0;
2832	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2833	}
2834
2835	LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
2836	pVCpu->cpum.GstCtx.rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2837	return rcStrict;
2838	}
2839
2840
2841	/** @page pg_nem_linux NEM/linux - Native Execution Manager, Linux.
2842	*
2843	* This is using KVM.
2844	*
2845	*/
2846

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp@ 93115

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