NEMR3Native-darwin-armv8.cpp@ 100725

Last change on this file since 100725 was 100725, checked in by vboxsync, 16 months ago
VMM/ARM: Add some more system registers to the vCPU state, bugref:10387, bugref:10390
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 81.7 KB

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1	/* $Id: NEMR3Native-darwin-armv8.cpp 100725 2023-07-28 09:48:52Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4	*
5	* Log group 2: Exit logging.
6	* Log group 3: Log context on exit.
7	* Log group 5: Ring-3 memory management
8	*/
9
10	/*
11	* Copyright (C) 2023 Oracle and/or its affiliates.
12	*
13	* This file is part of VirtualBox base platform packages, as
14	* available from https://www.virtualbox.org.
15	*
16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License
18	* as published by the Free Software Foundation, in version 3 of the
19	* License.
20	*
21	* This program is distributed in the hope that it will be useful, but
22	* WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24	* General Public License for more details.
25	*
26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, see <https://www.gnu.org/licenses>.
28	*
29	* SPDX-License-Identifier: GPL-3.0-only
30	*/
31
32
33	/*********************************************************************************************************************************
34	* Header Files *
35	*********************************************************************************************************************************/
36	#define LOG_GROUP LOG_GROUP_NEM
37	#define VMCPU_INCL_CPUM_GST_CTX
38	#define CPUM_WITH_NONCONST_HOST_FEATURES /* required for initializing parts of the g_CpumHostFeatures structure here. */
39	#include <VBox/vmm/nem.h>
40	#include <VBox/vmm/iem.h>
41	#include <VBox/vmm/em.h>
42	#include <VBox/vmm/gic.h>
43	#include <VBox/vmm/pdm.h>
44	#include <VBox/vmm/dbgftrace.h>
45	#include <VBox/vmm/gcm.h>
46	#include "NEMInternal.h"
47	#include <VBox/vmm/vmcc.h>
48	#include <VBox/vmm/vmm.h>
49	#include "dtrace/VBoxVMM.h"
50
51	#include <iprt/armv8.h>
52	#include <iprt/asm.h>
53	#include <iprt/asm-arm.h>
54	#include <iprt/asm-math.h>
55	#include <iprt/ldr.h>
56	#include <iprt/mem.h>
57	#include <iprt/path.h>
58	#include <iprt/string.h>
59	#include <iprt/system.h>
60	#include <iprt/utf16.h>
61
62	#include <iprt/formats/arm-psci.h>
63
64	#include <mach/mach_time.h>
65	#include <mach/kern_return.h>
66
67	#include <Hypervisor/Hypervisor.h>
68
69
70	/*********************************************************************************************************************************
71	* Defined Constants And Macros *
72	*********************************************************************************************************************************/
73
74
75	/** @todo The vTimer PPI for the virt platform, make it configurable. */
76	#define NEM_DARWIN_VTIMER_GIC_PPI_IRQ 11
77
78
79	/*********************************************************************************************************************************
80	* Structures and Typedefs *
81	*********************************************************************************************************************************/
82
83
84	/*********************************************************************************************************************************
85	* Global Variables *
86	*********************************************************************************************************************************/
87	/** The general registers. */
88	static const struct
89	{
90	hv_reg_t enmHvReg;
91	uint32_t fCpumExtrn;
92	uint32_t offCpumCtx;
93	} s_aCpumRegs[] =
94	{
95	#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
96	#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
97	CPUM_GREG_EMIT_X0_X3(0),
98	CPUM_GREG_EMIT_X0_X3(1),
99	CPUM_GREG_EMIT_X0_X3(2),
100	CPUM_GREG_EMIT_X0_X3(3),
101	CPUM_GREG_EMIT_X4_X28(4),
102	CPUM_GREG_EMIT_X4_X28(5),
103	CPUM_GREG_EMIT_X4_X28(6),
104	CPUM_GREG_EMIT_X4_X28(7),
105	CPUM_GREG_EMIT_X4_X28(8),
106	CPUM_GREG_EMIT_X4_X28(9),
107	CPUM_GREG_EMIT_X4_X28(10),
108	CPUM_GREG_EMIT_X4_X28(11),
109	CPUM_GREG_EMIT_X4_X28(12),
110	CPUM_GREG_EMIT_X4_X28(13),
111	CPUM_GREG_EMIT_X4_X28(14),
112	CPUM_GREG_EMIT_X4_X28(15),
113	CPUM_GREG_EMIT_X4_X28(16),
114	CPUM_GREG_EMIT_X4_X28(17),
115	CPUM_GREG_EMIT_X4_X28(18),
116	CPUM_GREG_EMIT_X4_X28(19),
117	CPUM_GREG_EMIT_X4_X28(20),
118	CPUM_GREG_EMIT_X4_X28(21),
119	CPUM_GREG_EMIT_X4_X28(22),
120	CPUM_GREG_EMIT_X4_X28(23),
121	CPUM_GREG_EMIT_X4_X28(24),
122	CPUM_GREG_EMIT_X4_X28(25),
123	CPUM_GREG_EMIT_X4_X28(26),
124	CPUM_GREG_EMIT_X4_X28(27),
125	CPUM_GREG_EMIT_X4_X28(28),
126	{ HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
127	{ HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
128	{ HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
129	{ HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
130	{ HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
131	#undef CPUM_GREG_EMIT_X0_X3
132	#undef CPUM_GREG_EMIT_X4_X28
133	};
134	/** SIMD/FP registers. */
135	static const struct
136	{
137	hv_simd_fp_reg_t enmHvReg;
138	uint32_t offCpumCtx;
139	} s_aCpumFpRegs[] =
140	{
141	#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
142	CPUM_VREG_EMIT(0),
143	CPUM_VREG_EMIT(1),
144	CPUM_VREG_EMIT(2),
145	CPUM_VREG_EMIT(3),
146	CPUM_VREG_EMIT(4),
147	CPUM_VREG_EMIT(5),
148	CPUM_VREG_EMIT(6),
149	CPUM_VREG_EMIT(7),
150	CPUM_VREG_EMIT(8),
151	CPUM_VREG_EMIT(9),
152	CPUM_VREG_EMIT(10),
153	CPUM_VREG_EMIT(11),
154	CPUM_VREG_EMIT(12),
155	CPUM_VREG_EMIT(13),
156	CPUM_VREG_EMIT(14),
157	CPUM_VREG_EMIT(15),
158	CPUM_VREG_EMIT(16),
159	CPUM_VREG_EMIT(17),
160	CPUM_VREG_EMIT(18),
161	CPUM_VREG_EMIT(19),
162	CPUM_VREG_EMIT(20),
163	CPUM_VREG_EMIT(21),
164	CPUM_VREG_EMIT(22),
165	CPUM_VREG_EMIT(23),
166	CPUM_VREG_EMIT(24),
167	CPUM_VREG_EMIT(25),
168	CPUM_VREG_EMIT(26),
169	CPUM_VREG_EMIT(27),
170	CPUM_VREG_EMIT(28),
171	CPUM_VREG_EMIT(29),
172	CPUM_VREG_EMIT(30),
173	CPUM_VREG_EMIT(31)
174	#undef CPUM_VREG_EMIT
175	};
176	/** Debug system registers. */
177	static const struct
178	{
179	hv_sys_reg_t enmHvReg;
180	uint32_t offCpumCtx;
181	} s_aCpumDbgRegs[] =
182	{
183	#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
184	{ HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
185	{ HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
186	/* Breakpoint registers. */
187	CPUM_DBGREG_EMIT(B, 0),
188	CPUM_DBGREG_EMIT(B, 1),
189	CPUM_DBGREG_EMIT(B, 2),
190	CPUM_DBGREG_EMIT(B, 3),
191	CPUM_DBGREG_EMIT(B, 4),
192	CPUM_DBGREG_EMIT(B, 5),
193	CPUM_DBGREG_EMIT(B, 6),
194	CPUM_DBGREG_EMIT(B, 7),
195	CPUM_DBGREG_EMIT(B, 8),
196	CPUM_DBGREG_EMIT(B, 9),
197	CPUM_DBGREG_EMIT(B, 10),
198	CPUM_DBGREG_EMIT(B, 11),
199	CPUM_DBGREG_EMIT(B, 12),
200	CPUM_DBGREG_EMIT(B, 13),
201	CPUM_DBGREG_EMIT(B, 14),
202	CPUM_DBGREG_EMIT(B, 15),
203	/* Watchpoint registers. */
204	CPUM_DBGREG_EMIT(W, 0),
205	CPUM_DBGREG_EMIT(W, 1),
206	CPUM_DBGREG_EMIT(W, 2),
207	CPUM_DBGREG_EMIT(W, 3),
208	CPUM_DBGREG_EMIT(W, 4),
209	CPUM_DBGREG_EMIT(W, 5),
210	CPUM_DBGREG_EMIT(W, 6),
211	CPUM_DBGREG_EMIT(W, 7),
212	CPUM_DBGREG_EMIT(W, 8),
213	CPUM_DBGREG_EMIT(W, 9),
214	CPUM_DBGREG_EMIT(W, 10),
215	CPUM_DBGREG_EMIT(W, 11),
216	CPUM_DBGREG_EMIT(W, 12),
217	CPUM_DBGREG_EMIT(W, 13),
218	CPUM_DBGREG_EMIT(W, 14),
219	CPUM_DBGREG_EMIT(W, 15),
220	{ HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
221	#undef CPUM_DBGREG_EMIT
222	};
223	/** PAuth key system registers. */
224	static const struct
225	{
226	hv_sys_reg_t enmHvReg;
227	uint32_t offCpumCtx;
228	} s_aCpumPAuthKeyRegs[] =
229	{
230	{ HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
231	{ HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
232	{ HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
233	{ HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
234	{ HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
235	{ HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
236	{ HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
237	{ HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
238	{ HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
239	{ HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
240	};
241	/** System registers. */
242	static const struct
243	{
244	hv_sys_reg_t enmHvReg;
245	uint32_t fCpumExtrn;
246	uint32_t offCpumCtx;
247	} s_aCpumSysRegs[] =
248	{
249	{ HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
250	{ HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
251	{ HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
252	{ HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
253	{ HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
254	{ HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
255	{ HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
256	{ HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
257	{ HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
258	{ HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
259	{ HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
260	{ HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
261	{ HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
262	{ HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
263	{ HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
264	{ HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
265	{ HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
266	{ HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
267	{ HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
268	{ HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
269	{ HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
270	{ HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
271	{ HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
272	{ HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
273
274	};
275	/** ID registers. */
276	static const struct
277	{
278	hv_feature_reg_t enmHvReg;
279	uint32_t offIdStruct;
280	} s_aIdRegs[] =
281	{
282	{ HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(HVIDREGS, u64IdDfReg0El1) },
283	{ HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(HVIDREGS, u64IdDfReg1El1) },
284	{ HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(HVIDREGS, u64IdIsaReg0El1) },
285	{ HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(HVIDREGS, u64IdIsaReg1El1) },
286	{ HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(HVIDREGS, u64IdMmfReg0El1) },
287	{ HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(HVIDREGS, u64IdMmfReg1El1) },
288	{ HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(HVIDREGS, u64IdPfReg0El1) },
289	{ HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(HVIDREGS, u64IdPfReg1El1) },
290	{ HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(HVIDREGS, u64ClidrEl1) },
291	{ HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(HVIDREGS, u64CtrEl0) },
292	{ HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(HVIDREGS, u64DczidEl1) },
293	};
294
295
296	/*********************************************************************************************************************************
297	* Internal Functions *
298	*********************************************************************************************************************************/
299
300
301	/**
302	* Converts a HV return code to a VBox status code.
303	*
304	* @returns VBox status code.
305	* @param hrc The HV return code to convert.
306	*/
307	DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
308	{
309	if (hrc == HV_SUCCESS)
310	return VINF_SUCCESS;
311
312	switch (hrc)
313	{
314	case HV_ERROR: return VERR_INVALID_STATE;
315	case HV_BUSY: return VERR_RESOURCE_BUSY;
316	case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
317	case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
318	case HV_NO_DEVICE: return VERR_NOT_FOUND;
319	case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
320	}
321
322	return VERR_IPE_UNEXPECTED_STATUS;
323	}
324
325
326	/**
327	* Returns a human readable string of the given exception class.
328	*
329	* @returns Pointer to the string matching the given EC.
330	* @param u32Ec The exception class to return the string for.
331	*/
332	static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
333	{
334	switch (u32Ec)
335	{
336	#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
337	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
338	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
339	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
340	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
341	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
342	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
343	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
344	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
345	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
346	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
347	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
348	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
349	ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
350	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
351	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
352	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
353	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
354	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
355	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
356	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
357	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
358	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
359	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
360	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
361	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
362	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
363	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
364	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
365	ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
366	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
367	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
368	ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
369	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
370	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
371	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
372	ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
373	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
374	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
375	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
376	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
377	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
378	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
379	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
380	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
381	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
382	#undef ARMV8_EC_CASE
383	default:
384	break;
385	}
386
387	return "<INVALID>";
388	}
389
390
391	/**
392	* Resolves a NEM page state from the given protection flags.
393	*
394	* @returns NEM page state.
395	* @param fPageProt The page protection flags.
396	*/
397	DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
398	{
399	switch (fPageProt)
400	{
401	case NEM_PAGE_PROT_NONE:
402	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
403	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE:
404	return NEM_DARWIN_PAGE_STATE_RX;
405	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE:
406	return NEM_DARWIN_PAGE_STATE_RW;
407	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE:
408	return NEM_DARWIN_PAGE_STATE_RWX;
409	default:
410	break;
411	}
412
413	AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
414	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
415	}
416
417
418	/**
419	* Unmaps the given guest physical address range (page aligned).
420	*
421	* @returns VBox status code.
422	* @param pVM The cross context VM structure.
423	* @param GCPhys The guest physical address to start unmapping at.
424	* @param cb The size of the range to unmap in bytes.
425	* @param pu2State Where to store the new state of the unmappd page, optional.
426	*/
427	DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
428	{
429	if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
430	{
431	Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
432	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
433	return VINF_SUCCESS;
434	}
435
436	LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
437	hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
438	if (RT_LIKELY(hrc == HV_SUCCESS))
439	{
440	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
441	if (pu2State)
442	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
443	Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
444	return VINF_SUCCESS;
445	}
446
447	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
448	LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
449	GCPhys, hrc));
450	return VERR_NEM_IPE_6;
451	}
452
453
454	/**
455	* Maps a given guest physical address range backed by the given memory with the given
456	* protection flags.
457	*
458	* @returns VBox status code.
459	* @param pVM The cross context VM structure.
460	* @param GCPhys The guest physical address to start mapping.
461	* @param pvRam The R3 pointer of the memory to back the range with.
462	* @param cb The size of the range, page aligned.
463	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
464	* @param pu2State Where to store the state for the new page, optional.
465	*/
466	DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void pvRam, size_t cb, uint32_t fPageProt, uint8_t pu2State)
467	{
468	LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
469
470	Assert(fPageProt != NEM_PAGE_PROT_NONE);
471	RT_NOREF(pVM);
472
473	hv_memory_flags_t fHvMemProt = 0;
474	if (fPageProt & NEM_PAGE_PROT_READ)
475	fHvMemProt \|= HV_MEMORY_READ;
476	if (fPageProt & NEM_PAGE_PROT_WRITE)
477	fHvMemProt \|= HV_MEMORY_WRITE;
478	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
479	fHvMemProt \|= HV_MEMORY_EXEC;
480
481	hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
482	if (hrc == HV_SUCCESS)
483	{
484	if (pu2State)
485	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
486	return VINF_SUCCESS;
487	}
488
489	return nemR3DarwinHvSts2Rc(hrc);
490	}
491
492
493	/**
494	* Changes the protection flags for the given guest physical address range.
495	*
496	* @returns VBox status code.
497	* @param GCPhys The guest physical address to start mapping.
498	* @param cb The size of the range, page aligned.
499	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
500	* @param pu2State Where to store the state for the new page, optional.
501	*/
502	DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
503	{
504	hv_memory_flags_t fHvMemProt = 0;
505	if (fPageProt & NEM_PAGE_PROT_READ)
506	fHvMemProt \|= HV_MEMORY_READ;
507	if (fPageProt & NEM_PAGE_PROT_WRITE)
508	fHvMemProt \|= HV_MEMORY_WRITE;
509	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
510	fHvMemProt \|= HV_MEMORY_EXEC;
511
512	hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
513	if (hrc == HV_SUCCESS)
514	{
515	if (pu2State)
516	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
517	return VINF_SUCCESS;
518	}
519
520	LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
521	GCPhys, cb, fPageProt, hrc));
522	return nemR3DarwinHvSts2Rc(hrc);
523	}
524
525
526	#ifdef LOG_ENABLED
527	/**
528	* Logs the current CPU state.
529	*/
530	static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
531	{
532	if (LogIs3Enabled())
533	{
534	char szRegs[4096];
535	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
536	"x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
537	"x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
538	"x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
539	"x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
540	"x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
541	"x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
542	"x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
543	"x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
544	"pc=%016VR{pc} pstate=%016VR{pstate}\n"
545	"sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
546	"sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
547	"ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
548	"vbar_el1=%016VR{vbar_el1}\n"
549	);
550	char szInstr[256]; RT_ZERO(szInstr);
551	#if 0
552	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
553	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
554	szInstr, sizeof(szInstr), NULL);
555	#endif
556	Log3(("%s%s\n", szRegs, szInstr));
557	}
558	}
559	#endif /* LOG_ENABLED */
560
561
562	static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
563	{
564	RT_NOREF(pVM);
565
566	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
567	if (hrc == HV_SUCCESS)
568	hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
569
570	if ( hrc == HV_SUCCESS
571	&& (fWhat & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR)))
572	{
573	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
574	{
575	if (s_aCpumRegs[i].fCpumExtrn & fWhat)
576	{
577	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
578	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
579	}
580	}
581	}
582
583	if ( hrc == HV_SUCCESS
584	&& (fWhat & CPUMCTX_EXTRN_V0_V31))
585	{
586	/* SIMD/FP registers. */
587	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
588	{
589	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
590	hrc \|= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
591	}
592	}
593
594	if ( hrc == HV_SUCCESS
595	&& (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
596	{
597	/* Debug registers. */
598	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
599	{
600	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
601	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
602	}
603	}
604
605	if ( hrc == HV_SUCCESS
606	&& (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
607	{
608	/* Debug registers. */
609	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
610	{
611	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
612	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
613	}
614	}
615
616	if ( hrc == HV_SUCCESS
617	&& (fWhat & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC)))
618	{
619	/* System registers. */
620	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
621	{
622	if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
623	{
624	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
625	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
626	}
627	}
628	}
629
630	if ( hrc == HV_SUCCESS
631	&& (fWhat & CPUMCTX_EXTRN_PSTATE))
632	{
633	uint64_t u64Tmp;
634	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
635	if (hrc == HV_SUCCESS)
636	pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
637	}
638
639	/* Almost done, just update extern flags. */
640	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
641	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
642	pVCpu->cpum.GstCtx.fExtrn = 0;
643
644	return nemR3DarwinHvSts2Rc(hrc);
645	}
646
647
648	/**
649	* Exports the guest state to HV for execution.
650	*
651	* @returns VBox status code.
652	* @param pVM The cross context VM structure.
653	* @param pVCpu The cross context virtual CPU structure of the
654	* calling EMT.
655	*/
656	static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
657	{
658	RT_NOREF(pVM);
659	hv_return_t hrc = HV_SUCCESS;
660
661	if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
662	!= (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
663	{
664	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
665	{
666	if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
667	{
668	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
669	hrc \|= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
670	}
671	}
672	}
673
674	if ( hrc == HV_SUCCESS
675	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
676	{
677	/* SIMD/FP registers. */
678	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
679	{
680	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
681	hrc \|= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
682	}
683	}
684
685	if ( hrc == HV_SUCCESS
686	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
687	{
688	/* Debug registers. */
689	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
690	{
691	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
692	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
693	}
694	}
695
696	if ( hrc == HV_SUCCESS
697	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
698	{
699	/* Debug registers. */
700	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
701	{
702	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
703	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
704	}
705	}
706
707	if ( hrc == HV_SUCCESS
708	&& (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
709	!= (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
710	{
711	/* System registers. */
712	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
713	{
714	if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
715	{
716	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
717	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
718	}
719	}
720	}
721
722	if ( hrc == HV_SUCCESS
723	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
724	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
725
726	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_NEM;
727	return nemR3DarwinHvSts2Rc(hrc);
728	}
729
730
731	/**
732	* Try initialize the native API.
733	*
734	* This may only do part of the job, more can be done in
735	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
736	*
737	* @returns VBox status code.
738	* @param pVM The cross context VM structure.
739	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
740	* the latter we'll fail if we cannot initialize.
741	* @param fForced Whether the HMForced flag is set and we should
742	* fail if we cannot initialize.
743	*/
744	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
745	{
746	AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
747
748	/*
749	* Some state init.
750	*/
751	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
752	RT_NOREF(pCfgNem);
753
754	/*
755	* Error state.
756	* The error message will be non-empty on failure and 'rc' will be set too.
757	*/
758	RTERRINFOSTATIC ErrInfo;
759	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
760
761	int rc = VINF_SUCCESS;
762	hv_return_t hrc = hv_vm_create(NULL);
763	if (hrc == HV_SUCCESS)
764	{
765	pVM->nem.s.fCreatedVm = true;
766	pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
767
768	/* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
769	pVM->nem.s.u64VTimerOff = 0;
770
771	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
772	Log(("NEM: Marked active!\n"));
773	PGMR3EnableNemMode(pVM);
774	}
775	else
776	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
777	"hv_vm_create() failed: %#x", hrc);
778
779	/*
780	* We only fail if in forced mode, otherwise just log the complaint and return.
781	*/
782	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API \|\| RTErrInfoIsSet(pErrInfo));
783	if ( (fForced \|\| !fFallback)
784	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
785	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
786
787	if (RTErrInfoIsSet(pErrInfo))
788	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
789	return VINF_SUCCESS;
790	}
791
792
793	/**
794	* Worker to create the vCPU handle on the EMT running it later on (as required by HV).
795	*
796	* @returns VBox status code
797	* @param pVM The VM handle.
798	* @param pVCpu The vCPU handle.
799	* @param idCpu ID of the CPU to create.
800	*/
801	static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
802	{
803	if (idCpu == 0)
804	{
805	Assert(pVM->nem.s.hVCpuCfg == NULL);
806
807	/* Create a new vCPU config and query the ID registers. */
808	pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
809	if (!pVM->nem.s.hVCpuCfg)
810	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
811	"Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
812
813	for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
814	{
815	uint64_t pu64 = (uint64_t )((uint8_t *)&pVM->nem.s.IdRegs + s_aIdRegs[i].offIdStruct);
816	hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
817	if (hrc != HV_SUCCESS)
818	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
819	"Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
820	}
821	}
822
823	hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
824	if (hrc != HV_SUCCESS)
825	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
826	"Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
827
828	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
829	if (hrc != HV_SUCCESS)
830	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
831	"Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
832
833	return VINF_SUCCESS;
834	}
835
836
837	/**
838	* Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
839	*
840	* @returns VBox status code.
841	* @param pVM The VM handle.
842	* @param pVCpu The vCPU handle.
843	*/
844	static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
845	{
846	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
847	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
848
849	if (pVCpu->idCpu == 0)
850	{
851	os_release(pVM->nem.s.hVCpuCfg);
852	pVM->nem.s.hVCpuCfg = NULL;
853	}
854	return VINF_SUCCESS;
855	}
856
857
858	/**
859	* This is called after CPUMR3Init is done.
860	*
861	* @returns VBox status code.
862	* @param pVM The VM handle..
863	*/
864	int nemR3NativeInitAfterCPUM(PVM pVM)
865	{
866	/*
867	* Validate sanity.
868	*/
869	AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
870	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
871
872	/*
873	* Setup the EMTs.
874	*/
875	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
876	{
877	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
878
879	int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
880	if (RT_FAILURE(rc))
881	{
882	/* Rollback. */
883	while (idCpu--)
884	VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
885
886	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
887	}
888	}
889
890	pVM->nem.s.fCreatedEmts = true;
891	return VINF_SUCCESS;
892	}
893
894
895	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
896	{
897	RT_NOREF(pVM, enmWhat);
898	return VINF_SUCCESS;
899	}
900
901
902	int nemR3NativeTerm(PVM pVM)
903	{
904	/*
905	* Delete the VM.
906	*/
907
908	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
909	{
910	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
911
912	/*
913	* Apple's documentation states that the vCPU should be destroyed
914	* on the thread running the vCPU but as all the other EMTs are gone
915	* at this point, destroying the VM would hang.
916	*
917	* We seem to be at luck here though as destroying apparently works
918	* from EMT(0) as well.
919	*/
920	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
921	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
922	}
923
924	pVM->nem.s.fCreatedEmts = false;
925	if (pVM->nem.s.fCreatedVm)
926	{
927	hv_return_t hrc = hv_vm_destroy();
928	if (hrc != HV_SUCCESS)
929	LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
930
931	pVM->nem.s.fCreatedVm = false;
932	}
933	return VINF_SUCCESS;
934	}
935
936
937	/**
938	* VM reset notification.
939	*
940	* @param pVM The cross context VM structure.
941	*/
942	void nemR3NativeReset(PVM pVM)
943	{
944	RT_NOREF(pVM);
945	}
946
947
948	/**
949	* Reset CPU due to INIT IPI or hot (un)plugging.
950	*
951	* @param pVCpu The cross context virtual CPU structure of the CPU being
952	* reset.
953	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
954	*/
955	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
956	{
957	RT_NOREF(pVCpu, fInitIpi);
958	}
959
960
961	/**
962	* Returns the byte size from the given access SAS value.
963	*
964	* @returns Number of bytes to transfer.
965	* @param uSas The SAS value to convert.
966	*/
967	DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
968	{
969	switch (uSas)
970	{
971	case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
972	case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
973	case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
974	case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
975	default:
976	AssertReleaseFailed();
977	}
978
979	return 0;
980	}
981
982
983	/**
984	* Sets the given general purpose register to the given value.
985	*
986	* @param pVCpu The cross context virtual CPU structure of the
987	* calling EMT.
988	* @param uReg The register index.
989	* @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
990	* @param fSignExtend Flag whether to sign extend the value.
991	* @param u64Val The value.
992	*/
993	DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
994	{
995	AssertReturnVoid(uReg < 31);
996
997	if (f64BitReg)
998	pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
999	else
1000	pVCpu->cpum.GstCtx.aGRegs[uReg].w = fSignExtend ? (int32_t)u64Val : u64Val; /** @todo Does this clear the upper half on real hardware? */
1001
1002	/* Mark the register as not extern anymore. */
1003	switch (uReg)
1004	{
1005	case 0:
1006	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
1007	break;
1008	case 1:
1009	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
1010	break;
1011	case 2:
1012	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
1013	break;
1014	case 3:
1015	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
1016	break;
1017	default:
1018	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
1019	/** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
1020	}
1021	}
1022
1023
1024	/**
1025	* Gets the given general purpose register and returns the value.
1026	*
1027	* @returns Value from the given register.
1028	* @param pVCpu The cross context virtual CPU structure of the
1029	* calling EMT.
1030	* @param uReg The register index.
1031	*/
1032	DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
1033	{
1034	AssertReturn(uReg <= ARMV8_AARCH64_REG_ZR, 0);
1035
1036	if (uReg == ARMV8_AARCH64_REG_ZR)
1037	return 0;
1038
1039	/** @todo Import the register if extern. */
1040	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
1041
1042	return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
1043	}
1044
1045
1046	/**
1047	* Works on the data abort exception (which will be a MMIO access most of the time).
1048	*
1049	* @returns VBox strict status code.
1050	* @param pVM The cross context VM structure.
1051	* @param pVCpu The cross context virtual CPU structure of the
1052	* calling EMT.
1053	* @param uIss The instruction specific syndrome value.
1054	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1055	* @param GCPtrDataAbrt The virtual GC address causing the data abort.
1056	* @param GCPhysDataAbrt The physical GC address which caused the data abort.
1057	*/
1058	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
1059	RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
1060	{
1061	bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
1062	bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
1063	bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
1064	bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
1065	bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
1066	uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
1067	uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
1068	size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
1069	LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
1070	fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
1071
1072	RT_NOREF(fL2Fault, GCPtrDataAbrt);
1073
1074	if (fWrite)
1075	{
1076	/*
1077	* Check whether this is one of the dirty tracked regions, mark it as dirty
1078	* and enable write support for this region again.
1079	*
1080	* This is required for proper VRAM tracking or the display might not get updated
1081	* and it is impossible to use the PGM generic facility as it operates on guest page sizes
1082	* but setting protection flags with Hypervisor.framework works only host page sized regions, so
1083	* we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
1084	* which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
1085	* write access again (due to a missing interpreter right now).
1086	*/
1087	for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1088	{
1089	PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1090
1091	if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
1092	&& GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
1093	{
1094	pMmio2Region->fDirty = true;
1095
1096	uint8_t u2State;
1097	int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
1098	NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE \| NEM_PAGE_PROT_WRITE, &u2State);
1099
1100	/* Restart the instruction if there is no instruction syndrome available. */
1101	if (RT_FAILURE(rc) \|\| !fIsv)
1102	return rc;
1103	}
1104	}
1105	}
1106
1107	AssertReturn(fIsv, VERR_NOT_SUPPORTED); /** @todo Implement using IEM when this should occur. */
1108
1109	EMHistoryAddExit(pVCpu,
1110	fWrite
1111	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1112	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1113	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1114
1115	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1116	uint64_t u64Val = 0;
1117	if (fWrite)
1118	{
1119	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1120	rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1121	Log4(("MmioExit/%u: %08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
1122	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1123	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1124	}
1125	else
1126	{
1127	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1128	Log4(("MmioExit/%u: %08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1129	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1130	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1131	if (rcStrict == VINF_SUCCESS)
1132	nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
1133	}
1134
1135	if (rcStrict == VINF_SUCCESS)
1136	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1137
1138	return rcStrict;
1139	}
1140
1141
1142	/**
1143	* Works on the trapped MRS, MSR and system instruction exception.
1144	*
1145	* @returns VBox strict status code.
1146	* @param pVM The cross context VM structure.
1147	* @param pVCpu The cross context virtual CPU structure of the
1148	* calling EMT.
1149	* @param uIss The instruction specific syndrome value.
1150	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1151	*/
1152	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
1153	{
1154	bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
1155	uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
1156	uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
1157	uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
1158	uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
1159	uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
1160	uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
1161	uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
1162	LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
1163	fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
1164
1165	/** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
1166	EMHistoryAddExit(pVCpu,
1167	fRead
1168	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1169	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1170	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1171
1172	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1173	uint64_t u64Val = 0;
1174	if (fRead)
1175	{
1176	RT_NOREF(pVM);
1177	rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
1178	Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
1179	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1180	VBOXSTRICTRC_VAL(rcStrict) ));
1181	if (rcStrict == VINF_SUCCESS)
1182	nemR3DarwinSetGReg(pVCpu, uReg, true /f64BitReg/, false /fSignExtend/, u64Val);
1183	}
1184	else
1185	{
1186	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1187	rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
1188	Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
1189	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1190	VBOXSTRICTRC_VAL(rcStrict) ));
1191	}
1192
1193	if (rcStrict == VINF_SUCCESS)
1194	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1195
1196	return rcStrict;
1197	}
1198
1199
1200	/**
1201	* Works on the trapped HVC instruction exception.
1202	*
1203	* @returns VBox strict status code.
1204	* @param pVM The cross context VM structure.
1205	* @param pVCpu The cross context virtual CPU structure of the
1206	* calling EMT.
1207	* @param uIss The instruction specific syndrome value.
1208	*/
1209	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss)
1210	{
1211	uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
1212	LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1213
1214	#if 0 /** @todo For later */
1215	EMHistoryAddExit(pVCpu,
1216	fRead
1217	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1218	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1219	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1220	#endif
1221
1222	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1223	if (u16Imm == 0)
1224	{
1225	/** @todo Raise exception to EL1 if PSCI not configured. */
1226	/** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
1227	uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_AARCH64_REG_X0].w;
1228	bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
1229	uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
1230	uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
1231	if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
1232	{
1233	switch (uFunNum)
1234	{
1235	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1236	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
1237	break;
1238	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1239	rcStrict = VMR3PowerOff(pVM->pUVM);
1240	break;
1241	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1242	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1243	{
1244	bool fHaltOnReset;
1245	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
1246	if (RT_SUCCESS(rc) && fHaltOnReset)
1247	{
1248	Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
1249	rc = VINF_EM_HALT;
1250	}
1251	else
1252	{
1253	/** @todo pVM->pdm.s.fResetFlags = fFlags; */
1254	VM_FF_SET(pVM, VM_FF_RESET);
1255	rc = VINF_EM_RESET;
1256	}
1257	break;
1258	}
1259	case ARM_PSCI_FUNC_ID_CPU_ON:
1260	{
1261	uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1262	RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X2);
1263	uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X3);
1264	VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
1265	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, true /f64BitReg/, false /fSignExtend/, ARM_PSCI_STS_SUCCESS);
1266	break;
1267	}
1268	case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
1269	{
1270	uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1271	switch (u32FunNum)
1272	{
1273	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1274	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1275	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1276	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1277	case ARM_PSCI_FUNC_ID_CPU_ON:
1278	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1279	false /f64BitReg/, false /fSignExtend/,
1280	(uint64_t)ARM_PSCI_STS_SUCCESS);
1281	break;
1282	default:
1283	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1284	false /f64BitReg/, false /fSignExtend/,
1285	(uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1286	}
1287	}
1288	default:
1289	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1290	}
1291	}
1292	else
1293	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1294	}
1295	/** @todo What to do if immediate is != 0? */
1296
1297	return rcStrict;
1298	}
1299
1300
1301	/**
1302	* Handles an exception VM exit.
1303	*
1304	* @returns VBox strict status code.
1305	* @param pVM The cross context VM structure.
1306	* @param pVCpu The cross context virtual CPU structure of the
1307	* calling EMT.
1308	* @param pExit Pointer to the exit information.
1309	*/
1310	static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
1311	{
1312	uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
1313	uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
1314	bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
1315
1316	LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1317	pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1318
1319	switch (uEc)
1320	{
1321	case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
1322	return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
1323	pExit->exception.physical_address);
1324	case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
1325	return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
1326	case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
1327	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
1328	case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
1329	{
1330	/* No need to halt if there is an interrupt pending already. */
1331	if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ)))
1332	return VINF_SUCCESS;
1333
1334	/* Set the vTimer expiration in order to get out of the halt at the right point in time. */
1335	if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
1336	&& !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
1337	{
1338	uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
1339
1340	/* Check whether it expired and start executing guest code. */
1341	if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
1342	return VINF_SUCCESS;
1343
1344	uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
1345	uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
1346
1347	/*
1348	* Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
1349	* + scheduling overhead which would increase the wakeup latency.
1350	* So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
1351	* between CPU load when the guest is idle and performance).
1352	*/
1353	if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
1354	return VINF_SUCCESS;
1355
1356	LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
1357	cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
1358	TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
1359	}
1360	else
1361	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
1362
1363	return VINF_EM_HALT;
1364	}
1365	case ARMV8_ESR_EL2_EC_UNKNOWN:
1366	default:
1367	LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1368	uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1369	AssertReleaseFailed();
1370	return VERR_NOT_IMPLEMENTED;
1371	}
1372
1373	return VINF_SUCCESS;
1374	}
1375
1376
1377	/**
1378	* Handles an exit from hv_vcpu_run().
1379	*
1380	* @returns VBox strict status code.
1381	* @param pVM The cross context VM structure.
1382	* @param pVCpu The cross context virtual CPU structure of the
1383	* calling EMT.
1384	*/
1385	static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
1386	{
1387	int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
1388	if (RT_FAILURE(rc))
1389	return rc;
1390
1391	#ifdef LOG_ENABLED
1392	if (LogIs3Enabled())
1393	nemR3DarwinLogState(pVM, pVCpu);
1394	#endif
1395
1396	hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
1397	switch (pExit->reason)
1398	{
1399	case HV_EXIT_REASON_CANCELED:
1400	return VINF_EM_RAW_INTERRUPT;
1401	case HV_EXIT_REASON_EXCEPTION:
1402	return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
1403	case HV_EXIT_REASON_VTIMER_ACTIVATED:
1404	{
1405	LogFlowFunc(("vTimer got activated\n"));
1406	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
1407	pVCpu->nem.s.fVTimerActivated = true;
1408	return GICPpiSet(pVCpu, NEM_DARWIN_VTIMER_GIC_PPI_IRQ, true /fAsserted/);
1409	}
1410	default:
1411	AssertReleaseFailed();
1412	break;
1413	}
1414
1415	return VERR_INVALID_STATE;
1416	}
1417
1418
1419	/**
1420	* Runs the guest once until an exit occurs.
1421	*
1422	* @returns HV status code.
1423	* @param pVM The cross context VM structure.
1424	* @param pVCpu The cross context virtual CPU structure.
1425	*/
1426	static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
1427	{
1428	TMNotifyStartOfExecution(pVM, pVCpu);
1429
1430	hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
1431
1432	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
1433
1434	return hrc;
1435	}
1436
1437
1438	/**
1439	* Prepares the VM to run the guest.
1440	*
1441	* @returns Strict VBox status code.
1442	* @param pVM The cross context VM structure.
1443	* @param pVCpu The cross context virtual CPU structure.
1444	* @param fSingleStepping Flag whether we run in single stepping mode.
1445	*/
1446	static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
1447	{
1448	#ifdef LOG_ENABLED
1449	bool fIrq = false;
1450	bool fFiq = false;
1451
1452	if (LogIs3Enabled())
1453	nemR3DarwinLogState(pVM, pVCpu);
1454	#endif
1455
1456	/** @todo */ RT_NOREF(fSingleStepping);
1457	int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
1458	AssertRCReturn(rc, rc);
1459
1460	/* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
1461	if (pVCpu->nem.s.fVTimerActivated)
1462	{
1463	/* Read the CNTV_CTL_EL0 register. */
1464	uint64_t u64CntvCtl = 0;
1465
1466	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
1467	AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1468
1469	if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_IMASK \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
1470	!= (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
1471	{
1472	/* Clear the interrupt. */
1473	GICPpiSet(pVCpu, NEM_DARWIN_VTIMER_GIC_PPI_IRQ, false /fAsserted/);
1474
1475	pVCpu->nem.s.fVTimerActivated = false;
1476	hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /vtimer_is_masked/);
1477	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1478	}
1479	}
1480
1481	/* Set the pending interrupt state. */
1482	hv_return_t hrc = HV_SUCCESS;
1483	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
1484	{
1485	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
1486	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1487	#ifdef LOG_ENABLED
1488	fIrq = true;
1489	#endif
1490	}
1491	else
1492	{
1493	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
1494	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1495	}
1496
1497	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
1498	{
1499	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
1500	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1501	#ifdef LOG_ENABLED
1502	fFiq = true;
1503	#endif
1504	}
1505	else
1506	{
1507	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
1508	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1509	}
1510
1511	LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
1512	pVCpu->nem.s.fEventPending = false;
1513	return VINF_SUCCESS;
1514	}
1515
1516
1517	/**
1518	* The normal runloop (no debugging features enabled).
1519	*
1520	* @returns Strict VBox status code.
1521	* @param pVM The cross context VM structure.
1522	* @param pVCpu The cross context virtual CPU structure.
1523	*/
1524	static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
1525	{
1526	/*
1527	* The run loop.
1528	*
1529	* Current approach to state updating to use the sledgehammer and sync
1530	* everything every time. This will be optimized later.
1531	*/
1532
1533	/* Update the vTimer offset after resuming if instructed. */
1534	if (pVCpu->nem.s.fVTimerOffUpdate)
1535	{
1536	hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
1537	if (hrc != HV_SUCCESS)
1538	return nemR3DarwinHvSts2Rc(hrc);
1539
1540	pVCpu->nem.s.fVTimerOffUpdate = false;
1541	}
1542
1543	/*
1544	* Poll timers and run for a bit.
1545	*/
1546	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
1547	* the whole polling job when timers have changed... */
1548	uint64_t offDeltaIgnored;
1549	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
1550	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1551	for (unsigned iLoop = 0;; iLoop++)
1552	{
1553	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
1554	if (rcStrict != VINF_SUCCESS)
1555	break;
1556
1557	hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
1558	if (hrc == HV_SUCCESS)
1559	{
1560	/*
1561	* Deal with the message.
1562	*/
1563	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
1564	if (rcStrict == VINF_SUCCESS)
1565	{ /* hopefully likely */ }
1566	else
1567	{
1568	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
1569	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
1570	break;
1571	}
1572	}
1573	else
1574	{
1575	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
1576	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
1577	}
1578	} /* the run loop */
1579
1580	return rcStrict;
1581	}
1582
1583
1584	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
1585	{
1586	#ifdef LOG_ENABLED
1587	if (LogIs3Enabled())
1588	nemR3DarwinLogState(pVM, pVCpu);
1589	#endif
1590
1591	AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
1592
1593	/*
1594	* Try switch to NEM runloop state.
1595	*/
1596	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
1597	{ /* likely */ }
1598	else
1599	{
1600	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
1601	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
1602	return VINF_SUCCESS;
1603	}
1604
1605	VBOXSTRICTRC rcStrict;
1606	#if 0
1607	if ( !pVCpu->nem.s.fUseDebugLoop
1608	&& !nemR3DarwinAnyExpensiveProbesEnabled()
1609	&& !DBGFIsStepping(pVCpu)
1610	&& !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1611	#endif
1612	rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
1613	#if 0
1614	else
1615	rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
1616	#endif
1617
1618	if (rcStrict == VINF_EM_RAW_TO_R3)
1619	rcStrict = VINF_SUCCESS;
1620
1621	/*
1622	* Convert any pending HM events back to TRPM due to premature exits.
1623	*
1624	* This is because execution may continue from IEM and we would need to inject
1625	* the event from there (hence place it back in TRPM).
1626	*/
1627	if (pVCpu->nem.s.fEventPending)
1628	{
1629	/** @todo */
1630	}
1631
1632
1633	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
1634	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
1635
1636	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
1637	{
1638	/* Try anticipate what we might need. */
1639	uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
1640	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
1641	\|\| RT_FAILURE(rcStrict))
1642	fImport = CPUMCTX_EXTRN_ALL;
1643	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ
1644	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
1645	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
1646
1647	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
1648	{
1649	/* Only import what is external currently. */
1650	int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
1651	if (RT_SUCCESS(rc2))
1652	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
1653	else if (RT_SUCCESS(rcStrict))
1654	rcStrict = rc2;
1655	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1656	pVCpu->cpum.GstCtx.fExtrn = 0;
1657	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
1658	}
1659	else
1660	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
1661	}
1662	else
1663	{
1664	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
1665	pVCpu->cpum.GstCtx.fExtrn = 0;
1666	}
1667
1668	return rcStrict;
1669	}
1670
1671
1672	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
1673	{
1674	RT_NOREF(pVM, pVCpu);
1675	return true; /** @todo Are there any cases where we have to emulate? */
1676	}
1677
1678
1679	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
1680	{
1681	VMCPU_ASSERT_EMT(pVCpu);
1682	bool fOld = pVCpu->nem.s.fSingleInstruction;
1683	pVCpu->nem.s.fSingleInstruction = fEnable;
1684	pVCpu->nem.s.fUseDebugLoop = fEnable \|\| pVM->nem.s.fUseDebugLoop;
1685	return fOld;
1686	}
1687
1688
1689	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
1690	{
1691	LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
1692
1693	RT_NOREF(pVM, fFlags);
1694
1695	hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
1696	if (hrc != HV_SUCCESS)
1697	LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
1698	}
1699
1700
1701	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
1702	{
1703	RT_NOREF(pVM, fUseDebugLoop);
1704	//AssertReleaseFailed();
1705	return false;
1706	}
1707
1708
1709	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
1710	{
1711	RT_NOREF(pVM, pVCpu, fUseDebugLoop);
1712	return fUseDebugLoop;
1713	}
1714
1715
1716	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
1717	uint8_t pu2State, uint32_t puNemRange)
1718	{
1719	RT_NOREF(pVM, puNemRange);
1720
1721	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
1722	#if defined(VBOX_WITH_PGM_NEM_MODE)
1723	if (pvR3)
1724	{
1725	int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
1726	if (RT_FAILURE(rc))
1727	{
1728	LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
1729	return VERR_NEM_MAP_PAGES_FAILED;
1730	}
1731	}
1732	return VINF_SUCCESS;
1733	#else
1734	RT_NOREF(pVM, GCPhys, cb, pvR3);
1735	return VERR_NEM_MAP_PAGES_FAILED;
1736	#endif
1737	}
1738
1739
1740	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
1741	{
1742	RT_NOREF(pVM);
1743	return true;
1744	}
1745
1746
1747	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
1748	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
1749	{
1750	RT_NOREF(pvRam);
1751
1752	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
1753	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
1754
1755	#if defined(VBOX_WITH_PGM_NEM_MODE)
1756	/*
1757	* Unmap the RAM we're replacing.
1758	*/
1759	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
1760	{
1761	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
1762	if (RT_SUCCESS(rc))
1763	{ /* likely */ }
1764	else if (pvMmio2)
1765	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
1766	GCPhys, cb, fFlags, rc));
1767	else
1768	{
1769	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
1770	GCPhys, cb, fFlags, rc));
1771	return VERR_NEM_UNMAP_PAGES_FAILED;
1772	}
1773	}
1774
1775	/*
1776	* Map MMIO2 if any.
1777	*/
1778	if (pvMmio2)
1779	{
1780	Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
1781
1782	/* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
1783	uint32_t fProt = NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE;
1784	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
1785	{
1786	/* Find a slot for dirty tracking. */
1787	PNEMHVMMIO2REGION pMmio2Region = NULL;
1788	uint32_t idSlot;
1789	for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1790	{
1791	if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
1792	&& pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
1793	{
1794	pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1795	break;
1796	}
1797	}
1798
1799	if (!pMmio2Region)
1800	{
1801	LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
1802	return VERR_NEM_MAP_PAGES_FAILED;
1803	}
1804
1805	pMmio2Region->GCPhysStart = GCPhys;
1806	pMmio2Region->GCPhysLast = GCPhys + cb - 1;
1807	pMmio2Region->fDirty = false;
1808	*puNemRange = idSlot;
1809	}
1810	else
1811	fProt \|= NEM_PAGE_PROT_WRITE;
1812
1813	int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
1814	if (RT_FAILURE(rc))
1815	{
1816	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
1817	GCPhys, cb, fFlags, pvMmio2, rc));
1818	return VERR_NEM_MAP_PAGES_FAILED;
1819	}
1820	}
1821	else
1822	Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
1823
1824	#else
1825	RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
1826	*pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
1827	#endif
1828	return VINF_SUCCESS;
1829	}
1830
1831
1832	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
1833	void pvRam, void pvMmio2, uint32_t *puNemRange)
1834	{
1835	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
1836	return VINF_SUCCESS;
1837	}
1838
1839
1840	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
1841	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
1842	{
1843	RT_NOREF(pVM, puNemRange);
1844
1845	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
1846	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
1847
1848	int rc = VINF_SUCCESS;
1849	#if defined(VBOX_WITH_PGM_NEM_MODE)
1850	/*
1851	* Unmap the MMIO2 pages.
1852	*/
1853	/** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
1854	* we may have more stuff to unmap even in case of pure MMIO... */
1855	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
1856	{
1857	rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
1858	if (RT_FAILURE(rc))
1859	{
1860	LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
1861	GCPhys, cb, fFlags, rc));
1862	rc = VERR_NEM_UNMAP_PAGES_FAILED;
1863	}
1864
1865	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
1866	{
1867	/* Reset tracking structure. */
1868	uint32_t idSlot = *puNemRange;
1869	*puNemRange = UINT32_MAX;
1870
1871	Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
1872	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
1873	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
1874	pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
1875	}
1876	}
1877
1878	/* Ensure the page is masked as unmapped if relevant. */
1879	Assert(!pu2State \|\| *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
1880
1881	/*
1882	* Restore the RAM we replaced.
1883	*/
1884	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
1885	{
1886	AssertPtr(pvRam);
1887	rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
1888	if (RT_SUCCESS(rc))
1889	{ /* likely */ }
1890	else
1891	{
1892	LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
1893	rc = VERR_NEM_MAP_PAGES_FAILED;
1894	}
1895	}
1896
1897	RT_NOREF(pvMmio2);
1898	#else
1899	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
1900	if (pu2State)
1901	*pu2State = UINT8_MAX;
1902	rc = VERR_NEM_UNMAP_PAGES_FAILED;
1903	#endif
1904	return rc;
1905	}
1906
1907
1908	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
1909	void *pvBitmap, size_t cbBitmap)
1910	{
1911	LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
1912	Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
1913
1914	/* Keep it simple for now and mark everything as dirty if it is. */
1915	int rc = VINF_SUCCESS;
1916	if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
1917	{
1918	ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
1919
1920	pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
1921	/* Restore as RX only. */
1922	uint8_t u2State;
1923	rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, &u2State);
1924	}
1925	else
1926	ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
1927
1928	return rc;
1929	}
1930
1931
1932	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
1933	uint8_t pu2State, uint32_t puNemRange)
1934	{
1935	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
1936
1937	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
1938	*pu2State = UINT8_MAX;
1939	*puNemRange = 0;
1940	return VINF_SUCCESS;
1941	}
1942
1943
1944	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
1945	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
1946	{
1947	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
1948	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
1949	*pu2State = UINT8_MAX;
1950
1951	#if defined(VBOX_WITH_PGM_NEM_MODE)
1952	/*
1953	* (Re-)map readonly.
1954	*/
1955	AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
1956
1957	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
1958	AssertRC(rc);
1959
1960	rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, pu2State);
1961	if (RT_FAILURE(rc))
1962	{
1963	LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
1964	GCPhys, cb, pvPages, fFlags, rc));
1965	return VERR_NEM_MAP_PAGES_FAILED;
1966	}
1967	RT_NOREF(fFlags, puNemRange);
1968	return VINF_SUCCESS;
1969	#else
1970	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
1971	return VERR_NEM_MAP_PAGES_FAILED;
1972	#endif
1973	}
1974
1975
1976	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1977	RTR3PTR pvMemR3, uint8_t *pu2State)
1978	{
1979	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
1980	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
1981
1982	*pu2State = UINT8_MAX;
1983	#if defined(VBOX_WITH_PGM_NEM_MODE)
1984	if (pvMemR3)
1985	{
1986	/* Unregister what was there before. */
1987	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
1988	AssertRC(rc);
1989
1990	rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
1991	AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
1992	pvMemR3, GCPhys, cb, rc));
1993	}
1994	RT_NOREF(enmKind);
1995	#else
1996	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
1997	AssertFailed();
1998	#endif
1999	}
2000
2001
2002	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
2003	{
2004	Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
2005	RT_NOREF(pVCpu, fEnabled);
2006	}
2007
2008
2009	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2010	{
2011	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2012	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2013	}
2014
2015
2016	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2017	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2018	{
2019	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2020	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2021	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2022	}
2023
2024
2025	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2026	PGMPAGETYPE enmType, uint8_t *pu2State)
2027	{
2028	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2029	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2030	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
2031
2032	AssertFailed();
2033	return VINF_SUCCESS;
2034	}
2035
2036
2037	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
2038	PGMPAGETYPE enmType, uint8_t *pu2State)
2039	{
2040	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2041	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2042	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
2043	}
2044
2045
2046	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2047	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2048	{
2049	Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2050	GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2051	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
2052
2053	AssertFailed();
2054	}
2055
2056
2057	/**
2058	* Interface for importing state on demand (used by IEM).
2059	*
2060	* @returns VBox status code.
2061	* @param pVCpu The cross context CPU structure.
2062	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2063	*/
2064	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2065	{
2066	LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
2067	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
2068
2069	return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
2070	}
2071
2072
2073	/**
2074	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
2075	*
2076	* @returns VBox status code.
2077	* @param pVCpu The cross context CPU structure.
2078	* @param pcTicks Where to return the CPU tick count.
2079	* @param puAux Where to return the TSC_AUX register value.
2080	*/
2081	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
2082	{
2083	LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
2084	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
2085
2086	if (puAux)
2087	*puAux = 0;
2088	pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; / This is the host timer minus the offset. */
2089	return VINF_SUCCESS;
2090	}
2091
2092
2093	/**
2094	* Resumes CPU clock (TSC) on all virtual CPUs.
2095	*
2096	* This is called by TM when the VM is started, restored, resumed or similar.
2097	*
2098	* @returns VBox status code.
2099	* @param pVM The cross context VM structure.
2100	* @param pVCpu The cross context CPU structure of the calling EMT.
2101	* @param uPausedTscValue The TSC value at the time of pausing.
2102	*/
2103	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
2104	{
2105	LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
2106	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
2107	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
2108
2109	/*
2110	* Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
2111	* the new offset to let the guest not notice the pause.
2112	*/
2113	uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
2114	Assert(u64TscNew >= uPausedTscValue);
2115	LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
2116	pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
2117	pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
2118
2119	pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
2120
2121	/*
2122	* Set the flag to update the vTimer offset when the vCPU resumes for the first time
2123	* (needs to be done on the actual EMT).
2124	*/
2125	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2126	{
2127	PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
2128	pVCpuDst->nem.s.fVTimerOffUpdate = true;
2129	}
2130
2131	return VINF_SUCCESS;
2132	}
2133
2134
2135	/**
2136	* Returns features supported by the NEM backend.
2137	*
2138	* @returns Flags of features supported by the native NEM backend.
2139	* @param pVM The cross context VM structure.
2140	*/
2141	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
2142	{
2143	RT_NOREF(pVM);
2144	/*
2145	* Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
2146	* and unrestricted guest execution support so we can safely return these flags here always.
2147	*/
2148	return NEM_FEAT_F_NESTED_PAGING \| NEM_FEAT_F_FULL_GST_EXEC \| NEM_FEAT_F_XSAVE_XRSTOR;
2149	}
2150
2151
2152	/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
2153	*
2154	* @todo Add notes as the implementation progresses...
2155	*/
2156

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 100725

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