1 | /* $Id: NEMR3.cpp 86115 2020-09-14 06:52:26Z vboxsync $ */
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2 | /** @file
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3 | * NEM - Native execution manager.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2018-2020 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | /** @page pg_nem NEM - Native Execution Manager.
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19 | *
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20 | * This is an alternative execution manage to HM and raw-mode. On one host
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21 | * (Windows) we're forced to use this, on the others we just do it because we
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22 | * can. Since this is host specific in nature, information about an
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23 | * implementation is contained in the NEMR3Native-xxxx.cpp files.
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24 | *
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25 | * @ref pg_nem_win
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26 | */
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Header Files *
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31 | *********************************************************************************************************************************/
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32 | #define LOG_GROUP LOG_GROUP_NEM
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33 | #include <VBox/vmm/nem.h>
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34 | #include <VBox/vmm/gim.h>
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35 | #include "NEMInternal.h"
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36 | #include <VBox/vmm/vm.h>
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37 | #include <VBox/vmm/uvm.h>
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38 | #include <VBox/err.h>
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39 |
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40 | #include <iprt/asm.h>
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41 |
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42 |
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43 |
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44 | /**
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45 | * Basic init and configuration reading.
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46 | *
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47 | * Always call NEMR3Term after calling this.
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48 | *
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49 | * @returns VBox status code.
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50 | * @param pVM The cross context VM structure.
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51 | */
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52 | VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
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53 | {
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54 | LogFlow(("NEMR3Init\n"));
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55 |
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56 | /*
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57 | * Assert alignment and sizes.
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58 | */
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59 | AssertCompileMemberAlignment(VM, nem.s, 64);
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60 | AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
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61 |
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62 | /*
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63 | * Initialize state info so NEMR3Term will always be happy.
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64 | * No returning prior to setting magics!
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65 | */
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66 | pVM->nem.s.u32Magic = NEM_MAGIC;
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67 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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68 | {
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69 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
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70 | pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
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71 | }
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72 |
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73 | /*
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74 | * Read configuration.
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75 | */
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76 | PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
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77 |
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78 | /*
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79 | * Validate the NEM settings.
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80 | */
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81 | int rc = CFGMR3ValidateConfig(pCfgNem,
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82 | "/NEM/",
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83 | "Enabled"
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84 | "|Allow64BitGuests"
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85 | "|LovelyMesaDrvWorkaround"
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86 | #ifdef RT_OS_WINDOWS
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87 | "|UseRing0Runloop"
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88 | #endif
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89 | ,
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90 | "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
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91 | if (RT_FAILURE(rc))
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92 | return rc;
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93 |
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94 | /** @cfgm{/NEM/NEMEnabled, bool, true}
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95 | * Whether NEM is enabled. */
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96 | rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
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97 | AssertLogRelRCReturn(rc, rc);
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98 |
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99 |
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100 | #ifdef VBOX_WITH_64_BITS_GUESTS
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101 | /** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
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102 | * Enables AMD64 CPU features.
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103 | * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
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104 | * already have the support. */
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105 | rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
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106 | AssertLogRelRCReturn(rc, rc);
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107 | #else
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108 | pVM->nem.s.fAllow64BitGuests = false;
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109 | #endif
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110 |
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111 | /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
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112 | * Workaround for mesa vmsvga 3d driver making incorrect assumptions about
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113 | * the hypervisor it is running under. */
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114 | bool f;
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115 | rc = CFGMR3QueryBoolDef(pCfgNem, "LovelyMesaDrvWorkaround", &f, false);
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116 | AssertLogRelRCReturn(rc, rc);
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117 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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118 | {
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119 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
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120 | pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv = f;
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121 | }
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122 |
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123 | #ifdef RT_OS_WINDOWS
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124 | /** @cfgm{/NEM/UseRing0Runloop, bool, true}
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125 | * Whether to use the ring-0 runloop (if enabled in the build) or the ring-3 one.
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126 | * The latter is generally slower. This option serves as a way out in case
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127 | * something breaks in the ring-0 loop. */
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128 | # ifdef NEM_WIN_USE_RING0_RUNLOOP_BY_DEFAULT
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129 | bool fUseRing0Runloop = true;
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130 | # else
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131 | bool fUseRing0Runloop = false;
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132 | # endif
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133 | rc = CFGMR3QueryBoolDef(pCfgNem, "UseRing0Runloop", &fUseRing0Runloop, fUseRing0Runloop);
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134 | AssertLogRelRCReturn(rc, rc);
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135 | pVM->nem.s.fUseRing0Runloop = fUseRing0Runloop;
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136 | #endif
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137 |
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138 | return VINF_SUCCESS;
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139 | }
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140 |
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141 |
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142 | /**
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143 | * This is called by HMR3Init() when HM cannot be used.
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144 | *
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145 | * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
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146 | * native hypervisor API to execute the VM.
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147 | *
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148 | * @returns VBox status code.
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149 | * @param pVM The cross context VM structure.
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150 | * @param fFallback Whether this is a fallback call. Cleared if the VM is
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151 | * configured to use NEM instead of HM.
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152 | * @param fForced Whether /HM/HMForced was set. If set and we fail to
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153 | * enable NEM, we'll return a failure status code.
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154 | * Otherwise we'll assume HMR3Init falls back on raw-mode.
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155 | */
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156 | VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
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157 | {
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158 | Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
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159 | int rc;
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160 | if (pVM->nem.s.fEnabled)
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161 | {
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162 | #ifdef VBOX_WITH_NATIVE_NEM
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163 | rc = nemR3NativeInit(pVM, fFallback, fForced);
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164 | ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
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165 | #else
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166 | RT_NOREF(fFallback);
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167 | rc = VINF_SUCCESS;
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168 | #endif
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169 | if (RT_SUCCESS(rc))
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170 | {
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171 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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172 | LogRel(("NEM: NEMR3Init: Active.\n"));
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173 | else
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174 | {
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175 | LogRel(("NEM: NEMR3Init: Not available.\n"));
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176 | if (fForced)
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177 | rc = VERR_NEM_NOT_AVAILABLE;
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178 | }
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179 | }
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180 | else
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181 | LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
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182 | }
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183 | else
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184 | {
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185 | LogRel(("NEM: NEMR3Init: Disabled.\n"));
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186 | rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
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187 | }
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188 | return rc;
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189 | }
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190 |
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191 |
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192 | /**
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193 | * Perform initialization that depends on CPUM working.
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194 | *
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195 | * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
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196 | *
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197 | * @returns VBox status code.
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198 | * @param pVM The cross context VM structure.
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199 | */
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200 | VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
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201 | {
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202 | int rc = VINF_SUCCESS;
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203 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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204 | {
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205 | /*
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206 | * Enable CPU features making general ASSUMPTIONS (there are two similar
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207 | * blocks of code in HM.cpp), to avoid duplicating this code. The
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208 | * native backend can make check capabilities and adjust as needed.
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209 | */
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210 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
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211 | if ( CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD
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212 | || CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_HYGON)
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213 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
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214 | if (pVM->nem.s.fAllow64BitGuests)
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215 | {
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216 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
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217 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
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218 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
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219 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
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220 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
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221 | }
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222 | /* Turn on NXE if PAE has been enabled. */
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223 | else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
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224 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
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225 |
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226 | /*
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227 | * Do native after-CPUM init.
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228 | */
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229 | #ifdef VBOX_WITH_NATIVE_NEM
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230 | rc = nemR3NativeInitAfterCPUM(pVM);
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231 | #else
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232 | RT_NOREF(pVM);
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233 | #endif
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234 | }
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235 | return rc;
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236 | }
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237 |
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238 |
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239 | /**
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240 | * Called when a init phase has completed.
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241 | *
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242 | * @returns VBox status code.
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243 | * @param pVM The cross context VM structure.
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244 | * @param enmWhat The phase that completed.
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245 | */
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246 | VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
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247 | {
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248 | /*
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249 | * Check if GIM needs #UD, since that applies to everyone.
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250 | */
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251 | if (enmWhat == VMINITCOMPLETED_RING3)
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252 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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253 | {
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254 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
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255 | pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
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256 | }
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257 |
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258 | /*
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259 | * Call native code.
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260 | */
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261 | int rc = VINF_SUCCESS;
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262 | #ifdef VBOX_WITH_NATIVE_NEM
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263 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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264 | rc = nemR3NativeInitCompleted(pVM, enmWhat);
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265 | #else
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266 | RT_NOREF(pVM, enmWhat);
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267 | #endif
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268 | return rc;
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269 | }
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270 |
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271 |
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272 | /**
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273 | *
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274 | * @returns VBox status code.
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275 | * @param pVM The cross context VM structure.
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276 | */
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277 | VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
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278 | {
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279 | AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
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280 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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281 | AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
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282 |
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283 | /* Do native termination. */
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284 | int rc = VINF_SUCCESS;
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285 | #ifdef VBOX_WITH_NATIVE_NEM
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286 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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287 | rc = nemR3NativeTerm(pVM);
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288 | #endif
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289 |
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290 | /* Mark it as terminated. */
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291 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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292 | {
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293 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
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294 | pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
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295 | }
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296 | pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
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297 | return rc;
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298 | }
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299 |
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300 | /**
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301 | * External interface for querying whether native execution API is used.
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302 | *
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303 | * @returns true if NEM is being used, otherwise false.
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304 | * @param pUVM The user mode VM handle.
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305 | * @sa HMR3IsEnabled
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306 | */
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307 | VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
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308 | {
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309 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
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310 | PVM pVM = pUVM->pVM;
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311 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
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312 | return VM_IS_NEM_ENABLED(pVM);
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313 | }
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314 |
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315 |
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316 | /**
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317 | * The VM is being reset.
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318 | *
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319 | * @param pVM The cross context VM structure.
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320 | */
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321 | VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
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322 | {
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323 | #ifdef VBOX_WITH_NATIVE_NEM
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324 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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325 | nemR3NativeReset(pVM);
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326 | #else
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327 | RT_NOREF(pVM);
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328 | #endif
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329 | }
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330 |
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331 |
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332 | /**
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333 | * Resets a virtual CPU.
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334 | *
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335 | * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
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336 | *
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337 | * @param pVCpu The cross context virtual CPU structure to reset.
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338 | * @param fInitIpi Set if being reset due to INIT IPI.
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339 | */
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340 | VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
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341 | {
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342 | #ifdef VBOX_WITH_NATIVE_NEM
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343 | if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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344 | nemR3NativeResetCpu(pVCpu, fInitIpi);
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345 | #else
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346 | RT_NOREF(pVCpu, fInitIpi);
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347 | #endif
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348 | }
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349 |
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350 |
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351 | /**
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352 | * Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
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353 | *
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354 | * @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
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355 | * @param pVM The cross context VM structure.
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356 | */
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357 | VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
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358 | {
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359 | #ifdef VBOX_WITH_NATIVE_NEM
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360 | # ifdef RT_OS_WINDOWS
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361 | if (VM_IS_NEM_ENABLED(pVM))
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362 | return true;
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363 | # endif
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364 | #else
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365 | RT_NOREF(pVM);
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366 | #endif
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367 | return false;
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368 | }
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369 |
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370 |
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371 | /**
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372 | * Gets the name of a generic NEM exit code.
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373 | *
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374 | * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
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375 | * @param uExit The NEM exit to name.
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376 | */
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377 | VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
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378 | {
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379 | switch ((NEMEXITTYPE)uExit)
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380 | {
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381 | case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
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382 | case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
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383 | case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
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384 | case NEMEXITTYPE_HALT: return "NEM halt";
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385 | case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
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386 | case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
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387 | case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
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388 | case NEMEXITTYPE_CANCELED: return "NEM canceled";
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389 | case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
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390 | }
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391 |
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392 | return NULL;
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393 | }
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394 |
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395 |
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396 | VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
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397 | {
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398 | Assert(VM_IS_NEM_ENABLED(pVM));
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399 | #ifdef VBOX_WITH_NATIVE_NEM
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400 | return nemR3NativeRunGC(pVM, pVCpu);
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401 | #else
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402 | NOREF(pVM); NOREF(pVCpu);
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403 | return VERR_INTERNAL_ERROR_3;
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404 | #endif
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405 | }
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406 |
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407 |
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408 | VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
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409 | {
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410 | Assert(VM_IS_NEM_ENABLED(pVM));
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411 | #ifdef VBOX_WITH_NATIVE_NEM
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412 | return nemR3NativeCanExecuteGuest(pVM, pVCpu);
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413 | #else
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414 | NOREF(pVM); NOREF(pVCpu);
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415 | return false;
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416 | #endif
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417 | }
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418 |
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419 |
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420 | VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
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421 | {
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422 | Assert(VM_IS_NEM_ENABLED(pVM));
|
---|
423 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
424 | return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
|
---|
425 | #else
|
---|
426 | NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
|
---|
427 | return false;
|
---|
428 | #endif
|
---|
429 | }
|
---|
430 |
|
---|
431 |
|
---|
432 | VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
|
---|
433 | {
|
---|
434 | AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
|
---|
435 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
436 | nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
|
---|
437 | #else
|
---|
438 | RT_NOREF(pVM, pVCpu, fFlags);
|
---|
439 | #endif
|
---|
440 | }
|
---|
441 |
|
---|
442 |
|
---|
443 |
|
---|
444 |
|
---|
445 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
|
---|
446 | {
|
---|
447 | int rc = VINF_SUCCESS;
|
---|
448 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
449 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
|
---|
450 | rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
|
---|
451 | #else
|
---|
452 | NOREF(pVM); NOREF(GCPhys); NOREF(cb);
|
---|
453 | #endif
|
---|
454 | return rc;
|
---|
455 | }
|
---|
456 |
|
---|
457 |
|
---|
458 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
|
---|
459 | {
|
---|
460 | int rc = VINF_SUCCESS;
|
---|
461 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
462 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
|
---|
463 | rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
|
---|
464 | #else
|
---|
465 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
|
---|
466 | #endif
|
---|
467 | return rc;
|
---|
468 | }
|
---|
469 |
|
---|
470 |
|
---|
471 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
|
---|
472 | {
|
---|
473 | int rc = VINF_SUCCESS;
|
---|
474 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
475 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
|
---|
476 | rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
|
---|
477 | #else
|
---|
478 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
|
---|
479 | #endif
|
---|
480 | return rc;
|
---|
481 | }
|
---|
482 |
|
---|
483 |
|
---|
484 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
|
---|
485 | {
|
---|
486 | int rc = VINF_SUCCESS;
|
---|
487 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
488 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
|
---|
489 | rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
|
---|
490 | #else
|
---|
491 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
|
---|
492 | #endif
|
---|
493 | return rc;
|
---|
494 | }
|
---|
495 |
|
---|
496 |
|
---|
497 | /**
|
---|
498 | * Called after the ROM range has been fully completed.
|
---|
499 | *
|
---|
500 | * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
|
---|
501 | * number of NEMHCNotifyPhysPageProtChanged calls.
|
---|
502 | *
|
---|
503 | * @returns VBox status code
|
---|
504 | * @param pVM The cross context VM structure.
|
---|
505 | * @param GCPhys The ROM address (page aligned).
|
---|
506 | * @param cb The size (page aligned).
|
---|
507 | * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
|
---|
508 | */
|
---|
509 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
|
---|
510 | {
|
---|
511 | int rc = VINF_SUCCESS;
|
---|
512 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
513 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
|
---|
514 | rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
|
---|
515 | #else
|
---|
516 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
|
---|
517 | #endif
|
---|
518 | return rc;
|
---|
519 | }
|
---|
520 |
|
---|
521 |
|
---|
522 | VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
|
---|
523 | {
|
---|
524 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
525 | if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
|
---|
526 | nemR3NativeNotifySetA20(pVCpu, fEnabled);
|
---|
527 | #else
|
---|
528 | NOREF(pVCpu); NOREF(fEnabled);
|
---|
529 | #endif
|
---|
530 | }
|
---|
531 |
|
---|