VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 86018

Last change on this file since 86018 was 86018, checked in by vboxsync, 4 years ago

NEM/Hyper-V: Make the unmap pages hack threshold configurable bugref:9044
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1/* $Id: NEMR3.cpp 86018 2020-09-03 09:13:51Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager.
4 */
5
6/*
7 * Copyright (C) 2018-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_nem NEM - Native Execution Manager.
19 *
20 * This is an alternative execution manage to HM and raw-mode. On one host
21 * (Windows) we're forced to use this, on the others we just do it because we
22 * can. Since this is host specific in nature, information about an
23 * implementation is contained in the NEMR3Native-xxxx.cpp files.
24 *
25 * @ref pg_nem_win
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_NEM
33#include <VBox/vmm/nem.h>
34#include <VBox/vmm/gim.h>
35#include "NEMInternal.h"
36#include <VBox/vmm/vm.h>
37#include <VBox/vmm/uvm.h>
38#include <VBox/err.h>
39
40#include <iprt/asm.h>
41
42
43
44/**
45 * Basic init and configuration reading.
46 *
47 * Always call NEMR3Term after calling this.
48 *
49 * @returns VBox status code.
50 * @param pVM The cross context VM structure.
51 */
52VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
53{
54 LogFlow(("NEMR3Init\n"));
55
56 /*
57 * Assert alignment and sizes.
58 */
59 AssertCompileMemberAlignment(VM, nem.s, 64);
60 AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
61
62 /*
63 * Initialize state info so NEMR3Term will always be happy.
64 * No returning prior to setting magics!
65 */
66 pVM->nem.s.u32Magic = NEM_MAGIC;
67 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
68 {
69 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
70 pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
71 }
72
73 /*
74 * Read configuration.
75 */
76 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
77
78 /*
79 * Validate the NEM settings.
80 */
81 int rc = CFGMR3ValidateConfig(pCfgNem,
82 "/NEM/",
83 "Enabled"
84 "|Allow64BitGuests"
85#ifdef RT_OS_WINDOWS
86 "|UseRing0Runloop"
87 "|MaxPagesMappedBeforeUnmap"
88#endif
89 ,
90 "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
91 if (RT_FAILURE(rc))
92 return rc;
93
94 /** @cfgm{/NEM/NEMEnabled, bool, true}
95 * Whether NEM is enabled. */
96 rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
97 AssertLogRelRCReturn(rc, rc);
98
99
100#ifdef VBOX_WITH_64_BITS_GUESTS
101 /** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
102 * Enables AMD64 CPU features.
103 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
104 * already have the support. */
105 rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
106 AssertLogRelRCReturn(rc, rc);
107#else
108 pVM->nem.s.fAllow64BitGuests = false;
109#endif
110
111#ifdef RT_OS_WINDOWS
112 /** @cfgm{/NEM/UseRing0Runloop, bool, true}
113 * Whether to use the ring-0 runloop (if enabled in the build) or the ring-3 one.
114 * The latter is generally slower. This option serves as a way out in case
115 * something breaks in the ring-0 loop. */
116# ifdef NEM_WIN_USE_RING0_RUNLOOP_BY_DEFAULT
117 bool fUseRing0Runloop = true;
118# else
119 bool fUseRing0Runloop = false;
120# endif
121 rc = CFGMR3QueryBoolDef(pCfgNem, "UseRing0Runloop", &fUseRing0Runloop, fUseRing0Runloop);
122 AssertLogRelRCReturn(rc, rc);
123 pVM->nem.s.fUseRing0Runloop = fUseRing0Runloop;
124
125 /** @cfgm{/NEM/MaxPagesMappedBeforeUnmap, bool, true}
126 * Maximum nuber of pages mapped before into the Hv partition before
127 * unmapping verything and starting from the beginning
128 * @bugref{9044}. */
129 uint32_t cMappedPagesMaxBeforeUnmap = 0;
130 rc = CFGMR3QueryU32Def(pCfgNem, "MaxPagesMappedBeforeUnmap", &cMappedPagesMaxBeforeUnmap, 0);
131 AssertLogRelRCReturn(rc, rc);
132
133 if ( cMappedPagesMaxBeforeUnmap < 4000
134 && cMappedPagesMaxBeforeUnmap != 0)
135 {
136 LogRel(("NEM: MaxPagesMappedBeforeUnmap too small %u, setting to 4000\n", cMappedPagesMaxBeforeUnmap));
137 cMappedPagesMaxBeforeUnmap = 4000;
138 }
139
140 LogRel(("NEM: cMappedPagesMaxBeforeUnmap=%u\n", cMappedPagesMaxBeforeUnmap));
141 pVM->nem.s.cMappedPagesMaxBeforeUnmap = cMappedPagesMaxBeforeUnmap;
142#endif
143
144 return VINF_SUCCESS;
145}
146
147
148/**
149 * This is called by HMR3Init() when HM cannot be used.
150 *
151 * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
152 * native hypervisor API to execute the VM.
153 *
154 * @returns VBox status code.
155 * @param pVM The cross context VM structure.
156 * @param fFallback Whether this is a fallback call. Cleared if the VM is
157 * configured to use NEM instead of HM.
158 * @param fForced Whether /HM/HMForced was set. If set and we fail to
159 * enable NEM, we'll return a failure status code.
160 * Otherwise we'll assume HMR3Init falls back on raw-mode.
161 */
162VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
163{
164 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
165 int rc;
166 if (pVM->nem.s.fEnabled)
167 {
168#ifdef VBOX_WITH_NATIVE_NEM
169 rc = nemR3NativeInit(pVM, fFallback, fForced);
170 ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
171#else
172 RT_NOREF(fFallback);
173 rc = VINF_SUCCESS;
174#endif
175 if (RT_SUCCESS(rc))
176 {
177 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
178 LogRel(("NEM: NEMR3Init: Active.\n"));
179 else
180 {
181 LogRel(("NEM: NEMR3Init: Not available.\n"));
182 if (fForced)
183 rc = VERR_NEM_NOT_AVAILABLE;
184 }
185 }
186 else
187 LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
188 }
189 else
190 {
191 LogRel(("NEM: NEMR3Init: Disabled.\n"));
192 rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
193 }
194 return rc;
195}
196
197
198/**
199 * Perform initialization that depends on CPUM working.
200 *
201 * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
202 *
203 * @returns VBox status code.
204 * @param pVM The cross context VM structure.
205 */
206VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
207{
208 int rc = VINF_SUCCESS;
209 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
210 {
211 /*
212 * Enable CPU features making general ASSUMPTIONS (there are two similar
213 * blocks of code in HM.cpp), to avoid duplicating this code. The
214 * native backend can make check capabilities and adjust as needed.
215 */
216 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
217 if ( CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD
218 || CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_HYGON)
219 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
220 if (pVM->nem.s.fAllow64BitGuests)
221 {
222 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
223 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
224 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
225 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
226 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
227 }
228 /* Turn on NXE if PAE has been enabled. */
229 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
230 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
231
232 /*
233 * Do native after-CPUM init.
234 */
235#ifdef VBOX_WITH_NATIVE_NEM
236 rc = nemR3NativeInitAfterCPUM(pVM);
237#else
238 RT_NOREF(pVM);
239#endif
240 }
241 return rc;
242}
243
244
245/**
246 * Called when a init phase has completed.
247 *
248 * @returns VBox status code.
249 * @param pVM The cross context VM structure.
250 * @param enmWhat The phase that completed.
251 */
252VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
253{
254 /*
255 * Check if GIM needs #UD, since that applies to everyone.
256 */
257 if (enmWhat == VMINITCOMPLETED_RING3)
258 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
259 {
260 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
261 pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
262 }
263
264 /*
265 * Call native code.
266 */
267 int rc = VINF_SUCCESS;
268#ifdef VBOX_WITH_NATIVE_NEM
269 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
270 rc = nemR3NativeInitCompleted(pVM, enmWhat);
271#else
272 RT_NOREF(pVM, enmWhat);
273#endif
274 return rc;
275}
276
277
278/**
279 *
280 * @returns VBox status code.
281 * @param pVM The cross context VM structure.
282 */
283VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
284{
285 AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
286 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
287 AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
288
289 /* Do native termination. */
290 int rc = VINF_SUCCESS;
291#ifdef VBOX_WITH_NATIVE_NEM
292 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
293 rc = nemR3NativeTerm(pVM);
294#endif
295
296 /* Mark it as terminated. */
297 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
298 {
299 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
300 pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
301 }
302 pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
303 return rc;
304}
305
306/**
307 * External interface for querying whether native execution API is used.
308 *
309 * @returns true if NEM is being used, otherwise false.
310 * @param pUVM The user mode VM handle.
311 * @sa HMR3IsEnabled
312 */
313VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
314{
315 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
316 PVM pVM = pUVM->pVM;
317 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
318 return VM_IS_NEM_ENABLED(pVM);
319}
320
321
322/**
323 * The VM is being reset.
324 *
325 * @param pVM The cross context VM structure.
326 */
327VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
328{
329#ifdef VBOX_WITH_NATIVE_NEM
330 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
331 nemR3NativeReset(pVM);
332#else
333 RT_NOREF(pVM);
334#endif
335}
336
337
338/**
339 * Resets a virtual CPU.
340 *
341 * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
342 *
343 * @param pVCpu The cross context virtual CPU structure to reset.
344 * @param fInitIpi Set if being reset due to INIT IPI.
345 */
346VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
347{
348#ifdef VBOX_WITH_NATIVE_NEM
349 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
350 nemR3NativeResetCpu(pVCpu, fInitIpi);
351#else
352 RT_NOREF(pVCpu, fInitIpi);
353#endif
354}
355
356
357/**
358 * Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
359 *
360 * @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
361 * @param pVM The cross context VM structure.
362 */
363VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
364{
365#ifdef VBOX_WITH_NATIVE_NEM
366# ifdef RT_OS_WINDOWS
367 if (VM_IS_NEM_ENABLED(pVM))
368 return true;
369# endif
370#else
371 RT_NOREF(pVM);
372#endif
373 return false;
374}
375
376
377/**
378 * Gets the name of a generic NEM exit code.
379 *
380 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
381 * @param uExit The NEM exit to name.
382 */
383VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
384{
385 switch ((NEMEXITTYPE)uExit)
386 {
387 case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
388 case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
389 case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
390 case NEMEXITTYPE_HALT: return "NEM halt";
391 case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
392 case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
393 case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
394 case NEMEXITTYPE_CANCELED: return "NEM canceled";
395 case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
396 }
397
398 return NULL;
399}
400
401
402VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
403{
404 Assert(VM_IS_NEM_ENABLED(pVM));
405#ifdef VBOX_WITH_NATIVE_NEM
406 return nemR3NativeRunGC(pVM, pVCpu);
407#else
408 NOREF(pVM); NOREF(pVCpu);
409 return VERR_INTERNAL_ERROR_3;
410#endif
411}
412
413
414VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
415{
416 Assert(VM_IS_NEM_ENABLED(pVM));
417#ifdef VBOX_WITH_NATIVE_NEM
418 return nemR3NativeCanExecuteGuest(pVM, pVCpu);
419#else
420 NOREF(pVM); NOREF(pVCpu);
421 return false;
422#endif
423}
424
425
426VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
427{
428 Assert(VM_IS_NEM_ENABLED(pVM));
429#ifdef VBOX_WITH_NATIVE_NEM
430 return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
431#else
432 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
433 return false;
434#endif
435}
436
437
438VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
439{
440 AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
441#ifdef VBOX_WITH_NATIVE_NEM
442 nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
443#else
444 RT_NOREF(pVM, pVCpu, fFlags);
445#endif
446}
447
448
449
450
451VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
452{
453 int rc = VINF_SUCCESS;
454#ifdef VBOX_WITH_NATIVE_NEM
455 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
456 rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
457#else
458 NOREF(pVM); NOREF(GCPhys); NOREF(cb);
459#endif
460 return rc;
461}
462
463
464VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
465{
466 int rc = VINF_SUCCESS;
467#ifdef VBOX_WITH_NATIVE_NEM
468 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
469 rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
470#else
471 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
472#endif
473 return rc;
474}
475
476
477VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
478{
479 int rc = VINF_SUCCESS;
480#ifdef VBOX_WITH_NATIVE_NEM
481 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
482 rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
483#else
484 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
485#endif
486 return rc;
487}
488
489
490VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
491{
492 int rc = VINF_SUCCESS;
493#ifdef VBOX_WITH_NATIVE_NEM
494 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
495 rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
496#else
497 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
498#endif
499 return rc;
500}
501
502
503/**
504 * Called after the ROM range has been fully completed.
505 *
506 * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
507 * number of NEMHCNotifyPhysPageProtChanged calls.
508 *
509 * @returns VBox status code
510 * @param pVM The cross context VM structure.
511 * @param GCPhys The ROM address (page aligned).
512 * @param cb The size (page aligned).
513 * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
514 */
515VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
516{
517 int rc = VINF_SUCCESS;
518#ifdef VBOX_WITH_NATIVE_NEM
519 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
520 rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
521#else
522 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
523#endif
524 return rc;
525}
526
527
528VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
529{
530#ifdef VBOX_WITH_NATIVE_NEM
531 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
532 nemR3NativeNotifySetA20(pVCpu, fEnabled);
533#else
534 NOREF(pVCpu); NOREF(fEnabled);
535#endif
536}
537
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