NEMR3.cpp@ 94617

Last change on this file since 94617 was 93905, checked in by vboxsync, 3 years ago
VMM: More arm tweaks. bugref:9898
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1	/* $Id: NEMR3.cpp 93905 2022-02-24 09:13:26Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager.
4	*/
5
6	/*
7	* Copyright (C) 2018-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_nem NEM - Native Execution Manager.
19	*
20	* This is an alternative execution manage to HM and raw-mode. On one host
21	* (Windows) we're forced to use this, on the others we just do it because we
22	* can. Since this is host specific in nature, information about an
23	* implementation is contained in the NEMR3Native-xxxx.cpp files.
24	*
25	* @ref pg_nem_win
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_NEM
33	#include <VBox/vmm/dbgf.h>
34	#include <VBox/vmm/nem.h>
35	#include <VBox/vmm/gim.h>
36	#include "NEMInternal.h"
37	#include <VBox/vmm/vm.h>
38	#include <VBox/vmm/uvm.h>
39	#include <VBox/err.h>
40
41	#include <iprt/asm.h>
42
43
44
45	/**
46	* Basic init and configuration reading.
47	*
48	* Always call NEMR3Term after calling this.
49	*
50	* @returns VBox status code.
51	* @param pVM The cross context VM structure.
52	*/
53	VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
54	{
55	LogFlow(("NEMR3Init\n"));
56
57	/*
58	* Assert alignment and sizes.
59	*/
60	AssertCompileMemberAlignment(VM, nem.s, 64);
61	AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
62
63	/*
64	* Initialize state info so NEMR3Term will always be happy.
65	* No returning prior to setting magics!
66	*/
67	pVM->nem.s.u32Magic = NEM_MAGIC;
68	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
69	{
70	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
71	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
72	}
73
74	/*
75	* Read configuration.
76	*/
77	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
78
79	/*
80	* Validate the NEM settings.
81	*/
82	int rc = CFGMR3ValidateConfig(pCfgNem,
83	"/NEM/",
84	"Enabled"
85	"\|Allow64BitGuests"
86	"\|LovelyMesaDrvWorkaround"
87	#ifdef RT_OS_WINDOWS
88	"\|UseRing0Runloop"
89	#elif defined(RT_OS_DARWIN)
90	"\|VmxPleGap"
91	"\|VmxPleWindow"
92	"\|VmxLbr"
93	#endif
94	,
95	"" /* pszValidNodes /, "NEM" / pszWho /, 0 / uInstance */);
96	if (RT_FAILURE(rc))
97	return rc;
98
99	/** @cfgm{/NEM/NEMEnabled, bool, true}
100	* Whether NEM is enabled. */
101	rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
102	AssertLogRelRCReturn(rc, rc);
103
104
105	#ifdef VBOX_WITH_64_BITS_GUESTS
106	/** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
107	* Enables AMD64 CPU features.
108	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
109	* already have the support. */
110	rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
111	AssertLogRelRCReturn(rc, rc);
112	#else
113	pVM->nem.s.fAllow64BitGuests = false;
114	#endif
115
116	/** @cfgm{/NEM/LovelyMesaDrvWorkaround, bool, false}
117	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
118	* the hypervisor it is running under. */
119	bool f;
120	rc = CFGMR3QueryBoolDef(pCfgNem, "LovelyMesaDrvWorkaround", &f, false);
121	AssertLogRelRCReturn(rc, rc);
122	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
123	{
124	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
125	pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv = f;
126	}
127
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	* This is called by HMR3Init() when HM cannot be used.
134	*
135	* Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
136	* native hypervisor API to execute the VM.
137	*
138	* @returns VBox status code.
139	* @param pVM The cross context VM structure.
140	* @param fFallback Whether this is a fallback call. Cleared if the VM is
141	* configured to use NEM instead of HM.
142	* @param fForced Whether /HM/HMForced was set. If set and we fail to
143	* enable NEM, we'll return a failure status code.
144	* Otherwise we'll assume HMR3Init falls back on raw-mode.
145	*/
146	VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
147	{
148	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
149	int rc;
150	if (pVM->nem.s.fEnabled)
151	{
152	#ifdef VBOX_WITH_NATIVE_NEM
153	rc = nemR3NativeInit(pVM, fFallback, fForced);
154	ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
155	#else
156	RT_NOREF(fFallback);
157	rc = VINF_SUCCESS;
158	#endif
159	if (RT_SUCCESS(rc))
160	{
161	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
162	{
163	#ifdef RT_OS_WINDOWS /* The WHv* API is extremely slow at handling VM exits. The AppleHv and
164	KVM APIs are much faster, thus the different mode name. :-) */
165	LogRel(("NEM:\n"
166	"NEM: NEMR3Init: Snail execution mode is active!\n"
167	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
168	"NEM: To see VirtualBox run at max speed you need to disable all Windows features\n"
169	"NEM: making use of Hyper-V. That is a moving target, so google how and carefully\n"
170	"NEM: consider the consequences of disabling these features.\n"
171	"NEM:\n"));
172	#else
173	LogRel(("NEM:\n"
174	"NEM: NEMR3Init: Turtle execution mode is active!\n"
175	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
176	"NEM:\n"));
177	#endif
178	}
179	else
180	{
181	LogRel(("NEM: NEMR3Init: Not available.\n"));
182	if (fForced)
183	rc = VERR_NEM_NOT_AVAILABLE;
184	}
185	}
186	else
187	LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
188	}
189	else
190	{
191	LogRel(("NEM: NEMR3Init: Disabled.\n"));
192	rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
193	}
194	return rc;
195	}
196
197
198	/**
199	* Perform initialization that depends on CPUM working.
200	*
201	* This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
202	*
203	* @returns VBox status code.
204	* @param pVM The cross context VM structure.
205	*/
206	VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
207	{
208	int rc = VINF_SUCCESS;
209	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
210	{
211	/*
212	* Enable CPU features making general ASSUMPTIONS (there are two similar
213	* blocks of code in HM.cpp), to avoid duplicating this code. The
214	* native backend can make check capabilities and adjust as needed.
215	*/
216	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
217	if ( CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD
218	\|\| CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_HYGON)
219	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
220	if (pVM->nem.s.fAllow64BitGuests)
221	{
222	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
223	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
224	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
225	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
226	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
227	}
228	/* Turn on NXE if PAE has been enabled. */
229	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
230	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
231
232	/*
233	* Do native after-CPUM init.
234	*/
235	#ifdef VBOX_WITH_NATIVE_NEM
236	rc = nemR3NativeInitAfterCPUM(pVM);
237	#else
238	RT_NOREF(pVM);
239	#endif
240	}
241	return rc;
242	}
243
244
245	/**
246	* Called when a init phase has completed.
247	*
248	* @returns VBox status code.
249	* @param pVM The cross context VM structure.
250	* @param enmWhat The phase that completed.
251	*/
252	VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
253	{
254	/*
255	* Check if GIM needs #UD, since that applies to everyone.
256	*/
257	if (enmWhat == VMINITCOMPLETED_RING3)
258	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
259	{
260	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
261	pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
262	}
263
264	/*
265	* Call native code.
266	*/
267	int rc = VINF_SUCCESS;
268	#ifdef VBOX_WITH_NATIVE_NEM
269	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
270	rc = nemR3NativeInitCompleted(pVM, enmWhat);
271	#else
272	RT_NOREF(pVM, enmWhat);
273	#endif
274	return rc;
275	}
276
277
278	/**
279	*
280	* @returns VBox status code.
281	* @param pVM The cross context VM structure.
282	*/
283	VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
284	{
285	AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
286	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
287	AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
288
289	/* Do native termination. */
290	int rc = VINF_SUCCESS;
291	#ifdef VBOX_WITH_NATIVE_NEM
292	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
293	rc = nemR3NativeTerm(pVM);
294	#endif
295
296	/* Mark it as terminated. */
297	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
298	{
299	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
300	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
301	}
302	pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
303	return rc;
304	}
305
306	/**
307	* External interface for querying whether native execution API is used.
308	*
309	* @returns true if NEM is being used, otherwise false.
310	* @param pUVM The user mode VM handle.
311	* @sa HMR3IsEnabled
312	*/
313	VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
314	{
315	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
316	PVM pVM = pUVM->pVM;
317	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
318	return VM_IS_NEM_ENABLED(pVM);
319	}
320
321
322	/**
323	* The VM is being reset.
324	*
325	* @param pVM The cross context VM structure.
326	*/
327	VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
328	{
329	#ifdef VBOX_WITH_NATIVE_NEM
330	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
331	nemR3NativeReset(pVM);
332	#else
333	RT_NOREF(pVM);
334	#endif
335	}
336
337
338	/**
339	* Resets a virtual CPU.
340	*
341	* Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
342	*
343	* @param pVCpu The cross context virtual CPU structure to reset.
344	* @param fInitIpi Set if being reset due to INIT IPI.
345	*/
346	VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
347	{
348	#ifdef VBOX_WITH_NATIVE_NEM
349	if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
350	nemR3NativeResetCpu(pVCpu, fInitIpi);
351	#else
352	RT_NOREF(pVCpu, fInitIpi);
353	#endif
354	}
355
356
357	/**
358	* Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
359	*
360	* @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
361	* @param pVM The cross context VM structure.
362	*/
363	VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
364	{
365	#ifdef VBOX_WITH_NATIVE_NEM
366	if (VM_IS_NEM_ENABLED(pVM))
367	return true;
368	#else
369	RT_NOREF(pVM);
370	#endif
371	return false;
372	}
373
374
375	/**
376	* Gets the name of a generic NEM exit code.
377	*
378	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
379	* @param uExit The NEM exit to name.
380	*/
381	VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
382	{
383	switch ((NEMEXITTYPE)uExit)
384	{
385	case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
386	case NEMEXITTYPE_HALT: return "NEM halt";
387
388	case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
389	case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
390	case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
391	case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
392	case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
393	case NEMEXITTYPE_CANCELED: return "NEM canceled";
394	case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
395
396	case NEMEXITTYPE_INTERNAL_ERROR_EMULATION: return "NEM emulation IPE";
397	case NEMEXITTYPE_INTERNAL_ERROR_FATAL: return "NEM fatal IPE";
398	case NEMEXITTYPE_INTERRUPTED: return "NEM interrupted";
399	case NEMEXITTYPE_FAILED_ENTRY: return "NEM failed VT-x/AMD-V entry";
400
401	case NEMEXITTYPE_INVALID:
402	case NEMEXITTYPE_END:
403	break;
404	}
405
406	return NULL;
407	}
408
409
410	VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
411	{
412	Assert(VM_IS_NEM_ENABLED(pVM));
413	#ifdef VBOX_WITH_NATIVE_NEM
414	return nemR3NativeRunGC(pVM, pVCpu);
415	#else
416	NOREF(pVM); NOREF(pVCpu);
417	return VERR_INTERNAL_ERROR_3;
418	#endif
419	}
420
421
422	#ifndef VBOX_WITH_NATIVE_NEM
423	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
424	{
425	RT_NOREF(pVM, pVCpu);
426	return false;
427	}
428	#endif
429
430
431	VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
432	{
433	Assert(VM_IS_NEM_ENABLED(pVM));
434	#ifdef VBOX_WITH_NATIVE_NEM
435	return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
436	#else
437	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
438	return false;
439	#endif
440	}
441
442
443	VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
444	{
445	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
446	#ifdef VBOX_WITH_NATIVE_NEM
447	nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
448	#else
449	RT_NOREF(pVM, pVCpu, fFlags);
450	#endif
451	}
452
453	#ifndef VBOX_WITH_NATIVE_NEM
454
455	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
456	{
457	RT_NOREF(pVCpu, fEnabled);
458	}
459
460	# ifdef VBOX_WITH_PGM_NEM_MODE
461
462	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
463	{
464	RT_NOREF(pVM);
465	return false;
466	}
467
468
469	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
470	void *pvBitmap, size_t cbBitmap)
471	{
472	RT_NOREF(pVM, GCPhys, cb, uNemRange, pvBitmap, cbBitmap);
473	AssertFailed();
474	return VERR_INTERNAL_ERROR_2;
475	}
476
477
478	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
479	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
480	{
481	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange);
482	AssertFailed();
483	return VERR_INTERNAL_ERROR_2;
484	}
485
486	# endif /* VBOX_WITH_PGM_NEM_MODE */
487	#endif /* !VBOX_WITH_NATIVE_NEM */
488
489	/**
490	* Notification callback from DBGF when interrupt breakpoints or generic debug
491	* event settings changes.
492	*
493	* DBGF will call NEMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
494	* function is just updating the VM globals.
495	*
496	* @param pVM The VM cross context VM structure.
497	* @thread EMT(0)
498	*/
499	VMMR3_INT_DECL(void) NEMR3NotifyDebugEventChanged(PVM pVM)
500	{
501	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
502
503	#ifdef VBOX_WITH_NATIVE_NEM
504	/* Interrupts. */
505	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
506	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
507
508	/* CPU Exceptions. */
509	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
510	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
511	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
512	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
513
514	/* Common VM exits. */
515	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
516	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
517	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
518	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
519
520	/* Done. */
521	pVM->nem.s.fUseDebugLoop = nemR3NativeNotifyDebugEventChanged(pVM, fUseDebugLoop);
522	#else
523	RT_NOREF(pVM);
524	#endif
525	}
526
527
528	/**
529	* Follow up notification callback to NEMR3NotifyDebugEventChanged for each CPU.
530	*
531	* NEM uses this to combine the decision made NEMR3NotifyDebugEventChanged with
532	* per CPU settings.
533	*
534	* @param pVM The VM cross context VM structure.
535	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
536	*/
537	VMMR3_INT_DECL(void) NEMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
538	{
539	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
540
541	#ifdef VBOX_WITH_NATIVE_NEM
542	pVCpu->nem.s.fUseDebugLoop = nemR3NativeNotifyDebugEventChangedPerCpu(pVM, pVCpu,
543	pVCpu->nem.s.fSingleInstruction \| pVM->nem.s.fUseDebugLoop);
544	#else
545	RT_NOREF(pVM, pVCpu);
546	#endif
547	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 94617

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