IOMR3IoPort.cpp@ 106022

Last change on this file since 106022 was 103407, checked in by vboxsync, 10 months ago
VMM/IOMR3IoPort.cpp: Typo, bugref:3409
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1	/* $Id: IOMR3IoPort.cpp 103407 2024-02-18 17:23:23Z vboxsync $ */
2	/** @file
3	* IOM - Input / Output Monitor, I/O port related APIs.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_IOM_IOPORT
33	#include <VBox/vmm/iom.h>
34	#include <VBox/sup.h>
35	#include <VBox/vmm/mm.h>
36	#include <VBox/vmm/stam.h>
37	#include <VBox/vmm/dbgf.h>
38	#include <VBox/vmm/pdmapi.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include "IOMInternal.h"
41	#include <VBox/vmm/vm.h>
42
43	#include <VBox/param.h>
44	#include <iprt/assert.h>
45	#include <iprt/mem.h>
46	#include <iprt/string.h>
47	#include <VBox/log.h>
48	#include <VBox/err.h>
49
50	#include "IOMInline.h"
51
52
53	#ifdef VBOX_WITH_STATISTICS
54
55	/**
56	* Register statistics for an I/O port entry.
57	*/
58	void iomR3IoPortRegStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry)
59	{
60	bool const fDoRZ = pRegEntry->fRing0 \|\| pRegEntry->fRawMode;
61	PIOMIOPORTSTATSENTRY pStats = &pVM->iom.s.paIoPortStats[pRegEntry->idxStats];
62	PCIOMIOPORTDESC pExtDesc = pRegEntry->paExtDescs;
63	unsigned uPort = pRegEntry->uPort;
64	unsigned const uFirstPort = uPort;
65	unsigned const uEndPort = uPort + pRegEntry->cPorts;
66
67	/* Register a dummy statistics for the prefix. */
68	char szName[80];
69	size_t cchPrefix;
70	if (uFirstPort < uEndPort - 1)
71	cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/IoPorts/%04x-%04x", uFirstPort, uEndPort - 1);
72	else
73	cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/IoPorts/%04x", uPort);
74	const char *pszDesc = pRegEntry->pszDesc;
75	char *pszFreeDesc = NULL;
76	if (pRegEntry->pDevIns && pRegEntry->pDevIns->iInstance > 0 && pszDesc)
77	pszDesc = pszFreeDesc = RTStrAPrintf2("%u / %s", pRegEntry->pDevIns->iInstance, pszDesc);
78	int rc = STAMR3Register(pVM, &pStats->Total, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName,
79	STAMUNIT_NONE, pRegEntry->pszDesc);
80	AssertRC(rc);
81	RTStrFree(pszFreeDesc);
82
83	/* Register stats for each port under it */
84	do
85	{
86	size_t cchBaseNm;
87	if (uFirstPort < uEndPort - 1)
88	cchBaseNm = cchPrefix + RTStrPrintf(&szName[cchPrefix], sizeof(szName) - cchPrefix, "/%04x-", uPort);
89	else
90	{
91	szName[cchPrefix] = '/';
92	cchBaseNm = cchPrefix + 1;
93	}
94
95	# define SET_NM_SUFFIX(a_sz) memcpy(&szName[cchBaseNm], a_sz, sizeof(a_sz));
96	const char * const pszInDesc = pExtDesc ? pExtDesc->pszIn : NULL;
97	const char * const pszOutDesc = pExtDesc ? pExtDesc->pszOut : NULL;
98
99	/* register the statistics counters. */
100	SET_NM_SUFFIX("In-R3");
101	rc = STAMR3Register(pVM, &pStats->InR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
102	SET_NM_SUFFIX("Out-R3");
103	rc = STAMR3Register(pVM, &pStats->OutR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
104	if (fDoRZ)
105	{
106	SET_NM_SUFFIX("In-RZ");
107	rc = STAMR3Register(pVM, &pStats->InRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
108	SET_NM_SUFFIX("Out-RZ");
109	rc = STAMR3Register(pVM, &pStats->OutRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
110	SET_NM_SUFFIX("In-RZtoR3");
111	rc = STAMR3Register(pVM, &pStats->InRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
112	SET_NM_SUFFIX("Out-RZtoR3");
113	rc = STAMR3Register(pVM, &pStats->OutRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
114	}
115
116	/* Profiling */
117	SET_NM_SUFFIX("In-R3-Prof");
118	rc = STAMR3Register(pVM, &pStats->ProfInR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
119	SET_NM_SUFFIX("Out-R3-Prof");
120	rc = STAMR3Register(pVM, &pStats->ProfOutR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
121	if (fDoRZ)
122	{
123	SET_NM_SUFFIX("In-RZ-Prof");
124	rc = STAMR3Register(pVM, &pStats->ProfInRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
125	SET_NM_SUFFIX("Out-RZ-Prof");
126	rc = STAMR3Register(pVM, &pStats->ProfOutRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
127	}
128
129	pStats++;
130	uPort++;
131	if (pExtDesc)
132	pExtDesc = pszInDesc \|\| pszOutDesc ? pExtDesc + 1 : NULL;
133	} while (uPort < uEndPort);
134	}
135
136
137	/**
138	* Deregister statistics for an I/O port entry.
139	*/
140	static void iomR3IoPortDeregStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry, unsigned uPort)
141	{
142	char szPrefix[80];
143	size_t cchPrefix;
144	if (pRegEntry->cPorts > 1)
145	cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/IoPorts/%04x-%04x", uPort, uPort + pRegEntry->cPorts - 1);
146	else
147	cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/IoPorts/%04x", uPort);
148	STAMR3DeregisterByPrefix(pVM->pUVM, szPrefix);
149	}
150
151	#endif /* VBOX_WITH_STATISTICS */
152
153
154	/**
155	* @callback_method_impl{FNIOMIOPORTNEWIN,
156	* Dummy Port I/O Handler for IN operations.}
157	*/
158	static DECLCALLBACK(VBOXSTRICTRC)
159	iomR3IOPortDummyNewIn(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
160	{
161	NOREF(pDevIns); NOREF(pvUser); NOREF(Port);
162	switch (cb)
163	{
164	case 1: *pu32 = 0xff; break;
165	case 2: *pu32 = 0xffff; break;
166	case 4: *pu32 = UINT32_C(0xffffffff); break;
167	default:
168	AssertReleaseMsgFailed(("cb=%d\n", cb));
169	return VERR_IOM_IOPORT_IPE_2;
170	}
171	return VINF_SUCCESS;
172	}
173
174
175	/**
176	* @callback_method_impl{FNIOMIOPORTNEWINSTRING,
177	* Dummy Port I/O Handler for string IN operations.}
178	*/
179	static DECLCALLBACK(VBOXSTRICTRC)
180	iomR3IOPortDummyNewInStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint8_t pbDst, uint32_t *pcTransfer, unsigned cb)
181	{
182	NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbDst); NOREF(pcTransfer); NOREF(cb);
183	return VINF_SUCCESS;
184	}
185
186
187	/**
188	* @callback_method_impl{FNIOMIOPORTNEWOUT,
189	* Dummy Port I/O Handler for OUT operations.}
190	*/
191	static DECLCALLBACK(VBOXSTRICTRC)
192	iomR3IOPortDummyNewOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
193	{
194	NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(u32); NOREF(cb);
195	return VINF_SUCCESS;
196	}
197
198
199	/**
200	* @callback_method_impl{FNIOMIOPORTNEWOUTSTRING,
201	* Dummy Port I/O Handler for string OUT operations.}
202	*/
203	static DECLCALLBACK(VBOXSTRICTRC)
204	iomR3IOPortDummyNewOutStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint8_t const pbSrc, uint32_t *pcTransfer, unsigned cb)
205	{
206	NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbSrc); NOREF(pcTransfer); NOREF(cb);
207	return VINF_SUCCESS;
208	}
209
210
211	#ifdef VBOX_WITH_STATISTICS
212	/**
213	* Grows the statistics table.
214	*
215	* @returns VBox status code.
216	* @param pVM The cross context VM structure.
217	* @param cNewEntries The minimum number of new entrie.
218	* @see IOMR0IoPortGrowStatisticsTable
219	*/
220	static int iomR3IoPortGrowStatisticsTable(PVM pVM, uint32_t cNewEntries)
221	{
222	AssertReturn(cNewEntries <= _64K, VERR_IOM_TOO_MANY_IOPORT_REGISTRATIONS);
223
224	int rc;
225	if (!SUPR3IsDriverless())
226	{
227	rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORT_STATS, cNewEntries, NULL);
228	AssertLogRelRCReturn(rc, rc);
229	AssertReturn(cNewEntries <= pVM->iom.s.cIoPortStatsAllocation, VERR_IOM_IOPORT_IPE_2);
230	}
231	else
232	{
233	/*
234	* Validate input and state.
235	*/
236	uint32_t const cOldEntries = pVM->iom.s.cIoPortStatsAllocation;
237	AssertReturn(cNewEntries > cOldEntries, VERR_IOM_IOPORT_IPE_1);
238	AssertReturn(pVM->iom.s.cIoPortStats <= cOldEntries, VERR_IOM_IOPORT_IPE_2);
239
240	/*
241	* Calc size and allocate a new table.
242	*/
243	uint32_t const cbNew = RT_ALIGN_32(cNewEntries * sizeof(IOMIOPORTSTATSENTRY), HOST_PAGE_SIZE);
244	cNewEntries = cbNew / sizeof(IOMIOPORTSTATSENTRY);
245
246	PIOMIOPORTSTATSENTRY const paIoPortStats = (PIOMIOPORTSTATSENTRY)RTMemPageAllocZ(cbNew);
247	if (paIoPortStats)
248	{
249	/*
250	* Anything to copy over, update and free the old one.
251	*/
252	PIOMIOPORTSTATSENTRY const pOldIoPortStats = pVM->iom.s.paIoPortStats;
253	if (pOldIoPortStats)
254	memcpy(paIoPortStats, pOldIoPortStats, cOldEntries * sizeof(IOMIOPORTSTATSENTRY));
255
256	pVM->iom.s.paIoPortStats = paIoPortStats;
257	pVM->iom.s.cIoPortStatsAllocation = cNewEntries;
258
259	RTMemPageFree(pOldIoPortStats, RT_ALIGN_32(cOldEntries * sizeof(IOMIOPORTSTATSENTRY), HOST_PAGE_SIZE));
260
261	rc = VINF_SUCCESS;
262	}
263	else
264	rc = VERR_NO_PAGE_MEMORY;
265	}
266
267	return rc;
268	}
269	#endif
270
271
272	/**
273	* Grows the I/O port registration statistics table.
274	*
275	* @returns VBox status code.
276	* @param pVM The cross context VM structure.
277	* @param cNewEntries The minimum number of new entrie.
278	* @see IOMR0IoPortGrowRegistrationTables
279	*/
280	static int iomR3IoPortGrowTable(PVM pVM, uint32_t cNewEntries)
281	{
282	AssertReturn(cNewEntries <= _4K, VERR_IOM_TOO_MANY_IOPORT_REGISTRATIONS);
283
284	int rc;
285	if (!SUPR3IsDriverless())
286	{
287	rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORTS, cNewEntries, NULL);
288	AssertLogRelRCReturn(rc, rc);
289	AssertReturn(cNewEntries <= pVM->iom.s.cIoPortAlloc, VERR_IOM_IOPORT_IPE_2);
290	}
291	else
292	{
293	/*
294	* Validate input and state.
295	*/
296	uint32_t const cOldEntries = pVM->iom.s.cIoPortAlloc;
297	AssertReturn(cNewEntries >= cOldEntries, VERR_IOM_IOPORT_IPE_1);
298
299	/*
300	* Allocate the new tables. We use a single allocation for the three tables (ring-0,
301	* ring-3, lookup) and does a partial mapping of the result to ring-3.
302	*/
303	uint32_t const cbRing3 = RT_ALIGN_32(cNewEntries * sizeof(IOMIOPORTENTRYR3), HOST_PAGE_SIZE);
304	uint32_t const cbShared = RT_ALIGN_32(cNewEntries * sizeof(IOMIOPORTLOOKUPENTRY), HOST_PAGE_SIZE);
305	uint32_t const cbNew = cbRing3 + cbShared;
306
307	/* Use the rounded up space as best we can. */
308	cNewEntries = RT_MIN(cbRing3 / sizeof(IOMIOPORTENTRYR3), cbShared / sizeof(IOMIOPORTLOOKUPENTRY));
309
310	PIOMIOPORTENTRYR3 const paRing3 = (PIOMIOPORTENTRYR3)RTMemPageAllocZ(cbNew);
311	if (paRing3)
312	{
313	PIOMIOPORTLOOKUPENTRY const paLookup = (PIOMIOPORTLOOKUPENTRY)((uintptr_t)paRing3 + cbRing3);
314
315	/*
316	* Copy over the old info and initialize the idxSelf and idxStats members.
317	*/
318	if (pVM->iom.s.paIoPortRegs != NULL)
319	{
320	memcpy(paRing3, pVM->iom.s.paIoPortRegs, sizeof(paRing3[0]) * cOldEntries);
321	memcpy(paLookup, pVM->iom.s.paIoPortLookup, sizeof(paLookup[0]) * cOldEntries);
322	}
323
324	size_t i = cbRing3 / sizeof(*paRing3);
325	while (i-- > cOldEntries)
326	{
327	paRing3[i].idxSelf = (uint16_t)i;
328	paRing3[i].idxStats = UINT16_MAX;
329	}
330
331	/*
332	* Update the variables and free the old memory.
333	*/
334	void * const pvFree = pVM->iom.s.paIoPortRegs;
335
336	pVM->iom.s.paIoPortRegs = paRing3;
337	pVM->iom.s.paIoPortLookup = paLookup;
338	pVM->iom.s.cIoPortAlloc = cNewEntries;
339
340	RTMemPageFree(pvFree,
341	RT_ALIGN_32(cOldEntries * sizeof(IOMIOPORTENTRYR3), HOST_PAGE_SIZE)
342	+ RT_ALIGN_32(cOldEntries * sizeof(IOMIOPORTLOOKUPENTRY), HOST_PAGE_SIZE));
343
344	rc = VINF_SUCCESS;
345	}
346	else
347	rc = VERR_NO_PAGE_MEMORY;
348	}
349	return rc;
350	}
351
352
353	/**
354	* Worker for PDMDEVHLPR3::pfnIoPortCreateEx.
355	*/
356	VMMR3_INT_DECL(int) IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
357	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
358	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
359	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
360	{
361	/*
362	* Validate input.
363	*/
364	AssertPtrReturn(phIoPorts, VERR_INVALID_POINTER);
365	*phIoPorts = UINT32_MAX;
366	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
367	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
368	AssertReturn(!pVM->iom.s.fIoPortsFrozen, VERR_WRONG_ORDER);
369
370	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
371
372	AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%#x\n", cPorts), VERR_OUT_OF_RANGE);
373	AssertReturn(!(fFlags & ~IOM_IOPORT_F_VALID_MASK), VERR_INVALID_FLAGS);
374
375	AssertReturn(pfnOut \|\| pfnIn \|\| pfnOutStr \|\| pfnInStr, VERR_INVALID_PARAMETER);
376	AssertPtrNullReturn(pfnOut, VERR_INVALID_POINTER);
377	AssertPtrNullReturn(pfnIn, VERR_INVALID_POINTER);
378	AssertPtrNullReturn(pfnOutStr, VERR_INVALID_POINTER);
379	AssertPtrNullReturn(pfnInStr, VERR_INVALID_POINTER);
380	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
381	AssertReturn(*pszDesc != '\0', VERR_INVALID_POINTER);
382	AssertReturn(strlen(pszDesc) < 128, VERR_INVALID_POINTER);
383	if (paExtDescs)
384	{
385	AssertPtrReturn(paExtDescs, VERR_INVALID_POINTER);
386	for (size_t i = 0;; i++)
387	{
388	const char *pszIn = paExtDescs[i].pszIn;
389	const char *pszOut = paExtDescs[i].pszOut;
390	if (!pszIn && !pszOut)
391	break;
392	AssertReturn(i < _8K, VERR_OUT_OF_RANGE);
393	AssertReturn(!pszIn \|\| strlen(pszIn) < 128, VERR_INVALID_POINTER);
394	AssertReturn(!pszOut \|\| strlen(pszOut) < 128, VERR_INVALID_POINTER);
395	}
396	}
397
398	/*
399	* Ensure that we've got table space for it.
400	*/
401	#ifndef VBOX_WITH_STATISTICS
402	uint16_t const idxStats = UINT16_MAX;
403	#else
404	uint32_t const idxStats = pVM->iom.s.cIoPortStats;
405	uint32_t const cNewIoPortStats = idxStats + cPorts;
406	AssertReturn(cNewIoPortStats <= _64K, VERR_IOM_TOO_MANY_IOPORT_REGISTRATIONS);
407	if (cNewIoPortStats > pVM->iom.s.cIoPortStatsAllocation)
408	{
409	int rc = iomR3IoPortGrowStatisticsTable(pVM, cNewIoPortStats);
410	AssertRCReturn(rc, rc);
411	AssertReturn(idxStats == pVM->iom.s.cIoPortStats, VERR_IOM_IOPORT_IPE_1);
412	}
413	#endif
414
415	uint32_t idx = pVM->iom.s.cIoPortRegs;
416	if (idx >= pVM->iom.s.cIoPortAlloc)
417	{
418	int rc = iomR3IoPortGrowTable(pVM, pVM->iom.s.cIoPortAlloc + 1);
419	AssertRCReturn(rc, rc);
420	AssertReturn(idx == pVM->iom.s.cIoPortRegs, VERR_IOM_IOPORT_IPE_1);
421	AssertReturn(idx < pVM->iom.s.cIoPortAlloc, VERR_IOM_IOPORT_IPE_2);
422	}
423
424	/*
425	* Enter it.
426	*/
427	pVM->iom.s.paIoPortRegs[idx].pvUser = pvUser;
428	pVM->iom.s.paIoPortRegs[idx].pDevIns = pDevIns;
429	pVM->iom.s.paIoPortRegs[idx].pfnOutCallback = pfnOut ? pfnOut : iomR3IOPortDummyNewOut;
430	pVM->iom.s.paIoPortRegs[idx].pfnInCallback = pfnIn ? pfnIn : iomR3IOPortDummyNewIn;
431	pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback = pfnOutStr ? pfnOutStr : iomR3IOPortDummyNewOutStr;
432	pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback = pfnInStr ? pfnInStr : iomR3IOPortDummyNewInStr;
433	pVM->iom.s.paIoPortRegs[idx].pszDesc = pszDesc;
434	pVM->iom.s.paIoPortRegs[idx].paExtDescs = paExtDescs;
435	pVM->iom.s.paIoPortRegs[idx].pPciDev = pPciDev;
436	pVM->iom.s.paIoPortRegs[idx].iPciRegion = iPciRegion;
437	pVM->iom.s.paIoPortRegs[idx].cPorts = cPorts;
438	pVM->iom.s.paIoPortRegs[idx].uPort = UINT16_MAX;
439	pVM->iom.s.paIoPortRegs[idx].idxStats = (uint16_t)idxStats;
440	pVM->iom.s.paIoPortRegs[idx].fMapped = false;
441	pVM->iom.s.paIoPortRegs[idx].fFlags = (uint8_t)fFlags;
442	pVM->iom.s.paIoPortRegs[idx].idxSelf = idx;
443
444	pVM->iom.s.cIoPortRegs = idx + 1;
445	#ifdef VBOX_WITH_STATISTICS
446	pVM->iom.s.cIoPortStats = cNewIoPortStats;
447	#endif
448	*phIoPorts = idx;
449	LogFlow(("IOMR3IoPortCreate: idx=%#x cPorts=%u %s\n", idx, cPorts, pszDesc));
450	return VINF_SUCCESS;
451	}
452
453
454	/**
455	* Worker for PDMDEVHLPR3::pfnIoPortMap.
456	*/
457	VMMR3_INT_DECL(int) IOMR3IoPortMap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT uPort)
458	{
459	/*
460	* Validate input and state.
461	*/
462	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
463	AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
464	PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
465	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
466
467	RTIOPORT const cPorts = pRegEntry->cPorts;
468	AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%s\n", cPorts), VERR_IOM_IOPORT_IPE_1);
469	AssertReturn((uint32_t)uPort + cPorts <= _64K, VERR_OUT_OF_RANGE);
470	RTIOPORT const uLastPort = uPort + cPorts - 1;
471	LogFlow(("IOMR3IoPortMap: hIoPorts=%#RX64 %RTiop..%RTiop (%u ports)\n", hIoPorts, uPort, uLastPort, cPorts));
472
473	/*
474	* Do the mapping.
475	*/
476	int rc = VINF_SUCCESS;
477	IOM_LOCK_EXCL(pVM);
478
479	if (!pRegEntry->fMapped)
480	{
481	uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
482	Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
483
484	PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
485	PIOMIOPORTLOOKUPENTRY pEntry;
486	if (cEntries > 0)
487	{
488	uint32_t iFirst = 0;
489	uint32_t iEnd = cEntries;
490	uint32_t i = cEntries / 2;
491	for (;;)
492	{
493	pEntry = &paEntries[i];
494	if (pEntry->uLastPort < uPort)
495	{
496	i += 1;
497	if (i < iEnd)
498	iFirst = i;
499	else
500	{
501	/* Insert after the entry we just considered: */
502	pEntry += 1;
503	if (i < cEntries)
504	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
505	break;
506	}
507	}
508	else if (pEntry->uFirstPort > uLastPort)
509	{
510	if (i > iFirst)
511	iEnd = i;
512	else
513	{
514	/* Insert at the entry we just considered: */
515	if (i < cEntries)
516	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
517	break;
518	}
519	}
520	else
521	{
522	/* Oops! We've got a conflict. */
523	AssertLogRelMsgFailed(("%x..%x (%s) conflicts with existing mapping %x..%x (%s)\n",
524	uPort, uLastPort, pRegEntry->pszDesc,
525	pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
526	IOM_UNLOCK_EXCL(pVM);
527	return VERR_IOM_IOPORT_RANGE_CONFLICT;
528	}
529
530	i = iFirst + (iEnd - iFirst) / 2;
531	}
532	}
533	else
534	pEntry = paEntries;
535
536	/*
537	* Fill in the entry and bump the table size.
538	*/
539	pEntry->idx = hIoPorts;
540	pEntry->uFirstPort = uPort;
541	pEntry->uLastPort = uLastPort;
542	pVM->iom.s.cIoPortLookupEntries = cEntries + 1;
543
544	pRegEntry->uPort = uPort;
545	pRegEntry->fMapped = true;
546
547	#ifdef VBOX_WITH_STATISTICS
548	/* Don't register stats here when we're creating the VM as the
549	statistics table may still be reallocated. */
550	if (pVM->enmVMState >= VMSTATE_CREATED)
551	iomR3IoPortRegStats(pVM, pRegEntry);
552	#endif
553
554	#ifdef VBOX_STRICT
555	/*
556	* Assert table sanity.
557	*/
558	AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
559	AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
560
561	RTIOPORT uPortPrev = paEntries[0].uLastPort;
562	for (size_t i = 1; i <= cEntries; i++)
563	{
564	AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
565	AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
566	AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
567	AssertMsg(paEntries[i].uLastPort - paEntries[i].uFirstPort + 1 == pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts,
568	("%u: %#x %#x..%#x -> %u, expected %u\n", i, uPortPrev, paEntries[i].uFirstPort, paEntries[i].uLastPort,
569	paEntries[i].uLastPort - paEntries[i].uFirstPort + 1, pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts));
570	uPortPrev = paEntries[i].uLastPort;
571	}
572	#endif
573	}
574	else
575	{
576	AssertFailed();
577	rc = VERR_IOM_IOPORTS_ALREADY_MAPPED;
578	}
579
580	IOM_UNLOCK_EXCL(pVM);
581	return rc;
582	}
583
584
585	/**
586	* Worker for PDMDEVHLPR3::pfnIoPortUnmap.
587	*/
588	VMMR3_INT_DECL(int) IOMR3IoPortUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
589	{
590	/*
591	* Validate input and state.
592	*/
593	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
594	AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
595	PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
596	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
597
598	/*
599	* Do the mapping.
600	*/
601	int rc;
602	IOM_LOCK_EXCL(pVM);
603
604	if (pRegEntry->fMapped)
605	{
606	RTIOPORT const uPort = pRegEntry->uPort;
607	RTIOPORT const uLastPort = uPort + pRegEntry->cPorts - 1;
608	uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
609	Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
610	Assert(cEntries > 0);
611	LogFlow(("IOMR3IoPortUnmap: hIoPorts=%#RX64 %RTiop..%RTiop (%u ports)\n", hIoPorts, uPort, uLastPort, pRegEntry->cPorts));
612
613	PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
614	uint32_t iFirst = 0;
615	uint32_t iEnd = cEntries;
616	uint32_t i = cEntries / 2;
617	for (;;)
618	{
619	PIOMIOPORTLOOKUPENTRY pEntry = &paEntries[i];
620	if (pEntry->uLastPort < uPort)
621	{
622	i += 1;
623	if (i < iEnd)
624	iFirst = i;
625	else
626	{
627	rc = VERR_IOM_IOPORT_IPE_1;
628	AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
629	}
630	}
631	else if (pEntry->uFirstPort > uLastPort)
632	{
633	if (i > iFirst)
634	iEnd = i;
635	else
636	{
637	rc = VERR_IOM_IOPORT_IPE_1;
638	AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
639	}
640	}
641	else if (pEntry->idx == hIoPorts)
642	{
643	Assert(pEntry->uFirstPort == uPort);
644	Assert(pEntry->uLastPort == uLastPort);
645	#ifdef VBOX_WITH_STATISTICS
646	iomR3IoPortDeregStats(pVM, pRegEntry, uPort);
647	#endif
648	if (i + 1 < cEntries)
649	memmove(pEntry, pEntry + 1, sizeof(pEntry) (cEntries - i - 1));
650	pVM->iom.s.cIoPortLookupEntries = cEntries - 1;
651	pRegEntry->uPort = UINT16_MAX;
652	pRegEntry->fMapped = false;
653	rc = VINF_SUCCESS;
654	break;
655	}
656	else
657	{
658	AssertLogRelMsgFailed(("Lookig for %x..%x (%s), found %x..%x (%s) instead!\n",
659	uPort, uLastPort, pRegEntry->pszDesc,
660	pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
661	rc = VERR_IOM_IOPORT_IPE_1;
662	break;
663	}
664
665	i = iFirst + (iEnd - iFirst) / 2;
666	}
667
668	#ifdef VBOX_STRICT
669	/*
670	* Assert table sanity.
671	*/
672	AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
673	AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
674
675	RTIOPORT uPortPrev = paEntries[0].uLastPort;
676	for (i = 1; i < cEntries - 1; i++)
677	{
678	AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
679	AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
680	AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
681	AssertMsg(paEntries[i].uLastPort - paEntries[i].uFirstPort + 1 == pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts,
682	("%u: %#x %#x..%#x -> %u, expected %u\n", i, uPortPrev, paEntries[i].uFirstPort, paEntries[i].uLastPort,
683	paEntries[i].uLastPort - paEntries[i].uFirstPort + 1, pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts));
684	uPortPrev = paEntries[i].uLastPort;
685	}
686	#endif
687	}
688	else
689	{
690	AssertFailed();
691	rc = VERR_IOM_IOPORTS_NOT_MAPPED;
692	}
693
694	IOM_UNLOCK_EXCL(pVM);
695	return rc;
696	}
697
698
699	/**
700	* Validates @a hIoPorts, making sure it belongs to @a pDevIns.
701	*
702	* @returns VBox status code.
703	* @param pVM The cross context VM structure.
704	* @param pDevIns The device which allegedly owns @a hIoPorts.
705	* @param hIoPorts The handle to validate.
706	*/
707	VMMR3_INT_DECL(int) IOMR3IoPortValidateHandle(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
708	{
709	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
710	AssertReturn(hIoPorts < RT_MIN(pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc), VERR_IOM_INVALID_IOPORT_HANDLE);
711	PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
712	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
713	return VINF_SUCCESS;
714	}
715
716
717	/**
718	* Gets the mapping address of I/O ports @a hIoPorts.
719	*
720	* @returns Mapping address if mapped, UINT32_MAX if not mapped or invalid
721	* input.
722	* @param pVM The cross context VM structure.
723	* @param pDevIns The device which allegedly owns @a hRegion.
724	* @param hIoPorts The handle to I/O port region.
725	*/
726	VMMR3_INT_DECL(uint32_t) IOMR3IoPortGetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
727	{
728	AssertPtrReturn(pDevIns, UINT32_MAX);
729	AssertReturn(hIoPorts < RT_MIN(pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc), UINT32_MAX);
730	IOMIOPORTENTRYR3 volatile * const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
731	AssertReturn(pRegEntry->pDevIns == pDevIns, UINT32_MAX);
732	for (uint32_t iTry = 0; ; iTry++)
733	{
734	bool fMapped = pRegEntry->fMapped;
735	RTIOPORT uPort = pRegEntry->uPort;
736	if ( ( ASMAtomicReadBool(&pRegEntry->fMapped) == fMapped
737	&& uPort == pRegEntry->uPort)
738	\|\| iTry > 1024)
739	return fMapped ? uPort : UINT32_MAX;
740	ASMNopPause();
741	}
742	}
743
744
745	/**
746	* Display all registered I/O port ranges.
747	*
748	* @param pVM The cross context VM structure.
749	* @param pHlp The info helpers.
750	* @param pszArgs Arguments, ignored.
751	*/
752	DECLCALLBACK(void) iomR3IoPortInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
753	{
754	RT_NOREF(pszArgs);
755
756	/* No locking needed here as registerations are only happening during VMSTATE_CREATING. */
757	pHlp->pfnPrintf(pHlp,
758	"I/O port registrations: %u (%u allocated)\n"
759	" ## Ctx Ports Mapping PCI Description\n",
760	pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc);
761	PIOMIOPORTENTRYR3 paRegs = pVM->iom.s.paIoPortRegs;
762	for (uint32_t i = 0; i < pVM->iom.s.cIoPortRegs; i++)
763	{
764	const char * const pszRing = paRegs[i].fRing0 ? paRegs[i].fRawMode ? "+0+C" : "+0 "
765	: paRegs[i].fRawMode ? "+C " : " ";
766	if (paRegs[i].fMapped && paRegs[i].pPciDev)
767	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
768	paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1,
769	paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
770	else if (paRegs[i].fMapped && !paRegs[i].pPciDev)
771	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
772	paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1, paRegs[i].pszDesc);
773	else if (paRegs[i].pPciDev)
774	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
775	paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
776	else
777	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped %s\n",
778	paRegs[i].idxSelf, pszRing, paRegs[i].cPorts, paRegs[i].pszDesc);
779	}
780	}
781

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source: vbox/trunk/src/VBox/VMM/VMMR3/IOMR3IoPort.cpp@ 106022

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