| 1 | /* $Id: IOM.cpp 103152 2024-01-31 15:43:28Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IOM - Input / Output Monitor.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 |
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| 29 | /** @page pg_iom IOM - The Input / Output Monitor
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| 30 | *
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| 31 | * The input/output monitor will handle I/O exceptions routing them to the
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| 32 | * appropriate device. It implements an API to register and deregister virtual
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| 33 | * I/0 port handlers and memory mapped I/O handlers. A handler is PDM devices
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| 34 | * and a set of callback functions.
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| 35 | *
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| 36 | * @see grp_iom
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| 37 | *
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| 38 | *
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| 39 | * @section sec_iom_rawmode Raw-Mode
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| 40 | *
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| 41 | * In raw-mode I/O port access is trapped (\#GP(0)) by ensuring that the actual
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| 42 | * IOPL is 0 regardless of what the guest IOPL is. The \#GP handler use the
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| 43 | * disassembler (DIS) to figure which instruction caused it (there are a number
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| 44 | * of instructions in addition to the I/O ones) and if it's an I/O port access
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| 45 | * it will hand it to IOMRCIOPortHandler (via EMInterpretPortIO).
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| 46 | * IOMRCIOPortHandler will lookup the port in the AVL tree of registered
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| 47 | * handlers. If found, the handler will be called otherwise default action is
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| 48 | * taken. (Default action is to write into the void and read all set bits.)
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| 49 | *
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| 50 | * Memory Mapped I/O (MMIO) is implemented as a slightly special case of PGM
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| 51 | * access handlers. An MMIO range is registered with IOM which then registers it
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| 52 | * with the PGM access handler sub-system. The access handler catches all
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| 53 | * access and will be called in the context of a \#PF handler. In RC and R0 this
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| 54 | * handler is iomMmioPfHandler while in ring-3 it's iomR3MmioHandler (although
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| 55 | * in ring-3 there can be alternative ways). iomMmioPfHandler will attempt to
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| 56 | * emulate the instruction that is doing the access and pass the corresponding
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| 57 | * reads / writes to the device.
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| 58 | *
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| 59 | * Emulating I/O port access is less complex and should be slightly faster than
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| 60 | * emulating MMIO, so in most cases we should encourage the OS to use port I/O.
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| 61 | * Devices which are frequently accessed should register GC handlers to speed up
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| 62 | * execution.
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| 63 | *
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| 64 | *
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| 65 | * @section sec_iom_hm Hardware Assisted Virtualization Mode
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| 66 | *
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| 67 | * When running in hardware assisted virtualization mode we'll be doing much the
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| 68 | * same things as in raw-mode. The main difference is that we're running in the
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| 69 | * host ring-0 context and that we don't get faults (\#GP(0) and \#PG) but
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| 70 | * exits.
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| 71 | *
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| 72 | *
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| 73 | * @section sec_iom_rem Recompiled Execution Mode
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| 74 | *
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| 75 | * When running in the recompiler things are different. I/O port access is
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| 76 | * handled by calling IOMIOPortRead and IOMIOPortWrite directly. While MMIO can
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| 77 | * be handled in one of two ways. The normal way is that we have a registered a
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| 78 | * special RAM range with the recompiler and in the three callbacks (for byte,
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| 79 | * word and dword access) we call IOMMMIORead and IOMMMIOWrite directly. The
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| 80 | * alternative ways that the physical memory access which goes via PGM will take
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| 81 | * care of it by calling iomR3MmioHandler via the PGM access handler machinery
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| 82 | * - this shouldn't happen but it is an alternative...
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| 83 | *
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| 84 | *
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| 85 | * @section sec_iom_other Other Accesses
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| 86 | *
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| 87 | * I/O ports aren't really exposed in any other way, unless you count the
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| 88 | * instruction interpreter in EM, but that's just what we're doing in the
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| 89 | * raw-mode \#GP(0) case really. Now, it's possible to call IOMIOPortRead and
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| 90 | * IOMIOPortWrite directly to talk to a device, but this is really bad behavior
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| 91 | * and should only be done as temporary hacks (the PC BIOS device used to setup
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| 92 | * the CMOS this way back in the dark ages).
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| 93 | *
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| 94 | * MMIO has similar direct routes as the I/O ports and these shouldn't be used
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| 95 | * for the same reasons and with the same restrictions. OTOH since MMIO is
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| 96 | * mapped into the physical memory address space, it can be accessed in a number
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| 97 | * of ways thru PGM.
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| 98 | *
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| 99 | *
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| 100 | * @section sec_iom_logging Logging Levels
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| 101 | *
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| 102 | * Following assignments:
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| 103 | * - Level 5 is used for defering I/O port and MMIO writes to ring-3.
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| 104 | *
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| 105 | */
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| 106 |
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| 107 | /** @todo MMIO - simplifying the device end.
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| 108 | * - Add a return status for doing DBGFSTOP on access where there are no known
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| 109 | * registers.
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| 110 | * -
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| 111 | *
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| 112 | * */
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| 113 |
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| 114 |
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| 115 | /*********************************************************************************************************************************
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| 116 | * Header Files *
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| 117 | *********************************************************************************************************************************/
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| 118 | #define LOG_GROUP LOG_GROUP_IOM
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| 119 | #include <VBox/vmm/iom.h>
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| 120 | #include <VBox/vmm/cpum.h>
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| 121 | #include <VBox/vmm/pgm.h>
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| 122 | #include <VBox/sup.h>
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| 123 | #include <VBox/vmm/hm.h>
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| 124 | #include <VBox/vmm/mm.h>
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| 125 | #include <VBox/vmm/stam.h>
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| 126 | #include <VBox/vmm/dbgf.h>
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| 127 | #include <VBox/vmm/pdmapi.h>
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| 128 | #include <VBox/vmm/pdmdev.h>
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| 129 | #include "IOMInternal.h"
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| 130 | #include <VBox/vmm/vm.h>
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| 131 |
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| 132 | #include <VBox/param.h>
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| 133 | #include <iprt/assert.h>
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| 134 | #include <iprt/alloc.h>
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| 135 | #include <iprt/string.h>
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| 136 | #include <VBox/log.h>
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| 137 | #include <VBox/err.h>
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| 138 |
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| 139 |
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| 140 |
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| 141 | /**
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| 142 | * Initializes the IOM.
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| 143 | *
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| 144 | * @returns VBox status code.
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| 145 | * @param pVM The cross context VM structure.
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| 146 | */
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| 147 | VMMR3_INT_DECL(int) IOMR3Init(PVM pVM)
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| 148 | {
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| 149 | LogFlow(("IOMR3Init:\n"));
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| 150 |
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| 151 | /*
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| 152 | * Assert alignment and sizes.
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| 153 | */
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| 154 | AssertCompileMemberAlignment(VM, iom.s, 32);
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| 155 | AssertCompile(sizeof(pVM->iom.s) <= sizeof(pVM->iom.padding));
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| 156 | AssertCompileMemberAlignment(IOM, CritSect, sizeof(uintptr_t));
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| 157 |
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| 158 | /*
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| 159 | * Initialize the REM critical section.
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| 160 | */
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| 161 | #ifdef IOM_WITH_CRIT_SECT_RW
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| 162 | int rc = PDMR3CritSectRwInit(pVM, &pVM->iom.s.CritSect, RT_SRC_POS, "IOM Lock");
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| 163 | #else
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| 164 | int rc = PDMR3CritSectInit(pVM, &pVM->iom.s.CritSect, RT_SRC_POS, "IOM Lock");
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| 165 | #endif
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| 166 | AssertRCReturn(rc, rc);
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| 167 |
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| 168 | /*
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| 169 | * Register the MMIO access handler type.
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| 170 | */
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| 171 | rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_MMIO, 0 /*fFlags*/,
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| 172 | iomMmioHandlerNew, "MMIO", &pVM->iom.s.hNewMmioHandlerType);
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| 173 | AssertRCReturn(rc, rc);
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| 174 |
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| 175 | /*
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| 176 | * Info.
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| 177 | */
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| 178 | DBGFR3InfoRegisterInternal(pVM, "ioport", "Dumps all IOPort ranges. No arguments.", &iomR3IoPortInfo);
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| 179 | DBGFR3InfoRegisterInternal(pVM, "mmio", "Dumps all MMIO ranges. No arguments.", &iomR3MmioInfo);
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| 180 |
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| 181 | /*
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| 182 | * Statistics (names are somewhat contorted to make the registration
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| 183 | * sub-trees appear at the end of each group).
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| 184 | */
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| 185 | STAM_REG(pVM, &pVM->iom.s.StatIoPortCommits, STAMTYPE_COUNTER, "/IOM/IoPortCommits", STAMUNIT_OCCURENCES, "Number of ring-3 I/O port commits.");
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| 186 | STAM_REG(pVM, &pVM->iom.s.StatIoPortIn, STAMTYPE_COUNTER, "/IOM/IoPortIN", STAMUNIT_OCCURENCES, "Number of IN instructions (attempts)");
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| 187 | STAM_REG(pVM, &pVM->iom.s.StatIoPortInS, STAMTYPE_COUNTER, "/IOM/IoPortINS", STAMUNIT_OCCURENCES, "Number of INS instructions (attempts)");
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| 188 | STAM_REG(pVM, &pVM->iom.s.StatIoPortOutS, STAMTYPE_COUNTER, "/IOM/IoPortOUT", STAMUNIT_OCCURENCES, "Number of OUT instructions (attempts)");
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| 189 | STAM_REG(pVM, &pVM->iom.s.StatIoPortOutS, STAMTYPE_COUNTER, "/IOM/IoPortOUTS", STAMUNIT_OCCURENCES, "Number of OUTS instructions (attempts)");
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| 190 |
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| 191 | STAM_REG(pVM, &pVM->iom.s.StatMmioHandlerR3, STAMTYPE_COUNTER, "/IOM/MmioHandlerR3", STAMUNIT_OCCURENCES, "Number of calls to iomMmioHandlerNew from ring-3.");
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| 192 | STAM_REG(pVM, &pVM->iom.s.StatMmioHandlerR0, STAMTYPE_COUNTER, "/IOM/MmioHandlerR0", STAMUNIT_OCCURENCES, "Number of calls to iomMmioHandlerNew from ring-0.");
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| 193 | STAM_REG(pVM, &pVM->iom.s.StatMmioReadsR0ToR3, STAMTYPE_COUNTER, "/IOM/MmioR0ToR3Reads", STAMUNIT_OCCURENCES, "Number of reads deferred to ring-3.");
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| 194 | STAM_REG(pVM, &pVM->iom.s.StatMmioWritesR0ToR3, STAMTYPE_COUNTER, "/IOM/MmioR0ToR3Writes", STAMUNIT_OCCURENCES, "Number of writes deferred to ring-3.");
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| 195 | STAM_REG(pVM, &pVM->iom.s.StatMmioCommitsR0ToR3,STAMTYPE_COUNTER, "/IOM/MmioR0ToR3Commits", STAMUNIT_OCCURENCES, "Number of commits deferred to ring-3.");
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| 196 | STAM_REG(pVM, &pVM->iom.s.StatMmioPfHandler, STAMTYPE_PROFILE, "/IOM/MmioPfHandler", STAMUNIT_TICKS_PER_CALL, "Number of calls to iomMmioPfHandlerNew.");
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| 197 | STAM_REG(pVM, &pVM->iom.s.StatMmioPhysHandler, STAMTYPE_PROFILE, "/IOM/MmioPhysHandler", STAMUNIT_TICKS_PER_CALL, "Number of calls to IOMR0MmioPhysHandler.");
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| 198 | STAM_REG(pVM, &pVM->iom.s.StatMmioCommitsDirect,STAMTYPE_COUNTER, "/IOM/MmioCommitsDirect", STAMUNIT_OCCURENCES, "Number of ring-3 MMIO commits direct to handler via handle hint.");
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| 199 | STAM_REG(pVM, &pVM->iom.s.StatMmioCommitsPgm, STAMTYPE_COUNTER, "/IOM/MmioCommitsPgm", STAMUNIT_OCCURENCES, "Number of ring-3 MMIO commits via PGM.");
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| 200 | STAM_REL_REG(pVM, &pVM->iom.s.StatMmioStaleMappings, STAMTYPE_COUNTER, "/IOM/MmioMappingsStale", STAMUNIT_TICKS_PER_CALL, "Number of times iomMmioHandlerNew got a call for a remapped range at the old mapping.");
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| 201 | STAM_REL_REG(pVM, &pVM->iom.s.StatMmioTooDeepRecursion, STAMTYPE_COUNTER, "/IOM/MmioTooDeepRecursion", STAMUNIT_OCCURENCES, "Number of times iomMmioHandlerNew detected too deep recursion and took default action.");
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| 202 | STAM_REG(pVM, &pVM->iom.s.StatMmioDevLockContentionR0, STAMTYPE_COUNTER, "/IOM/MmioDevLockContentionR0", STAMUNIT_OCCURENCES, "Number of device lock contention force return to ring-3.");
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| 203 |
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| 204 | LogFlow(("IOMR3Init: returns VINF_SUCCESS\n"));
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| 205 | return VINF_SUCCESS;
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| 206 | }
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| 207 |
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| 208 |
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| 209 | /**
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| 210 | * Called when a VM initialization stage is completed.
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| 211 | *
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| 212 | * @returns VBox status code.
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| 213 | * @param pVM The cross context VM structure.
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| 214 | * @param enmWhat The initialization state that was completed.
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| 215 | */
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| 216 | VMMR3_INT_DECL(int) IOMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
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| 217 | {
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| 218 | #ifdef VBOX_WITH_STATISTICS
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| 219 | if (enmWhat == VMINITCOMPLETED_RING0)
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| 220 | {
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| 221 | /*
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| 222 | * Synchronize the ring-3 I/O port and MMIO statistics indices into the
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| 223 | * ring-0 tables to simplify ring-0 code. This also make sure that any
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| 224 | * later calls to grow the statistics tables will fail.
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| 225 | */
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| 226 | if (!SUPR3IsDriverless())
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| 227 | {
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| 228 | int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_SYNC_STATS_INDICES, 0, NULL);
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| 229 | AssertLogRelRCReturn(rc, rc);
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| 230 | }
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| 231 |
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| 232 | /*
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| 233 | * Register I/O port and MMIO stats now that we're done registering MMIO
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| 234 | * regions and won't grow the table again.
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| 235 | */
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| 236 | for (uint32_t i = 0; i < pVM->iom.s.cIoPortRegs; i++)
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| 237 | {
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| 238 | PIOMIOPORTENTRYR3 pRegEntry = &pVM->iom.s.paIoPortRegs[i];
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| 239 | if ( pRegEntry->fMapped
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| 240 | && pRegEntry->idxStats != UINT16_MAX)
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| 241 | iomR3IoPortRegStats(pVM, pRegEntry);
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| 242 | }
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| 243 |
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| 244 | for (uint32_t i = 0; i < pVM->iom.s.cMmioRegs; i++)
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| 245 | {
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| 246 | PIOMMMIOENTRYR3 pRegEntry = &pVM->iom.s.paMmioRegs[i];
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| 247 | if ( pRegEntry->fMapped
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| 248 | && pRegEntry->idxStats != UINT16_MAX)
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| 249 | iomR3MmioRegStats(pVM, pRegEntry);
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| 250 | }
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| 251 | }
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| 252 | #else
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| 253 | RT_NOREF(pVM, enmWhat);
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| 254 | #endif
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| 255 |
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| 256 | /*
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| 257 | * Freeze I/O port and MMIO registrations.
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| 258 | */
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| 259 | pVM->iom.s.fIoPortsFrozen = true;
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| 260 | pVM->iom.s.fMmioFrozen = true;
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| 261 | return VINF_SUCCESS;
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| 262 | }
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| 263 |
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| 264 |
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| 265 | /**
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| 266 | * The VM is being reset.
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| 267 | *
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| 268 | * @param pVM The cross context VM structure.
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| 269 | */
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| 270 | VMMR3_INT_DECL(void) IOMR3Reset(PVM pVM)
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| 271 | {
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| 272 | RT_NOREF(pVM);
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| 273 | }
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| 274 |
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| 275 |
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| 276 | /**
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| 277 | * Applies relocations to data and code managed by this
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| 278 | * component. This function will be called at init and
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| 279 | * whenever the VMM need to relocate it self inside the GC.
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| 280 | *
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| 281 | * The IOM will update the addresses used by the switcher.
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| 282 | *
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| 283 | * @param pVM The cross context VM structure.
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| 284 | * @param offDelta Relocation delta relative to old location.
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| 285 | */
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| 286 | VMMR3_INT_DECL(void) IOMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
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| 287 | {
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| 288 | RT_NOREF(pVM, offDelta);
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| 289 | }
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| 290 |
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| 291 | /**
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| 292 | * Terminates the IOM.
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| 293 | *
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| 294 | * Termination means cleaning up and freeing all resources,
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| 295 | * the VM it self is at this point powered off or suspended.
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| 296 | *
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| 297 | * @returns VBox status code.
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| 298 | * @param pVM The cross context VM structure.
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| 299 | */
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| 300 | VMMR3_INT_DECL(int) IOMR3Term(PVM pVM)
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| 301 | {
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| 302 | /*
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| 303 | * IOM is not owning anything but automatically freed resources,
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| 304 | * so there's nothing to do here.
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| 305 | */
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| 306 | NOREF(pVM);
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| 307 | return VINF_SUCCESS;
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| 308 | }
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| 309 |
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| 310 |
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| 311 | /**
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| 312 | * Handles the unlikely and probably fatal merge cases.
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| 313 | *
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| 314 | * @returns Merged status code.
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| 315 | * @param rcStrict Current EM status code.
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| 316 | * @param rcStrictCommit The IOM I/O or MMIO write commit status to merge
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| 317 | * with @a rcStrict.
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| 318 | * @param rcIom For logging purposes only.
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| 319 | * @param pVCpu The cross context virtual CPU structure of the
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| 320 | * calling EMT. For logging purposes.
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| 321 | */
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| 322 | DECL_NO_INLINE(static, VBOXSTRICTRC) iomR3MergeStatusSlow(VBOXSTRICTRC rcStrict, VBOXSTRICTRC rcStrictCommit,
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| 323 | int rcIom, PVMCPU pVCpu)
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| 324 | {
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| 325 | if (RT_FAILURE_NP(rcStrict))
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| 326 | return rcStrict;
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| 327 |
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| 328 | if (RT_FAILURE_NP(rcStrictCommit))
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| 329 | return rcStrictCommit;
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| 330 |
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| 331 | if (rcStrict == rcStrictCommit)
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| 332 | return rcStrictCommit;
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| 333 |
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| 334 | AssertLogRelMsgFailed(("rcStrictCommit=%Rrc rcStrict=%Rrc IOPort={%#06x<-%#xx/%u} MMIO={%RGp<-%.*Rhxs} (rcIom=%Rrc)\n",
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| 335 | VBOXSTRICTRC_VAL(rcStrictCommit), VBOXSTRICTRC_VAL(rcStrict),
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| 336 | pVCpu->iom.s.PendingIOPortWrite.IOPort,
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| 337 | pVCpu->iom.s.PendingIOPortWrite.u32Value, pVCpu->iom.s.PendingIOPortWrite.cbValue,
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| 338 | pVCpu->iom.s.PendingMmioWrite.GCPhys,
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| 339 | pVCpu->iom.s.PendingMmioWrite.cbValue, &pVCpu->iom.s.PendingMmioWrite.abValue[0], rcIom));
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| 340 | return VERR_IOM_FF_STATUS_IPE;
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| 341 | }
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| 342 |
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| 343 |
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| 344 | /**
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| 345 | * Helper for IOMR3ProcessForceFlag.
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| 346 | *
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| 347 | * @returns Merged status code.
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| 348 | * @param rcStrict Current EM status code.
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| 349 | * @param rcStrictCommit The IOM I/O or MMIO write commit status to merge
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| 350 | * with @a rcStrict.
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| 351 | * @param rcIom Either VINF_IOM_R3_IOPORT_COMMIT_WRITE or
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| 352 | * VINF_IOM_R3_MMIO_COMMIT_WRITE.
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| 353 | * @param pVCpu The cross context virtual CPU structure of the
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| 354 | * calling EMT.
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| 355 | */
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| 356 | DECLINLINE(VBOXSTRICTRC) iomR3MergeStatus(VBOXSTRICTRC rcStrict, VBOXSTRICTRC rcStrictCommit, int rcIom, PVMCPU pVCpu)
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| 357 | {
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| 358 | /* Simple. */
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| 359 | if (RT_LIKELY(rcStrict == rcIom || rcStrict == VINF_EM_RAW_TO_R3 || rcStrict == VINF_SUCCESS))
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| 360 | return rcStrictCommit;
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| 361 |
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| 362 | if (RT_LIKELY(rcStrictCommit == VINF_SUCCESS))
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| 363 | return rcStrict;
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| 364 |
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| 365 | /* EM scheduling status codes. */
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| 366 | if (RT_LIKELY( rcStrict >= VINF_EM_FIRST
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| 367 | && rcStrict <= VINF_EM_LAST))
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| 368 | {
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| 369 | if (RT_LIKELY( rcStrictCommit >= VINF_EM_FIRST
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| 370 | && rcStrictCommit <= VINF_EM_LAST))
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| 371 | return rcStrict < rcStrictCommit ? rcStrict : rcStrictCommit;
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| 372 | }
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| 373 |
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| 374 | /* Unlikely */
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| 375 | return iomR3MergeStatusSlow(rcStrict, rcStrictCommit, rcIom, pVCpu);
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| 376 | }
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| 377 |
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| 378 |
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| 379 | /**
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| 380 | * Called by force-flag handling code when VMCPU_FF_IOM is set.
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| 381 | *
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| 382 | * @returns Merge between @a rcStrict and what the commit operation returned.
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| 383 | * @param pVM The cross context VM structure.
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| 384 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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| 385 | * @param rcStrict The status code returned by ring-0 or raw-mode.
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| 386 | * @thread EMT(pVCpu)
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| 387 | *
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| 388 | * @remarks The VMCPU_FF_IOM flag is handled before the status codes by EM, so
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| 389 | * we're very likely to see @a rcStrict set to
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| 390 | * VINF_IOM_R3_IOPORT_COMMIT_WRITE and VINF_IOM_R3_MMIO_COMMIT_WRITE
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| 391 | * here.
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| 392 | */
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| 393 | VMMR3_INT_DECL(VBOXSTRICTRC) IOMR3ProcessForceFlag(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rcStrict)
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| 394 | {
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| 395 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_IOM);
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| 396 | Assert(pVCpu->iom.s.PendingIOPortWrite.cbValue || pVCpu->iom.s.PendingMmioWrite.cbValue);
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| 397 |
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| 398 | if (pVCpu->iom.s.PendingIOPortWrite.cbValue)
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| 399 | {
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| 400 | Log5(("IOM: Dispatching pending I/O port write: %#x LB %u -> %RTiop\n", pVCpu->iom.s.PendingIOPortWrite.u32Value,
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| 401 | pVCpu->iom.s.PendingIOPortWrite.cbValue, pVCpu->iom.s.PendingIOPortWrite.IOPort));
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| 402 | STAM_COUNTER_INC(&pVM->iom.s.StatIoPortCommits);
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| 403 | VBOXSTRICTRC rcStrictCommit = IOMIOPortWrite(pVM, pVCpu, pVCpu->iom.s.PendingIOPortWrite.IOPort,
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| 404 | pVCpu->iom.s.PendingIOPortWrite.u32Value,
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| 405 | pVCpu->iom.s.PendingIOPortWrite.cbValue);
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| 406 | pVCpu->iom.s.PendingIOPortWrite.cbValue = 0;
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| 407 | rcStrict = iomR3MergeStatus(rcStrict, rcStrictCommit, VINF_IOM_R3_IOPORT_COMMIT_WRITE, pVCpu);
|
|---|
| 408 | }
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|---|
| 409 |
|
|---|
| 410 |
|
|---|
| 411 | if (pVCpu->iom.s.PendingMmioWrite.cbValue)
|
|---|
| 412 | {
|
|---|
| 413 | Log5(("IOM: Dispatching pending MMIO write: %RGp LB %#x\n",
|
|---|
| 414 | pVCpu->iom.s.PendingMmioWrite.GCPhys, pVCpu->iom.s.PendingMmioWrite.cbValue));
|
|---|
| 415 |
|
|---|
| 416 | /* Use new MMIO handle hint and bypass PGM if it still looks right. */
|
|---|
| 417 | size_t idxMmioRegionHint = pVCpu->iom.s.PendingMmioWrite.idxMmioRegionHint;
|
|---|
| 418 | if (idxMmioRegionHint < pVM->iom.s.cMmioRegs)
|
|---|
| 419 | {
|
|---|
| 420 | PIOMMMIOENTRYR3 pRegEntry = &pVM->iom.s.paMmioRegs[idxMmioRegionHint];
|
|---|
| 421 | RTGCPHYS const GCPhysMapping = pRegEntry->GCPhysMapping;
|
|---|
| 422 | RTGCPHYS const offRegion = pVCpu->iom.s.PendingMmioWrite.GCPhys - GCPhysMapping;
|
|---|
| 423 | if (offRegion < pRegEntry->cbRegion && GCPhysMapping != NIL_RTGCPHYS)
|
|---|
| 424 | {
|
|---|
| 425 | STAM_COUNTER_INC(&pVM->iom.s.StatMmioCommitsDirect);
|
|---|
| 426 | VBOXSTRICTRC rcStrictCommit = iomR3MmioCommitWorker(pVM, pVCpu, pRegEntry, offRegion);
|
|---|
| 427 | pVCpu->iom.s.PendingMmioWrite.cbValue = 0;
|
|---|
| 428 | return iomR3MergeStatus(rcStrict, rcStrictCommit, VINF_IOM_R3_MMIO_COMMIT_WRITE, pVCpu);
|
|---|
| 429 | }
|
|---|
| 430 | }
|
|---|
| 431 |
|
|---|
| 432 | /* Fall back on PGM. */
|
|---|
| 433 | STAM_COUNTER_INC(&pVM->iom.s.StatMmioCommitsPgm);
|
|---|
| 434 | VBOXSTRICTRC rcStrictCommit = PGMPhysWrite(pVM, pVCpu->iom.s.PendingMmioWrite.GCPhys,
|
|---|
| 435 | pVCpu->iom.s.PendingMmioWrite.abValue, pVCpu->iom.s.PendingMmioWrite.cbValue,
|
|---|
| 436 | PGMACCESSORIGIN_IOM);
|
|---|
| 437 | pVCpu->iom.s.PendingMmioWrite.cbValue = 0;
|
|---|
| 438 | rcStrict = iomR3MergeStatus(rcStrict, rcStrictCommit, VINF_IOM_R3_MMIO_COMMIT_WRITE, pVCpu);
|
|---|
| 439 | }
|
|---|
| 440 |
|
|---|
| 441 | return rcStrict;
|
|---|
| 442 | }
|
|---|
| 443 |
|
|---|
| 444 |
|
|---|
| 445 | /**
|
|---|
| 446 | * Notification from DBGF that the number of active I/O port or MMIO
|
|---|
| 447 | * breakpoints has change.
|
|---|
| 448 | *
|
|---|
| 449 | * For performance reasons, IOM will only call DBGF before doing I/O and MMIO
|
|---|
| 450 | * accesses where there are armed breakpoints.
|
|---|
| 451 | *
|
|---|
| 452 | * @param pVM The cross context VM structure.
|
|---|
| 453 | * @param fPortIo True if there are armed I/O port breakpoints.
|
|---|
| 454 | * @param fMmio True if there are armed MMIO breakpoints.
|
|---|
| 455 | */
|
|---|
| 456 | VMMR3_INT_DECL(void) IOMR3NotifyBreakpointCountChange(PVM pVM, bool fPortIo, bool fMmio)
|
|---|
| 457 | {
|
|---|
| 458 | /** @todo I/O breakpoints. */
|
|---|
| 459 | RT_NOREF3(pVM, fPortIo, fMmio);
|
|---|
| 460 | }
|
|---|
| 461 |
|
|---|
| 462 |
|
|---|
| 463 | /**
|
|---|
| 464 | * Notification from DBGF that an event has been enabled or disabled.
|
|---|
| 465 | *
|
|---|
| 466 | * For performance reasons, IOM may cache the state of events it implements.
|
|---|
| 467 | *
|
|---|
| 468 | * @param pVM The cross context VM structure.
|
|---|
| 469 | * @param enmEvent The event.
|
|---|
| 470 | * @param fEnabled The new state.
|
|---|
| 471 | */
|
|---|
| 472 | VMMR3_INT_DECL(void) IOMR3NotifyDebugEventChange(PVM pVM, DBGFEVENT enmEvent, bool fEnabled)
|
|---|
| 473 | {
|
|---|
| 474 | /** @todo IOM debug events. */
|
|---|
| 475 | RT_NOREF3(pVM, enmEvent, fEnabled);
|
|---|
| 476 | }
|
|---|
| 477 |
|
|---|
