IEMR3.cpp@ 101521

Last change on this file since 101521 was 101163, checked in by vboxsync, 15 months ago
VMM/IEM: Experimental recompilation of threaded blocks into native code on linux.amd64. bugref:10370
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 36.1 KB

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1	/* $Id: IEMR3.cpp 101163 2023-09-18 20:44:24Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#include <VBox/vmm/iem.h>
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/vmm/mm.h>
37	#if defined(VBOX_VMM_TARGET_ARMV8)
38	# include "IEMInternal-armv8.h"
39	#else
40	# include "IEMInternal.h"
41	#endif
42	#include <VBox/vmm/vm.h>
43	#include <VBox/vmm/vmapi.h>
44	#include <VBox/err.h>
45	#ifdef VBOX_WITH_DEBUGGER
46	# include <VBox/dbg.h>
47	#endif
48
49	#include <iprt/assert.h>
50	#include <iprt/getopt.h>
51	#include <iprt/string.h>
52
53
54	/*********************************************************************************************************************************
55	* Internal Functions *
56	*********************************************************************************************************************************/
57	static FNDBGFINFOARGVINT iemR3InfoITlb;
58	static FNDBGFINFOARGVINT iemR3InfoDTlb;
59	#ifdef VBOX_WITH_DEBUGGER
60	static void iemR3RegisterDebuggerCommands(void);
61	#endif
62
63
64	#if !defined(VBOX_VMM_TARGET_ARMV8)
65	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
66	{
67	switch (enmTargetCpu)
68	{
69	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
70	CASE_RET_STR(IEMTARGETCPU_8086);
71	CASE_RET_STR(IEMTARGETCPU_V20);
72	CASE_RET_STR(IEMTARGETCPU_186);
73	CASE_RET_STR(IEMTARGETCPU_286);
74	CASE_RET_STR(IEMTARGETCPU_386);
75	CASE_RET_STR(IEMTARGETCPU_486);
76	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
77	CASE_RET_STR(IEMTARGETCPU_PPRO);
78	CASE_RET_STR(IEMTARGETCPU_CURRENT);
79	#undef CASE_RET_STR
80	default: return "Unknown";
81	}
82	}
83	#endif
84
85
86	/**
87	* Initializes the interpreted execution manager.
88	*
89	* This must be called after CPUM as we're quering information from CPUM about
90	* the guest and host CPUs.
91	*
92	* @returns VBox status code.
93	* @param pVM The cross context VM structure.
94	*/
95	VMMR3DECL(int) IEMR3Init(PVM pVM)
96	{
97	/*
98	* Read configuration.
99	*/
100	#if (!defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)) \|\| defined(VBOX_WITH_IEM_RECOMPILER)
101	PCFGMNODE const pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
102	int rc;
103	#endif
104
105	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
106	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
107	* Controls whether the custom VBox specific CPUID host call interface is
108	* enabled or not. */
109	# ifdef DEBUG_bird
110	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
111	# else
112	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
113	# endif
114	AssertLogRelRCReturn(rc, rc);
115	#endif
116
117	#ifdef VBOX_WITH_IEM_RECOMPILER
118	/** @cfgm{/IEM/MaxTbCount, uint32_t, 524288}
119	* Max number of TBs per EMT. */
120	uint32_t cMaxTbs = 0;
121	rc = CFGMR3QueryU32Def(pIem, "MaxTbCount", &cMaxTbs, _512K);
122	AssertLogRelRCReturn(rc, rc);
123	if (cMaxTbs < _16K \|\| cMaxTbs > _8M)
124	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
125	"MaxTbCount value %u (%#x) is out of range (min %u, max %u)", cMaxTbs, cMaxTbs, _16K, _8M);
126
127	/** @cfgm{/IEM/InitialTbCount, uint32_t, 32678}
128	* Initial (minimum) number of TBs per EMT in ring-3. */
129	uint32_t cInitialTbs = 0;
130	rc = CFGMR3QueryU32Def(pIem, "InitialTbCount", &cInitialTbs, RT_MIN(cMaxTbs, _32K));
131	AssertLogRelRCReturn(rc, rc);
132	if (cInitialTbs < _16K \|\| cInitialTbs > _8M)
133	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
134	"InitialTbCount value %u (%#x) is out of range (min %u, max %u)", cInitialTbs, cInitialTbs, _16K, _8M);
135
136	/* Check that the two values makes sense together. Expect user/api to do
137	the right thing or get lost. */
138	if (cInitialTbs > cMaxTbs)
139	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
140	"InitialTbCount value %u (%#x) is higher than the MaxTbCount value %u (%#x)",
141	cInitialTbs, cInitialTbs, cMaxTbs, cMaxTbs);
142
143	/** @cfgm{/IEM/MaxExecMem, uint64_t, 512 MiB}
144	* Max executable memory for recompiled code per EMT. */
145	uint64_t cbMaxExec = 0;
146	rc = CFGMR3QueryU64Def(pIem, "MaxExecMem", &cbMaxExec, _512M);
147	AssertLogRelRCReturn(rc, rc);
148	if (cbMaxExec < _1M \|\| cbMaxExec > 16*_1G64)
149	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
150	"MaxExecMem value %'RU64 (%#RX64) is out of range (min %'RU64, max %'RU64)",
151	cbMaxExec, cbMaxExec, (uint64_t)_1M, 16*_1G64);
152
153	/** @cfgm{/IEM/ExecChunkSize, uint32_t, 0 (auto)}
154	* The executable memory allocator chunk size. */
155	uint32_t cbChunkExec = 0;
156	rc = CFGMR3QueryU32Def(pIem, "ExecChunkSize", &cbChunkExec, 0);
157	AssertLogRelRCReturn(rc, rc);
158	if (cbChunkExec != 0 && cbChunkExec != UINT32_MAX && (cbChunkExec < _1M \|\| cbChunkExec > _256M))
159	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
160	"ExecChunkSize value %'RU32 (%#RX32) is out of range (min %'RU32, max %'RU32)",
161	cbChunkExec, cbChunkExec, _1M, _256M);
162
163	/** @cfgm{/IEM/InitialExecMemSize, uint64_t, 1}
164	* The initial executable memory allocator size (per EMT). The value is
165	* rounded up to the nearest chunk size, so 1 byte means one chunk. */
166	uint64_t cbInitialExec = 0;
167	rc = CFGMR3QueryU64Def(pIem, "InitialExecMemSize", &cbInitialExec, 0);
168	AssertLogRelRCReturn(rc, rc);
169	if (cbInitialExec > cbMaxExec)
170	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
171	"InitialExecMemSize value %'RU64 (%#RX64) is out of range (max %'RU64)",
172	cbInitialExec, cbInitialExec, cbMaxExec);
173
174	#endif /* VBOX_WITH_IEM_RECOMPILER*/
175
176	/*
177	* Initialize per-CPU data and register statistics.
178	*/
179	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
180	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
181
182	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
183	{
184	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
185	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
186
187	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
188	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
189
190	/*
191	* Host and guest CPU information.
192	*/
193	if (idCpu == 0)
194	{
195	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
196	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
197	#if !defined(VBOX_VMM_TARGET_ARMV8)
198	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
199	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
200	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
201	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
202	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
203	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
204	else
205	# endif
206	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
207	#else
208	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
209	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
210	#endif
211
212	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
213	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
214	{
215	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
216	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
217	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
218	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
219	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
220	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
221	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
222	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
223	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
224	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
225	}
226	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
227	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
228	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
229	#else
230	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
231	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
232	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
233	#endif
234	}
235	else
236	{
237	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
238	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
239	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
240	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
241	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
242	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
243	#endif
244	}
245
246	/*
247	* Mark all buffers free.
248	*/
249	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
250	while (iMemMap-- > 0)
251	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
252	}
253
254
255	#ifdef VBOX_WITH_IEM_RECOMPILER
256	/*
257	* Initialize the TB allocator and cache (/ hash table).
258	*
259	* This is done by each EMT to try get more optimal thread/numa locality of
260	* the allocations.
261	*/
262	rc = VMR3ReqCallWait(pVM, VMCPUID_ALL, (PFNRT)iemTbInit, 6,
263	pVM, cInitialTbs, cMaxTbs, cbInitialExec, cbMaxExec, cbChunkExec);
264	AssertLogRelRCReturn(rc, rc);
265	#endif
266
267	/*
268	* Register statistics.
269	*/
270	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
271	{
272	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) /* quick fix for stupid structure duplication non-sense */
273	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
274
275	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
276	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
277	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
278	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
279	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
280	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
281	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
282	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
283	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
284	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
285	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
286	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
287	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
288	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
289	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
290	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
291	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
292	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
293
294	# ifdef VBOX_WITH_STATISTICS
295	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
296	"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
297	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
298	"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
299	# endif
300	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
301	"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
302	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
303	"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
304	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
305	"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
306	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
307	"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
308
309	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
310	"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
311	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
312	"Data TLB safe read path", "/IEM/CPU%u/DataTlb-SafeReads", idCpu);
313	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeWritePath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
314	"Data TLB safe write path", "/IEM/CPU%u/DataTlb-SafeWrites", idCpu);
315	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
316	"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
317	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
318	"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
319
320	#ifdef VBOX_WITH_IEM_RECOMPILER
321	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecNative, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
322	"Executed native translation block", "/IEM/CPU%u/re/cTbExecNative", idCpu);
323	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecThreaded, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
324	"Executed threaded translation block", "/IEM/CPU%u/re/cTbExecThreaded", idCpu);
325	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
326	"Times TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecBreaks", idCpu);
327
328	PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
329	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatAllocs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
330	"Translation block allocations", "/IEM/CPU%u/re/cTbAllocCalls", idCpu);
331	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatFrees, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
332	"Translation block frees", "/IEM/CPU%u/re/cTbFreeCalls", idCpu);
333	# ifdef VBOX_WITH_STATISTICS
334	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
335	"Time spent freeing up TBs when full at alloc", "/IEM/CPU%u/re/TbPruningAlloc", idCpu);
336	# endif
337	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cAllocatedChunks, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
338	"Populated TB chunks", "/IEM/CPU%u/re/cTbChunks", idCpu);
339	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxChunks, STAMTYPE_U8, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
340	"Max number of TB chunks", "/IEM/CPU%u/re/cTbChunksMax", idCpu);
341	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cTotalTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
342	"Total number of TBs in the allocator", "/IEM/CPU%u/re/cTbTotal", idCpu);
343	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
344	"Max total number of TBs allowed", "/IEM/CPU%u/re/cTbTotalMax", idCpu);
345	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cInUseTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
346	"Number of currently allocated TBs", "/IEM/CPU%u/re/cTbAllocated", idCpu);
347	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cNativeTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
348	"Number of currently allocated native TBs", "/IEM/CPU%u/re/cTbAllocatedNative", idCpu);
349	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cThreadedTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
350	"Number of currently allocated threaded TBs", "/IEM/CPU%u/re/cTbAllocatedThreaded", idCpu);
351
352	PIEMTBCACHE const pTbCache = pVCpu->iem.s.pTbCacheR3;
353	STAMR3RegisterF(pVM, (void *)&pTbCache->cHash, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
354	"Translation block lookup table size", "/IEM/CPU%u/re/cTbHashTab", idCpu);
355
356	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHits, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
357	"Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
358	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
359	"Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
360	STAMR3RegisterF(pVM, (void *)&pTbCache->cCollisions, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
361	"Translation block hash table collisions", "/IEM/CPU%u/re/cTbCollisions", idCpu);
362	# ifdef VBOX_WITH_STATISTICS
363	STAMR3RegisterF(pVM, (void *)&pTbCache->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
364	"Time spent shortening collision lists", "/IEM/CPU%u/re/TbPruningCollisions", idCpu);
365	# endif
366
367	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
368	"Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
369	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
370	"Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
371
372	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
373	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
374	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
375	"TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
376	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
377	"Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
378	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
379	"Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
380	#endif
381
382	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
383	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
384	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
385	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
386	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
387	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
388
389	# if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
390	/* Instruction statistics: */
391	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
392	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
393	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
394	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
395	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
396	# include "IEMInstructionStatisticsTmpl.h"
397	# undef IEM_DO_INSTR_STAT
398	# endif
399
400	#endif /* !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) - quick fix for stupid structure duplication non-sense */
401	}
402
403	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
404	/*
405	* Register the per-VM VMX APIC-access page handler type.
406	*/
407	if (pVM->cpum.ro.GuestFeatures.fVmx)
408	{
409	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
410	iemVmxApicAccessPageHandler,
411	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
412	AssertLogRelRCReturn(rc, rc);
413	}
414	#endif
415
416	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
417	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
418	#ifdef VBOX_WITH_DEBUGGER
419	iemR3RegisterDebuggerCommands();
420	#endif
421
422	return VINF_SUCCESS;
423	}
424
425
426	VMMR3DECL(int) IEMR3Term(PVM pVM)
427	{
428	NOREF(pVM);
429	return VINF_SUCCESS;
430	}
431
432
433	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
434	{
435	RT_NOREF(pVM);
436	}
437
438
439	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
440	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
441	{
442	if (*pfHeader)
443	return;
444	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
445	*pfHeader = true;
446	}
447
448
449	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
450	static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe, uint32_t uSlot)
451	{
452	pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
453	uSlot,
454	(pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
455	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
456	: "expired",
457	(pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
458	pTlbe->GCPhys, pTlbe->pbMappingR3,
459	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
460	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
461	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
462	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
463	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
464	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
465	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
466	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
467	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
468	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
469	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
470	}
471
472
473	/** Displays one or more TLB slots. */
474	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
475	uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
476	{
477	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
478	{
479	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
480	{
481	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
482	cSlots, RT_ELEMENTS(pTlb->aEntries));
483	cSlots = RT_ELEMENTS(pTlb->aEntries);
484	}
485
486	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
487	while (cSlots-- > 0)
488	{
489	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
490	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
491	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
492	}
493	}
494	else
495	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
496	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
497	}
498
499
500	/** Displays the TLB slot for the given address. */
501	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
502	uint64_t uAddress, bool *pfHeader)
503	{
504	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
505
506	uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
507	uint32_t const uSlot = (uint8_t)uTag;
508	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
509	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
510	Tlbe.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
511	: (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
512	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
513	}
514
515
516	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
517	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
518	{
519	/*
520	* This is entirely argument driven.
521	*/
522	static RTGETOPTDEF const s_aOptions[] =
523	{
524	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
525	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
526	{ "all", 'A', RTGETOPT_REQ_NOTHING },
527	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
528	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
529	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
530	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
531	};
532
533	char szDefault[] = "-A";
534	char *papszDefaults[2] = { szDefault, NULL };
535	if (cArgs == 0)
536	{
537	cArgs = 1;
538	papszArgs = papszDefaults;
539	}
540
541	RTGETOPTSTATE State;
542	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
543	AssertRCReturnVoid(rc);
544
545	bool fNeedHeader = true;
546	bool fAddressMode = true;
547	PVMCPU pVCpu = VMMGetCpu(pVM);
548	if (!pVCpu)
549	pVCpu = VMMGetCpuById(pVM, 0);
550
551	RTGETOPTUNION ValueUnion;
552	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
553	{
554	switch (rc)
555	{
556	case 'c':
557	if (ValueUnion.u32 >= pVM->cCpus)
558	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
559	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
560	{
561	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
562	fNeedHeader = true;
563	}
564	break;
565
566	case 'a':
567	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
568	ValueUnion.u64, &fNeedHeader);
569	fAddressMode = true;
570	break;
571
572	case 'A':
573	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
574	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
575	break;
576
577	case 'r':
578	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
579	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
580	fAddressMode = false;
581	break;
582
583	case 's':
584	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
585	ValueUnion.u32, 1, &fNeedHeader);
586	fAddressMode = false;
587	break;
588
589	case VINF_GETOPT_NOT_OPTION:
590	if (fAddressMode)
591	{
592	uint64_t uAddr;
593	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
594	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
595	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
596	uAddr, &fNeedHeader);
597	else
598	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
599	}
600	else
601	{
602	uint32_t uSlot;
603	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
604	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
605	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
606	uSlot, 1, &fNeedHeader);
607	else
608	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
609	}
610	break;
611
612	case 'h':
613	pHlp->pfnPrintf(pHlp,
614	"Usage: info %ctlb [options]\n"
615	"\n"
616	"Options:\n"
617	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
618	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
619	" -A, --all, all\n"
620	" Display all the TLB entries (default if no other args).\n"
621	" -a<virt>, --address=<virt>\n"
622	" Shows the TLB entry for the specified guest virtual address.\n"
623	" -r<slot:count>, --range=<slot:count>\n"
624	" Shows the TLB entries for the specified slot range.\n"
625	" -s<slot>,--slot=<slot>\n"
626	" Shows the given TLB slot.\n"
627	"\n"
628	"Non-options are interpreted according to the last -a, -r or -s option,\n"
629	"defaulting to addresses if not preceeded by any of those options.\n"
630	, fITlb ? 'i' : 'd');
631	return;
632
633	default:
634	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
635	return;
636	}
637	}
638	}
639
640
641	/**
642	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
643	*/
644	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
645	{
646	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
647	}
648
649
650	/**
651	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
652	*/
653	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
654	{
655	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
656	}
657
658
659	#ifdef VBOX_WITH_DEBUGGER
660
661	/** @callback_method_impl{FNDBGCCMD,
662	* Implements the '.alliem' command. }
663	*/
664	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
665	{
666	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
667	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
668	if (pVCpu)
669	{
670	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
671	return VINF_SUCCESS;
672	}
673	RT_NOREF(paArgs, cArgs);
674	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
675	}
676
677
678	/**
679	* Called by IEMR3Init to register debugger commands.
680	*/
681	static void iemR3RegisterDebuggerCommands(void)
682	{
683	/*
684	* Register debugger commands.
685	*/
686	static DBGCCMD const s_aCmds[] =
687	{
688	{
689	/* .pszCmd = */ "iemflushtlb",
690	/* .cArgsMin = */ 0,
691	/* .cArgsMax = */ 0,
692	/* .paArgDescs = */ NULL,
693	/* .cArgDescs = */ 0,
694	/* .fFlags = */ 0,
695	/* .pfnHandler = */ iemR3DbgFlushTlbs,
696	/* .pszSyntax = */ "",
697	/* .pszDescription = */ "Flushed the code and data TLBs"
698	},
699	};
700
701	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
702	AssertLogRelRC(rc);
703	}
704
705	#endif
706

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 101521

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