VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HWACCM.cpp@ 42062

Last change on this file since 42062 was 42033, checked in by vboxsync, 12 years ago

VMM: RDTSCP support bits.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 137.2 KB
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1/* $Id: HWACCM.cpp 42033 2012-07-06 03:27:36Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hwacc_vmx.h>
38#include <VBox/vmm/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/asm-amd64-x86.h>
48#include <iprt/string.h>
49#include <iprt/env.h>
50#include <iprt/thread.h>
51
52/*******************************************************************************
53* Global Variables *
54*******************************************************************************/
55#ifdef VBOX_WITH_STATISTICS
56# define EXIT_REASON(def, val, str) #def " - " #val " - " str
57# define EXIT_REASON_NIL() NULL
58/** Exit reason descriptions for VT-x, used to describe statistics. */
59static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
60{
61 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
62 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
63 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
64 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
65 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
66 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
67 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
68 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
71 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
74 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
75 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
76 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
77 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
78 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
79 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
80 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
81 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
82 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
83 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
84 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
85 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
86 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
87 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
88 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
89 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
90 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
91 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
92 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
93 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
94 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
95 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
98 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
101 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
102 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
105 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
108 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
109 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
110 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
111 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
112 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
113 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
114 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
115 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
116 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
117 EXIT_REASON_NIL()
118};
119/** Exit reason descriptions for AMD-V, used to describe statistics. */
120static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
121{
122 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
123 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
124 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
125 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
126 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
127 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
128 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
129 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
130 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
131 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
132 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
133 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
134 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
135 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
136 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
137 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
154 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
155 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
156 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
157 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
158 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
159 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
160 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
161 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
162 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
163 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
164 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
165 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
166 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
167 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
168 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
169 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
218 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
219 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
221 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
222 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
223 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
224 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
225 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
226 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
232 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
233 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
234 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
235 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
236 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
237 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
238 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
239 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
240 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
241 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
242 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
243 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
245 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
246 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
247 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
248 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
249 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
250 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
251 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
252 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
253 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
254 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
255 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
256 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
257 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
258 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
259 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
260 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
261 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
262 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
263 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
264 EXIT_REASON_NIL()
265};
266# undef EXIT_REASON
267# undef EXIT_REASON_NIL
268#endif /* VBOX_WITH_STATISTICS */
269
270/*******************************************************************************
271* Internal Functions *
272*******************************************************************************/
273static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
274static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
275static int hwaccmR3InitCPU(PVM pVM);
276static int hwaccmR3InitFinalizeR0(PVM pVM);
277static int hwaccmR3TermCPU(PVM pVM);
278
279
280/**
281 * Initializes the HWACCM.
282 *
283 * @returns VBox status code.
284 * @param pVM Pointer to the VM.
285 */
286VMMR3DECL(int) HWACCMR3Init(PVM pVM)
287{
288 LogFlow(("HWACCMR3Init\n"));
289
290 /*
291 * Assert alignment and sizes.
292 */
293 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
294 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
295
296 /* Some structure checks. */
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
300
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
306 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
307 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
308 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
311 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
312
313
314 /*
315 * Register the saved state data unit.
316 */
317 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
318 NULL, NULL, NULL,
319 NULL, hwaccmR3Save, NULL,
320 NULL, hwaccmR3Load, NULL);
321 if (RT_FAILURE(rc))
322 return rc;
323
324 /* Misc initialisation. */
325 pVM->hwaccm.s.vmx.fSupported = false;
326 pVM->hwaccm.s.svm.fSupported = false;
327 pVM->hwaccm.s.vmx.fEnabled = false;
328 pVM->hwaccm.s.svm.fEnabled = false;
329
330 pVM->hwaccm.s.fNestedPaging = false;
331 pVM->hwaccm.s.fLargePages = false;
332
333 /* Disabled by default. */
334 pVM->fHWACCMEnabled = false;
335
336 /*
337 * Check CFGM options.
338 */
339 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
340 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
341 /* Nested paging: disabled by default. */
342 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
343 AssertRC(rc);
344
345 /* Large pages: disabled by default. */
346 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
347 AssertRC(rc);
348
349 /* VT-x VPID: disabled by default. */
350 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
351 AssertRC(rc);
352
353 /* HWACCM support must be explicitely enabled in the configuration file. */
354 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
355 AssertRC(rc);
356
357 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
358 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
359 AssertRC(rc);
360
361#ifdef RT_OS_DARWIN
362 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
363#else
364 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
365#endif
366 {
367 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
368 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
369 return VERR_HWACCM_CONFIG_MISMATCH;
370 }
371
372 if (VMMIsHwVirtExtForced(pVM))
373 pVM->fHWACCMEnabled = true;
374
375#if HC_ARCH_BITS == 32
376 /*
377 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
378 * (To use the default, don't set 64bitEnabled in CFGM.)
379 */
380 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
381 AssertLogRelRCReturn(rc, rc);
382 if (pVM->hwaccm.s.fAllow64BitGuests)
383 {
384# ifdef RT_OS_DARWIN
385 if (!VMMIsHwVirtExtForced(pVM))
386# else
387 if (!pVM->hwaccm.s.fAllowed)
388# endif
389 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
390 }
391#else
392 /*
393 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
394 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
395 */
396 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
397 AssertLogRelRCReturn(rc, rc);
398#endif
399
400
401 /*
402 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
403 * or local init each time we wish to execute guest code.
404 *
405 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
406 */
407 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
408#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
409 false
410#else
411 true
412#endif
413 );
414
415 /* Max number of resume loops. */
416 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
417 AssertRC(rc);
418
419 return rc;
420}
421
422
423/**
424 * Initializes the per-VCPU HWACCM.
425 *
426 * @returns VBox status code.
427 * @param pVM Pointer to the VM.
428 */
429static int hwaccmR3InitCPU(PVM pVM)
430{
431 LogFlow(("HWACCMR3InitCPU\n"));
432
433 for (VMCPUID i = 0; i < pVM->cCpus; i++)
434 {
435 PVMCPU pVCpu = &pVM->aCpus[i];
436
437 pVCpu->hwaccm.s.fActive = false;
438 }
439
440#ifdef VBOX_WITH_STATISTICS
441 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
442 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
443 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
444 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
445
446 /*
447 * Statistics.
448 */
449 for (VMCPUID i = 0; i < pVM->cCpus; i++)
450 {
451 PVMCPU pVCpu = &pVM->aCpus[i];
452 int rc;
453
454 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
455 "/PROF/HWACCM/CPU%d/Poke", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
458 "/PROF/HWACCM/CPU%d/PokeWait", i);
459 AssertRC(rc);
460 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
461 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
462 AssertRC(rc);
463 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
464 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
465 AssertRC(rc);
466 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
467 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
468 AssertRC(rc);
469 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
470 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
471 AssertRC(rc);
472# if 1 /* temporary for tracking down darwin holdup. */
473 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
474 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
475 AssertRC(rc);
476 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
477 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
478 AssertRC(rc);
479 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
480 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
481 AssertRC(rc);
482# endif
483 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
484 "/PROF/HWACCM/CPU%d/InGC", i);
485 AssertRC(rc);
486
487# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
488 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
489 "/PROF/HWACCM/CPU%d/Switcher3264", i);
490 AssertRC(rc);
491# endif
492
493# define HWACCM_REG_COUNTER(a, b) \
494 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
495 AssertRC(rc);
496
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPFEM, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF-EM");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestBP, "/HWACCM/CPU%d/Exit/Trap/Gst/#BP");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXF, "/HWACCM/CPU%d/Exit/Trap/Gst/#XF");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXcpUnk, "/HWACCM/CPU%d/Exit/Trap/Gst/Other");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtscp, "/HWACCM/CPU%d/Exit/Instr/Rdtscp");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMTF, "/HWACCM/CPU%d/Exit/MonitorTrapFlag");
541
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
544
545 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
548
549 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
552 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
553 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
554 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
555 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
556 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
557 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
558 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
559 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
560 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
561 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
562
563 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
564 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
565 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
566
567 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
568 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
569 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
570
571 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadMinimal, "/HWACCM/CPU%d/Load/Minimal");
572 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadFull, "/HWACCM/CPU%d/Load/Full");
573
574#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
575 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
576 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
577#endif
578
579 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite); j++)
580 {
581 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
582 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
583 AssertRC(rc);
584 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
585 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
586 AssertRC(rc);
587 }
588
589#undef HWACCM_REG_COUNTER
590
591 pVCpu->hwaccm.s.paStatExitReason = NULL;
592
593 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
594 AssertRC(rc);
595 if (RT_SUCCESS(rc))
596 {
597 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
598 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
599 {
600 if (papszDesc[j])
601 {
602 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
603 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
604 AssertRC(rc);
605 }
606 }
607 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
608 AssertRC(rc);
609 }
610 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
611# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
612 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
613# else
614 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
615# endif
616
617 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
618 AssertRCReturn(rc, rc);
619 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
620# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
621 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
622# else
623 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
624# endif
625 for (unsigned j = 0; j < 255; j++)
626 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
627 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
628
629 }
630#endif /* VBOX_WITH_STATISTICS */
631
632#ifdef VBOX_WITH_CRASHDUMP_MAGIC
633 /* Magic marker for searching in crash dumps. */
634 for (VMCPUID i = 0; i < pVM->cCpus; i++)
635 {
636 PVMCPU pVCpu = &pVM->aCpus[i];
637
638 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
639 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
640 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
641 }
642#endif
643 return VINF_SUCCESS;
644}
645
646
647/**
648 * Called when a init phase has completed.
649 *
650 * @returns VBox status code.
651 * @param pVM The VM.
652 * @param enmWhat The phase that completed.
653 */
654VMMR3_INT_DECL(int) HWACCMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
655{
656 switch (enmWhat)
657 {
658 case VMINITCOMPLETED_RING3:
659 return hwaccmR3InitCPU(pVM);
660 case VMINITCOMPLETED_RING0:
661 return hwaccmR3InitFinalizeR0(pVM);
662 default:
663 return VINF_SUCCESS;
664 }
665}
666
667
668/**
669 * Turns off normal raw mode features.
670 *
671 * @param pVM Pointer to the VM.
672 */
673static void hwaccmR3DisableRawMode(PVM pVM)
674{
675 /* Disable PATM & CSAM. */
676 PATMR3AllowPatching(pVM, false);
677 CSAMDisableScanning(pVM);
678
679 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
680 SELMR3DisableMonitoring(pVM);
681 TRPMR3DisableMonitoring(pVM);
682
683 /* Disable the switcher code (safety precaution). */
684 VMMR3DisableSwitcher(pVM);
685
686 /* Disable mapping of the hypervisor into the shadow page table. */
687 PGMR3MappingsDisable(pVM);
688
689 /* Disable the switcher */
690 VMMR3DisableSwitcher(pVM);
691
692 /* Reinit the paging mode to force the new shadow mode. */
693 for (VMCPUID i = 0; i < pVM->cCpus; i++)
694 {
695 PVMCPU pVCpu = &pVM->aCpus[i];
696
697 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
698 }
699}
700
701
702/**
703 * Initialize VT-x or AMD-V.
704 *
705 * @returns VBox status code.
706 * @param pVM Pointer to the VM.
707 */
708static int hwaccmR3InitFinalizeR0(PVM pVM)
709{
710 int rc;
711
712 /*
713 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
714 * is already using AMD-V.
715 */
716 if ( !pVM->hwaccm.s.vmx.fSupported
717 && !pVM->hwaccm.s.svm.fSupported
718 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
719 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
720 {
721 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
722 pVM->hwaccm.s.svm.fSupported = true;
723 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
724 }
725 else
726 if ( !pVM->hwaccm.s.vmx.fSupported
727 && !pVM->hwaccm.s.svm.fSupported)
728 {
729 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
730 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
731
732 if (VMMIsHwVirtExtForced(pVM))
733 {
734 switch (pVM->hwaccm.s.lLastError)
735 {
736 case VERR_VMX_NO_VMX:
737 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
738 case VERR_VMX_IN_VMX_ROOT_MODE:
739 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
740 case VERR_SVM_IN_USE:
741 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
742 case VERR_SVM_NO_SVM:
743 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
744 case VERR_SVM_DISABLED:
745 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
746 default:
747 return pVM->hwaccm.s.lLastError;
748 }
749 }
750 return VINF_SUCCESS;
751 }
752
753 if (pVM->hwaccm.s.vmx.fSupported)
754 {
755 rc = SUPR3QueryVTxSupported();
756 if (RT_FAILURE(rc))
757 {
758#ifdef RT_OS_LINUX
759 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
760#else
761 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
762#endif
763 if ( pVM->cCpus > 1
764 || VMMIsHwVirtExtForced(pVM))
765 return rc;
766
767 /* silently fall back to raw mode */
768 return VINF_SUCCESS;
769 }
770 }
771
772 if (!pVM->hwaccm.s.fAllowed)
773 return VINF_SUCCESS; /* nothing to do */
774
775 /* Enable VT-x or AMD-V on all host CPUs. */
776 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
777 if (RT_FAILURE(rc))
778 {
779 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
780 return rc;
781 }
782 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
783
784 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
785 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
786 if (!pVM->hwaccm.s.fHasIoApic)
787 {
788 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
789 pVM->hwaccm.s.fTRPPatchingAllowed = false;
790 }
791
792 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
793 if (pVM->hwaccm.s.vmx.fSupported)
794 {
795 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
796
797 if ( pVM->hwaccm.s.fInitialized == false
798 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
799 {
800 uint64_t val;
801 RTGCPHYS GCPhys = 0;
802
803 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
804 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
805 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
806 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
807 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
808 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
809 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
810 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
811
812 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
813 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
814 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
816 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
818 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
820 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
822 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
823 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
825 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
827 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
831
832 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
833 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
834 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
836 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
866 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
868 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
869 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
870 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
871 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
872 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
873 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
874 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
875 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
876
877 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
878 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
879 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
880 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
892 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
894 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
896 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
898 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
904 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
905 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
907 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
909 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
910 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
911 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
912 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
913 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
914 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
915 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
916 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
917 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
918 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
919 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
920
921 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
922 {
923 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
924 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
925 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
926 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
927 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
928 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
929 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
930 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
931 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
932 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP\n"));
933 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
934 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
935 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
936 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
937 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
938 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
939 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
940 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
941 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
943
944 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
945 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
947 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
948 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
949 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
950 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP *must* be set\n"));
951 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
952 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
953 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
954 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
955 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
956 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
957 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
958 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
959 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
960 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
961 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
962 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
963 }
964
965 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
966 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
967 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
968 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
969 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
970 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
971 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
972 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
973 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
974 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
975 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
976 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
977 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
978 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
979 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
980 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
981 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
982 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
983 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
984 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
985 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
986 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
987 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
988 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
989 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
990 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
991 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
992 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
993 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
994 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
995 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
996
997 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
998 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
999 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1000 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
1001 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1002 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
1003 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1004 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
1005 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1006 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
1007 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1008 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
1009 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1010 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
1011 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1012 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
1013 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1014 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
1015 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1016 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1017 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
1018 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1019 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
1020 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1021 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
1022 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1023 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
1024 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1025 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
1026 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1027 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
1028 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1029 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
1030 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1031 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
1032
1033 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
1034 {
1035 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
1036
1037 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
1038 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
1039 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
1040 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
1041 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
1042 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
1043 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1044 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1045 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1046 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1047 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1048 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1049 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1050 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1051 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1052 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1053 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1054 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1055 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1056 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1057 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1058 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1059 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1060 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1061 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1062 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1063 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1064 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1065 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1066 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1067 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1068 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1069 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1070 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1071 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1072 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1073 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT)
1074 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT\n"));
1075 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS)
1076 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS\n"));
1077 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1078 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1079 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR)
1080 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR\n"));
1081 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT)
1082 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT\n"));
1083 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS)
1084 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS\n"));
1085 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS)
1086 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1087 }
1088
1089 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1090 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc) == pVM->hwaccm.s.vmx.cPreemptTimerShift)
1091 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1092 else
1093 {
1094 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n",
1095 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift));
1096 }
1097 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1098 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1099 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1100 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1101
1102 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1103 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1104 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1105 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1106 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1107
1108 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1109
1110 /* Paranoia */
1111 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1112
1113 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1114 {
1115 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1116 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
1117 }
1118
1119 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1120 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1121
1122 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1123 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1124
1125 /*
1126 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1127 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1128 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1129 */
1130 if (!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1131 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1132 {
1133 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1134 }
1135
1136 /* Unrestricted guest execution relies on EPT. */
1137 if ( pVM->hwaccm.s.fNestedPaging
1138 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1139 {
1140 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1141 }
1142
1143 /* Only try once. */
1144 pVM->hwaccm.s.fInitialized = true;
1145
1146 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1147 {
1148 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1149 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1150 if (RT_SUCCESS(rc))
1151 {
1152 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1153 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1154 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1155 /* Bit set to 0 means redirection enabled. */
1156 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1157 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1158 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1159 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1160
1161 /*
1162 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1163 * real and protected mode without paging with EPT.
1164 */
1165 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1166 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1167 {
1168 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1169 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1170 }
1171
1172 /* We convert it here every time as pci regions could be reconfigured. */
1173 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1174 AssertRC(rc);
1175 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1176
1177 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1178 AssertRC(rc);
1179 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1180 }
1181 else
1182 {
1183 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1184 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1185 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1186 }
1187 }
1188
1189 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1190 AssertRC(rc);
1191 if (rc == VINF_SUCCESS)
1192 {
1193 pVM->fHWACCMEnabled = true;
1194 pVM->hwaccm.s.vmx.fEnabled = true;
1195 hwaccmR3DisableRawMode(pVM);
1196
1197 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1198#ifdef VBOX_ENABLE_64_BITS_GUESTS
1199 if (pVM->hwaccm.s.fAllow64BitGuests)
1200 {
1201 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1202 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1203 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1204 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1205 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1206 }
1207 else
1208 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1209 /* Todo: this needs to be fixed properly!! */
1210 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1211 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1212 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1213
1214 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1215 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1216 : "HWACCM: 32-bit guests supported.\n"));
1217#else
1218 LogRel(("HWACCM: 32-bit guests supported.\n"));
1219#endif
1220 LogRel(("HWACCM: VMX enabled!\n"));
1221 if (pVM->hwaccm.s.fNestedPaging)
1222 {
1223 LogRel(("HWACCM: Enabled nested paging\n"));
1224 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1225 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1226 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1227
1228#if HC_ARCH_BITS == 64
1229 if (pVM->hwaccm.s.fLargePages)
1230 {
1231 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1232 PGMSetLargePageUsage(pVM, true);
1233 LogRel(("HWACCM: Large page support enabled!\n"));
1234 }
1235#endif
1236 LogRel(("HWACCM: enmFlushEPT %d\n", pVM->hwaccm.s.vmx.enmFlushEPT));
1237 }
1238 else
1239 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1240
1241 if (pVM->hwaccm.s.vmx.fVPID)
1242 {
1243 LogRel(("HWACCM: Enabled VPID\n"));
1244 LogRel(("HWACCM: enmFlushVPID %d\n", pVM->hwaccm.s.vmx.enmFlushVPID));
1245 }
1246 else if (pVM->hwaccm.s.vmx.enmFlushVPID == VMX_FLUSH_VPID_NOT_SUPPORTED)
1247 LogRel(("HWACCM: Ignoring VPID capabilities of CPU.\n"));
1248
1249 /* TPR patching status logging. */
1250 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1251 {
1252 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1253 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1254 {
1255 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1256 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1257 }
1258 else
1259 {
1260 uint32_t u32Eax, u32Dummy;
1261
1262 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1263 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1264 if ( u32Eax < 0x80000001
1265 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1266 {
1267 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1268 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1269 }
1270 }
1271 }
1272 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1273
1274 /*
1275 * Check for preemption timer config override and log the state of it.
1276 */
1277 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1278 {
1279 PCFGMNODE pCfgHwAccM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWACCM");
1280 int rc2 = CFGMR3QueryBoolDef(pCfgHwAccM, "UsePreemptTimer", &pVM->hwaccm.s.vmx.fUsePreemptTimer, true);
1281 AssertLogRelRC(rc2);
1282 }
1283 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1284 LogRel(("HWACCM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hwaccm.s.vmx.cPreemptTimerShift));
1285 }
1286 else
1287 {
1288 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1289 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1290 pVM->fHWACCMEnabled = false;
1291 }
1292 }
1293 }
1294 else
1295 if (pVM->hwaccm.s.svm.fSupported)
1296 {
1297 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1298
1299 if (pVM->hwaccm.s.fInitialized == false)
1300 {
1301 /* Erratum 170 which requires a forced TLB flush for each world switch:
1302 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1303 *
1304 * All BH-G1/2 and DH-G1/2 models include a fix:
1305 * Athlon X2: 0x6b 1/2
1306 * 0x68 1/2
1307 * Athlon 64: 0x7f 1
1308 * 0x6f 2
1309 * Sempron: 0x7f 1/2
1310 * 0x6f 2
1311 * 0x6c 2
1312 * 0x7c 2
1313 * Turion 64: 0x68 2
1314 *
1315 */
1316 uint32_t u32Dummy;
1317 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1318 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1319 u32BaseFamily= (u32Version >> 8) & 0xf;
1320 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1321 u32Model = ((u32Version >> 4) & 0xf);
1322 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1323 u32Stepping = u32Version & 0xf;
1324 if ( u32Family == 0xf
1325 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1326 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1327 {
1328 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1329 }
1330
1331 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1332 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1333 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1334 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1335 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1336 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1337 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1338 {
1339#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1340 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1341 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1342 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1343 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1344 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1345 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1346 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1347 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1348 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1349 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1350 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1351#undef FLAG_NAME
1352 };
1353 uint32_t fSvmFeatures = pVM->hwaccm.s.svm.u32Features;
1354 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1355 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1356 {
1357 LogRel(("HWACCM: %s\n", s_aSvmFeatures[i].pszName));
1358 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1359 }
1360 if (fSvmFeatures)
1361 for (unsigned iBit = 0; iBit < 32; iBit++)
1362 if (RT_BIT_32(iBit) & fSvmFeatures)
1363 LogRel(("HWACCM: Reserved bit %u\n", iBit));
1364
1365 /* Only try once. */
1366 pVM->hwaccm.s.fInitialized = true;
1367
1368 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1369 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1370
1371 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1372 AssertRC(rc);
1373 if (rc == VINF_SUCCESS)
1374 {
1375 pVM->fHWACCMEnabled = true;
1376 pVM->hwaccm.s.svm.fEnabled = true;
1377
1378 if (pVM->hwaccm.s.fNestedPaging)
1379 {
1380 LogRel(("HWACCM: Enabled nested paging\n"));
1381#if HC_ARCH_BITS == 64
1382 if (pVM->hwaccm.s.fLargePages)
1383 {
1384 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1385 PGMSetLargePageUsage(pVM, true);
1386 LogRel(("HWACCM: Large page support enabled!\n"));
1387 }
1388#endif
1389 }
1390
1391 hwaccmR3DisableRawMode(pVM);
1392 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1393 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1394#ifdef VBOX_ENABLE_64_BITS_GUESTS
1395 if (pVM->hwaccm.s.fAllow64BitGuests)
1396 {
1397 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1398 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1399 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1400 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1401 }
1402 else
1403 /* Turn on NXE if PAE has been enabled. */
1404 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1405 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1406#endif
1407
1408 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1409 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1410 : "HWACCM: 32-bit guest supported.\n"));
1411
1412 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1413 }
1414 else
1415 {
1416 pVM->fHWACCMEnabled = false;
1417 }
1418 }
1419 }
1420 if (pVM->fHWACCMEnabled)
1421 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1422 RTLogRelSetBuffering(fOldBuffered);
1423 return VINF_SUCCESS;
1424}
1425
1426
1427/**
1428 * Applies relocations to data and code managed by this
1429 * component. This function will be called at init and
1430 * whenever the VMM need to relocate it self inside the GC.
1431 *
1432 * @param pVM The VM.
1433 */
1434VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1435{
1436 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1437
1438 /* Fetch the current paging mode during the relocate callback during state loading. */
1439 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1440 {
1441 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1442 {
1443 PVMCPU pVCpu = &pVM->aCpus[i];
1444
1445 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1446 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1447 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1448 }
1449 }
1450#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1451 if (pVM->fHWACCMEnabled)
1452 {
1453 int rc;
1454 switch (PGMGetHostMode(pVM))
1455 {
1456 case PGMMODE_32_BIT:
1457 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1458 break;
1459
1460 case PGMMODE_PAE:
1461 case PGMMODE_PAE_NX:
1462 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1463 break;
1464
1465 default:
1466 AssertFailed();
1467 break;
1468 }
1469 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1470 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1471
1472 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1473 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1474
1475 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1476 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1477
1478 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1479 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1480
1481# ifdef DEBUG
1482 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1483 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1484# endif
1485 }
1486#endif
1487 return;
1488}
1489
1490
1491/**
1492 * Checks if hardware accelerated raw mode is allowed.
1493 *
1494 * @returns true if hardware acceleration is allowed, otherwise false.
1495 * @param pVM Pointer to the VM.
1496 */
1497VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1498{
1499 return pVM->hwaccm.s.fAllowed;
1500}
1501
1502
1503/**
1504 * Notification callback which is called whenever there is a chance that a CR3
1505 * value might have changed.
1506 *
1507 * This is called by PGM.
1508 *
1509 * @param pVM Pointer to the VM.
1510 * @param pVCpu Pointer to the VMCPU.
1511 * @param enmShadowMode New shadow paging mode.
1512 * @param enmGuestMode New guest paging mode.
1513 */
1514VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1515{
1516 /* Ignore page mode changes during state loading. */
1517 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1518 return;
1519
1520 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1521
1522 if ( pVM->hwaccm.s.vmx.fEnabled
1523 && pVM->fHWACCMEnabled)
1524 {
1525 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1526 && enmGuestMode >= PGMMODE_PROTECTED)
1527 {
1528 PCPUMCTX pCtx;
1529
1530 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1531
1532 /* After a real mode switch to protected mode we must force
1533 CPL to 0. Our real mode emulation had to set it to 3. */
1534 pCtx->ss.Attr.n.u2Dpl = 0;
1535 }
1536 }
1537
1538 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1539 {
1540 /* Keep track of paging mode changes. */
1541 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1542 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1543
1544 /* Did we miss a change, because all code was executed in the recompiler? */
1545 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1546 {
1547 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1548 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1549 }
1550 }
1551
1552 /* Reset the contents of the read cache. */
1553 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1554 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1555 pCache->Read.aFieldVal[j] = 0;
1556}
1557
1558
1559/**
1560 * Terminates the HWACCM.
1561 *
1562 * Termination means cleaning up and freeing all resources,
1563 * the VM itself is, at this point, powered off or suspended.
1564 *
1565 * @returns VBox status code.
1566 * @param pVM Pointer to the VM.
1567 */
1568VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1569{
1570 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1571 {
1572 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1573 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1574 }
1575 hwaccmR3TermCPU(pVM);
1576 return 0;
1577}
1578
1579
1580/**
1581 * Terminates the per-VCPU HWACCM.
1582 *
1583 * @returns VBox status code.
1584 * @param pVM Pointer to the VM.
1585 */
1586static int hwaccmR3TermCPU(PVM pVM)
1587{
1588 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1589 {
1590 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1591
1592#ifdef VBOX_WITH_STATISTICS
1593 if (pVCpu->hwaccm.s.paStatExitReason)
1594 {
1595 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1596 pVCpu->hwaccm.s.paStatExitReason = NULL;
1597 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1598 }
1599 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1600 {
1601 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1602 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1603 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1604 }
1605#endif
1606
1607#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1608 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1609 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1610 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1611#endif
1612 }
1613 return 0;
1614}
1615
1616
1617/**
1618 * Resets a virtual CPU.
1619 *
1620 * Used by HWACCMR3Reset and CPU hot plugging.
1621 *
1622 * @param pVCpu The CPU to reset.
1623 */
1624VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1625{
1626 /* On first entry we'll sync everything. */
1627 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1628
1629 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1630 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1631
1632 pVCpu->hwaccm.s.fActive = false;
1633 pVCpu->hwaccm.s.Event.fPending = false;
1634
1635 /* Reset state information for real-mode emulation in VT-x. */
1636 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1637 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1638 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1639
1640 /* Reset the contents of the read cache. */
1641 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1642 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1643 pCache->Read.aFieldVal[j] = 0;
1644
1645#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1646 /* Magic marker for searching in crash dumps. */
1647 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1648 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1649#endif
1650}
1651
1652
1653/**
1654 * The VM is being reset.
1655 *
1656 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1657 * needs to be removed.
1658 *
1659 * @param pVM Pointer to the VM.
1660 */
1661VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1662{
1663 LogFlow(("HWACCMR3Reset:\n"));
1664
1665 if (pVM->fHWACCMEnabled)
1666 hwaccmR3DisableRawMode(pVM);
1667
1668 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1669 {
1670 PVMCPU pVCpu = &pVM->aCpus[i];
1671
1672 HWACCMR3ResetCpu(pVCpu);
1673 }
1674
1675 /* Clear all patch information. */
1676 pVM->hwaccm.s.pGuestPatchMem = 0;
1677 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1678 pVM->hwaccm.s.cbGuestPatchMem = 0;
1679 pVM->hwaccm.s.cPatches = 0;
1680 pVM->hwaccm.s.PatchTree = 0;
1681 pVM->hwaccm.s.fTPRPatchingActive = false;
1682 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1683}
1684
1685
1686/**
1687 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1688 *
1689 * @returns VBox strict status code.
1690 * @param pVM Pointer to the VM.
1691 * @param pVCpu The VMCPU for the EMT we're being called on.
1692 * @param pvUser Unused.
1693 */
1694DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1695{
1696 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1697
1698 /* Only execute the handler on the VCPU the original patch request was issued. */
1699 if (pVCpu->idCpu != idCpu)
1700 return VINF_SUCCESS;
1701
1702 Log(("hwaccmR3RemovePatches\n"));
1703 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1704 {
1705 uint8_t abInstr[15];
1706 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1707 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1708 int rc;
1709
1710#ifdef LOG_ENABLED
1711 char szOutput[256];
1712
1713 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1714 szOutput, sizeof(szOutput), NULL);
1715 if (RT_SUCCESS(rc))
1716 Log(("Patched instr: %s\n", szOutput));
1717#endif
1718
1719 /* Check if the instruction is still the same. */
1720 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1721 if (rc != VINF_SUCCESS)
1722 {
1723 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1724 continue; /* swapped out or otherwise removed; skip it. */
1725 }
1726
1727 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1728 {
1729 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1730 continue; /* skip it. */
1731 }
1732
1733 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1734 AssertRC(rc);
1735
1736#ifdef LOG_ENABLED
1737 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1738 szOutput, sizeof(szOutput), NULL);
1739 if (RT_SUCCESS(rc))
1740 Log(("Original instr: %s\n", szOutput));
1741#endif
1742 }
1743 pVM->hwaccm.s.cPatches = 0;
1744 pVM->hwaccm.s.PatchTree = 0;
1745 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1746 pVM->hwaccm.s.fTPRPatchingActive = false;
1747 return VINF_SUCCESS;
1748}
1749
1750
1751/**
1752 * Worker for enabling patching in a VT-x/AMD-V guest.
1753 *
1754 * @returns VBox status code.
1755 * @param pVM Pointer to the VM.
1756 * @param idCpu VCPU to execute hwaccmR3RemovePatches on.
1757 * @param pPatchMem Patch memory range.
1758 * @param cbPatchMem Size of the memory range.
1759 */
1760static int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1761{
1762 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)idCpu);
1763 AssertRC(rc);
1764
1765 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1766 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1767 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1768 return VINF_SUCCESS;
1769}
1770
1771
1772/**
1773 * Enable patching in a VT-x/AMD-V guest
1774 *
1775 * @returns VBox status code.
1776 * @param pVM Pointer to the VM.
1777 * @param pPatchMem Patch memory range.
1778 * @param cbPatchMem Size of the memory range.
1779 */
1780VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1781{
1782 VM_ASSERT_EMT(pVM);
1783 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1784 if (pVM->cCpus > 1)
1785 {
1786 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1787 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1788 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1789 AssertRC(rc);
1790 return rc;
1791 }
1792 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1793}
1794
1795
1796/**
1797 * Disable patching in a VT-x/AMD-V guest.
1798 *
1799 * @returns VBox status code.
1800 * @param pVM Pointer to the VM.
1801 * @param pPatchMem Patch memory range.
1802 * @param cbPatchMem Size of the memory range.
1803 */
1804VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1805{
1806 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1807
1808 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1809 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1810
1811 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1812 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)VMMGetCpuId(pVM));
1813 AssertRC(rc);
1814
1815 pVM->hwaccm.s.pGuestPatchMem = 0;
1816 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1817 pVM->hwaccm.s.cbGuestPatchMem = 0;
1818 pVM->hwaccm.s.fTPRPatchingActive = false;
1819 return VINF_SUCCESS;
1820}
1821
1822
1823/**
1824 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1825 *
1826 * @returns VBox strict status code.
1827 * @param pVM Pointer to the VM.
1828 * @param pVCpu The VMCPU for the EMT we're being called on.
1829 * @param pvUser User specified CPU context.
1830 *
1831 */
1832DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1833{
1834 /*
1835 * Only execute the handler on the VCPU the original patch request was
1836 * issued. (The other CPU(s) might not yet have switched to protected
1837 * mode, nor have the correct memory context.)
1838 */
1839 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1840 if (pVCpu->idCpu != idCpu)
1841 return VINF_SUCCESS;
1842
1843 /*
1844 * We're racing other VCPUs here, so don't try patch the instruction twice
1845 * and make sure there is still room for our patch record.
1846 */
1847 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1848 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1849 if (pPatch)
1850 {
1851 Log(("hwaccmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1852 return VINF_SUCCESS;
1853 }
1854 uint32_t const idx = pVM->hwaccm.s.cPatches;
1855 if (idx >= RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1856 {
1857 Log(("hwaccmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1858 return VINF_SUCCESS;
1859 }
1860 pPatch = &pVM->hwaccm.s.aPatches[idx];
1861
1862 Log(("hwaccmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1863
1864 /*
1865 * Disassembler the instruction and get cracking.
1866 */
1867 DBGFR3DisasInstrCurrentLog(pVCpu, "hwaccmR3ReplaceTprInstr");
1868 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1869 uint32_t cbOp;
1870 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1871 AssertRC(rc);
1872 if ( rc == VINF_SUCCESS
1873 && pDis->pCurInstr->uOpcode == OP_MOV
1874 && cbOp >= 3)
1875 {
1876 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1877
1878 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1879 AssertRC(rc);
1880
1881 pPatch->cbOp = cbOp;
1882
1883 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1884 {
1885 /* write. */
1886 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1887 {
1888 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1889 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1890 Log(("hwaccmR3ReplaceTprInstr: HWACCMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1891 }
1892 else
1893 {
1894 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1895 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1896 pPatch->uSrcOperand = pDis->Param2.uValue;
1897 Log(("hwaccmR3ReplaceTprInstr: HWACCMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1898 }
1899 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1900 AssertRC(rc);
1901
1902 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1903 pPatch->cbNewOp = sizeof(s_abVMMCall);
1904 }
1905 else
1906 {
1907 /*
1908 * TPR Read.
1909 *
1910 * Found:
1911 * mov eax, dword [fffe0080] (5 bytes)
1912 * Check if next instruction is:
1913 * shr eax, 4
1914 */
1915 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1916
1917 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1918 uint8_t const cbOpMmio = cbOp;
1919 uint64_t const uSavedRip = pCtx->rip;
1920
1921 pCtx->rip += cbOp;
1922 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1923 DBGFR3DisasInstrCurrentLog(pVCpu, "Following read");
1924 pCtx->rip = uSavedRip;
1925
1926 if ( rc == VINF_SUCCESS
1927 && pDis->pCurInstr->uOpcode == OP_SHR
1928 && pDis->Param1.fUse == DISUSE_REG_GEN32
1929 && pDis->Param1.Base.idxGenReg == idxMmioReg
1930 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1931 && pDis->Param2.uValue == 4
1932 && cbOpMmio + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1933 {
1934 uint8_t abInstr[15];
1935
1936 /* Replacing two instructions now. */
1937 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1938 AssertRC(rc);
1939
1940 pPatch->cbOp = cbOpMmio + cbOp;
1941
1942 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1943 abInstr[0] = 0xF0;
1944 abInstr[1] = 0x0F;
1945 abInstr[2] = 0x20;
1946 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1947 for (unsigned i = 4; i < pPatch->cbOp; i++)
1948 abInstr[i] = 0x90; /* nop */
1949
1950 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1951 AssertRC(rc);
1952
1953 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1954 pPatch->cbNewOp = pPatch->cbOp;
1955
1956 Log(("Acceptable read/shr candidate!\n"));
1957 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1958 }
1959 else
1960 {
1961 pPatch->enmType = HWACCMTPRINSTR_READ;
1962 pPatch->uDstOperand = idxMmioReg;
1963
1964 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1965 AssertRC(rc);
1966
1967 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1968 pPatch->cbNewOp = sizeof(s_abVMMCall);
1969 Log(("hwaccmR3ReplaceTprInstr: HWACCMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1970 }
1971 }
1972
1973 pPatch->Core.Key = pCtx->eip;
1974 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1975 AssertRC(rc);
1976
1977 pVM->hwaccm.s.cPatches++;
1978 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1979 return VINF_SUCCESS;
1980 }
1981
1982 /*
1983 * Save invalid patch, so we will not try again.
1984 */
1985 Log(("hwaccmR3ReplaceTprInstr: Failed to patch instr!\n"));
1986 pPatch->Core.Key = pCtx->eip;
1987 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1988 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1989 AssertRC(rc);
1990 pVM->hwaccm.s.cPatches++;
1991 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1992 return VINF_SUCCESS;
1993}
1994
1995
1996/**
1997 * Callback to patch a TPR instruction (jump to generated code).
1998 *
1999 * @returns VBox strict status code.
2000 * @param pVM Pointer to the VM.
2001 * @param pVCpu The VMCPU for the EMT we're being called on.
2002 * @param pvUser User specified CPU context.
2003 *
2004 */
2005DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2006{
2007 /*
2008 * Only execute the handler on the VCPU the original patch request was
2009 * issued. (The other CPU(s) might not yet have switched to protected
2010 * mode, nor have the correct memory context.)
2011 */
2012 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2013 if (pVCpu->idCpu != idCpu)
2014 return VINF_SUCCESS;
2015
2016 /*
2017 * We're racing other VCPUs here, so don't try patch the instruction twice
2018 * and make sure there is still room for our patch record.
2019 */
2020 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2021 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2022 if (pPatch)
2023 {
2024 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2025 return VINF_SUCCESS;
2026 }
2027 uint32_t const idx = pVM->hwaccm.s.cPatches;
2028 if (idx >= RT_ELEMENTS(pVM->hwaccm.s.aPatches))
2029 {
2030 Log(("hwaccmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2031 return VINF_SUCCESS;
2032 }
2033 pPatch = &pVM->hwaccm.s.aPatches[idx];
2034
2035 Log(("hwaccmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2036 DBGFR3DisasInstrCurrentLog(pVCpu, "hwaccmR3PatchTprInstr");
2037
2038 /*
2039 * Disassemble the instruction and get cracking.
2040 */
2041 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2042 uint32_t cbOp;
2043 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2044 AssertRC(rc);
2045 if ( rc == VINF_SUCCESS
2046 && pDis->pCurInstr->uOpcode == OP_MOV
2047 && cbOp >= 5)
2048 {
2049 uint8_t aPatch[64];
2050 uint32_t off = 0;
2051
2052 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2053 AssertRC(rc);
2054
2055 pPatch->cbOp = cbOp;
2056 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
2057
2058 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2059 {
2060 /*
2061 * TPR write:
2062 *
2063 * push ECX [51]
2064 * push EDX [52]
2065 * push EAX [50]
2066 * xor EDX,EDX [31 D2]
2067 * mov EAX,EAX [89 C0]
2068 * or
2069 * mov EAX,0000000CCh [B8 CC 00 00 00]
2070 * mov ECX,0C0000082h [B9 82 00 00 C0]
2071 * wrmsr [0F 30]
2072 * pop EAX [58]
2073 * pop EDX [5A]
2074 * pop ECX [59]
2075 * jmp return_address [E9 return_address]
2076 *
2077 */
2078 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2079
2080 aPatch[off++] = 0x51; /* push ecx */
2081 aPatch[off++] = 0x52; /* push edx */
2082 if (!fUsesEax)
2083 aPatch[off++] = 0x50; /* push eax */
2084 aPatch[off++] = 0x31; /* xor edx, edx */
2085 aPatch[off++] = 0xD2;
2086 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2087 {
2088 if (!fUsesEax)
2089 {
2090 aPatch[off++] = 0x89; /* mov eax, src_reg */
2091 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2092 }
2093 }
2094 else
2095 {
2096 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2097 aPatch[off++] = 0xB8; /* mov eax, immediate */
2098 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2099 off += sizeof(uint32_t);
2100 }
2101 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2102 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2103 off += sizeof(uint32_t);
2104
2105 aPatch[off++] = 0x0F; /* wrmsr */
2106 aPatch[off++] = 0x30;
2107 if (!fUsesEax)
2108 aPatch[off++] = 0x58; /* pop eax */
2109 aPatch[off++] = 0x5A; /* pop edx */
2110 aPatch[off++] = 0x59; /* pop ecx */
2111 }
2112 else
2113 {
2114 /*
2115 * TPR read:
2116 *
2117 * push ECX [51]
2118 * push EDX [52]
2119 * push EAX [50]
2120 * mov ECX,0C0000082h [B9 82 00 00 C0]
2121 * rdmsr [0F 32]
2122 * mov EAX,EAX [89 C0]
2123 * pop EAX [58]
2124 * pop EDX [5A]
2125 * pop ECX [59]
2126 * jmp return_address [E9 return_address]
2127 *
2128 */
2129 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2130
2131 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2132 aPatch[off++] = 0x51; /* push ecx */
2133 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2134 aPatch[off++] = 0x52; /* push edx */
2135 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2136 aPatch[off++] = 0x50; /* push eax */
2137
2138 aPatch[off++] = 0x31; /* xor edx, edx */
2139 aPatch[off++] = 0xD2;
2140
2141 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2142 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2143 off += sizeof(uint32_t);
2144
2145 aPatch[off++] = 0x0F; /* rdmsr */
2146 aPatch[off++] = 0x32;
2147
2148 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2149 {
2150 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2151 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2152 }
2153
2154 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2155 aPatch[off++] = 0x58; /* pop eax */
2156 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2157 aPatch[off++] = 0x5A; /* pop edx */
2158 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2159 aPatch[off++] = 0x59; /* pop ecx */
2160 }
2161 aPatch[off++] = 0xE9; /* jmp return_address */
2162 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2163 off += sizeof(RTRCUINTPTR);
2164
2165 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2166 {
2167 /* Write new code to the patch buffer. */
2168 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2169 AssertRC(rc);
2170
2171#ifdef LOG_ENABLED
2172 uint32_t cbCurInstr;
2173 for (RTGCPTR GCPtrInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2174 GCPtrInstr < pVM->hwaccm.s.pFreeGuestPatchMem + off;
2175 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2176 {
2177 char szOutput[256];
2178 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2179 szOutput, sizeof(szOutput), &cbCurInstr);
2180 if (RT_SUCCESS(rc))
2181 Log(("Patch instr %s\n", szOutput));
2182 else
2183 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2184 }
2185#endif
2186
2187 pPatch->aNewOpcode[0] = 0xE9;
2188 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2189
2190 /* Overwrite the TPR instruction with a jump. */
2191 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2192 AssertRC(rc);
2193
2194 DBGFR3DisasInstrCurrentLog(pVCpu, "Jump");
2195
2196 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2197 pPatch->cbNewOp = 5;
2198
2199 pPatch->Core.Key = pCtx->eip;
2200 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2201 AssertRC(rc);
2202
2203 pVM->hwaccm.s.cPatches++;
2204 pVM->hwaccm.s.fTPRPatchingActive = true;
2205 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2206 return VINF_SUCCESS;
2207 }
2208
2209 Log(("Ran out of space in our patch buffer!\n"));
2210 }
2211 else
2212 Log(("hwaccmR3PatchTprInstr: Failed to patch instr!\n"));
2213
2214
2215 /*
2216 * Save invalid patch, so we will not try again.
2217 */
2218 pPatch = &pVM->hwaccm.s.aPatches[idx];
2219 pPatch->Core.Key = pCtx->eip;
2220 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2221 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2222 AssertRC(rc);
2223 pVM->hwaccm.s.cPatches++;
2224 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2225 return VINF_SUCCESS;
2226}
2227
2228
2229/**
2230 * Attempt to patch TPR mmio instructions.
2231 *
2232 * @returns VBox status code.
2233 * @param pVM Pointer to the VM.
2234 * @param pVCpu Pointer to the VMCPU.
2235 * @param pCtx Pointer to the guest CPU context.
2236 */
2237VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2238{
2239 NOREF(pCtx);
2240 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2241 pVM->hwaccm.s.pGuestPatchMem ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr,
2242 (void *)(uintptr_t)pVCpu->idCpu);
2243 AssertRC(rc);
2244 return rc;
2245}
2246
2247
2248/**
2249 * Force execution of the current IO code in the recompiler.
2250 *
2251 * @returns VBox status code.
2252 * @param pVM Pointer to the VM.
2253 * @param pCtx Partial VM execution context.
2254 */
2255VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2256{
2257 PVMCPU pVCpu = VMMGetCpu(pVM);
2258
2259 Assert(pVM->fHWACCMEnabled);
2260 Log(("HWACCMR3EmulateIoBlock\n"));
2261
2262 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2263 if (HWACCMCanEmulateIoBlockEx(pCtx))
2264 {
2265 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2266 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2267 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2268 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2269 return VINF_EM_RESCHEDULE_REM;
2270 }
2271 return VINF_SUCCESS;
2272}
2273
2274
2275/**
2276 * Checks if we can currently use hardware accelerated raw mode.
2277 *
2278 * @returns true if we can currently use hardware acceleration, otherwise false.
2279 * @param pVM Pointer to the VM.
2280 * @param pCtx Partial VM execution context.
2281 */
2282VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2283{
2284 PVMCPU pVCpu = VMMGetCpu(pVM);
2285
2286 Assert(pVM->fHWACCMEnabled);
2287
2288 /* If we're still executing the IO code, then return false. */
2289 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2290 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2291 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2292 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2293 return false;
2294
2295 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2296
2297 /* AMD-V supports real & protected mode with or without paging. */
2298 if (pVM->hwaccm.s.svm.fEnabled)
2299 {
2300 pVCpu->hwaccm.s.fActive = true;
2301 return true;
2302 }
2303
2304 pVCpu->hwaccm.s.fActive = false;
2305
2306 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2307 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2308
2309 bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2310 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2311 {
2312 /*
2313 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2314 * guest execution feature i missing (VT-x only).
2315 */
2316 if (fSupportsRealMode)
2317 {
2318 if (CPUMIsGuestInRealModeEx(pCtx))
2319 {
2320 /* VT-x will not allow high selector bases in v86 mode; fall
2321 back to the recompiler in that case.
2322 The base must also be equal to (sel << 4). */
2323 if ( ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2324 && pCtx->cs.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2325 || (pCtx->cs.u32Limit != 0xffff)
2326 || (pCtx->ds.u32Limit != 0xffff)
2327 || (pCtx->es.u32Limit != 0xffff)
2328 || (pCtx->ss.u32Limit != 0xffff)
2329 || (pCtx->fs.u32Limit != 0xffff)
2330 || (pCtx->gs.u32Limit != 0xffff)
2331 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2332 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2333 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2334 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2335 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4))
2336 {
2337 return false;
2338 }
2339 }
2340 else
2341 {
2342 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2343 /* Verify the requirements for executing code in protected
2344 mode. VT-x can't handle the CPU state right after a switch
2345 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2346 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2347 && enmGuestMode >= PGMMODE_PROTECTED)
2348 {
2349 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2350 || (pCtx->ds.Sel & X86_SEL_RPL)
2351 || (pCtx->es.Sel & X86_SEL_RPL)
2352 || (pCtx->fs.Sel & X86_SEL_RPL)
2353 || (pCtx->gs.Sel & X86_SEL_RPL)
2354 || (pCtx->ss.Sel & X86_SEL_RPL))
2355 {
2356 return false;
2357 }
2358 }
2359 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2360 if ( pCtx->gdtr.cbGdt
2361 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2362 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2363 {
2364 return false;
2365 }
2366 }
2367 }
2368 else
2369 {
2370 if ( !CPUMIsGuestInLongModeEx(pCtx)
2371 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2372 {
2373 /** @todo This should (probably) be set on every excursion to the REM,
2374 * however it's too risky right now. So, only apply it when we go
2375 * back to REM for real mode execution. (The XP hack below doesn't
2376 * work reliably without this.)
2377 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2378 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2379
2380 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2381 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2382 return false;
2383
2384 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2385 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2386 return false;
2387
2388 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2389 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2390 * hidden registers (possible recompiler bug; see load_seg_vm) */
2391 if (pCtx->cs.Attr.n.u1Present == 0)
2392 return false;
2393 if (pCtx->ss.Attr.n.u1Present == 0)
2394 return false;
2395
2396 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2397 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2398 /** @todo This check is actually wrong, it doesn't take the direction of the
2399 * stack segment into account. But, it does the job for now. */
2400 if (pCtx->rsp >= pCtx->ss.u32Limit)
2401 return false;
2402#if 0
2403 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2404 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2405 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2406 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2407 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2408 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2409 return false;
2410#endif
2411 }
2412 }
2413 }
2414
2415 if (pVM->hwaccm.s.vmx.fEnabled)
2416 {
2417 uint32_t mask;
2418
2419 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2420 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2421 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2422 mask &= ~X86_CR0_NE;
2423
2424 if (fSupportsRealMode)
2425 {
2426 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2427 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2428 }
2429 else
2430 {
2431 /* We support protected mode without paging using identity mapping. */
2432 mask &= ~X86_CR0_PG;
2433 }
2434 if ((pCtx->cr0 & mask) != mask)
2435 return false;
2436
2437 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2438 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2439 if ((pCtx->cr0 & mask) != 0)
2440 return false;
2441
2442 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2443 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2444 mask &= ~X86_CR4_VMXE;
2445 if ((pCtx->cr4 & mask) != mask)
2446 return false;
2447
2448 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2449 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2450 if ((pCtx->cr4 & mask) != 0)
2451 return false;
2452
2453 pVCpu->hwaccm.s.fActive = true;
2454 return true;
2455 }
2456
2457 return false;
2458}
2459
2460
2461/**
2462 * Checks if we need to reschedule due to VMM device heap changes.
2463 *
2464 * @returns true if a reschedule is required, otherwise false.
2465 * @param pVM Pointer to the VM.
2466 * @param pCtx VM execution context.
2467 */
2468VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2469{
2470 /*
2471 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2472 * when the unrestricted guest execution feature is missing (VT-x only).
2473 */
2474 if ( pVM->hwaccm.s.vmx.fEnabled
2475 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest
2476 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2477 && !PDMVMMDevHeapIsEnabled(pVM)
2478 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2479 return true;
2480
2481 return false;
2482}
2483
2484
2485/**
2486 * Notification from EM about a rescheduling into hardware assisted execution
2487 * mode.
2488 *
2489 * @param pVCpu Pointer to the current VMCPU.
2490 */
2491VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2492{
2493 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2494}
2495
2496
2497/**
2498 * Notification from EM about returning from instruction emulation (REM / EM).
2499 *
2500 * @param pVCpu Pointer to the VMCPU.
2501 */
2502VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2503{
2504 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2505}
2506
2507
2508/**
2509 * Checks if we are currently using hardware accelerated raw mode.
2510 *
2511 * @returns true if hardware acceleration is being used, otherwise false.
2512 * @param pVCpu Pointer to the VMCPU.
2513 */
2514VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2515{
2516 return pVCpu->hwaccm.s.fActive;
2517}
2518
2519
2520/**
2521 * Checks if we are currently using nested paging.
2522 *
2523 * @returns true if nested paging is being used, otherwise false.
2524 * @param pVM Pointer to the VM.
2525 */
2526VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2527{
2528 return pVM->hwaccm.s.fNestedPaging;
2529}
2530
2531
2532/**
2533 * Checks if we are currently using VPID in VT-x mode.
2534 *
2535 * @returns true if VPID is being used, otherwise false.
2536 * @param pVM Pointer to the VM.
2537 */
2538VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2539{
2540 return pVM->hwaccm.s.vmx.fVPID;
2541}
2542
2543
2544/**
2545 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2546 *
2547 * @returns true if an internal event is pending, otherwise false.
2548 * @param pVM Pointer to the VM.
2549 */
2550VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2551{
2552 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2553}
2554
2555
2556/**
2557 * Checks if the VMX-preemption timer is being used.
2558 *
2559 * @returns true if the VMX-preemption timer is being used, otherwise false.
2560 * @param pVM Pointer to the VM.
2561 */
2562VMMR3DECL(bool) HWACCMR3IsVmxPreemptionTimerUsed(PVM pVM)
2563{
2564 return HWACCMIsEnabled(pVM)
2565 && pVM->hwaccm.s.vmx.fEnabled
2566 && pVM->hwaccm.s.vmx.fUsePreemptTimer;
2567}
2568
2569
2570/**
2571 * Restart an I/O instruction that was refused in ring-0
2572 *
2573 * @returns Strict VBox status code. Informational status codes other than the one documented
2574 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2575 * @retval VINF_SUCCESS Success.
2576 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2577 * status code must be passed on to EM.
2578 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2579 *
2580 * @param pVM Pointer to the VM.
2581 * @param pVCpu Pointer to the VMCPU.
2582 * @param pCtx Pointer to the guest CPU context.
2583 */
2584VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2585{
2586 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2587
2588 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2589
2590 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2591 || enmType == HWACCMPENDINGIO_INVALID)
2592 return VERR_NOT_FOUND;
2593
2594 VBOXSTRICTRC rcStrict;
2595 switch (enmType)
2596 {
2597 case HWACCMPENDINGIO_PORT_READ:
2598 {
2599 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2600 uint32_t u32Val = 0;
2601
2602 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2603 &u32Val,
2604 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2605 if (IOM_SUCCESS(rcStrict))
2606 {
2607 /* Write back to the EAX register. */
2608 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2609 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2610 }
2611 break;
2612 }
2613
2614 case HWACCMPENDINGIO_PORT_WRITE:
2615 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2616 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2617 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2618 if (IOM_SUCCESS(rcStrict))
2619 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2620 break;
2621
2622 default:
2623 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2624 }
2625
2626 return rcStrict;
2627}
2628
2629
2630/**
2631 * Inject an NMI into a running VM (only VCPU 0!)
2632 *
2633 * @returns boolean
2634 * @param pVM Pointer to the VM.
2635 */
2636VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2637{
2638 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2639 return VINF_SUCCESS;
2640}
2641
2642
2643/**
2644 * Check fatal VT-x/AMD-V error and produce some meaningful
2645 * log release message.
2646 *
2647 * @param pVM Pointer to the VM.
2648 * @param iStatusCode VBox status code.
2649 */
2650VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2651{
2652 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2653 {
2654 switch(iStatusCode)
2655 {
2656 case VERR_VMX_INVALID_VMCS_FIELD:
2657 break;
2658
2659 case VERR_VMX_INVALID_VMCS_PTR:
2660 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
2661 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2662 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2663 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2664 break;
2665
2666 case VERR_VMX_UNABLE_TO_START_VM:
2667 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2668 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2669#if 0 /* @todo dump the current control fields to the release log */
2670 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2671 {
2672
2673 }
2674#endif
2675 break;
2676
2677 case VERR_VMX_UNABLE_TO_RESUME_VM:
2678 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2679 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2680 break;
2681
2682 case VERR_VMX_INVALID_VMXON_PTR:
2683 break;
2684 }
2685 }
2686}
2687
2688
2689/**
2690 * Execute state save operation.
2691 *
2692 * @returns VBox status code.
2693 * @param pVM Pointer to the VM.
2694 * @param pSSM SSM operation handle.
2695 */
2696static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2697{
2698 int rc;
2699
2700 Log(("hwaccmR3Save:\n"));
2701
2702 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2703 {
2704 /*
2705 * Save the basic bits - fortunately all the other things can be resynced on load.
2706 */
2707 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2708 AssertRCReturn(rc, rc);
2709 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2710 AssertRCReturn(rc, rc);
2711 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2712 AssertRCReturn(rc, rc);
2713
2714 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2715 AssertRCReturn(rc, rc);
2716 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2717 AssertRCReturn(rc, rc);
2718 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2719 AssertRCReturn(rc, rc);
2720 }
2721#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2722 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2723 AssertRCReturn(rc, rc);
2724 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2725 AssertRCReturn(rc, rc);
2726 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2727 AssertRCReturn(rc, rc);
2728
2729 /* Store all the guest patch records too. */
2730 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2731 AssertRCReturn(rc, rc);
2732
2733 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2734 {
2735 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2736
2737 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2738 AssertRCReturn(rc, rc);
2739
2740 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2741 AssertRCReturn(rc, rc);
2742
2743 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2744 AssertRCReturn(rc, rc);
2745
2746 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2747 AssertRCReturn(rc, rc);
2748
2749 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2750 AssertRCReturn(rc, rc);
2751
2752 AssertCompileSize(HWACCMTPRINSTR, 4);
2753 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2754 AssertRCReturn(rc, rc);
2755
2756 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2757 AssertRCReturn(rc, rc);
2758
2759 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2760 AssertRCReturn(rc, rc);
2761
2762 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2763 AssertRCReturn(rc, rc);
2764
2765 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2766 AssertRCReturn(rc, rc);
2767 }
2768#endif
2769 return VINF_SUCCESS;
2770}
2771
2772
2773/**
2774 * Execute state load operation.
2775 *
2776 * @returns VBox status code.
2777 * @param pVM Pointer to the VM.
2778 * @param pSSM SSM operation handle.
2779 * @param uVersion Data layout version.
2780 * @param uPass The data pass.
2781 */
2782static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2783{
2784 int rc;
2785
2786 Log(("hwaccmR3Load:\n"));
2787 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2788
2789 /*
2790 * Validate version.
2791 */
2792 if ( uVersion != HWACCM_SSM_VERSION
2793 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2794 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2795 {
2796 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2797 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2798 }
2799 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2800 {
2801 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2802 AssertRCReturn(rc, rc);
2803 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2804 AssertRCReturn(rc, rc);
2805 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2806 AssertRCReturn(rc, rc);
2807
2808 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2809 {
2810 uint32_t val;
2811
2812 rc = SSMR3GetU32(pSSM, &val);
2813 AssertRCReturn(rc, rc);
2814 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2815
2816 rc = SSMR3GetU32(pSSM, &val);
2817 AssertRCReturn(rc, rc);
2818 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2819
2820 rc = SSMR3GetU32(pSSM, &val);
2821 AssertRCReturn(rc, rc);
2822 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2823 }
2824 }
2825#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2826 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2827 {
2828 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2829 AssertRCReturn(rc, rc);
2830 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2831 AssertRCReturn(rc, rc);
2832 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2833 AssertRCReturn(rc, rc);
2834
2835 /* Fetch all TPR patch records. */
2836 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2837 AssertRCReturn(rc, rc);
2838
2839 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2840 {
2841 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2842
2843 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2844 AssertRCReturn(rc, rc);
2845
2846 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2847 AssertRCReturn(rc, rc);
2848
2849 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2850 AssertRCReturn(rc, rc);
2851
2852 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2853 AssertRCReturn(rc, rc);
2854
2855 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2856 AssertRCReturn(rc, rc);
2857
2858 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2859 AssertRCReturn(rc, rc);
2860
2861 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2862 pVM->hwaccm.s.fTPRPatchingActive = true;
2863
2864 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2865
2866 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2867 AssertRCReturn(rc, rc);
2868
2869 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2870 AssertRCReturn(rc, rc);
2871
2872 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2873 AssertRCReturn(rc, rc);
2874
2875 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2876 AssertRCReturn(rc, rc);
2877
2878 Log(("hwaccmR3Load: patch %d\n", i));
2879 Log(("Key = %x\n", pPatch->Core.Key));
2880 Log(("cbOp = %d\n", pPatch->cbOp));
2881 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2882 Log(("type = %d\n", pPatch->enmType));
2883 Log(("srcop = %d\n", pPatch->uSrcOperand));
2884 Log(("dstop = %d\n", pPatch->uDstOperand));
2885 Log(("cFaults = %d\n", pPatch->cFaults));
2886 Log(("target = %x\n", pPatch->pJumpTarget));
2887 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2888 AssertRC(rc);
2889 }
2890 }
2891#endif
2892
2893 /* Recheck all VCPUs if we can go straight into hwaccm execution mode. */
2894 if (HWACCMIsEnabled(pVM))
2895 {
2896 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2897 {
2898 PVMCPU pVCpu = &pVM->aCpus[i];
2899
2900 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2901 }
2902 }
2903 return VINF_SUCCESS;
2904}
2905
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