HM.cpp@ 94961

Last change on this file since 94961 was 94946, checked in by vboxsync, 3 years ago
VMM/HM: Use g_CpumHostFeatures instead of the copy in the VM structure. [arm build fix] bugref:10093
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1	/* $Id: HM.cpp 94946 2022-05-09 10:38:40Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/pdmapi.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/gim.h>
48	#include <VBox/vmm/gcm.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/selm.h>
54	#include <VBox/vmm/nem.h>
55	#include <VBox/vmm/hm_vmx.h>
56	#include <VBox/vmm/hm_svm.h>
57	#include "HMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/err.h>
60	#include <VBox/param.h>
61
62	#include <iprt/assert.h>
63	#include <VBox/log.h>
64	#include <iprt/asm.h>
65	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
66	# include <iprt/asm-amd64-x86.h>
67	#endif
68	#include <iprt/env.h>
69	#include <iprt/thread.h>
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75	/** @def HMVMX_REPORT_FEAT
76	* Reports VT-x feature to the release log.
77	*
78	* @param a_uAllowed1 Mask of allowed-1 feature bits.
79	* @param a_uAllowed0 Mask of allowed-0 feature bits.
80	* @param a_StrDesc The description string to report.
81	* @param a_Featflag Mask of the feature to report.
82	*/
83	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
84	do { \
85	if ((a_uAllowed1) & (a_Featflag)) \
86	{ \
87	if ((a_uAllowed0) & (a_Featflag)) \
88	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
89	else \
90	LogRel(("HM: " a_StrDesc "\n")); \
91	} \
92	else \
93	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
94	} while (0)
95
96	/** @def HMVMX_REPORT_ALLOWED_FEAT
97	* Reports an allowed VT-x feature to the release log.
98	*
99	* @param a_uAllowed1 Mask of allowed-1 feature bits.
100	* @param a_StrDesc The description string to report.
101	* @param a_FeatFlag Mask of the feature to report.
102	*/
103	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
104	do { \
105	if ((a_uAllowed1) & (a_FeatFlag)) \
106	LogRel(("HM: " a_StrDesc "\n")); \
107	else \
108	LogRel(("HM: " a_StrDesc " not supported\n")); \
109	} while (0)
110
111	/** @def HMVMX_REPORT_MSR_CAP
112	* Reports MSR feature capability.
113	*
114	* @param a_MsrCaps Mask of MSR feature bits.
115	* @param a_StrDesc The description string to report.
116	* @param a_fCap Mask of the feature to report.
117	*/
118	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
119	do { \
120	if ((a_MsrCaps) & (a_fCap)) \
121	LogRel(("HM: " a_StrDesc "\n")); \
122	} while (0)
123
124	/** @def HMVMX_LOGREL_FEAT
125	* Dumps a feature flag from a bitmap of features to the release log.
126	*
127	* @param a_fVal The value of all the features.
128	* @param a_fMask The specific bitmask of the feature.
129	*/
130	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
131	do { \
132	if ((a_fVal) & (a_fMask)) \
133	LogRel(("HM: %s\n", #a_fMask)); \
134	} while (0)
135
136
137	/*********************************************************************************************************************************
138	* Internal Functions *
139	*********************************************************************************************************************************/
140	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
141	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
142	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
145	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
146	static int hmR3InitFinalizeR3(PVM pVM);
147	static int hmR3InitFinalizeR0(PVM pVM);
148	static int hmR3InitFinalizeR0Intel(PVM pVM);
149	static int hmR3InitFinalizeR0Amd(PVM pVM);
150	static int hmR3TermCPU(PVM pVM);
151
152
153	#ifdef VBOX_WITH_STATISTICS
154	/**
155	* Returns the name of the hardware exception.
156	*
157	* @returns The name of the hardware exception.
158	* @param uVector The exception vector.
159	*/
160	static const char *hmR3GetXcptName(uint8_t uVector)
161	{
162	switch (uVector)
163	{
164	case X86_XCPT_DE: return "#DE";
165	case X86_XCPT_DB: return "#DB";
166	case X86_XCPT_NMI: return "#NMI";
167	case X86_XCPT_BP: return "#BP";
168	case X86_XCPT_OF: return "#OF";
169	case X86_XCPT_BR: return "#BR";
170	case X86_XCPT_UD: return "#UD";
171	case X86_XCPT_NM: return "#NM";
172	case X86_XCPT_DF: return "#DF";
173	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
174	case X86_XCPT_TS: return "#TS";
175	case X86_XCPT_NP: return "#NP";
176	case X86_XCPT_SS: return "#SS";
177	case X86_XCPT_GP: return "#GP";
178	case X86_XCPT_PF: return "#PF";
179	case X86_XCPT_MF: return "#MF";
180	case X86_XCPT_AC: return "#AC";
181	case X86_XCPT_MC: return "#MC";
182	case X86_XCPT_XF: return "#XF";
183	case X86_XCPT_VE: return "#VE";
184	case X86_XCPT_CP: return "#CP";
185	case X86_XCPT_VC: return "#VC";
186	case X86_XCPT_SX: return "#SX";
187	}
188	return "Reserved";
189	}
190	#endif /* VBOX_WITH_STATISTICS */
191
192
193	/**
194	* Initializes the HM.
195	*
196	* This is the very first component to really do init after CFGM so that we can
197	* establish the predominant execution engine for the VM prior to initializing
198	* other modules. It takes care of NEM initialization if needed (HM disabled or
199	* not available in HW).
200	*
201	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
202	* hypervisor API via NEM, and then back on raw-mode if that isn't available
203	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
204	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
205	* X, OS/2 and others).
206	*
207	* Note that a lot of the set up work is done in ring-0 and thus postponed till
208	* the ring-3 and ring-0 callback to HMR3InitCompleted.
209	*
210	* @returns VBox status code.
211	* @param pVM The cross context VM structure.
212	*
213	* @remarks Be careful with what we call here, since most of the VMM components
214	* are uninitialized.
215	*/
216	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
217	{
218	LogFlowFunc(("\n"));
219
220	/*
221	* Assert alignment and sizes.
222	*/
223	AssertCompileMemberAlignment(VM, hm.s, 32);
224	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
225
226	/*
227	* Register the saved state data unit.
228	*/
229	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
230	NULL, NULL, NULL,
231	NULL, hmR3Save, NULL,
232	NULL, hmR3Load, NULL);
233	if (RT_FAILURE(rc))
234	return rc;
235
236	/*
237	* Read configuration.
238	*/
239	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
240
241	/*
242	* Validate the HM settings.
243	*/
244	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
245	"HMForced" /* implied 'true' these days */
246	"\|UseNEMInstead"
247	"\|FallbackToNEM"
248	"\|FallbackToIEM"
249	"\|EnableNestedPaging"
250	"\|EnableUX"
251	"\|EnableLargePages"
252	"\|EnableVPID"
253	"\|IBPBOnVMExit"
254	"\|IBPBOnVMEntry"
255	"\|SpecCtrlByHost"
256	"\|L1DFlushOnSched"
257	"\|L1DFlushOnVMEntry"
258	"\|MDSClearOnSched"
259	"\|MDSClearOnVMEntry"
260	"\|TPRPatchingEnabled"
261	"\|64bitEnabled"
262	"\|Exclusive"
263	"\|MaxResumeLoops"
264	"\|VmxPleGap"
265	"\|VmxPleWindow"
266	"\|VmxLbr"
267	"\|UseVmxPreemptTimer"
268	"\|SvmPauseFilter"
269	"\|SvmPauseFilterThreshold"
270	"\|SvmVirtVmsaveVmload"
271	"\|SvmVGif"
272	"\|LovelyMesaDrvWorkaround"
273	"\|MissingOS2TlbFlushWorkaround",
274	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
275	if (RT_FAILURE(rc))
276	return rc;
277
278	/** @cfgm{/HM/HMForced, bool, false}
279	* Forces hardware virtualization, no falling back on raw-mode. HM must be
280	* enabled, i.e. /HMEnabled must be true. */
281	bool const fHMForced = true;
282	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
283	AssertRelease(pVM->fHMEnabled);
284	#else
285	AssertRelease(!pVM->fHMEnabled);
286	#endif
287
288	/** @cfgm{/HM/UseNEMInstead, bool, true}
289	* Don't use HM, use NEM instead. */
290	bool fUseNEMInstead = false;
291	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
292	AssertRCReturn(rc, rc);
293	if (fUseNEMInstead && pVM->fHMEnabled)
294	{
295	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
296	pVM->fHMEnabled = false;
297	}
298
299	/** @cfgm{/HM/FallbackToNEM, bool, true}
300	* Enables fallback on NEM. */
301	bool fFallbackToNEM = true;
302	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
303	AssertRCReturn(rc, rc);
304
305	/** @cfgm{/HM/FallbackToIEM, bool, false on AMD64 else true }
306	* Enables fallback on NEM. */
307	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
308	bool fFallbackToIEM = false;
309	#else
310	bool fFallbackToIEM = true;
311	#endif
312	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToIEM", &fFallbackToIEM, fFallbackToIEM);
313	AssertRCReturn(rc, rc);
314
315	/** @cfgm{/HM/EnableNestedPaging, bool, false}
316	* Enables nested paging (aka extended page tables). */
317	bool fAllowNestedPaging = false;
318	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
319	AssertRCReturn(rc, rc);
320
321	/** @cfgm{/HM/EnableUX, bool, true}
322	* Enables the VT-x unrestricted execution feature. */
323	bool fAllowUnrestricted = true;
324	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
325	AssertRCReturn(rc, rc);
326
327	/** @cfgm{/HM/EnableLargePages, bool, false}
328	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
329	* page table walking and maybe better TLB hit rate in some cases. */
330	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
331	AssertRCReturn(rc, rc);
332
333	/** @cfgm{/HM/EnableVPID, bool, false}
334	* Enables the VT-x VPID feature. */
335	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
336	AssertRCReturn(rc, rc);
337
338	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
339	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
340	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
341	AssertRCReturn(rc, rc);
342
343	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
344	* Enables AMD64 cpu features.
345	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
346	* already have the support. */
347	#ifdef VBOX_WITH_64_BITS_GUESTS
348	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
349	AssertLogRelRCReturn(rc, rc);
350	#else
351	pVM->hm.s.fAllow64BitGuestsCfg = false;
352	#endif
353
354	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
355	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
356	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
357	* latest PAUSE instruction to be start of a new PAUSE loop.
358	*/
359	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
360	AssertRCReturn(rc, rc);
361
362	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
363	* The pause-filter exiting window in TSC ticks. When the number of ticks
364	* between the current PAUSE instruction and first PAUSE of a loop exceeds
365	* VmxPleWindow, a VM-exit is triggered.
366	*
367	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
368	*/
369	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/VmxLbr, bool, false}
373	* Whether to enable LBR for the guest. This is disabled by default as it's only
374	* useful while debugging and enabling it causes a noticeable performance hit. */
375	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
376	AssertRCReturn(rc, rc);
377
378	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
379	* A counter that is decrement each time a PAUSE instruction is executed by the
380	* guest. When the counter is 0, a \#VMEXIT is triggered.
381	*
382	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
383	*/
384	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
385	AssertRCReturn(rc, rc);
386
387	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
388	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
389	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
390	* PauseFilter count is reset to its initial value. However, if PAUSE is
391	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
392	* be triggered.
393	*
394	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
395	* activated.
396	*/
397	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
398	AssertRCReturn(rc, rc);
399
400	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
401	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
402	* available. */
403	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
404	AssertRCReturn(rc, rc);
405
406	/** @cfgm{/HM/SvmVGif, bool, true}
407	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
408	* if it's available. */
409	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
410	AssertRCReturn(rc, rc);
411
412	/** @cfgm{/HM/SvmLbrVirt, bool, false}
413	* Whether to make use of the LBR virtualization feature of the CPU if it's
414	* available. This is disabled by default as it's only useful while debugging
415	* and enabling it causes a small hit to performance. */
416	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
417	AssertRCReturn(rc, rc);
418
419	/** @cfgm{/HM/Exclusive, bool}
420	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
421	* global init for each host CPU. If false, we do local init each time we wish
422	* to execute guest code.
423	*
424	* On Windows, default is false due to the higher risk of conflicts with other
425	* hypervisors.
426	*
427	* On Mac OS X, this setting is ignored since the code does not handle local
428	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
429	*/
430	#if defined(RT_OS_DARWIN)
431	pVM->hm.s.fGlobalInit = true;
432	#else
433	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
434	# if defined(RT_OS_WINDOWS)
435	false
436	# else
437	true
438	# endif
439	);
440	AssertLogRelRCReturn(rc, rc);
441	#endif
442
443	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
444	* The number of times to resume guest execution before we forcibly return to
445	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
446	* determines the default value. */
447	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
448	AssertLogRelRCReturn(rc, rc);
449
450	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
451	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
452	* available. */
453	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
454	AssertLogRelRCReturn(rc, rc);
455
456	/** @cfgm{/HM/IBPBOnVMExit, bool}
457	* Costly paranoia setting. */
458	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
459	AssertLogRelRCReturn(rc, rc);
460
461	/** @cfgm{/HM/IBPBOnVMEntry, bool}
462	* Costly paranoia setting. */
463	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
464	AssertLogRelRCReturn(rc, rc);
465
466	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
467	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
468	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
469	AssertLogRelRCReturn(rc, rc);
470
471	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
472	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
474	AssertLogRelRCReturn(rc, rc);
475
476	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
477	if (pVM->hm.s.fL1dFlushOnVmEntry)
478	pVM->hm.s.fL1dFlushOnSched = false;
479
480	/** @cfgm{/HM/SpecCtrlByHost, bool}
481	* Another expensive paranoia setting. */
482	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
483	AssertLogRelRCReturn(rc, rc);
484
485	/** @cfgm{/HM/MDSClearOnSched, bool, true}
486	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
487	* ignored on CPUs that aren't affected. */
488	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
489	AssertLogRelRCReturn(rc, rc);
490
491	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
492	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
493	* ignored on CPUs that aren't affected. */
494	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
495	AssertLogRelRCReturn(rc, rc);
496
497	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
498	if (pVM->hm.s.fMdsClearOnVmEntry)
499	pVM->hm.s.fMdsClearOnSched = false;
500
501	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
502	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
503	* the hypervisor it is running under. */
504	bool fMesaWorkaround;
505	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
506	AssertLogRelRCReturn(rc, rc);
507	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
508	{
509	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
510	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
511	}
512
513	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
514	* Workaround OS/2 not flushing the TLB after page directory and page table
515	* modifications when returning to protected mode from a real mode call
516	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
517	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
518	AssertLogRelRCReturn(rc, rc);
519
520	/*
521	* Check if VT-x or AMD-v support according to the users wishes.
522	*/
523	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
524	* VERR_SVM_IN_USE. */
525	if (pVM->fHMEnabled)
526	{
527	uint32_t fCaps;
528	rc = SUPR3QueryVTCaps(&fCaps);
529	if (RT_SUCCESS(rc))
530	{
531	if (fCaps & SUPVTCAPS_AMD_V)
532	{
533	pVM->hm.s.svm.fSupported = true;
534	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
535	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
536	}
537	else if (fCaps & SUPVTCAPS_VT_X)
538	{
539	const char *pszWhy;
540	rc = SUPR3QueryVTxSupported(&pszWhy);
541	if (RT_SUCCESS(rc))
542	{
543	pVM->hm.s.vmx.fSupported = true;
544	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
545	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
546	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
547	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
548	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
549	}
550	else
551	{
552	/*
553	* Before failing, try fallback to NEM if we're allowed to do that.
554	*/
555	pVM->fHMEnabled = false;
556	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
557	if (fFallbackToNEM)
558	{
559	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
560	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
561
562	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
563	if ( RT_SUCCESS(rc2)
564	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
565	rc = VINF_SUCCESS;
566	}
567	if (RT_FAILURE(rc))
568	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
569	}
570	}
571	else
572	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
573	VERR_INTERNAL_ERROR_5);
574
575	/*
576	* Disable nested paging and unrestricted guest execution now if they're
577	* configured so that CPUM can make decisions based on our configuration.
578	*/
579	if ( fAllowNestedPaging
580	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
581	{
582	pVM->hm.s.fNestedPagingCfg = true;
583	if (fCaps & SUPVTCAPS_VT_X)
584	{
585	if ( fAllowUnrestricted
586	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
587	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
588	else
589	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
590	}
591	}
592	else
593	Assert(!pVM->hm.s.fNestedPagingCfg);
594	}
595	else
596	{
597	const char *pszMsg;
598	switch (rc)
599	{
600	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
601	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
602	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
603	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
604	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
605	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
606	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
607	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
608	default:
609	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
610	}
611
612	/*
613	* Before failing, try fallback to NEM if we're allowed to do that.
614	*/
615	pVM->fHMEnabled = false;
616	if (fFallbackToNEM)
617	{
618	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
619	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
620	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
621	if ( RT_SUCCESS(rc2)
622	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
623	{
624	rc = VINF_SUCCESS;
625
626	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
627	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
628	}
629	}
630
631	/*
632	* Then try fall back on IEM if NEM isn't available and we're allowed to.
633	*/
634	if (RT_FAILURE(rc))
635	{
636	if ( fFallbackToIEM
637	&& (!fFallbackToNEM \|\| rc == VERR_NEM_NOT_AVAILABLE \|\| rc == VERR_SUP_DRIVERLESS))
638	{
639	LogRel(("HM: HMR3Init: Falling back on IEM: %s\n", !fFallbackToNEM ? pszMsg : "NEM not available"));
640	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
641	#ifdef VBOX_WITH_PGM_NEM_MODE
642	PGMR3EnableNemMode(pVM);
643	#endif
644	}
645	else
646	return VM_SET_ERROR(pVM, rc, pszMsg);
647	}
648	}
649	}
650	else
651	{
652	/*
653	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
654	*/
655	rc = VERR_NEM_NOT_AVAILABLE;
656	if (fUseNEMInstead)
657	{
658	rc = NEMR3Init(pVM, false /fFallback/, true);
659	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
660	if (RT_SUCCESS(rc))
661	{
662	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
663	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
664	}
665	else if (!fFallbackToIEM \|\| rc != VERR_NEM_NOT_AVAILABLE)
666	return rc;
667	}
668
669	if (fFallbackToIEM && rc == VERR_NEM_NOT_AVAILABLE)
670	{
671	LogRel(("HM: HMR3Init: Falling back on IEM%s\n", fUseNEMInstead ? ": NEM not available" : ""));
672	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
673	#ifdef VBOX_WITH_PGM_NEM_MODE
674	PGMR3EnableNemMode(pVM);
675	#endif
676	}
677
678	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
679	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
680	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
681	}
682
683	if (pVM->fHMEnabled)
684	{
685	/*
686	* Register info handlers now that HM is used for sure.
687	*/
688	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
689	AssertRCReturn(rc, rc);
690
691	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
692	DBGFINFO_FLAGS_ALL_EMTS);
693	AssertRCReturn(rc, rc);
694
695	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
696	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
697	AssertRCReturn(rc, rc);
698
699	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
700	AssertRCReturn(rc, rc);
701	}
702
703	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
704	return VINF_SUCCESS;
705	}
706
707
708	/**
709	* Initializes HM components after ring-3 phase has been fully initialized.
710	*
711	* @returns VBox status code.
712	* @param pVM The cross context VM structure.
713	*/
714	static int hmR3InitFinalizeR3(PVM pVM)
715	{
716	LogFlowFunc(("\n"));
717
718	if (!HMIsEnabled(pVM))
719	return VINF_SUCCESS;
720
721	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
722	{
723	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
724	pVCpu->hm.s.fActive = false;
725	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
726	pVCpu->hm.s.fGCMTrapXcptDE = GCMShouldTrapXcptDE(pVCpu); /* Is safe to call now since GCMR3Init() has completed. */
727	}
728
729	#if defined(RT_ARCH_AMD64) \|\|defined(RT_ARCH_X86)
730	/*
731	* Check if L1D flush is needed/possible.
732	*/
733	if ( !g_CpumHostFeatures.s.fFlushCmd
734	\|\| g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
735	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
736	\|\| g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d
737	\|\| g_CpumHostFeatures.s.fArchRdclNo)
738	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
739
740	/*
741	* Check if MDS flush is needed/possible.
742	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
743	*/
744	if ( !g_CpumHostFeatures.s.fMdsClear
745	\|\| g_CpumHostFeatures.s.fArchMdsNo)
746	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
747	else if ( ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
748	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
749	\|\| ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
750	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
751	{
752	if (!pVM->hm.s.fMdsClearOnSched)
753	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
754	pVM->hm.s.fMdsClearOnVmEntry = false;
755	}
756	else if ( g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
757	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
758	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
759	#endif
760
761	/*
762	* Statistics.
763	*/
764	#ifdef VBOX_WITH_STATISTICS
765	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
766	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
767	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
768	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
769	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
770	#endif
771
772	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
773	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
774	#else
775	bool const fCpuSupportsVmx = false;
776	#endif
777	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
778	{
779	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
780	PHMCPU pHmCpu = &pVCpu->hm.s;
781	int rc;
782
783	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
784	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
785	AssertRC(rc); \
786	} while (0)
787	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
788	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
789
790	#ifdef VBOX_WITH_STATISTICS
791
792	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
793	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
794	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
795	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
796	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
797	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
798	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
799	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
800	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
801	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
802	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
803	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
804	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
805	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
806	# ifdef HM_PROFILE_EXIT_DISPATCH
807	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
808	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
809	# endif
810	#endif
811	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
812
813	#ifdef VBOX_WITH_STATISTICS
814	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
815	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
816	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
817	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
818	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
819	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
820	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
821	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
822	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
823	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
824	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
825	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
826	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
827	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
828	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
829	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
830	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
831	#endif
832	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
833	if (fCpuSupportsVmx)
834	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
835	#ifdef VBOX_WITH_STATISTICS
836	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
837	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
838	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
839	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
840	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
841	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
842	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
843	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
844	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
845	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
846	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
847	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
848	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
849	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
850	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
851	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
852	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
853	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
854	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
855	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
856	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
857	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
858	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
859	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
860	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
861	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
862	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
863	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
864	#endif
865	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
866	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
867	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
868	#ifdef VBOX_WITH_STATISTICS
869	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
870	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
871	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
872
873	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
874	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
875	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
876	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
877	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
878	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
879	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
880	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
881	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
882	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
883	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
884	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
885	#endif
886	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
887	#ifdef VBOX_WITH_STATISTICS
888	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
889
890	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
891	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
892	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
893	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
894	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
895	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
896
897	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
898	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
899	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
900	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
901	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
902	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
903	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
904	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
905	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
906	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
907	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
908	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
909	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
910	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
911	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
912
913	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
914	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
915	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
916
917	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
918	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
919	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
920
921	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
922	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
923	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
924	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
925
926	if (fCpuSupportsVmx)
927	{
928	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
929	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
930	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
931	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
932	}
933
934	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
935	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
936	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
937
938	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
939	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
940	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
941
942	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
943	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
944	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
945	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
946	#endif
947	if (fCpuSupportsVmx)
948	{
949	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
950	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
951	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
952	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
953	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
954	}
955	#ifdef VBOX_WITH_STATISTICS
956	/*
957	* Guest Exit reason stats.
958	*/
959	if (fCpuSupportsVmx)
960	{
961	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
962	{
963	const char *pszExitName = HMGetVmxExitName(j);
964	if (pszExitName)
965	{
966	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
967	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
968	AssertRCReturn(rc, rc);
969	}
970	}
971	}
972	else
973	{
974	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
975	{
976	const char *pszExitName = HMGetSvmExitName(j);
977	if (pszExitName)
978	{
979	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
980	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
981	AssertRC(rc);
982	}
983	}
984	}
985	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
986
987	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
988	/*
989	* Nested-guest VM-exit reason stats.
990	*/
991	if (fCpuSupportsVmx)
992	{
993	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
994	{
995	const char *pszExitName = HMGetVmxExitName(j);
996	if (pszExitName)
997	{
998	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
999	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
1000	AssertRC(rc);
1001	}
1002	}
1003	}
1004	else
1005	{
1006	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1007	{
1008	const char *pszExitName = HMGetSvmExitName(j);
1009	if (pszExitName)
1010	{
1011	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1012	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
1013	AssertRC(rc);
1014	}
1015	}
1016	}
1017	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
1018	#endif
1019
1020	/*
1021	* Injected interrupts stats.
1022	*/
1023	char szDesc[64];
1024	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
1025	{
1026	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
1027	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1028	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
1029	AssertRC(rc);
1030	}
1031
1032	/*
1033	* Injected exception stats.
1034	*/
1035	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
1036	{
1037	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
1038	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1039	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
1040	AssertRC(rc);
1041	}
1042
1043	#endif /* VBOX_WITH_STATISTICS */
1044	#undef HM_REG_COUNTER
1045	#undef HM_REG_PROFILE
1046	#undef HM_REG_STAT
1047	}
1048
1049	return VINF_SUCCESS;
1050	}
1051
1052
1053	/**
1054	* Called when a init phase has completed.
1055	*
1056	* @returns VBox status code.
1057	* @param pVM The cross context VM structure.
1058	* @param enmWhat The phase that completed.
1059	*/
1060	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1061	{
1062	switch (enmWhat)
1063	{
1064	case VMINITCOMPLETED_RING3:
1065	return hmR3InitFinalizeR3(pVM);
1066	case VMINITCOMPLETED_RING0:
1067	return hmR3InitFinalizeR0(pVM);
1068	default:
1069	return VINF_SUCCESS;
1070	}
1071	}
1072
1073
1074	/**
1075	* Turns off normal raw mode features.
1076	*
1077	* @param pVM The cross context VM structure.
1078	*/
1079	static void hmR3DisableRawMode(PVM pVM)
1080	{
1081	/** @todo r=bird: HM shouldn't be doing this crap. */
1082	/* Reinit the paging mode to force the new shadow mode. */
1083	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1084	{
1085	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1086	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1087	}
1088	}
1089
1090
1091	/**
1092	* Initialize VT-x or AMD-V.
1093	*
1094	* @returns VBox status code.
1095	* @param pVM The cross context VM structure.
1096	*/
1097	static int hmR3InitFinalizeR0(PVM pVM)
1098	{
1099	int rc;
1100
1101	if (!HMIsEnabled(pVM))
1102	return VINF_SUCCESS;
1103
1104	/*
1105	* Hack to allow users to work around broken BIOSes that incorrectly set
1106	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1107	*/
1108	if ( !pVM->hm.s.vmx.fSupported
1109	&& !pVM->hm.s.svm.fSupported
1110	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1111	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1112	{
1113	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1114	pVM->hm.s.svm.fSupported = true;
1115	pVM->hm.s.svm.fIgnoreInUseError = true;
1116	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1117	}
1118
1119	/*
1120	* Report ring-0 init errors.
1121	*/
1122	if ( !pVM->hm.s.vmx.fSupported
1123	&& !pVM->hm.s.svm.fSupported)
1124	{
1125	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1126	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1127	switch (pVM->hm.s.ForR3.rcInit)
1128	{
1129	case VERR_VMX_IN_VMX_ROOT_MODE:
1130	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1131	case VERR_VMX_NO_VMX:
1132	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1133	case VERR_VMX_MSR_VMX_DISABLED:
1134	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1135	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1136	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1137	case VERR_VMX_MSR_LOCKING_FAILED:
1138	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1139	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1140	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1141	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1142	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1143
1144	case VERR_SVM_IN_USE:
1145	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1146	case VERR_SVM_NO_SVM:
1147	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1148	case VERR_SVM_DISABLED:
1149	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1150	}
1151	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1152	}
1153
1154	/*
1155	* Enable VT-x or AMD-V on all host CPUs.
1156	*/
1157	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1158	if (RT_FAILURE(rc))
1159	{
1160	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1161	HMR3CheckError(pVM, rc);
1162	return rc;
1163	}
1164
1165	/*
1166	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1167	* (Main should have taken care of this already)
1168	*/
1169	if (!PDMHasIoApic(pVM))
1170	{
1171	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1172	pVM->hm.s.fTprPatchingAllowed = false;
1173	}
1174
1175	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1176	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1177	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1178
1179	/*
1180	* Do the vendor specific initialization
1181	*
1182	* Note! We disable release log buffering here since we're doing relatively
1183	* lot of logging and doesn't want to hit the disk with each LogRel
1184	* statement.
1185	*/
1186	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1187	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1188	if (pVM->hm.s.vmx.fSupported)
1189	rc = hmR3InitFinalizeR0Intel(pVM);
1190	else
1191	rc = hmR3InitFinalizeR0Amd(pVM);
1192	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1193	: "HM: VT-x/AMD-V init method: Local\n"));
1194	RTLogRelSetBuffering(fOldBuffered);
1195	pVM->hm.s.fInitialized = true;
1196
1197	return rc;
1198	}
1199
1200
1201	/**
1202	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1203	*/
1204	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1205	{
1206	NOREF(pVM);
1207	NOREF(pvAllocation);
1208	NOREF(GCPhysAllocation);
1209	}
1210
1211
1212	/**
1213	* Returns a description of the VMCS (and associated regions') memory type given the
1214	* IA32_VMX_BASIC MSR.
1215	*
1216	* @returns The descriptive memory type.
1217	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1218	*/
1219	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1220	{
1221	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1222	switch (uMemType)
1223	{
1224	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1225	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1226	}
1227	return "Unknown";
1228	}
1229
1230
1231	/**
1232	* Returns a single-line description of all the activity-states supported by the CPU
1233	* given the IA32_VMX_MISC MSR.
1234	*
1235	* @returns All supported activity states.
1236	* @param uMsrMisc IA32_VMX_MISC MSR value.
1237	*/
1238	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1239	{
1240	static const char * const s_apszActStates[] =
1241	{
1242	"",
1243	" ( HLT )",
1244	" ( SHUTDOWN )",
1245	" ( HLT SHUTDOWN )",
1246	" ( SIPI_WAIT )",
1247	" ( HLT SIPI_WAIT )",
1248	" ( SHUTDOWN SIPI_WAIT )",
1249	" ( HLT SHUTDOWN SIPI_WAIT )"
1250	};
1251	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1252	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1253	return s_apszActStates[idxActStates];
1254	}
1255
1256
1257	/**
1258	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1259	*
1260	* @param fFeatMsr The feature control MSR value.
1261	*/
1262	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1263	{
1264	uint64_t const val = fFeatMsr;
1265	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1266	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1267	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1268	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1269	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1270	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1271	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1272	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1273	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1274	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1275	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1276	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1277	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1278	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1279	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1280	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1281	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1282	}
1283
1284
1285	/**
1286	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1287	*
1288	* @param uBasicMsr The VMX basic MSR value.
1289	*/
1290	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1291	{
1292	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1293	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1294	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1295	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1296	"< 4 GB" : "None"));
1297	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1298	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1299	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1300	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1301	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1302	}
1303
1304
1305	/**
1306	* Reports MSR_IA32_PINBASED_CTLS to the log.
1307	*
1308	* @param pVmxMsr Pointer to the VMX MSR.
1309	*/
1310	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1311	{
1312	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1313	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1314	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1315	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1316	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1317	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1318	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1319	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1320	}
1321
1322
1323	/**
1324	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1325	*
1326	* @param pVmxMsr Pointer to the VMX MSR.
1327	*/
1328	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1329	{
1330	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1331	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1332	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1351	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1352	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1353	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1354	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1355	}
1356
1357
1358	/**
1359	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1360	*
1361	* @param pVmxMsr Pointer to the VMX MSR.
1362	*/
1363	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1364	{
1365	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1366	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1367	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1368	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1369	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1387	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1388	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1389	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1390	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1391	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1392	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1393	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1395	}
1396
1397
1398	/**
1399	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1400	*
1401	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1402	*/
1403	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1404	{
1405	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1406	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1407	}
1408
1409
1410	/**
1411	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1412	*
1413	* @param pVmxMsr Pointer to the VMX MSR.
1414	*/
1415	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1416	{
1417	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1418	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1419	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1420	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1421	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1422	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1423	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1424	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1425	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1426	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1427	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1428	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1429	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1430	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1431	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1432	}
1433
1434
1435	/**
1436	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1437	*
1438	* @param pVmxMsr Pointer to the VMX MSR.
1439	*/
1440	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1441	{
1442	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1443	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1444	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1445	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1446	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1447	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1448	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1449	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1450	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1451	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1452	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1453	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1454	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1455	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1456	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1457	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1458	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1459	}
1460
1461
1462	/**
1463	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1464	*
1465	* @param fCaps The VMX EPT/VPID capability MSR value.
1466	*/
1467	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1468	{
1469	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1470	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1471	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1472	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1473	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1474	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1475	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1476	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1477	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1478	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1479	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1480	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1481	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1482	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1483	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1484	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1485	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1486	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1487	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1488	}
1489
1490
1491	/**
1492	* Reports MSR_IA32_VMX_MISC MSR to the log.
1493	*
1494	* @param pVM Pointer to the VM.
1495	* @param fMisc The VMX misc. MSR value.
1496	*/
1497	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1498	{
1499	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1500	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1501	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1502	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1503	else
1504	{
1505	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1506	pVM->hm.s.vmx.cPreemptTimerShift));
1507	}
1508	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1509	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1510	hmR3VmxGetActivityStateAllDesc(fMisc)));
1511	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1512	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1513	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1514	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1515	VMX_MISC_MAX_MSRS(fMisc)));
1516	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1517	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1518	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1519	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1520	}
1521
1522
1523	/**
1524	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1525	*
1526	* @param uVmcsEnum The VMX VMCS enum MSR value.
1527	*/
1528	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1529	{
1530	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1531	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1532	}
1533
1534
1535	/**
1536	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1537	*
1538	* @param uVmFunc The VMX VMFUNC MSR value.
1539	*/
1540	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1541	{
1542	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1543	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1544	}
1545
1546
1547	/**
1548	* Reports VMX CR0, CR4 fixed MSRs.
1549	*
1550	* @param pMsrs Pointer to the VMX MSRs.
1551	*/
1552	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1553	{
1554	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1555	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1556	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1557	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1558	}
1559
1560
1561	/**
1562	* Finish VT-x initialization (after ring-0 init).
1563	*
1564	* @returns VBox status code.
1565	* @param pVM The cross context VM structure.
1566	*/
1567	static int hmR3InitFinalizeR0Intel(PVM pVM)
1568	{
1569	int rc;
1570
1571	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1572	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1573
1574	LogRel(("HM: Using VT-x implementation 3.0\n"));
1575	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1576	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1577	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1578	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1579
1580	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1581	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1582
1583	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1584	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1585	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1586	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1587	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1588	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1589
1590	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1591	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1592
1593	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1594	{
1595	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1596	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1597	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1598	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1599	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1600	}
1601
1602	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1603	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1604	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1605	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1606	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1607	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1608	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1609
1610	#ifdef TODO_9217_VMCSINFO
1611	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1612	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1613	{
1614	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1615	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1616	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1617	}
1618	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1619	if (pVM->cpum.ro.GuestFeatures.fVmx)
1620	{
1621	LogRel(("HM: Nested-guest:\n"));
1622	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1623	{
1624	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1625	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1626	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1627	}
1628	}
1629	#endif
1630	#endif /* TODO_9217_VMCSINFO */
1631
1632	/*
1633	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1634	*/
1635	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1636	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1637	VERR_HM_IPE_1);
1638	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1639	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1640	&& pVM->hm.s.fNestedPagingCfg),
1641	VERR_HM_IPE_1);
1642
1643	/*
1644	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1645	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1646	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1647	*/
1648	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1649	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1650	{
1651	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1652	LogRel(("HM: Disabled RDTSCP\n"));
1653	}
1654
1655	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1656	{
1657	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1658	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1659	if (RT_SUCCESS(rc))
1660	{
1661	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1662	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1663	esp. Figure 20-5.*/
1664	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1665	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1666
1667	/* Bit set to 0 means software interrupts are redirected to the
1668	8086 program interrupt handler rather than switching to
1669	protected-mode handler. */
1670	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1671
1672	/* Allow all port IO, so that port IO instructions do not cause
1673	exceptions and would instead cause a VM-exit (based on VT-x's
1674	IO bitmap which we currently configure to always cause an exit). */
1675	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1676	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1677
1678	/*
1679	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1680	* page table used in real and protected mode without paging with EPT.
1681	*/
1682	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1683	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1684	{
1685	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1686	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1687	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1688	\| X86_PDE4M_G;
1689	}
1690
1691	/* We convert it here every time as PCI regions could be reconfigured. */
1692	if (PDMVmmDevHeapIsEnabled(pVM))
1693	{
1694	RTGCPHYS GCPhys;
1695	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1696	AssertRCReturn(rc, rc);
1697	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1698
1699	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1700	AssertRCReturn(rc, rc);
1701	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1702	}
1703	}
1704	else
1705	{
1706	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1707	pVM->hm.s.vmx.pRealModeTSS = NULL;
1708	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1709	return VMSetError(pVM, rc, RT_SRC_POS,
1710	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1711	}
1712	}
1713
1714	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1715	: "HM: Guest support: 32-bit only\n"));
1716
1717	/*
1718	* Call ring-0 to set up the VM.
1719	*/
1720	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1721	if (rc != VINF_SUCCESS)
1722	{
1723	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1724	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1725	{
1726	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1727	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1728	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1729	}
1730	HMR3CheckError(pVM, rc);
1731	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1732	}
1733
1734	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1735	LogRel(("HM: Enabled VMX\n"));
1736	pVM->hm.s.vmx.fEnabled = true;
1737
1738	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1739
1740	/*
1741	* Change the CPU features.
1742	*/
1743	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1744	if (pVM->hm.s.fAllow64BitGuestsCfg)
1745	{
1746	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1747	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1748	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1749	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1750	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1751	}
1752	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1753	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1754	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1755
1756	/*
1757	* Log configuration details.
1758	*/
1759	if (pVM->hm.s.fNestedPagingCfg)
1760	{
1761	LogRel(("HM: Enabled nested paging\n"));
1762	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1763	LogRel(("HM: EPT flush type = Single context\n"));
1764	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1765	LogRel(("HM: EPT flush type = All contexts\n"));
1766	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1767	LogRel(("HM: EPT flush type = Not supported\n"));
1768	else
1769	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1770
1771	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1772	LogRel(("HM: Enabled unrestricted guest execution\n"));
1773
1774	if (pVM->hm.s.fLargePages)
1775	{
1776	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1777	PGMSetLargePageUsage(pVM, true);
1778	LogRel(("HM: Enabled large page support\n"));
1779	}
1780	}
1781	else
1782	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1783
1784	if (pVM->hm.s.ForR3.vmx.fVpid)
1785	{
1786	LogRel(("HM: Enabled VPID\n"));
1787	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1788	LogRel(("HM: VPID flush type = Individual addresses\n"));
1789	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1790	LogRel(("HM: VPID flush type = Single context\n"));
1791	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1792	LogRel(("HM: VPID flush type = All contexts\n"));
1793	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1794	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1795	else
1796	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1797	}
1798	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1799	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1800
1801	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1802	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1803	else
1804	LogRel(("HM: Disabled VMX-preemption timer\n"));
1805
1806	if (pVM->hm.s.fVirtApicRegs)
1807	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1808
1809	if (pVM->hm.s.fPostedIntrs)
1810	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1811
1812	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1813	{
1814	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1815	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1816	}
1817
1818	return VINF_SUCCESS;
1819	}
1820
1821
1822	/**
1823	* Finish AMD-V initialization (after ring-0 init).
1824	*
1825	* @returns VBox status code.
1826	* @param pVM The cross context VM structure.
1827	*/
1828	static int hmR3InitFinalizeR0Amd(PVM pVM)
1829	{
1830	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1831
1832	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1833
1834	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1835	uint32_t u32Family;
1836	uint32_t u32Model;
1837	uint32_t u32Stepping;
1838	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1839	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1840	#endif
1841	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1842	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1843	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1844	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1845	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1846
1847	/*
1848	* Enumerate AMD-V features.
1849	*/
1850	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1851	{
1852	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1853	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1854	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1855	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1856	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1857	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1858	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1859	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1860	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1861	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1862	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1863	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1864	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1865	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1866	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1867	#undef HMSVM_REPORT_FEATURE
1868	};
1869
1870	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1871	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1872	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1873	{
1874	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1875	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1876	}
1877	if (fSvmFeatures)
1878	for (unsigned iBit = 0; iBit < 32; iBit++)
1879	if (RT_BIT_32(iBit) & fSvmFeatures)
1880	LogRel(("HM: Reserved bit %u\n", iBit));
1881
1882	/*
1883	* Nested paging is determined in HMR3Init, verify the sanity of that.
1884	*/
1885	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1886	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1887	VERR_HM_IPE_1);
1888
1889	#if 0
1890	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1891	* here. */
1892	if (RTR0IsPostIpiSupport())
1893	pVM->hm.s.fPostedIntrs = true;
1894	#endif
1895
1896	/*
1897	* Determine whether we need to intercept #UD in SVM mode for emulating
1898	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1899	* when executed in long-mode. This is only really applicable when
1900	* non-default CPU profiles are in effect, i.e. guest vendor differs
1901	* from the host one.
1902	*/
1903	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1904	switch (CPUMGetGuestCpuVendor(pVM))
1905	{
1906	case CPUMCPUVENDOR_INTEL:
1907	case CPUMCPUVENDOR_VIA: /?/
1908	case CPUMCPUVENDOR_SHANGHAI: /?/
1909	switch (CPUMGetHostCpuVendor(pVM))
1910	{
1911	case CPUMCPUVENDOR_AMD:
1912	case CPUMCPUVENDOR_HYGON:
1913	if (pVM->hm.s.fAllow64BitGuestsCfg)
1914	{
1915	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1916	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1917	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1918	}
1919	break;
1920	default: break;
1921	}
1922	default: break;
1923	}
1924
1925	/*
1926	* Call ring-0 to set up the VM.
1927	*/
1928	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1929	if (rc != VINF_SUCCESS)
1930	{
1931	AssertMsgFailed(("%Rrc\n", rc));
1932	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1933	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1934	}
1935
1936	LogRel(("HM: Enabled SVM\n"));
1937	pVM->hm.s.svm.fEnabled = true;
1938
1939	if (pVM->hm.s.fNestedPagingCfg)
1940	{
1941	LogRel(("HM: Enabled nested paging\n"));
1942
1943	/*
1944	* Enable large pages (2 MB) if applicable.
1945	*/
1946	if (pVM->hm.s.fLargePages)
1947	{
1948	PGMSetLargePageUsage(pVM, true);
1949	LogRel(("HM: Enabled large page support\n"));
1950	}
1951	}
1952
1953	if (pVM->hm.s.fVirtApicRegs)
1954	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1955
1956	if (pVM->hm.s.fPostedIntrs)
1957	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1958
1959	hmR3DisableRawMode(pVM);
1960
1961	/*
1962	* Change the CPU features.
1963	*/
1964	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1965	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1966	if (pVM->hm.s.fAllow64BitGuestsCfg)
1967	{
1968	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1969	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1970	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1971	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1972	}
1973	/* Turn on NXE if PAE has been enabled. */
1974	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1975	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1976
1977	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1978	: "HM: Disabled TPR patching\n"));
1979
1980	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1981	: "HM: Guest support: 32-bit only\n"));
1982	return VINF_SUCCESS;
1983	}
1984
1985
1986	/**
1987	* Applies relocations to data and code managed by this
1988	* component. This function will be called at init and
1989	* whenever the VMM need to relocate it self inside the GC.
1990	*
1991	* @param pVM The cross context VM structure.
1992	*/
1993	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1994	{
1995	/* Fetch the current paging mode during the relocate callback during state loading. */
1996	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1997	{
1998	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1999	{
2000	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2001	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2002	}
2003	}
2004	}
2005
2006
2007	/**
2008	* Terminates the HM.
2009	*
2010	* Termination means cleaning up and freeing all resources,
2011	* the VM itself is, at this point, powered off or suspended.
2012	*
2013	* @returns VBox status code.
2014	* @param pVM The cross context VM structure.
2015	*/
2016	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2017	{
2018	if (pVM->hm.s.vmx.pRealModeTSS)
2019	{
2020	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2021	pVM->hm.s.vmx.pRealModeTSS = 0;
2022	}
2023	hmR3TermCPU(pVM);
2024	return 0;
2025	}
2026
2027
2028	/**
2029	* Terminates the per-VCPU HM.
2030	*
2031	* @returns VBox status code.
2032	* @param pVM The cross context VM structure.
2033	*/
2034	static int hmR3TermCPU(PVM pVM)
2035	{
2036	RT_NOREF(pVM);
2037	return VINF_SUCCESS;
2038	}
2039
2040
2041	/**
2042	* Resets a virtual CPU.
2043	*
2044	* Used by HMR3Reset and CPU hot plugging.
2045	*
2046	* @param pVCpu The cross context virtual CPU structure to reset.
2047	*/
2048	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2049	{
2050	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2051	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2052	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2053
2054	pVCpu->hm.s.fActive = false;
2055	pVCpu->hm.s.Event.fPending = false;
2056	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2057	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2058	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2059	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2060	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2061	#endif
2062	}
2063
2064
2065	/**
2066	* The VM is being reset.
2067	*
2068	* For the HM component this means that any GDT/LDT/TSS monitors
2069	* needs to be removed.
2070	*
2071	* @param pVM The cross context VM structure.
2072	*/
2073	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2074	{
2075	LogFlow(("HMR3Reset:\n"));
2076
2077	if (HMIsEnabled(pVM))
2078	hmR3DisableRawMode(pVM);
2079
2080	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2081	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2082
2083	/* Clear all patch information. */
2084	pVM->hm.s.pGuestPatchMem = 0;
2085	pVM->hm.s.pFreeGuestPatchMem = 0;
2086	pVM->hm.s.cbGuestPatchMem = 0;
2087	pVM->hm.s.cPatches = 0;
2088	pVM->hm.s.PatchTree = 0;
2089	pVM->hm.s.fTprPatchingActive = false;
2090	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2091	}
2092
2093
2094	/**
2095	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2096	*
2097	* @returns VBox strict status code.
2098	* @param pVM The cross context VM structure.
2099	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2100	* @param pvUser Unused.
2101	*/
2102	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2103	{
2104	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2105
2106	/* Only execute the handler on the VCPU the original patch request was issued. */
2107	if (pVCpu->idCpu != idCpu)
2108	return VINF_SUCCESS;
2109
2110	Log(("hmR3RemovePatches\n"));
2111	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2112	{
2113	uint8_t abInstr[15];
2114	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2115	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2116	int rc;
2117
2118	#ifdef LOG_ENABLED
2119	char szOutput[256];
2120	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2121	szOutput, sizeof(szOutput), NULL);
2122	if (RT_SUCCESS(rc))
2123	Log(("Patched instr: %s\n", szOutput));
2124	#endif
2125
2126	/* Check if the instruction is still the same. */
2127	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2128	if (rc != VINF_SUCCESS)
2129	{
2130	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2131	continue; /* swapped out or otherwise removed; skip it. */
2132	}
2133
2134	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2135	{
2136	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2137	continue; /* skip it. */
2138	}
2139
2140	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2141	AssertRC(rc);
2142
2143	#ifdef LOG_ENABLED
2144	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2145	szOutput, sizeof(szOutput), NULL);
2146	if (RT_SUCCESS(rc))
2147	Log(("Original instr: %s\n", szOutput));
2148	#endif
2149	}
2150	pVM->hm.s.cPatches = 0;
2151	pVM->hm.s.PatchTree = 0;
2152	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2153	pVM->hm.s.fTprPatchingActive = false;
2154	return VINF_SUCCESS;
2155	}
2156
2157
2158	/**
2159	* Worker for enabling patching in a VT-x/AMD-V guest.
2160	*
2161	* @returns VBox status code.
2162	* @param pVM The cross context VM structure.
2163	* @param idCpu VCPU to execute hmR3RemovePatches on.
2164	* @param pPatchMem Patch memory range.
2165	* @param cbPatchMem Size of the memory range.
2166	*/
2167	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2168	{
2169	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2170	AssertRC(rc);
2171
2172	pVM->hm.s.pGuestPatchMem = pPatchMem;
2173	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2174	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2175	return VINF_SUCCESS;
2176	}
2177
2178
2179	/**
2180	* Enable patching in a VT-x/AMD-V guest
2181	*
2182	* @returns VBox status code.
2183	* @param pVM The cross context VM structure.
2184	* @param pPatchMem Patch memory range.
2185	* @param cbPatchMem Size of the memory range.
2186	*/
2187	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2188	{
2189	VM_ASSERT_EMT(pVM);
2190	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2191	if (pVM->cCpus > 1)
2192	{
2193	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2194	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2195	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2196	AssertRC(rc);
2197	return rc;
2198	}
2199	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2200	}
2201
2202
2203	/**
2204	* Disable patching in a VT-x/AMD-V guest.
2205	*
2206	* @returns VBox status code.
2207	* @param pVM The cross context VM structure.
2208	* @param pPatchMem Patch memory range.
2209	* @param cbPatchMem Size of the memory range.
2210	*/
2211	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2212	{
2213	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2214	RT_NOREF2(pPatchMem, cbPatchMem);
2215
2216	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2217	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2218
2219	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2220	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2221	(void *)(uintptr_t)VMMGetCpuId(pVM));
2222	AssertRC(rc);
2223
2224	pVM->hm.s.pGuestPatchMem = 0;
2225	pVM->hm.s.pFreeGuestPatchMem = 0;
2226	pVM->hm.s.cbGuestPatchMem = 0;
2227	pVM->hm.s.fTprPatchingActive = false;
2228	return VINF_SUCCESS;
2229	}
2230
2231
2232	/**
2233	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2234	*
2235	* @returns VBox strict status code.
2236	* @param pVM The cross context VM structure.
2237	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2238	* @param pvUser User specified CPU context.
2239	*
2240	*/
2241	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2242	{
2243	/*
2244	* Only execute the handler on the VCPU the original patch request was
2245	* issued. (The other CPU(s) might not yet have switched to protected
2246	* mode, nor have the correct memory context.)
2247	*/
2248	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2249	if (pVCpu->idCpu != idCpu)
2250	return VINF_SUCCESS;
2251
2252	/*
2253	* We're racing other VCPUs here, so don't try patch the instruction twice
2254	* and make sure there is still room for our patch record.
2255	*/
2256	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2257	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2258	if (pPatch)
2259	{
2260	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2261	return VINF_SUCCESS;
2262	}
2263	uint32_t const idx = pVM->hm.s.cPatches;
2264	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2265	{
2266	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2267	return VINF_SUCCESS;
2268	}
2269	pPatch = &pVM->hm.s.aPatches[idx];
2270
2271	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2272
2273	/*
2274	* Disassembler the instruction and get cracking.
2275	*/
2276	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2277	DISCPUSTATE Dis;
2278	uint32_t cbOp;
2279	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2280	AssertRC(rc);
2281	if ( rc == VINF_SUCCESS
2282	&& Dis.pCurInstr->uOpcode == OP_MOV
2283	&& cbOp >= 3)
2284	{
2285	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2286
2287	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2288	AssertRC(rc);
2289
2290	pPatch->cbOp = cbOp;
2291
2292	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2293	{
2294	/* write. */
2295	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2296	{
2297	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2298	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2299	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2300	}
2301	else
2302	{
2303	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2304	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2305	pPatch->uSrcOperand = Dis.Param2.uValue;
2306	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2307	}
2308	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2309	AssertRC(rc);
2310
2311	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2312	pPatch->cbNewOp = sizeof(s_abVMMCall);
2313	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2314	}
2315	else
2316	{
2317	/*
2318	* TPR Read.
2319	*
2320	* Found:
2321	* mov eax, dword [fffe0080] (5 bytes)
2322	* Check if next instruction is:
2323	* shr eax, 4
2324	*/
2325	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2326
2327	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2328	uint8_t const cbOpMmio = cbOp;
2329	uint64_t const uSavedRip = pCtx->rip;
2330
2331	pCtx->rip += cbOp;
2332	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2333	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2334	pCtx->rip = uSavedRip;
2335
2336	if ( rc == VINF_SUCCESS
2337	&& Dis.pCurInstr->uOpcode == OP_SHR
2338	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2339	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2340	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2341	&& Dis.Param2.uValue == 4
2342	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2343	{
2344	uint8_t abInstr[15];
2345
2346	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2347	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2348	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2349	AssertRC(rc);
2350
2351	pPatch->cbOp = cbOpMmio + cbOp;
2352
2353	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2354	abInstr[0] = 0xf0;
2355	abInstr[1] = 0x0f;
2356	abInstr[2] = 0x20;
2357	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2358	for (unsigned i = 4; i < pPatch->cbOp; i++)
2359	abInstr[i] = 0x90; /* nop */
2360
2361	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2362	AssertRC(rc);
2363
2364	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2365	pPatch->cbNewOp = pPatch->cbOp;
2366	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2367
2368	Log(("Acceptable read/shr candidate!\n"));
2369	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2370	}
2371	else
2372	{
2373	pPatch->enmType = HMTPRINSTR_READ;
2374	pPatch->uDstOperand = idxMmioReg;
2375
2376	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2377	AssertRC(rc);
2378
2379	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2380	pPatch->cbNewOp = sizeof(s_abVMMCall);
2381	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2382	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2383	}
2384	}
2385
2386	pPatch->Core.Key = pCtx->eip;
2387	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2388	AssertRC(rc);
2389
2390	pVM->hm.s.cPatches++;
2391	return VINF_SUCCESS;
2392	}
2393
2394	/*
2395	* Save invalid patch, so we will not try again.
2396	*/
2397	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2398	pPatch->Core.Key = pCtx->eip;
2399	pPatch->enmType = HMTPRINSTR_INVALID;
2400	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2401	AssertRC(rc);
2402	pVM->hm.s.cPatches++;
2403	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2404	return VINF_SUCCESS;
2405	}
2406
2407
2408	/**
2409	* Callback to patch a TPR instruction (jump to generated code).
2410	*
2411	* @returns VBox strict status code.
2412	* @param pVM The cross context VM structure.
2413	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2414	* @param pvUser User specified CPU context.
2415	*
2416	*/
2417	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2418	{
2419	/*
2420	* Only execute the handler on the VCPU the original patch request was
2421	* issued. (The other CPU(s) might not yet have switched to protected
2422	* mode, nor have the correct memory context.)
2423	*/
2424	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2425	if (pVCpu->idCpu != idCpu)
2426	return VINF_SUCCESS;
2427
2428	/*
2429	* We're racing other VCPUs here, so don't try patch the instruction twice
2430	* and make sure there is still room for our patch record.
2431	*/
2432	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2433	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2434	if (pPatch)
2435	{
2436	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2437	return VINF_SUCCESS;
2438	}
2439	uint32_t const idx = pVM->hm.s.cPatches;
2440	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2441	{
2442	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2443	return VINF_SUCCESS;
2444	}
2445	pPatch = &pVM->hm.s.aPatches[idx];
2446
2447	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2448	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2449
2450	/*
2451	* Disassemble the instruction and get cracking.
2452	*/
2453	DISCPUSTATE Dis;
2454	uint32_t cbOp;
2455	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2456	AssertRC(rc);
2457	if ( rc == VINF_SUCCESS
2458	&& Dis.pCurInstr->uOpcode == OP_MOV
2459	&& cbOp >= 5)
2460	{
2461	uint8_t aPatch[64];
2462	uint32_t off = 0;
2463
2464	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2465	AssertRC(rc);
2466
2467	pPatch->cbOp = cbOp;
2468	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2469
2470	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2471	{
2472	/*
2473	* TPR write:
2474	*
2475	* push ECX [51]
2476	* push EDX [52]
2477	* push EAX [50]
2478	* xor EDX,EDX [31 D2]
2479	* mov EAX,EAX [89 C0]
2480	* or
2481	* mov EAX,0000000CCh [B8 CC 00 00 00]
2482	* mov ECX,0C0000082h [B9 82 00 00 C0]
2483	* wrmsr [0F 30]
2484	* pop EAX [58]
2485	* pop EDX [5A]
2486	* pop ECX [59]
2487	* jmp return_address [E9 return_address]
2488	*/
2489	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2490
2491	aPatch[off++] = 0x51; /* push ecx */
2492	aPatch[off++] = 0x52; /* push edx */
2493	if (!fUsesEax)
2494	aPatch[off++] = 0x50; /* push eax */
2495	aPatch[off++] = 0x31; /* xor edx, edx */
2496	aPatch[off++] = 0xd2;
2497	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2498	{
2499	if (!fUsesEax)
2500	{
2501	aPatch[off++] = 0x89; /* mov eax, src_reg */
2502	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2503	}
2504	}
2505	else
2506	{
2507	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2508	aPatch[off++] = 0xb8; /* mov eax, immediate */
2509	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2510	off += sizeof(uint32_t);
2511	}
2512	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2513	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2514	off += sizeof(uint32_t);
2515
2516	aPatch[off++] = 0x0f; /* wrmsr */
2517	aPatch[off++] = 0x30;
2518	if (!fUsesEax)
2519	aPatch[off++] = 0x58; /* pop eax */
2520	aPatch[off++] = 0x5a; /* pop edx */
2521	aPatch[off++] = 0x59; /* pop ecx */
2522	}
2523	else
2524	{
2525	/*
2526	* TPR read:
2527	*
2528	* push ECX [51]
2529	* push EDX [52]
2530	* push EAX [50]
2531	* mov ECX,0C0000082h [B9 82 00 00 C0]
2532	* rdmsr [0F 32]
2533	* mov EAX,EAX [89 C0]
2534	* pop EAX [58]
2535	* pop EDX [5A]
2536	* pop ECX [59]
2537	* jmp return_address [E9 return_address]
2538	*/
2539	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2540
2541	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2542	aPatch[off++] = 0x51; /* push ecx */
2543	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2544	aPatch[off++] = 0x52; /* push edx */
2545	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2546	aPatch[off++] = 0x50; /* push eax */
2547
2548	aPatch[off++] = 0x31; /* xor edx, edx */
2549	aPatch[off++] = 0xd2;
2550
2551	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2552	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2553	off += sizeof(uint32_t);
2554
2555	aPatch[off++] = 0x0f; /* rdmsr */
2556	aPatch[off++] = 0x32;
2557
2558	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2559	{
2560	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2561	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2562	}
2563
2564	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2565	aPatch[off++] = 0x58; /* pop eax */
2566	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2567	aPatch[off++] = 0x5a; /* pop edx */
2568	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2569	aPatch[off++] = 0x59; /* pop ecx */
2570	}
2571	aPatch[off++] = 0xe9; /* jmp return_address */
2572	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2573	off += sizeof(RTRCUINTPTR);
2574
2575	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2576	{
2577	/* Write new code to the patch buffer. */
2578	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2579	AssertRC(rc);
2580
2581	#ifdef LOG_ENABLED
2582	uint32_t cbCurInstr;
2583	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2584	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2585	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2586	{
2587	char szOutput[256];
2588	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2589	szOutput, sizeof(szOutput), &cbCurInstr);
2590	if (RT_SUCCESS(rc))
2591	Log(("Patch instr %s\n", szOutput));
2592	else
2593	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2594	}
2595	#endif
2596
2597	pPatch->aNewOpcode[0] = 0xE9;
2598	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2599
2600	/* Overwrite the TPR instruction with a jump. */
2601	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2602	AssertRC(rc);
2603
2604	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2605
2606	pVM->hm.s.pFreeGuestPatchMem += off;
2607	pPatch->cbNewOp = 5;
2608
2609	pPatch->Core.Key = pCtx->eip;
2610	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2611	AssertRC(rc);
2612
2613	pVM->hm.s.cPatches++;
2614	pVM->hm.s.fTprPatchingActive = true;
2615	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2616	return VINF_SUCCESS;
2617	}
2618
2619	Log(("Ran out of space in our patch buffer!\n"));
2620	}
2621	else
2622	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2623
2624
2625	/*
2626	* Save invalid patch, so we will not try again.
2627	*/
2628	pPatch = &pVM->hm.s.aPatches[idx];
2629	pPatch->Core.Key = pCtx->eip;
2630	pPatch->enmType = HMTPRINSTR_INVALID;
2631	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2632	AssertRC(rc);
2633	pVM->hm.s.cPatches++;
2634	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2635	return VINF_SUCCESS;
2636	}
2637
2638
2639	/**
2640	* Attempt to patch TPR mmio instructions.
2641	*
2642	* @returns VBox status code.
2643	* @param pVM The cross context VM structure.
2644	* @param pVCpu The cross context virtual CPU structure.
2645	*/
2646	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2647	{
2648	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2649	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2650	(void *)(uintptr_t)pVCpu->idCpu);
2651	AssertRC(rc);
2652	return rc;
2653	}
2654
2655
2656	/**
2657	* Checks if we need to reschedule due to VMM device heap changes.
2658	*
2659	* @returns true if a reschedule is required, otherwise false.
2660	* @param pVM The cross context VM structure.
2661	* @param pCtx VM execution context.
2662	*/
2663	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2664	{
2665	/*
2666	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2667	* when the unrestricted guest execution feature is missing (VT-x only).
2668	*/
2669	if ( pVM->hm.s.vmx.fEnabled
2670	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2671	&& CPUMIsGuestInRealModeEx(pCtx)
2672	&& !PDMVmmDevHeapIsEnabled(pVM))
2673	return true;
2674
2675	return false;
2676	}
2677
2678
2679	/**
2680	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2681	* event settings changes.
2682	*
2683	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2684	* function is just updating the VM globals.
2685	*
2686	* @param pVM The VM cross context VM structure.
2687	* @thread EMT(0)
2688	*/
2689	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2690	{
2691	/* Interrupts. */
2692	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2693	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2694
2695	/* CPU Exceptions. */
2696	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2697	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2698	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2699	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2700
2701	/* Common VM exits. */
2702	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2703	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2704	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2705	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2706
2707	/* Vendor specific VM exits. */
2708	if (HMR3IsVmxEnabled(pVM->pUVM))
2709	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2710	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2711	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2712	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2713	else
2714	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2715	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2716	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2717	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2718
2719	/* Done. */
2720	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2721	}
2722
2723
2724	/**
2725	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2726	*
2727	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2728	* per CPU settings.
2729	*
2730	* @param pVM The VM cross context VM structure.
2731	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2732	*/
2733	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2734	{
2735	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2736	}
2737
2738
2739	/**
2740	* Checks if we are currently using hardware acceleration.
2741	*
2742	* @returns true if hardware acceleration is being used, otherwise false.
2743	* @param pVCpu The cross context virtual CPU structure.
2744	*/
2745	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2746	{
2747	return pVCpu->hm.s.fActive;
2748	}
2749
2750
2751	/**
2752	* External interface for querying whether hardware acceleration is enabled.
2753	*
2754	* @returns true if VT-x or AMD-V is being used, otherwise false.
2755	* @param pUVM The user mode VM handle.
2756	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2757	*/
2758	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2759	{
2760	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2761	PVM pVM = pUVM->pVM;
2762	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2763	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2764	}
2765
2766
2767	/**
2768	* External interface for querying whether VT-x is being used.
2769	*
2770	* @returns true if VT-x is being used, otherwise false.
2771	* @param pUVM The user mode VM handle.
2772	* @sa HMR3IsSvmEnabled, HMIsEnabled
2773	*/
2774	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2775	{
2776	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2777	PVM pVM = pUVM->pVM;
2778	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2779	return pVM->hm.s.vmx.fEnabled
2780	&& pVM->hm.s.vmx.fSupported
2781	&& pVM->fHMEnabled;
2782	}
2783
2784
2785	/**
2786	* External interface for querying whether AMD-V is being used.
2787	*
2788	* @returns true if VT-x is being used, otherwise false.
2789	* @param pUVM The user mode VM handle.
2790	* @sa HMR3IsVmxEnabled, HMIsEnabled
2791	*/
2792	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2793	{
2794	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2795	PVM pVM = pUVM->pVM;
2796	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2797	return pVM->hm.s.svm.fEnabled
2798	&& pVM->hm.s.svm.fSupported
2799	&& pVM->fHMEnabled;
2800	}
2801
2802
2803	/**
2804	* Checks if we are currently using nested paging.
2805	*
2806	* @returns true if nested paging is being used, otherwise false.
2807	* @param pUVM The user mode VM handle.
2808	*/
2809	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2810	{
2811	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2812	PVM pVM = pUVM->pVM;
2813	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2814	return pVM->hm.s.fNestedPagingCfg;
2815	}
2816
2817
2818	/**
2819	* Checks if virtualized APIC registers are enabled.
2820	*
2821	* When enabled this feature allows the hardware to access most of the
2822	* APIC registers in the virtual-APIC page without causing VM-exits. See
2823	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2824	*
2825	* @returns true if virtualized APIC registers is enabled, otherwise
2826	* false.
2827	* @param pUVM The user mode VM handle.
2828	*/
2829	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2830	{
2831	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2832	PVM pVM = pUVM->pVM;
2833	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2834	return pVM->hm.s.fVirtApicRegs;
2835	}
2836
2837
2838	/**
2839	* Checks if APIC posted-interrupt processing is enabled.
2840	*
2841	* This returns whether we can deliver interrupts to the guest without
2842	* leaving guest-context by updating APIC state from host-context.
2843	*
2844	* @returns true if APIC posted-interrupt processing is enabled,
2845	* otherwise false.
2846	* @param pUVM The user mode VM handle.
2847	*/
2848	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2849	{
2850	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2851	PVM pVM = pUVM->pVM;
2852	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2853	return pVM->hm.s.fPostedIntrs;
2854	}
2855
2856
2857	/**
2858	* Checks if we are currently using VPID in VT-x mode.
2859	*
2860	* @returns true if VPID is being used, otherwise false.
2861	* @param pUVM The user mode VM handle.
2862	*/
2863	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2864	{
2865	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2866	PVM pVM = pUVM->pVM;
2867	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2868	return pVM->hm.s.ForR3.vmx.fVpid;
2869	}
2870
2871
2872	/**
2873	* Checks if we are currently using VT-x unrestricted execution,
2874	* aka UX.
2875	*
2876	* @returns true if UX is being used, otherwise false.
2877	* @param pUVM The user mode VM handle.
2878	*/
2879	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2880	{
2881	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2882	PVM pVM = pUVM->pVM;
2883	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2884	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2885	\|\| pVM->hm.s.svm.fSupported;
2886	}
2887
2888
2889	/**
2890	* Checks if the VMX-preemption timer is being used.
2891	*
2892	* @returns true if the VMX-preemption timer is being used, otherwise false.
2893	* @param pVM The cross context VM structure.
2894	*/
2895	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2896	{
2897	return HMIsEnabled(pVM)
2898	&& pVM->hm.s.vmx.fEnabled
2899	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2900	}
2901
2902
2903	#ifdef TODO_9217_VMCSINFO
2904	/**
2905	* Helper for HMR3CheckError to log VMCS controls to the release log.
2906	*
2907	* @param idCpu The Virtual CPU ID.
2908	* @param pVmcsInfo The VMCS info. object.
2909	*/
2910	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2911	{
2912	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2913	{
2914	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2920	}
2921	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2922	{
2923	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2946	}
2947	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2948	{
2949	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2966	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2967	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2968	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2969	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2975	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2976	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2977	}
2978	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2979	{
2980	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2989	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2990	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2993	}
2994	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2995	{
2996	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2997	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2998	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2999	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3000	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3001	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3002	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3003	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3004	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3005	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3006	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3007	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3008	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3009	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
3010	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
3011	}
3012	}
3013	#endif
3014
3015
3016	/**
3017	* Check fatal VT-x/AMD-V error and produce some meaningful
3018	* log release message.
3019	*
3020	* @param pVM The cross context VM structure.
3021	* @param iStatusCode VBox status code.
3022	*/
3023	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3024	{
3025	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3026	{
3027	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3028	* might be getting inaccurate values for non-guru'ing EMTs. */
3029	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3030	#ifdef TODO_9217_VMCSINFO
3031	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3032	#endif
3033	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3034	switch (iStatusCode)
3035	{
3036	case VERR_VMX_INVALID_VMCS_PTR:
3037	{
3038	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3039	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3040	#ifdef TODO_9217_VMCSINFO
3041	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3042	pVmcsInfo->HCPhysVmcs));
3043	#endif
3044	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3045	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3046	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3047	break;
3048	}
3049
3050	case VERR_VMX_UNABLE_TO_START_VM:
3051	{
3052	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3053	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3054	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3055	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3056
3057	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3058	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3059	{
3060	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3061	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3062	}
3063	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3064	{
3065	#ifdef TODO_9217_VMCSINFO
3066	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3067	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3068	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3069	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3070	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3071	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3072	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3073	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3074	#endif
3075	}
3076	/** @todo Log VM-entry event injection control fields
3077	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3078	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3079	break;
3080	}
3081
3082	case VERR_VMX_INVALID_GUEST_STATE:
3083	{
3084	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3085	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3086	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3087	#ifdef TODO_9217_VMCSINFO
3088	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3089	#endif
3090	break;
3091	}
3092
3093	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3094	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3095	case VERR_VMX_INVALID_VMXON_PTR:
3096	case VERR_VMX_UNEXPECTED_EXIT:
3097	case VERR_VMX_INVALID_VMCS_FIELD:
3098	case VERR_SVM_UNKNOWN_EXIT:
3099	case VERR_SVM_UNEXPECTED_EXIT:
3100	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3101	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3102	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3103	break;
3104	}
3105	}
3106
3107	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3108	{
3109	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3110	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3111	}
3112	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3113	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3114	}
3115
3116
3117	/**
3118	* Execute state save operation.
3119	*
3120	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3121	* is because we always save the VM state from ring-3 and thus most HM state
3122	* will be re-synced dynamically at runtime and don't need to be part of the VM
3123	* saved state.
3124	*
3125	* @returns VBox status code.
3126	* @param pVM The cross context VM structure.
3127	* @param pSSM SSM operation handle.
3128	*/
3129	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3130	{
3131	Log(("hmR3Save:\n"));
3132
3133	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3134	{
3135	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3136	Assert(!pVCpu->hm.s.Event.fPending);
3137	if (pVM->cpum.ro.GuestFeatures.fSvm)
3138	{
3139	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3140	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3141	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3142	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3143	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3144	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3145	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3146	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3147	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3148	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3149	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3150	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3151	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3152	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3153	}
3154	}
3155
3156	/* Save the guest patch data. */
3157	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3158	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3159	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3160
3161	/* Store all the guest patch records too. */
3162	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3163	if (RT_FAILURE(rc))
3164	return rc;
3165
3166	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3167	{
3168	AssertCompileSize(HMTPRINSTR, 4);
3169	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3170	SSMR3PutU32(pSSM, pPatch->Core.Key);
3171	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3172	SSMR3PutU32(pSSM, pPatch->cbOp);
3173	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3174	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3175	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3176	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3177	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3178	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3179	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3180	if (RT_FAILURE(rc))
3181	return rc;
3182	}
3183
3184	return VINF_SUCCESS;
3185	}
3186
3187
3188	/**
3189	* Execute state load operation.
3190	*
3191	* @returns VBox status code.
3192	* @param pVM The cross context VM structure.
3193	* @param pSSM SSM operation handle.
3194	* @param uVersion Data layout version.
3195	* @param uPass The data pass.
3196	*/
3197	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3198	{
3199	int rc;
3200
3201	LogFlowFunc(("uVersion=%u\n", uVersion));
3202	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3203
3204	/*
3205	* Validate version.
3206	*/
3207	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3208	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3209	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3210	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3211	{
3212	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3213	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3214	}
3215
3216	/*
3217	* Load per-VCPU state.
3218	*/
3219	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3220	{
3221	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3222	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3223	{
3224	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3225	if (pVM->cpum.ro.GuestFeatures.fSvm)
3226	{
3227	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3228	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3229	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3230	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3231	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3232	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3233	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3234	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3235	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3236	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3237	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3238	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3239	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3240	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3241	AssertRCReturn(rc, rc);
3242	}
3243	}
3244	else
3245	{
3246	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3247	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3248	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3249	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3250
3251	/* VMX fWasInRealMode related data. */
3252	uint32_t uDummy;
3253	SSMR3GetU32(pSSM, &uDummy);
3254	SSMR3GetU32(pSSM, &uDummy);
3255	rc = SSMR3GetU32(pSSM, &uDummy);
3256	AssertRCReturn(rc, rc);
3257	}
3258	}
3259
3260	/*
3261	* Load TPR patching data.
3262	*/
3263	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3264	{
3265	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3266	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3267	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3268
3269	/* Fetch all TPR patch records. */
3270	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3271	AssertRCReturn(rc, rc);
3272	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3273	{
3274	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3275	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3276	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3277	SSMR3GetU32(pSSM, &pPatch->cbOp);
3278	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3279	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3280	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3281
3282	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3283	pVM->hm.s.fTprPatchingActive = true;
3284	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3285
3286	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3287	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3288	SSMR3GetU32(pSSM, &pPatch->cFaults);
3289	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3290	AssertRCReturn(rc, rc);
3291
3292	LogFlow(("hmR3Load: patch %d\n", i));
3293	LogFlow(("Key = %x\n", pPatch->Core.Key));
3294	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3295	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3296	LogFlow(("type = %d\n", pPatch->enmType));
3297	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3298	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3299	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3300	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3301
3302	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3303	AssertRCReturn(rc, rc);
3304	}
3305	}
3306
3307	return VINF_SUCCESS;
3308	}
3309
3310
3311	/**
3312	* Displays HM info.
3313	*
3314	* @param pVM The cross context VM structure.
3315	* @param pHlp The info helper functions.
3316	* @param pszArgs Arguments, ignored.
3317	*/
3318	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3319	{
3320	NOREF(pszArgs);
3321	PVMCPU pVCpu = VMMGetCpu(pVM);
3322	if (!pVCpu)
3323	pVCpu = pVM->apCpusR3[0];
3324
3325	if (HMIsEnabled(pVM))
3326	{
3327	if (pVM->hm.s.vmx.fSupported)
3328	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3329	else
3330	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3331	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3332	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3333	if (pVM->hm.s.vmx.fSupported)
3334	{
3335	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3336	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3337	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3338
3339	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3340	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3341	if (fRealOnV86Active)
3342	{
3343	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3344	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3345	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3346	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3347	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3348	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3349	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3350	}
3351	}
3352	}
3353	else
3354	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3355	}
3356
3357
3358	/**
3359	* Displays the HM Last-Branch-Record info. for the guest.
3360	*
3361	* @param pVM The cross context VM structure.
3362	* @param pHlp The info helper functions.
3363	* @param pszArgs Arguments, ignored.
3364	*/
3365	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3366	{
3367	NOREF(pszArgs);
3368	PVMCPU pVCpu = VMMGetCpu(pVM);
3369	if (!pVCpu)
3370	pVCpu = pVM->apCpusR3[0];
3371
3372	if (!HMIsEnabled(pVM))
3373	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3374	else if (HMIsVmxActive(pVM))
3375	{
3376	if (pVM->hm.s.vmx.fLbrCfg)
3377	{
3378	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3379	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3380
3381	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3382	* 0xf should cover everything we support thus far. Fix if necessary
3383	* later. */
3384	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3385	if (idxTopOfStack > cLbrStack)
3386	{
3387	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3388	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3389	return;
3390	}
3391
3392	/*
3393	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3394	*/
3395	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3396	uint32_t idxCurrent = idxTopOfStack;
3397	Assert(idxTopOfStack < cLbrStack);
3398	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3399	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3400	for (;;)
3401	{
3402	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3403	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3404	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3405	else
3406	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3407
3408	idxCurrent = (idxCurrent - 1) % cLbrStack;
3409	if (idxCurrent == idxTopOfStack)
3410	break;
3411	}
3412	}
3413	else
3414	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3415	}
3416	else
3417	{
3418	Assert(HMIsSvmActive(pVM));
3419	/** @todo SVM: LBRs (get them from VMCB if possible). */
3420	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3421	}
3422	}
3423
3424
3425	/**
3426	* Displays the HM pending event.
3427	*
3428	* @param pVM The cross context VM structure.
3429	* @param pHlp The info helper functions.
3430	* @param pszArgs Arguments, ignored.
3431	*/
3432	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3433	{
3434	NOREF(pszArgs);
3435	PVMCPU pVCpu = VMMGetCpu(pVM);
3436	if (!pVCpu)
3437	pVCpu = pVM->apCpusR3[0];
3438
3439	if (HMIsEnabled(pVM))
3440	{
3441	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3442	if (pVCpu->hm.s.Event.fPending)
3443	{
3444	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3445	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3446	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3447	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3448	}
3449	}
3450	else
3451	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3452	}
3453
3454
3455	/**
3456	* Displays the SVM nested-guest VMCB cache.
3457	*
3458	* @param pVM The cross context VM structure.
3459	* @param pHlp The info helper functions.
3460	* @param pszArgs Arguments, ignored.
3461	*/
3462	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3463	{
3464	NOREF(pszArgs);
3465	PVMCPU pVCpu = VMMGetCpu(pVM);
3466	if (!pVCpu)
3467	pVCpu = pVM->apCpusR3[0];
3468
3469	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3470	if ( fSvmEnabled
3471	&& pVM->cpum.ro.GuestFeatures.fSvm)
3472	{
3473	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3474	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3475	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3476	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3477	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3478	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3479	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3480	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3481	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3482	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3483	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3484	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3485	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3486	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3487	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3488	}
3489	else
3490	{
3491	if (!fSvmEnabled)
3492	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3493	else
3494	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3495	}
3496	}
3497

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 94961

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