HM.cpp@ 91281

Last change on this file since 91281 was 91270, checked in by vboxsync, 3 years ago
VMM/HM: Moved various stats from the hyper heap and into the VM structure. (fixed missing array subscript) bugref:10093
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 154.2 KB

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1	/* $Id: HM.cpp 91270 2021-09-16 07:36:06Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/pdmapi.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/gim.h>
48	#include <VBox/vmm/trpm.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/iom.h>
51	#include <VBox/vmm/iem.h>
52	#include <VBox/vmm/selm.h>
53	#include <VBox/vmm/nem.h>
54	#include <VBox/vmm/hm_vmx.h>
55	#include <VBox/vmm/hm_svm.h>
56	#include "HMInternal.h"
57	#include <VBox/vmm/vmcc.h>
58	#include <VBox/err.h>
59	#include <VBox/param.h>
60
61	#include <iprt/assert.h>
62	#include <VBox/log.h>
63	#include <iprt/asm.h>
64	#include <iprt/asm-amd64-x86.h>
65	#include <iprt/env.h>
66	#include <iprt/thread.h>
67
68
69	/*********************************************************************************************************************************
70	* Defined Constants And Macros *
71	*********************************************************************************************************************************/
72	/** @def HMVMX_REPORT_FEAT
73	* Reports VT-x feature to the release log.
74	*
75	* @param a_uAllowed1 Mask of allowed-1 feature bits.
76	* @param a_uAllowed0 Mask of allowed-0 feature bits.
77	* @param a_StrDesc The description string to report.
78	* @param a_Featflag Mask of the feature to report.
79	*/
80	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
81	do { \
82	if ((a_uAllowed1) & (a_Featflag)) \
83	{ \
84	if ((a_uAllowed0) & (a_Featflag)) \
85	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
86	else \
87	LogRel(("HM: " a_StrDesc "\n")); \
88	} \
89	else \
90	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
91	} while (0)
92
93	/** @def HMVMX_REPORT_ALLOWED_FEAT
94	* Reports an allowed VT-x feature to the release log.
95	*
96	* @param a_uAllowed1 Mask of allowed-1 feature bits.
97	* @param a_StrDesc The description string to report.
98	* @param a_FeatFlag Mask of the feature to report.
99	*/
100	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
101	do { \
102	if ((a_uAllowed1) & (a_FeatFlag)) \
103	LogRel(("HM: " a_StrDesc "\n")); \
104	else \
105	LogRel(("HM: " a_StrDesc " not supported\n")); \
106	} while (0)
107
108	/** @def HMVMX_REPORT_MSR_CAP
109	* Reports MSR feature capability.
110	*
111	* @param a_MsrCaps Mask of MSR feature bits.
112	* @param a_StrDesc The description string to report.
113	* @param a_fCap Mask of the feature to report.
114	*/
115	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
116	do { \
117	if ((a_MsrCaps) & (a_fCap)) \
118	LogRel(("HM: " a_StrDesc "\n")); \
119	} while (0)
120
121	/** @def HMVMX_LOGREL_FEAT
122	* Dumps a feature flag from a bitmap of features to the release log.
123	*
124	* @param a_fVal The value of all the features.
125	* @param a_fMask The specific bitmask of the feature.
126	*/
127	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
128	do { \
129	if ((a_fVal) & (a_fMask)) \
130	LogRel(("HM: %s\n", #a_fMask)); \
131	} while (0)
132
133
134	/*********************************************************************************************************************************
135	* Internal Functions *
136	*********************************************************************************************************************************/
137	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
138	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
139	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
140	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static int hmR3InitFinalizeR3(PVM pVM);
144	static int hmR3InitFinalizeR0(PVM pVM);
145	static int hmR3InitFinalizeR0Intel(PVM pVM);
146	static int hmR3InitFinalizeR0Amd(PVM pVM);
147	static int hmR3TermCPU(PVM pVM);
148
149
150	#ifdef VBOX_WITH_STATISTICS
151	/**
152	* Returns the name of the hardware exception.
153	*
154	* @returns The name of the hardware exception.
155	* @param uVector The exception vector.
156	*/
157	static const char *hmR3GetXcptName(uint8_t uVector)
158	{
159	switch (uVector)
160	{
161	case X86_XCPT_DE: return "#DE";
162	case X86_XCPT_DB: return "#DB";
163	case X86_XCPT_NMI: return "#NMI";
164	case X86_XCPT_BP: return "#BP";
165	case X86_XCPT_OF: return "#OF";
166	case X86_XCPT_BR: return "#BR";
167	case X86_XCPT_UD: return "#UD";
168	case X86_XCPT_NM: return "#NM";
169	case X86_XCPT_DF: return "#DF";
170	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
171	case X86_XCPT_TS: return "#TS";
172	case X86_XCPT_NP: return "#NP";
173	case X86_XCPT_SS: return "#SS";
174	case X86_XCPT_GP: return "#GP";
175	case X86_XCPT_PF: return "#PF";
176	case X86_XCPT_MF: return "#MF";
177	case X86_XCPT_AC: return "#AC";
178	case X86_XCPT_MC: return "#MC";
179	case X86_XCPT_XF: return "#XF";
180	case X86_XCPT_VE: return "#VE";
181	case X86_XCPT_CP: return "#CP";
182	case X86_XCPT_VC: return "#VC";
183	case X86_XCPT_SX: return "#SX";
184	}
185	return "Reserved";
186	}
187	#endif /* VBOX_WITH_STATISTICS */
188
189
190	/**
191	* Initializes the HM.
192	*
193	* This is the very first component to really do init after CFGM so that we can
194	* establish the predominant execution engine for the VM prior to initializing
195	* other modules. It takes care of NEM initialization if needed (HM disabled or
196	* not available in HW).
197	*
198	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
199	* hypervisor API via NEM, and then back on raw-mode if that isn't available
200	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
201	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
202	* X, OS/2 and others).
203	*
204	* Note that a lot of the set up work is done in ring-0 and thus postponed till
205	* the ring-3 and ring-0 callback to HMR3InitCompleted.
206	*
207	* @returns VBox status code.
208	* @param pVM The cross context VM structure.
209	*
210	* @remarks Be careful with what we call here, since most of the VMM components
211	* are uninitialized.
212	*/
213	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
214	{
215	LogFlowFunc(("\n"));
216
217	/*
218	* Assert alignment and sizes.
219	*/
220	AssertCompileMemberAlignment(VM, hm.s, 32);
221	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
222
223	/*
224	* Register the saved state data unit.
225	*/
226	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
227	NULL, NULL, NULL,
228	NULL, hmR3Save, NULL,
229	NULL, hmR3Load, NULL);
230	if (RT_FAILURE(rc))
231	return rc;
232
233	/*
234	* Register info handlers.
235	*/
236	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
237	AssertRCReturn(rc, rc);
238
239	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
240	DBGFINFO_FLAGS_ALL_EMTS);
241	AssertRCReturn(rc, rc);
242
243	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
244	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
245	AssertRCReturn(rc, rc);
246
247	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
248	AssertRCReturn(rc, rc);
249
250	/*
251	* Read configuration.
252	*/
253	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
254
255	/*
256	* Validate the HM settings.
257	*/
258	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
259	"HMForced" /* implied 'true' these days */
260	"\|UseNEMInstead"
261	"\|FallbackToNEM"
262	"\|EnableNestedPaging"
263	"\|EnableUX"
264	"\|EnableLargePages"
265	"\|EnableVPID"
266	"\|IBPBOnVMExit"
267	"\|IBPBOnVMEntry"
268	"\|SpecCtrlByHost"
269	"\|L1DFlushOnSched"
270	"\|L1DFlushOnVMEntry"
271	"\|MDSClearOnSched"
272	"\|MDSClearOnVMEntry"
273	"\|TPRPatchingEnabled"
274	"\|64bitEnabled"
275	"\|Exclusive"
276	"\|MaxResumeLoops"
277	"\|VmxPleGap"
278	"\|VmxPleWindow"
279	"\|VmxLbr"
280	"\|UseVmxPreemptTimer"
281	"\|SvmPauseFilter"
282	"\|SvmPauseFilterThreshold"
283	"\|SvmVirtVmsaveVmload"
284	"\|SvmVGif"
285	"\|LovelyMesaDrvWorkaround",
286	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
287	if (RT_FAILURE(rc))
288	return rc;
289
290	/** @cfgm{/HM/HMForced, bool, false}
291	* Forces hardware virtualization, no falling back on raw-mode. HM must be
292	* enabled, i.e. /HMEnabled must be true. */
293	bool fHMForced;
294	AssertRelease(pVM->fHMEnabled);
295	fHMForced = true;
296
297	/** @cfgm{/HM/UseNEMInstead, bool, true}
298	* Don't use HM, use NEM instead. */
299	bool fUseNEMInstead = false;
300	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
301	AssertRCReturn(rc, rc);
302	if (fUseNEMInstead && pVM->fHMEnabled)
303	{
304	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
305	pVM->fHMEnabled = false;
306	}
307
308	/** @cfgm{/HM/FallbackToNEM, bool, true}
309	* Enables fallback on NEM. */
310	bool fFallbackToNEM = true;
311	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
312	AssertRCReturn(rc, rc);
313
314	/** @cfgm{/HM/EnableNestedPaging, bool, false}
315	* Enables nested paging (aka extended page tables). */
316	bool fAllowNestedPaging = false;
317	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
318	AssertRCReturn(rc, rc);
319
320	/** @cfgm{/HM/EnableUX, bool, true}
321	* Enables the VT-x unrestricted execution feature. */
322	bool fAllowUnrestricted = true;
323	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
324	AssertRCReturn(rc, rc);
325
326	/** @cfgm{/HM/EnableLargePages, bool, false}
327	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
328	* page table walking and maybe better TLB hit rate in some cases. */
329	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
330	AssertRCReturn(rc, rc);
331
332	/** @cfgm{/HM/EnableVPID, bool, false}
333	* Enables the VT-x VPID feature. */
334	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
335	AssertRCReturn(rc, rc);
336
337	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
338	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
339	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
340	AssertRCReturn(rc, rc);
341
342	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
343	* Enables AMD64 cpu features.
344	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
345	* already have the support. */
346	#ifdef VBOX_WITH_64_BITS_GUESTS
347	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
348	AssertLogRelRCReturn(rc, rc);
349	#else
350	pVM->hm.s.fAllow64BitGuestsCfg = false;
351	#endif
352
353	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
354	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
355	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
356	* latest PAUSE instruction to be start of a new PAUSE loop.
357	*/
358	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
359	AssertRCReturn(rc, rc);
360
361	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
362	* The pause-filter exiting window in TSC ticks. When the number of ticks
363	* between the current PAUSE instruction and first PAUSE of a loop exceeds
364	* VmxPleWindow, a VM-exit is triggered.
365	*
366	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
367	*/
368	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
369	AssertRCReturn(rc, rc);
370
371	/** @cfgm{/HM/VmxLbr, bool, false}
372	* Whether to enable LBR for the guest. This is disabled by default as it's only
373	* useful while debugging and enabling it causes a noticeable performance hit. */
374	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
375	AssertRCReturn(rc, rc);
376
377	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
378	* A counter that is decrement each time a PAUSE instruction is executed by the
379	* guest. When the counter is 0, a \#VMEXIT is triggered.
380	*
381	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
382	*/
383	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
384	AssertRCReturn(rc, rc);
385
386	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
387	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
388	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
389	* PauseFilter count is reset to its initial value. However, if PAUSE is
390	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
391	* be triggered.
392	*
393	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
394	* activated.
395	*/
396	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
397	AssertRCReturn(rc, rc);
398
399	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
400	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
401	* available. */
402	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
403	AssertRCReturn(rc, rc);
404
405	/** @cfgm{/HM/SvmVGif, bool, true}
406	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
407	* if it's available. */
408	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
409	AssertRCReturn(rc, rc);
410
411	/** @cfgm{/HM/SvmLbrVirt, bool, false}
412	* Whether to make use of the LBR virtualization feature of the CPU if it's
413	* available. This is disabled by default as it's only useful while debugging
414	* and enabling it causes a small hit to performance. */
415	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
416	AssertRCReturn(rc, rc);
417
418	/** @cfgm{/HM/Exclusive, bool}
419	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
420	* global init for each host CPU. If false, we do local init each time we wish
421	* to execute guest code.
422	*
423	* On Windows, default is false due to the higher risk of conflicts with other
424	* hypervisors.
425	*
426	* On Mac OS X, this setting is ignored since the code does not handle local
427	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
428	*/
429	#if defined(RT_OS_DARWIN)
430	pVM->hm.s.fGlobalInit = true;
431	#else
432	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
433	# if defined(RT_OS_WINDOWS)
434	false
435	# else
436	true
437	# endif
438	);
439	AssertLogRelRCReturn(rc, rc);
440	#endif
441
442	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
443	* The number of times to resume guest execution before we forcibly return to
444	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445	* determines the default value. */
446	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
447	AssertLogRelRCReturn(rc, rc);
448
449	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
450	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
451	* available. */
452	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
453	AssertLogRelRCReturn(rc, rc);
454
455	/** @cfgm{/HM/IBPBOnVMExit, bool}
456	* Costly paranoia setting. */
457	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
458	AssertLogRelRCReturn(rc, rc);
459
460	/** @cfgm{/HM/IBPBOnVMEntry, bool}
461	* Costly paranoia setting. */
462	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
463	AssertLogRelRCReturn(rc, rc);
464
465	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
466	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
467	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
468	AssertLogRelRCReturn(rc, rc);
469
470	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
471	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
472	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
473	AssertLogRelRCReturn(rc, rc);
474
475	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
476	if (pVM->hm.s.fL1dFlushOnVmEntry)
477	pVM->hm.s.fL1dFlushOnSched = false;
478
479	/** @cfgm{/HM/SpecCtrlByHost, bool}
480	* Another expensive paranoia setting. */
481	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
482	AssertLogRelRCReturn(rc, rc);
483
484	/** @cfgm{/HM/MDSClearOnSched, bool, true}
485	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
486	* ignored on CPUs that aren't affected. */
487	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
488	AssertLogRelRCReturn(rc, rc);
489
490	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
491	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
492	* ignored on CPUs that aren't affected. */
493	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
494	AssertLogRelRCReturn(rc, rc);
495
496	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
497	if (pVM->hm.s.fMdsClearOnVmEntry)
498	pVM->hm.s.fMdsClearOnSched = false;
499
500	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
501	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
502	* the hypervisor it is running under. */
503	bool f;
504	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
505	AssertLogRelRCReturn(rc, rc);
506	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
507	{
508	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
509	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = f;
510	}
511
512	/*
513	* Check if VT-x or AMD-v support according to the users wishes.
514	*/
515	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
516	* VERR_SVM_IN_USE. */
517	if (pVM->fHMEnabled)
518	{
519	uint32_t fCaps;
520	rc = SUPR3QueryVTCaps(&fCaps);
521	if (RT_SUCCESS(rc))
522	{
523	if (fCaps & SUPVTCAPS_AMD_V)
524	{
525	pVM->hm.s.svm.fSupported = true;
526	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
527	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
528	}
529	else if (fCaps & SUPVTCAPS_VT_X)
530	{
531	const char *pszWhy;
532	rc = SUPR3QueryVTxSupported(&pszWhy);
533	if (RT_SUCCESS(rc))
534	{
535	pVM->hm.s.vmx.fSupported = true;
536	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
537	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
538	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
539	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
540	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
541	}
542	else
543	{
544	/*
545	* Before failing, try fallback to NEM if we're allowed to do that.
546	*/
547	pVM->fHMEnabled = false;
548	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
549	if (fFallbackToNEM)
550	{
551	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
552	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
553
554	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
555	if ( RT_SUCCESS(rc2)
556	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
557	rc = VINF_SUCCESS;
558	}
559	if (RT_FAILURE(rc))
560	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
561	}
562	}
563	else
564	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
565	VERR_INTERNAL_ERROR_5);
566
567	/*
568	* Disable nested paging and unrestricted guest execution now if they're
569	* configured so that CPUM can make decisions based on our configuration.
570	*/
571	if ( fAllowNestedPaging
572	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
573	{
574	pVM->hm.s.fNestedPagingCfg = true;
575	if (fCaps & SUPVTCAPS_VT_X)
576	{
577	if ( fAllowUnrestricted
578	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
579	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
580	else
581	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
582	}
583	}
584	else
585	Assert(!pVM->hm.s.fNestedPagingCfg);
586	}
587	else
588	{
589	const char *pszMsg;
590	switch (rc)
591	{
592	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
593	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
594	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
595	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
596	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
597	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
598	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
599	default:
600	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
601	}
602
603	/*
604	* Before failing, try fallback to NEM if we're allowed to do that.
605	*/
606	pVM->fHMEnabled = false;
607	if (fFallbackToNEM)
608	{
609	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
610	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
611	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
612	if ( RT_SUCCESS(rc2)
613	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
614	rc = VINF_SUCCESS;
615	}
616	if (RT_FAILURE(rc))
617	return VM_SET_ERROR(pVM, rc, pszMsg);
618	}
619	}
620	else
621	{
622	/*
623	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
624	*/
625	if (fUseNEMInstead)
626	{
627	rc = NEMR3Init(pVM, false /fFallback/, true);
628	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
629	if (RT_FAILURE(rc))
630	return rc;
631	}
632	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
633	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
634	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
635	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
636	}
637
638	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
639	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
640	return VINF_SUCCESS;
641	}
642
643
644	/**
645	* Initializes HM components after ring-3 phase has been fully initialized.
646	*
647	* @returns VBox status code.
648	* @param pVM The cross context VM structure.
649	*/
650	static int hmR3InitFinalizeR3(PVM pVM)
651	{
652	LogFlowFunc(("\n"));
653
654	if (!HMIsEnabled(pVM))
655	return VINF_SUCCESS;
656
657	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
658	{
659	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
660	pVCpu->hm.s.fActive = false;
661	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
662	}
663
664	/*
665	* Check if L1D flush is needed/possible.
666	*/
667	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
668	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
669	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
670	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
671	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
672	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
673
674	/*
675	* Check if MDS flush is needed/possible.
676	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
677	*/
678	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
679	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
680	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
681	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
682	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
683	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
684	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
685	{
686	if (!pVM->hm.s.fMdsClearOnSched)
687	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
688	pVM->hm.s.fMdsClearOnVmEntry = false;
689	}
690	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
691	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
692	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
693
694	/*
695	* Statistics.
696	*/
697	#ifdef VBOX_WITH_STATISTICS
698	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
699	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
700	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
701	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
702	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
703	#endif
704
705	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
706	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
707	{
708	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
709	PHMCPU pHmCpu = &pVCpu->hm.s;
710	int rc;
711
712	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
713	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
714	AssertRC(rc); \
715	} while (0)
716	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
717	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
718
719	#ifdef VBOX_WITH_STATISTICS
720
721	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
722	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
723	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
724	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
725	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
726	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
727	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
728	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
729	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
730	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
731	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
732	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
733	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
734	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
735	# ifdef HM_PROFILE_EXIT_DISPATCH
736	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
737	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
738	# endif
739	#endif
740	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
741
742	#ifdef VBOX_WITH_STATISTICS
743	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
744	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
745	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
746	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
747	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
748	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
749	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
750	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
751	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
752	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
753	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
754	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
755	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
756	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
757	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
758	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
759	#endif
760	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
761	if (fCpuSupportsVmx)
762	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
763	#ifdef VBOX_WITH_STATISTICS
764	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
765	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
766	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
767	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
768	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
769	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
770	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
771	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
772	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
773	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
774	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
775	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
776	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
777	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
778	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
779	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
780	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
781	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
782	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
783	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
784	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
785	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
786	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
787	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
788	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
789	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
790	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
791	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
792	#endif
793	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
794	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
795	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
796	#ifdef VBOX_WITH_STATISTICS
797	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
798	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
799	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
800
801	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
802	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
803	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
804	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
805	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
806	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
807	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
808	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
809	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
810	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
811	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
812	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
813	#endif
814	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
815	#ifdef VBOX_WITH_STATISTICS
816	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
817
818	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
819	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
820	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
821	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
822	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
823	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
824
825	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
826	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
827	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
828	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
829	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
830	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
831	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
832	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
833	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
834	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
835	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
836	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
837	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
838	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
839	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
840
841	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
842	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
843	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
844
845	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
846	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
847	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
848
849	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
850	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
851	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
852	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
853
854	if (fCpuSupportsVmx)
855	{
856	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
857	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
858	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
859	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
860	}
861
862	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
863	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
864	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
865
866	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
867	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
868	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
869
870	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
871	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
872	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
873	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
874	#endif
875	if (fCpuSupportsVmx)
876	{
877	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
878	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
879	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
880	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
881	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
882	}
883	#ifdef VBOX_WITH_STATISTICS
884	/*
885	* Guest Exit reason stats.
886	*/
887	if (fCpuSupportsVmx)
888	{
889	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
890	{
891	const char *pszExitName = HMGetVmxExitName(j);
892	if (pszExitName)
893	{
894	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
895	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
896	AssertRCReturn(rc, rc);
897	}
898	}
899	}
900	else
901	{
902	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
903	{
904	const char *pszExitName = HMGetSvmExitName(j);
905	if (pszExitName)
906	{
907	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
908	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
909	AssertRC(rc);
910	}
911	}
912	}
913	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
914
915	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
916	/*
917	* Nested-guest VM-exit reason stats.
918	*/
919	if (fCpuSupportsVmx)
920	{
921	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
922	{
923	const char *pszExitName = HMGetVmxExitName(j);
924	if (pszExitName)
925	{
926	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
927	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
928	AssertRC(rc);
929	}
930	}
931	}
932	else
933	{
934	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
935	{
936	const char *pszExitName = HMGetSvmExitName(j);
937	if (pszExitName)
938	{
939	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
940	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
941	AssertRC(rc);
942	}
943	}
944	}
945	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
946	#endif
947
948	/*
949	* Injected interrupts stats.
950	*/
951	char szDesc[64];
952	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
953	{
954	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
955	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
956	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
957	AssertRC(rc);
958	}
959
960	/*
961	* Injected exception stats.
962	*/
963	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
964	{
965	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
966	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
967	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
968	AssertRC(rc);
969	}
970
971	#endif /* VBOX_WITH_STATISTICS */
972	#undef HM_REG_COUNTER
973	#undef HM_REG_PROFILE
974	#undef HM_REG_STAT
975	}
976
977	return VINF_SUCCESS;
978	}
979
980
981	/**
982	* Called when a init phase has completed.
983	*
984	* @returns VBox status code.
985	* @param pVM The cross context VM structure.
986	* @param enmWhat The phase that completed.
987	*/
988	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
989	{
990	switch (enmWhat)
991	{
992	case VMINITCOMPLETED_RING3:
993	return hmR3InitFinalizeR3(pVM);
994	case VMINITCOMPLETED_RING0:
995	return hmR3InitFinalizeR0(pVM);
996	default:
997	return VINF_SUCCESS;
998	}
999	}
1000
1001
1002	/**
1003	* Turns off normal raw mode features.
1004	*
1005	* @param pVM The cross context VM structure.
1006	*/
1007	static void hmR3DisableRawMode(PVM pVM)
1008	{
1009	/** @todo r=bird: HM shouldn't be doing this crap. */
1010	/* Reinit the paging mode to force the new shadow mode. */
1011	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1012	{
1013	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1014	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1015	}
1016	}
1017
1018
1019	/**
1020	* Initialize VT-x or AMD-V.
1021	*
1022	* @returns VBox status code.
1023	* @param pVM The cross context VM structure.
1024	*/
1025	static int hmR3InitFinalizeR0(PVM pVM)
1026	{
1027	int rc;
1028
1029	if (!HMIsEnabled(pVM))
1030	return VINF_SUCCESS;
1031
1032	/*
1033	* Hack to allow users to work around broken BIOSes that incorrectly set
1034	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1035	*/
1036	if ( !pVM->hm.s.vmx.fSupported
1037	&& !pVM->hm.s.svm.fSupported
1038	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1039	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1040	{
1041	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1042	pVM->hm.s.svm.fSupported = true;
1043	pVM->hm.s.svm.fIgnoreInUseError = true;
1044	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1045	}
1046
1047	/*
1048	* Report ring-0 init errors.
1049	*/
1050	if ( !pVM->hm.s.vmx.fSupported
1051	&& !pVM->hm.s.svm.fSupported)
1052	{
1053	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1054	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl));
1055	switch (pVM->hm.s.ForR3.rcInit)
1056	{
1057	case VERR_VMX_IN_VMX_ROOT_MODE:
1058	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1059	case VERR_VMX_NO_VMX:
1060	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1061	case VERR_VMX_MSR_VMX_DISABLED:
1062	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1063	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1064	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1065	case VERR_VMX_MSR_LOCKING_FAILED:
1066	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1067	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1068	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1069	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1070	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1071
1072	case VERR_SVM_IN_USE:
1073	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1074	case VERR_SVM_NO_SVM:
1075	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1076	case VERR_SVM_DISABLED:
1077	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1078	}
1079	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1080	}
1081
1082	/*
1083	* Enable VT-x or AMD-V on all host CPUs.
1084	*/
1085	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1086	if (RT_FAILURE(rc))
1087	{
1088	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1089	HMR3CheckError(pVM, rc);
1090	return rc;
1091	}
1092
1093	/*
1094	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1095	* (Main should have taken care of this already)
1096	*/
1097	if (!PDMHasIoApic(pVM))
1098	{
1099	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1100	pVM->hm.s.fTprPatchingAllowed = false;
1101	}
1102
1103	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1104	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1105	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1106
1107	/*
1108	* Do the vendor specific initialization
1109	*
1110	* Note! We disable release log buffering here since we're doing relatively
1111	* lot of logging and doesn't want to hit the disk with each LogRel
1112	* statement.
1113	*/
1114	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1115	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1116	if (pVM->hm.s.vmx.fSupported)
1117	rc = hmR3InitFinalizeR0Intel(pVM);
1118	else
1119	rc = hmR3InitFinalizeR0Amd(pVM);
1120	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1121	: "HM: VT-x/AMD-V init method: Local\n"));
1122	RTLogRelSetBuffering(fOldBuffered);
1123	pVM->hm.s.fInitialized = true;
1124
1125	return rc;
1126	}
1127
1128
1129	/**
1130	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1131	*/
1132	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1133	{
1134	NOREF(pVM);
1135	NOREF(pvAllocation);
1136	NOREF(GCPhysAllocation);
1137	}
1138
1139
1140	/**
1141	* Returns a description of the VMCS (and associated regions') memory type given the
1142	* IA32_VMX_BASIC MSR.
1143	*
1144	* @returns The descriptive memory type.
1145	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1146	*/
1147	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1148	{
1149	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1150	switch (uMemType)
1151	{
1152	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1153	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1154	}
1155	return "Unknown";
1156	}
1157
1158
1159	/**
1160	* Returns a single-line description of all the activity-states supported by the CPU
1161	* given the IA32_VMX_MISC MSR.
1162	*
1163	* @returns All supported activity states.
1164	* @param uMsrMisc IA32_VMX_MISC MSR value.
1165	*/
1166	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1167	{
1168	static const char * const s_apszActStates[] =
1169	{
1170	"",
1171	" ( HLT )",
1172	" ( SHUTDOWN )",
1173	" ( HLT SHUTDOWN )",
1174	" ( SIPI_WAIT )",
1175	" ( HLT SIPI_WAIT )",
1176	" ( SHUTDOWN SIPI_WAIT )",
1177	" ( HLT SHUTDOWN SIPI_WAIT )"
1178	};
1179	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1180	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1181	return s_apszActStates[idxActStates];
1182	}
1183
1184
1185	/**
1186	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1187	*
1188	* @param fFeatMsr The feature control MSR value.
1189	*/
1190	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1191	{
1192	uint64_t const val = fFeatMsr;
1193	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1194	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1195	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1196	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1197	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1198	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1199	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1200	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1201	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1202	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1203	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1204	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1205	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1206	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1207	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1208	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1209	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1210	}
1211
1212
1213	/**
1214	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1215	*
1216	* @param uBasicMsr The VMX basic MSR value.
1217	*/
1218	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1219	{
1220	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1221	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1222	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1223	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1224	"< 4 GB" : "None"));
1225	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1226	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1227	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1228	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1229	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1230	}
1231
1232
1233	/**
1234	* Reports MSR_IA32_PINBASED_CTLS to the log.
1235	*
1236	* @param pVmxMsr Pointer to the VMX MSR.
1237	*/
1238	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1239	{
1240	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1241	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1242	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1243	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1244	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1245	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1246	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1247	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1248	}
1249
1250
1251	/**
1252	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1253	*
1254	* @param pVmxMsr Pointer to the VMX MSR.
1255	*/
1256	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1257	{
1258	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1259	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1260	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1261	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1262	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1263	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1264	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1265	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1266	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1267	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1268	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1269	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1270	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1271	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1272	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1273	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1274	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1275	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1276	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1277	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1278	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1279	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1280	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1281	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1282	}
1283
1284
1285	/**
1286	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1287	*
1288	* @param pVmxMsr Pointer to the VMX MSR.
1289	*/
1290	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1291	{
1292	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1293	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1294	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1295	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1296	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1297	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1298	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1299	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1300	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1301	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1302	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1303	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1314	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1315	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1316	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1317	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1318	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1319	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1320	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1321	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1322	}
1323
1324
1325	/**
1326	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1327	*
1328	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1329	*/
1330	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1331	{
1332	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1333	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1334	}
1335
1336
1337	/**
1338	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1339	*
1340	* @param pVmxMsr Pointer to the VMX MSR.
1341	*/
1342	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1343	{
1344	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1345	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1346	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1351	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1352	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1353	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1354	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1355	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1356	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1357	}
1358
1359
1360	/**
1361	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1362	*
1363	* @param pVmxMsr Pointer to the VMX MSR.
1364	*/
1365	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1366	{
1367	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1368	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1369	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1382	}
1383
1384
1385	/**
1386	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1387	*
1388	* @param fCaps The VMX EPT/VPID capability MSR value.
1389	*/
1390	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1391	{
1392	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1393	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1394	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1395	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1396	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1397	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1398	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1399	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1400	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1401	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1402	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT);
1403	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1404	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1405	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1406	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1407	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1408	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1409	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1410	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1411	}
1412
1413
1414	/**
1415	* Reports MSR_IA32_VMX_MISC MSR to the log.
1416	*
1417	* @param pVM Pointer to the VM.
1418	* @param fMisc The VMX misc. MSR value.
1419	*/
1420	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1421	{
1422	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1423	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1424	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1425	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1426	else
1427	{
1428	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1429	pVM->hm.s.vmx.cPreemptTimerShift));
1430	}
1431	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1432	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1433	hmR3VmxGetActivityStateAllDesc(fMisc)));
1434	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1435	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1436	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1437	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1438	VMX_MISC_MAX_MSRS(fMisc)));
1439	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1440	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1441	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1442	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1443	}
1444
1445
1446	/**
1447	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1448	*
1449	* @param uVmcsEnum The VMX VMCS enum MSR value.
1450	*/
1451	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1452	{
1453	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1454	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1455	}
1456
1457
1458	/**
1459	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1460	*
1461	* @param uVmFunc The VMX VMFUNC MSR value.
1462	*/
1463	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1464	{
1465	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1466	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1467	}
1468
1469
1470	/**
1471	* Reports VMX CR0, CR4 fixed MSRs.
1472	*
1473	* @param pMsrs Pointer to the VMX MSRs.
1474	*/
1475	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1476	{
1477	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1478	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1479	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1480	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1481	}
1482
1483
1484	/**
1485	* Finish VT-x initialization (after ring-0 init).
1486	*
1487	* @returns VBox status code.
1488	* @param pVM The cross context VM structure.
1489	*/
1490	static int hmR3InitFinalizeR0Intel(PVM pVM)
1491	{
1492	int rc;
1493
1494	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1495	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1496
1497	LogRel(("HM: Using VT-x implementation 3.0\n"));
1498	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1499	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1500	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1501	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1502
1503	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl);
1504	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1505
1506	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1507	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1508	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1509	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1510	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1511	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1512
1513	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1514	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1515
1516	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1517	{
1518	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1519	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1520	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1521	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1522	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1523	}
1524
1525	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1526	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1527	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1528	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1529	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1530	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1531	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1532
1533	#ifdef TODO_9217_VMCSINFO
1534	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1535	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1536	{
1537	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1538	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1539	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1540	}
1541	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1542	if (pVM->cpum.ro.GuestFeatures.fVmx)
1543	{
1544	LogRel(("HM: Nested-guest:\n"));
1545	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1546	{
1547	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1548	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1549	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1550	}
1551	}
1552	#endif
1553	#endif /* TODO_9217_VMCSINFO */
1554
1555	/*
1556	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1557	*/
1558	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1559	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1560	VERR_HM_IPE_1);
1561	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1562	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1563	&& pVM->hm.s.fNestedPagingCfg),
1564	VERR_HM_IPE_1);
1565
1566	/*
1567	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1568	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1569	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1570	*/
1571	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1572	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1573	{
1574	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1575	LogRel(("HM: Disabled RDTSCP\n"));
1576	}
1577
1578	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1579	{
1580	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1581	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1582	if (RT_SUCCESS(rc))
1583	{
1584	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1585	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1586	esp. Figure 20-5.*/
1587	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1588	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1589
1590	/* Bit set to 0 means software interrupts are redirected to the
1591	8086 program interrupt handler rather than switching to
1592	protected-mode handler. */
1593	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1594
1595	/* Allow all port IO, so that port IO instructions do not cause
1596	exceptions and would instead cause a VM-exit (based on VT-x's
1597	IO bitmap which we currently configure to always cause an exit). */
1598	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1599	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1600
1601	/*
1602	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1603	* page table used in real and protected mode without paging with EPT.
1604	*/
1605	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1606	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1607	{
1608	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1609	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1610	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1611	\| X86_PDE4M_G;
1612	}
1613
1614	/* We convert it here every time as PCI regions could be reconfigured. */
1615	if (PDMVmmDevHeapIsEnabled(pVM))
1616	{
1617	RTGCPHYS GCPhys;
1618	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1619	AssertRCReturn(rc, rc);
1620	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1621
1622	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1623	AssertRCReturn(rc, rc);
1624	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1625	}
1626	}
1627	else
1628	{
1629	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1630	pVM->hm.s.vmx.pRealModeTSS = NULL;
1631	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1632	return VMSetError(pVM, rc, RT_SRC_POS,
1633	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1634	}
1635	}
1636
1637	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1638	: "HM: Guest support: 32-bit only\n"));
1639
1640	/*
1641	* Call ring-0 to set up the VM.
1642	*/
1643	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1644	if (rc != VINF_SUCCESS)
1645	{
1646	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1647	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1648	{
1649	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1650	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1651	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1652	}
1653	HMR3CheckError(pVM, rc);
1654	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1655	}
1656
1657	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1658	LogRel(("HM: Enabled VMX\n"));
1659	pVM->hm.s.vmx.fEnabled = true;
1660
1661	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1662
1663	/*
1664	* Change the CPU features.
1665	*/
1666	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1667	if (pVM->hm.s.fAllow64BitGuestsCfg)
1668	{
1669	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1670	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1671	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1672	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1673	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1674	}
1675	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1676	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1677	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1678
1679	/*
1680	* Log configuration details.
1681	*/
1682	if (pVM->hm.s.fNestedPagingCfg)
1683	{
1684	LogRel(("HM: Enabled nested paging\n"));
1685	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1686	LogRel(("HM: EPT flush type = Single context\n"));
1687	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1688	LogRel(("HM: EPT flush type = All contexts\n"));
1689	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1690	LogRel(("HM: EPT flush type = Not supported\n"));
1691	else
1692	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1693
1694	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1695	LogRel(("HM: Enabled unrestricted guest execution\n"));
1696
1697	if (pVM->hm.s.fLargePages)
1698	{
1699	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1700	PGMSetLargePageUsage(pVM, true);
1701	LogRel(("HM: Enabled large page support\n"));
1702	}
1703	}
1704	else
1705	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1706
1707	if (pVM->hm.s.ForR3.vmx.fVpid)
1708	{
1709	LogRel(("HM: Enabled VPID\n"));
1710	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1711	LogRel(("HM: VPID flush type = Individual addresses\n"));
1712	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1713	LogRel(("HM: VPID flush type = Single context\n"));
1714	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1715	LogRel(("HM: VPID flush type = All contexts\n"));
1716	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1717	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1718	else
1719	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1720	}
1721	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1722	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1723
1724	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1725	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1726	else
1727	LogRel(("HM: Disabled VMX-preemption timer\n"));
1728
1729	if (pVM->hm.s.fVirtApicRegs)
1730	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1731
1732	if (pVM->hm.s.fPostedIntrs)
1733	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1734
1735	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1736	{
1737	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1738	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1739	}
1740
1741	return VINF_SUCCESS;
1742	}
1743
1744
1745	/**
1746	* Finish AMD-V initialization (after ring-0 init).
1747	*
1748	* @returns VBox status code.
1749	* @param pVM The cross context VM structure.
1750	*/
1751	static int hmR3InitFinalizeR0Amd(PVM pVM)
1752	{
1753	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1754
1755	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1756
1757	uint32_t u32Family;
1758	uint32_t u32Model;
1759	uint32_t u32Stepping;
1760	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1761	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1762	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1763	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1764	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1765	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1766	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1767
1768	/*
1769	* Enumerate AMD-V features.
1770	*/
1771	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1772	{
1773	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1774	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1775	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1776	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1777	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1778	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1779	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1780	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1781	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1782	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1783	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1784	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1785	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1786	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1787	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1788	#undef HMSVM_REPORT_FEATURE
1789	};
1790
1791	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1792	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1793	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1794	{
1795	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1796	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1797	}
1798	if (fSvmFeatures)
1799	for (unsigned iBit = 0; iBit < 32; iBit++)
1800	if (RT_BIT_32(iBit) & fSvmFeatures)
1801	LogRel(("HM: Reserved bit %u\n", iBit));
1802
1803	/*
1804	* Nested paging is determined in HMR3Init, verify the sanity of that.
1805	*/
1806	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1807	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1808	VERR_HM_IPE_1);
1809
1810	#if 0
1811	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1812	* here. */
1813	if (RTR0IsPostIpiSupport())
1814	pVM->hm.s.fPostedIntrs = true;
1815	#endif
1816
1817	/*
1818	* Determine whether we need to intercept #UD in SVM mode for emulating
1819	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1820	* when executed in long-mode. This is only really applicable when
1821	* non-default CPU profiles are in effect, i.e. guest vendor differs
1822	* from the host one.
1823	*/
1824	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1825	switch (CPUMGetGuestCpuVendor(pVM))
1826	{
1827	case CPUMCPUVENDOR_INTEL:
1828	case CPUMCPUVENDOR_VIA: /?/
1829	case CPUMCPUVENDOR_SHANGHAI: /?/
1830	switch (CPUMGetHostCpuVendor(pVM))
1831	{
1832	case CPUMCPUVENDOR_AMD:
1833	case CPUMCPUVENDOR_HYGON:
1834	if (pVM->hm.s.fAllow64BitGuestsCfg)
1835	{
1836	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1837	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1838	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1839	}
1840	break;
1841	default: break;
1842	}
1843	default: break;
1844	}
1845
1846	/*
1847	* Call ring-0 to set up the VM.
1848	*/
1849	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1850	if (rc != VINF_SUCCESS)
1851	{
1852	AssertMsgFailed(("%Rrc\n", rc));
1853	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1854	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1855	}
1856
1857	LogRel(("HM: Enabled SVM\n"));
1858	pVM->hm.s.svm.fEnabled = true;
1859
1860	if (pVM->hm.s.fNestedPagingCfg)
1861	{
1862	LogRel(("HM: Enabled nested paging\n"));
1863
1864	/*
1865	* Enable large pages (2 MB) if applicable.
1866	*/
1867	if (pVM->hm.s.fLargePages)
1868	{
1869	PGMSetLargePageUsage(pVM, true);
1870	LogRel(("HM: Enabled large page support\n"));
1871	}
1872	}
1873
1874	if (pVM->hm.s.fVirtApicRegs)
1875	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1876
1877	if (pVM->hm.s.fPostedIntrs)
1878	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1879
1880	hmR3DisableRawMode(pVM);
1881
1882	/*
1883	* Change the CPU features.
1884	*/
1885	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1886	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1887	if (pVM->hm.s.fAllow64BitGuestsCfg)
1888	{
1889	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1890	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1891	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1892	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1893	}
1894	/* Turn on NXE if PAE has been enabled. */
1895	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1896	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1897
1898	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1899	: "HM: Disabled TPR patching\n"));
1900
1901	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1902	: "HM: Guest support: 32-bit only\n"));
1903	return VINF_SUCCESS;
1904	}
1905
1906
1907	/**
1908	* Applies relocations to data and code managed by this
1909	* component. This function will be called at init and
1910	* whenever the VMM need to relocate it self inside the GC.
1911	*
1912	* @param pVM The cross context VM structure.
1913	*/
1914	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1915	{
1916	/* Fetch the current paging mode during the relocate callback during state loading. */
1917	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1918	{
1919	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1920	{
1921	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1922	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1923	}
1924	}
1925	}
1926
1927
1928	/**
1929	* Terminates the HM.
1930	*
1931	* Termination means cleaning up and freeing all resources,
1932	* the VM itself is, at this point, powered off or suspended.
1933	*
1934	* @returns VBox status code.
1935	* @param pVM The cross context VM structure.
1936	*/
1937	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1938	{
1939	if (pVM->hm.s.vmx.pRealModeTSS)
1940	{
1941	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1942	pVM->hm.s.vmx.pRealModeTSS = 0;
1943	}
1944	hmR3TermCPU(pVM);
1945	return 0;
1946	}
1947
1948
1949	/**
1950	* Terminates the per-VCPU HM.
1951	*
1952	* @returns VBox status code.
1953	* @param pVM The cross context VM structure.
1954	*/
1955	static int hmR3TermCPU(PVM pVM)
1956	{
1957	RT_NOREF(pVM);
1958	return VINF_SUCCESS;
1959	}
1960
1961
1962	/**
1963	* Resets a virtual CPU.
1964	*
1965	* Used by HMR3Reset and CPU hot plugging.
1966	*
1967	* @param pVCpu The cross context virtual CPU structure to reset.
1968	*/
1969	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1970	{
1971	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
1972	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1973	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1974
1975	pVCpu->hm.s.fActive = false;
1976	pVCpu->hm.s.Event.fPending = false;
1977	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
1978	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
1979	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1980	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
1981	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
1982	#endif
1983	}
1984
1985
1986	/**
1987	* The VM is being reset.
1988	*
1989	* For the HM component this means that any GDT/LDT/TSS monitors
1990	* needs to be removed.
1991	*
1992	* @param pVM The cross context VM structure.
1993	*/
1994	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1995	{
1996	LogFlow(("HMR3Reset:\n"));
1997
1998	if (HMIsEnabled(pVM))
1999	hmR3DisableRawMode(pVM);
2000
2001	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2002	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2003
2004	/* Clear all patch information. */
2005	pVM->hm.s.pGuestPatchMem = 0;
2006	pVM->hm.s.pFreeGuestPatchMem = 0;
2007	pVM->hm.s.cbGuestPatchMem = 0;
2008	pVM->hm.s.cPatches = 0;
2009	pVM->hm.s.PatchTree = 0;
2010	pVM->hm.s.fTprPatchingActive = false;
2011	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2012	}
2013
2014
2015	/**
2016	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2017	*
2018	* @returns VBox strict status code.
2019	* @param pVM The cross context VM structure.
2020	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2021	* @param pvUser Unused.
2022	*/
2023	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2024	{
2025	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2026
2027	/* Only execute the handler on the VCPU the original patch request was issued. */
2028	if (pVCpu->idCpu != idCpu)
2029	return VINF_SUCCESS;
2030
2031	Log(("hmR3RemovePatches\n"));
2032	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2033	{
2034	uint8_t abInstr[15];
2035	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2036	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2037	int rc;
2038
2039	#ifdef LOG_ENABLED
2040	char szOutput[256];
2041	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2042	szOutput, sizeof(szOutput), NULL);
2043	if (RT_SUCCESS(rc))
2044	Log(("Patched instr: %s\n", szOutput));
2045	#endif
2046
2047	/* Check if the instruction is still the same. */
2048	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2049	if (rc != VINF_SUCCESS)
2050	{
2051	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2052	continue; /* swapped out or otherwise removed; skip it. */
2053	}
2054
2055	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2056	{
2057	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2058	continue; /* skip it. */
2059	}
2060
2061	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2062	AssertRC(rc);
2063
2064	#ifdef LOG_ENABLED
2065	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2066	szOutput, sizeof(szOutput), NULL);
2067	if (RT_SUCCESS(rc))
2068	Log(("Original instr: %s\n", szOutput));
2069	#endif
2070	}
2071	pVM->hm.s.cPatches = 0;
2072	pVM->hm.s.PatchTree = 0;
2073	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2074	pVM->hm.s.fTprPatchingActive = false;
2075	return VINF_SUCCESS;
2076	}
2077
2078
2079	/**
2080	* Worker for enabling patching in a VT-x/AMD-V guest.
2081	*
2082	* @returns VBox status code.
2083	* @param pVM The cross context VM structure.
2084	* @param idCpu VCPU to execute hmR3RemovePatches on.
2085	* @param pPatchMem Patch memory range.
2086	* @param cbPatchMem Size of the memory range.
2087	*/
2088	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2089	{
2090	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2091	AssertRC(rc);
2092
2093	pVM->hm.s.pGuestPatchMem = pPatchMem;
2094	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2095	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2096	return VINF_SUCCESS;
2097	}
2098
2099
2100	/**
2101	* Enable patching in a VT-x/AMD-V guest
2102	*
2103	* @returns VBox status code.
2104	* @param pVM The cross context VM structure.
2105	* @param pPatchMem Patch memory range.
2106	* @param cbPatchMem Size of the memory range.
2107	*/
2108	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2109	{
2110	VM_ASSERT_EMT(pVM);
2111	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2112	if (pVM->cCpus > 1)
2113	{
2114	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2115	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2116	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2117	AssertRC(rc);
2118	return rc;
2119	}
2120	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2121	}
2122
2123
2124	/**
2125	* Disable patching in a VT-x/AMD-V guest.
2126	*
2127	* @returns VBox status code.
2128	* @param pVM The cross context VM structure.
2129	* @param pPatchMem Patch memory range.
2130	* @param cbPatchMem Size of the memory range.
2131	*/
2132	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2133	{
2134	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2135	RT_NOREF2(pPatchMem, cbPatchMem);
2136
2137	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2138	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2139
2140	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2141	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2142	(void *)(uintptr_t)VMMGetCpuId(pVM));
2143	AssertRC(rc);
2144
2145	pVM->hm.s.pGuestPatchMem = 0;
2146	pVM->hm.s.pFreeGuestPatchMem = 0;
2147	pVM->hm.s.cbGuestPatchMem = 0;
2148	pVM->hm.s.fTprPatchingActive = false;
2149	return VINF_SUCCESS;
2150	}
2151
2152
2153	/**
2154	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2155	*
2156	* @returns VBox strict status code.
2157	* @param pVM The cross context VM structure.
2158	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2159	* @param pvUser User specified CPU context.
2160	*
2161	*/
2162	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2163	{
2164	/*
2165	* Only execute the handler on the VCPU the original patch request was
2166	* issued. (The other CPU(s) might not yet have switched to protected
2167	* mode, nor have the correct memory context.)
2168	*/
2169	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2170	if (pVCpu->idCpu != idCpu)
2171	return VINF_SUCCESS;
2172
2173	/*
2174	* We're racing other VCPUs here, so don't try patch the instruction twice
2175	* and make sure there is still room for our patch record.
2176	*/
2177	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2178	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2179	if (pPatch)
2180	{
2181	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2182	return VINF_SUCCESS;
2183	}
2184	uint32_t const idx = pVM->hm.s.cPatches;
2185	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2186	{
2187	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2188	return VINF_SUCCESS;
2189	}
2190	pPatch = &pVM->hm.s.aPatches[idx];
2191
2192	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2193
2194	/*
2195	* Disassembler the instruction and get cracking.
2196	*/
2197	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2198	DISCPUSTATE Dis;
2199	uint32_t cbOp;
2200	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2201	AssertRC(rc);
2202	if ( rc == VINF_SUCCESS
2203	&& Dis.pCurInstr->uOpcode == OP_MOV
2204	&& cbOp >= 3)
2205	{
2206	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2207
2208	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2209	AssertRC(rc);
2210
2211	pPatch->cbOp = cbOp;
2212
2213	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2214	{
2215	/* write. */
2216	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2217	{
2218	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2219	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2220	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2221	}
2222	else
2223	{
2224	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2225	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2226	pPatch->uSrcOperand = Dis.Param2.uValue;
2227	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2228	}
2229	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2230	AssertRC(rc);
2231
2232	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2233	pPatch->cbNewOp = sizeof(s_abVMMCall);
2234	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2235	}
2236	else
2237	{
2238	/*
2239	* TPR Read.
2240	*
2241	* Found:
2242	* mov eax, dword [fffe0080] (5 bytes)
2243	* Check if next instruction is:
2244	* shr eax, 4
2245	*/
2246	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2247
2248	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2249	uint8_t const cbOpMmio = cbOp;
2250	uint64_t const uSavedRip = pCtx->rip;
2251
2252	pCtx->rip += cbOp;
2253	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2254	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2255	pCtx->rip = uSavedRip;
2256
2257	if ( rc == VINF_SUCCESS
2258	&& Dis.pCurInstr->uOpcode == OP_SHR
2259	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2260	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2261	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2262	&& Dis.Param2.uValue == 4
2263	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2264	{
2265	uint8_t abInstr[15];
2266
2267	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2268	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2269	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2270	AssertRC(rc);
2271
2272	pPatch->cbOp = cbOpMmio + cbOp;
2273
2274	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2275	abInstr[0] = 0xf0;
2276	abInstr[1] = 0x0f;
2277	abInstr[2] = 0x20;
2278	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2279	for (unsigned i = 4; i < pPatch->cbOp; i++)
2280	abInstr[i] = 0x90; /* nop */
2281
2282	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2283	AssertRC(rc);
2284
2285	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2286	pPatch->cbNewOp = pPatch->cbOp;
2287	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2288
2289	Log(("Acceptable read/shr candidate!\n"));
2290	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2291	}
2292	else
2293	{
2294	pPatch->enmType = HMTPRINSTR_READ;
2295	pPatch->uDstOperand = idxMmioReg;
2296
2297	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2298	AssertRC(rc);
2299
2300	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2301	pPatch->cbNewOp = sizeof(s_abVMMCall);
2302	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2303	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2304	}
2305	}
2306
2307	pPatch->Core.Key = pCtx->eip;
2308	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2309	AssertRC(rc);
2310
2311	pVM->hm.s.cPatches++;
2312	return VINF_SUCCESS;
2313	}
2314
2315	/*
2316	* Save invalid patch, so we will not try again.
2317	*/
2318	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2319	pPatch->Core.Key = pCtx->eip;
2320	pPatch->enmType = HMTPRINSTR_INVALID;
2321	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2322	AssertRC(rc);
2323	pVM->hm.s.cPatches++;
2324	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2325	return VINF_SUCCESS;
2326	}
2327
2328
2329	/**
2330	* Callback to patch a TPR instruction (jump to generated code).
2331	*
2332	* @returns VBox strict status code.
2333	* @param pVM The cross context VM structure.
2334	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2335	* @param pvUser User specified CPU context.
2336	*
2337	*/
2338	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2339	{
2340	/*
2341	* Only execute the handler on the VCPU the original patch request was
2342	* issued. (The other CPU(s) might not yet have switched to protected
2343	* mode, nor have the correct memory context.)
2344	*/
2345	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2346	if (pVCpu->idCpu != idCpu)
2347	return VINF_SUCCESS;
2348
2349	/*
2350	* We're racing other VCPUs here, so don't try patch the instruction twice
2351	* and make sure there is still room for our patch record.
2352	*/
2353	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2354	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2355	if (pPatch)
2356	{
2357	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2358	return VINF_SUCCESS;
2359	}
2360	uint32_t const idx = pVM->hm.s.cPatches;
2361	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2362	{
2363	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2364	return VINF_SUCCESS;
2365	}
2366	pPatch = &pVM->hm.s.aPatches[idx];
2367
2368	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2369	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2370
2371	/*
2372	* Disassemble the instruction and get cracking.
2373	*/
2374	DISCPUSTATE Dis;
2375	uint32_t cbOp;
2376	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2377	AssertRC(rc);
2378	if ( rc == VINF_SUCCESS
2379	&& Dis.pCurInstr->uOpcode == OP_MOV
2380	&& cbOp >= 5)
2381	{
2382	uint8_t aPatch[64];
2383	uint32_t off = 0;
2384
2385	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2386	AssertRC(rc);
2387
2388	pPatch->cbOp = cbOp;
2389	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2390
2391	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2392	{
2393	/*
2394	* TPR write:
2395	*
2396	* push ECX [51]
2397	* push EDX [52]
2398	* push EAX [50]
2399	* xor EDX,EDX [31 D2]
2400	* mov EAX,EAX [89 C0]
2401	* or
2402	* mov EAX,0000000CCh [B8 CC 00 00 00]
2403	* mov ECX,0C0000082h [B9 82 00 00 C0]
2404	* wrmsr [0F 30]
2405	* pop EAX [58]
2406	* pop EDX [5A]
2407	* pop ECX [59]
2408	* jmp return_address [E9 return_address]
2409	*/
2410	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2411
2412	aPatch[off++] = 0x51; /* push ecx */
2413	aPatch[off++] = 0x52; /* push edx */
2414	if (!fUsesEax)
2415	aPatch[off++] = 0x50; /* push eax */
2416	aPatch[off++] = 0x31; /* xor edx, edx */
2417	aPatch[off++] = 0xd2;
2418	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2419	{
2420	if (!fUsesEax)
2421	{
2422	aPatch[off++] = 0x89; /* mov eax, src_reg */
2423	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2424	}
2425	}
2426	else
2427	{
2428	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2429	aPatch[off++] = 0xb8; /* mov eax, immediate */
2430	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2431	off += sizeof(uint32_t);
2432	}
2433	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2434	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2435	off += sizeof(uint32_t);
2436
2437	aPatch[off++] = 0x0f; /* wrmsr */
2438	aPatch[off++] = 0x30;
2439	if (!fUsesEax)
2440	aPatch[off++] = 0x58; /* pop eax */
2441	aPatch[off++] = 0x5a; /* pop edx */
2442	aPatch[off++] = 0x59; /* pop ecx */
2443	}
2444	else
2445	{
2446	/*
2447	* TPR read:
2448	*
2449	* push ECX [51]
2450	* push EDX [52]
2451	* push EAX [50]
2452	* mov ECX,0C0000082h [B9 82 00 00 C0]
2453	* rdmsr [0F 32]
2454	* mov EAX,EAX [89 C0]
2455	* pop EAX [58]
2456	* pop EDX [5A]
2457	* pop ECX [59]
2458	* jmp return_address [E9 return_address]
2459	*/
2460	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2461
2462	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2463	aPatch[off++] = 0x51; /* push ecx */
2464	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2465	aPatch[off++] = 0x52; /* push edx */
2466	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2467	aPatch[off++] = 0x50; /* push eax */
2468
2469	aPatch[off++] = 0x31; /* xor edx, edx */
2470	aPatch[off++] = 0xd2;
2471
2472	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2473	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2474	off += sizeof(uint32_t);
2475
2476	aPatch[off++] = 0x0f; /* rdmsr */
2477	aPatch[off++] = 0x32;
2478
2479	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2480	{
2481	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2482	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2483	}
2484
2485	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2486	aPatch[off++] = 0x58; /* pop eax */
2487	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2488	aPatch[off++] = 0x5a; /* pop edx */
2489	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2490	aPatch[off++] = 0x59; /* pop ecx */
2491	}
2492	aPatch[off++] = 0xe9; /* jmp return_address */
2493	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2494	off += sizeof(RTRCUINTPTR);
2495
2496	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2497	{
2498	/* Write new code to the patch buffer. */
2499	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2500	AssertRC(rc);
2501
2502	#ifdef LOG_ENABLED
2503	uint32_t cbCurInstr;
2504	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2505	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2506	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2507	{
2508	char szOutput[256];
2509	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2510	szOutput, sizeof(szOutput), &cbCurInstr);
2511	if (RT_SUCCESS(rc))
2512	Log(("Patch instr %s\n", szOutput));
2513	else
2514	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2515	}
2516	#endif
2517
2518	pPatch->aNewOpcode[0] = 0xE9;
2519	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2520
2521	/* Overwrite the TPR instruction with a jump. */
2522	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2523	AssertRC(rc);
2524
2525	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2526
2527	pVM->hm.s.pFreeGuestPatchMem += off;
2528	pPatch->cbNewOp = 5;
2529
2530	pPatch->Core.Key = pCtx->eip;
2531	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2532	AssertRC(rc);
2533
2534	pVM->hm.s.cPatches++;
2535	pVM->hm.s.fTprPatchingActive = true;
2536	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2537	return VINF_SUCCESS;
2538	}
2539
2540	Log(("Ran out of space in our patch buffer!\n"));
2541	}
2542	else
2543	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2544
2545
2546	/*
2547	* Save invalid patch, so we will not try again.
2548	*/
2549	pPatch = &pVM->hm.s.aPatches[idx];
2550	pPatch->Core.Key = pCtx->eip;
2551	pPatch->enmType = HMTPRINSTR_INVALID;
2552	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2553	AssertRC(rc);
2554	pVM->hm.s.cPatches++;
2555	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2556	return VINF_SUCCESS;
2557	}
2558
2559
2560	/**
2561	* Attempt to patch TPR mmio instructions.
2562	*
2563	* @returns VBox status code.
2564	* @param pVM The cross context VM structure.
2565	* @param pVCpu The cross context virtual CPU structure.
2566	*/
2567	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2568	{
2569	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2570	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2571	(void *)(uintptr_t)pVCpu->idCpu);
2572	AssertRC(rc);
2573	return rc;
2574	}
2575
2576
2577	/**
2578	* Checks if we need to reschedule due to VMM device heap changes.
2579	*
2580	* @returns true if a reschedule is required, otherwise false.
2581	* @param pVM The cross context VM structure.
2582	* @param pCtx VM execution context.
2583	*/
2584	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2585	{
2586	/*
2587	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2588	* when the unrestricted guest execution feature is missing (VT-x only).
2589	*/
2590	if ( pVM->hm.s.vmx.fEnabled
2591	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2592	&& CPUMIsGuestInRealModeEx(pCtx)
2593	&& !PDMVmmDevHeapIsEnabled(pVM))
2594	return true;
2595
2596	return false;
2597	}
2598
2599
2600	/**
2601	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2602	* event settings changes.
2603	*
2604	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2605	* function is just updating the VM globals.
2606	*
2607	* @param pVM The VM cross context VM structure.
2608	* @thread EMT(0)
2609	*/
2610	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2611	{
2612	/* Interrupts. */
2613	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2614	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2615
2616	/* CPU Exceptions. */
2617	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2618	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2619	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2620	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2621
2622	/* Common VM exits. */
2623	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2624	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2625	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2626	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2627
2628	/* Vendor specific VM exits. */
2629	if (HMR3IsVmxEnabled(pVM->pUVM))
2630	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2631	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2632	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2633	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2634	else
2635	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2636	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2637	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2638	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2639
2640	/* Done. */
2641	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2642	}
2643
2644
2645	/**
2646	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2647	*
2648	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2649	* per CPU settings.
2650	*
2651	* @param pVM The VM cross context VM structure.
2652	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2653	*/
2654	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2655	{
2656	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2657	}
2658
2659
2660	/**
2661	* Checks if we are currently using hardware acceleration.
2662	*
2663	* @returns true if hardware acceleration is being used, otherwise false.
2664	* @param pVCpu The cross context virtual CPU structure.
2665	*/
2666	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2667	{
2668	return pVCpu->hm.s.fActive;
2669	}
2670
2671
2672	/**
2673	* External interface for querying whether hardware acceleration is enabled.
2674	*
2675	* @returns true if VT-x or AMD-V is being used, otherwise false.
2676	* @param pUVM The user mode VM handle.
2677	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2678	*/
2679	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2680	{
2681	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2682	PVM pVM = pUVM->pVM;
2683	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2684	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2685	}
2686
2687
2688	/**
2689	* External interface for querying whether VT-x is being used.
2690	*
2691	* @returns true if VT-x is being used, otherwise false.
2692	* @param pUVM The user mode VM handle.
2693	* @sa HMR3IsSvmEnabled, HMIsEnabled
2694	*/
2695	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2696	{
2697	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2698	PVM pVM = pUVM->pVM;
2699	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2700	return pVM->hm.s.vmx.fEnabled
2701	&& pVM->hm.s.vmx.fSupported
2702	&& pVM->fHMEnabled;
2703	}
2704
2705
2706	/**
2707	* External interface for querying whether AMD-V is being used.
2708	*
2709	* @returns true if VT-x is being used, otherwise false.
2710	* @param pUVM The user mode VM handle.
2711	* @sa HMR3IsVmxEnabled, HMIsEnabled
2712	*/
2713	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2714	{
2715	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2716	PVM pVM = pUVM->pVM;
2717	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2718	return pVM->hm.s.svm.fEnabled
2719	&& pVM->hm.s.svm.fSupported
2720	&& pVM->fHMEnabled;
2721	}
2722
2723
2724	/**
2725	* Checks if we are currently using nested paging.
2726	*
2727	* @returns true if nested paging is being used, otherwise false.
2728	* @param pUVM The user mode VM handle.
2729	*/
2730	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2731	{
2732	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2733	PVM pVM = pUVM->pVM;
2734	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2735	return pVM->hm.s.fNestedPagingCfg;
2736	}
2737
2738
2739	/**
2740	* Checks if virtualized APIC registers are enabled.
2741	*
2742	* When enabled this feature allows the hardware to access most of the
2743	* APIC registers in the virtual-APIC page without causing VM-exits. See
2744	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2745	*
2746	* @returns true if virtualized APIC registers is enabled, otherwise
2747	* false.
2748	* @param pUVM The user mode VM handle.
2749	*/
2750	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2751	{
2752	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2753	PVM pVM = pUVM->pVM;
2754	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2755	return pVM->hm.s.fVirtApicRegs;
2756	}
2757
2758
2759	/**
2760	* Checks if APIC posted-interrupt processing is enabled.
2761	*
2762	* This returns whether we can deliver interrupts to the guest without
2763	* leaving guest-context by updating APIC state from host-context.
2764	*
2765	* @returns true if APIC posted-interrupt processing is enabled,
2766	* otherwise false.
2767	* @param pUVM The user mode VM handle.
2768	*/
2769	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2770	{
2771	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2772	PVM pVM = pUVM->pVM;
2773	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2774	return pVM->hm.s.fPostedIntrs;
2775	}
2776
2777
2778	/**
2779	* Checks if we are currently using VPID in VT-x mode.
2780	*
2781	* @returns true if VPID is being used, otherwise false.
2782	* @param pUVM The user mode VM handle.
2783	*/
2784	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2785	{
2786	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2787	PVM pVM = pUVM->pVM;
2788	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2789	return pVM->hm.s.ForR3.vmx.fVpid;
2790	}
2791
2792
2793	/**
2794	* Checks if we are currently using VT-x unrestricted execution,
2795	* aka UX.
2796	*
2797	* @returns true if UX is being used, otherwise false.
2798	* @param pUVM The user mode VM handle.
2799	*/
2800	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2801	{
2802	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2803	PVM pVM = pUVM->pVM;
2804	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2805	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2806	\|\| pVM->hm.s.svm.fSupported;
2807	}
2808
2809
2810	/**
2811	* Checks if the VMX-preemption timer is being used.
2812	*
2813	* @returns true if the VMX-preemption timer is being used, otherwise false.
2814	* @param pVM The cross context VM structure.
2815	*/
2816	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2817	{
2818	return HMIsEnabled(pVM)
2819	&& pVM->hm.s.vmx.fEnabled
2820	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2821	}
2822
2823
2824	#ifdef TODO_9217_VMCSINFO
2825	/**
2826	* Helper for HMR3CheckError to log VMCS controls to the release log.
2827	*
2828	* @param idCpu The Virtual CPU ID.
2829	* @param pVmcsInfo The VMCS info. object.
2830	*/
2831	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2832	{
2833	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2834	{
2835	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2836	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2837	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2838	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2839	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2840	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2841	}
2842	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2843	{
2844	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2845	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2846	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2847	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2848	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2849	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2850	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2851	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2852	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2853	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2854	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2855	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2856	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2857	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2858	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2859	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2860	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2861	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2862	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2863	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2864	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2865	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2866	}
2867	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2868	{
2869	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2870	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2871	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2872	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2873	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2874	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2875	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2876	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2877	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2878	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2879	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2880	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2881	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2882	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2883	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2884	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2885	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2886	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2887	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2888	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2889	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2890	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2891	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2892	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2893	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2894	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2895	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2896	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2897	}
2898	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2899	{
2900	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2902	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2903	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2904	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2905	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2906	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2907	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2908	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2911	}
2912	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2913	{
2914	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2927	}
2928	}
2929	#endif
2930
2931
2932	/**
2933	* Check fatal VT-x/AMD-V error and produce some meaningful
2934	* log release message.
2935	*
2936	* @param pVM The cross context VM structure.
2937	* @param iStatusCode VBox status code.
2938	*/
2939	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2940	{
2941	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2942	{
2943	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2944	* might be getting inaccurate values for non-guru'ing EMTs. */
2945	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2946	#ifdef TODO_9217_VMCSINFO
2947	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
2948	#endif
2949	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
2950	switch (iStatusCode)
2951	{
2952	case VERR_VMX_INVALID_VMCS_PTR:
2953	{
2954	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2955	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2956	#ifdef TODO_9217_VMCSINFO
2957	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2958	pVmcsInfo->HCPhysVmcs));
2959	#endif
2960	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2961	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2962	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2963	break;
2964	}
2965
2966	case VERR_VMX_UNABLE_TO_START_VM:
2967	{
2968	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2969	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2970	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
2971	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2972
2973	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
2974	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
2975	{
2976	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2977	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2978	}
2979	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
2980	{
2981	#ifdef TODO_9217_VMCSINFO
2982	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
2983	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
2984	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
2985	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
2986	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
2987	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
2988	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
2989	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
2990	#endif
2991	}
2992	/** @todo Log VM-entry event injection control fields
2993	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2994	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2995	break;
2996	}
2997
2998	case VERR_VMX_INVALID_GUEST_STATE:
2999	{
3000	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3001	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3002	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3003	#ifdef TODO_9217_VMCSINFO
3004	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3005	#endif
3006	break;
3007	}
3008
3009	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3010	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3011	case VERR_VMX_INVALID_VMXON_PTR:
3012	case VERR_VMX_UNEXPECTED_EXIT:
3013	case VERR_VMX_INVALID_VMCS_FIELD:
3014	case VERR_SVM_UNKNOWN_EXIT:
3015	case VERR_SVM_UNEXPECTED_EXIT:
3016	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3017	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3018	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3019	break;
3020	}
3021	}
3022
3023	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3024	{
3025	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3026	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3027	}
3028	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3029	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3030	}
3031
3032
3033	/**
3034	* Execute state save operation.
3035	*
3036	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3037	* is because we always save the VM state from ring-3 and thus most HM state
3038	* will be re-synced dynamically at runtime and don't need to be part of the VM
3039	* saved state.
3040	*
3041	* @returns VBox status code.
3042	* @param pVM The cross context VM structure.
3043	* @param pSSM SSM operation handle.
3044	*/
3045	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3046	{
3047	Log(("hmR3Save:\n"));
3048
3049	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3050	{
3051	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3052	Assert(!pVCpu->hm.s.Event.fPending);
3053	if (pVM->cpum.ro.GuestFeatures.fSvm)
3054	{
3055	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3056	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3057	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3058	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3059	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3060	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3061	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3062	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3063	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3064	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3065	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3066	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3067	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3068	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3069	}
3070	}
3071
3072	/* Save the guest patch data. */
3073	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3074	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3075	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3076
3077	/* Store all the guest patch records too. */
3078	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3079	if (RT_FAILURE(rc))
3080	return rc;
3081
3082	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3083	{
3084	AssertCompileSize(HMTPRINSTR, 4);
3085	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3086	SSMR3PutU32(pSSM, pPatch->Core.Key);
3087	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3088	SSMR3PutU32(pSSM, pPatch->cbOp);
3089	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3090	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3091	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3092	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3093	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3094	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3095	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3096	if (RT_FAILURE(rc))
3097	return rc;
3098	}
3099
3100	return VINF_SUCCESS;
3101	}
3102
3103
3104	/**
3105	* Execute state load operation.
3106	*
3107	* @returns VBox status code.
3108	* @param pVM The cross context VM structure.
3109	* @param pSSM SSM operation handle.
3110	* @param uVersion Data layout version.
3111	* @param uPass The data pass.
3112	*/
3113	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3114	{
3115	int rc;
3116
3117	LogFlowFunc(("uVersion=%u\n", uVersion));
3118	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3119
3120	/*
3121	* Validate version.
3122	*/
3123	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3124	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3125	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3126	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3127	{
3128	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3129	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3130	}
3131
3132	/*
3133	* Load per-VCPU state.
3134	*/
3135	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3136	{
3137	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3138	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3139	{
3140	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3141	if (pVM->cpum.ro.GuestFeatures.fSvm)
3142	{
3143	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3144	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3145	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3146	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3147	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3148	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3149	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3150	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3151	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3152	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3153	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3154	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3155	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3156	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3157	AssertRCReturn(rc, rc);
3158	}
3159	}
3160	else
3161	{
3162	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3163	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3164	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3165	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3166
3167	/* VMX fWasInRealMode related data. */
3168	uint32_t uDummy;
3169	SSMR3GetU32(pSSM, &uDummy);
3170	SSMR3GetU32(pSSM, &uDummy);
3171	rc = SSMR3GetU32(pSSM, &uDummy);
3172	AssertRCReturn(rc, rc);
3173	}
3174	}
3175
3176	/*
3177	* Load TPR patching data.
3178	*/
3179	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3180	{
3181	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3182	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3183	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3184
3185	/* Fetch all TPR patch records. */
3186	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3187	AssertRCReturn(rc, rc);
3188	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3189	{
3190	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3191	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3192	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3193	SSMR3GetU32(pSSM, &pPatch->cbOp);
3194	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3195	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3196	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3197
3198	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3199	pVM->hm.s.fTprPatchingActive = true;
3200	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3201
3202	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3203	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3204	SSMR3GetU32(pSSM, &pPatch->cFaults);
3205	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3206	AssertRCReturn(rc, rc);
3207
3208	LogFlow(("hmR3Load: patch %d\n", i));
3209	LogFlow(("Key = %x\n", pPatch->Core.Key));
3210	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3211	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3212	LogFlow(("type = %d\n", pPatch->enmType));
3213	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3214	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3215	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3216	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3217
3218	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3219	AssertRCReturn(rc, rc);
3220	}
3221	}
3222
3223	return VINF_SUCCESS;
3224	}
3225
3226
3227	/**
3228	* Displays HM info.
3229	*
3230	* @param pVM The cross context VM structure.
3231	* @param pHlp The info helper functions.
3232	* @param pszArgs Arguments, ignored.
3233	*/
3234	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3235	{
3236	NOREF(pszArgs);
3237	PVMCPU pVCpu = VMMGetCpu(pVM);
3238	if (!pVCpu)
3239	pVCpu = pVM->apCpusR3[0];
3240
3241	if (HMIsEnabled(pVM))
3242	{
3243	if (pVM->hm.s.vmx.fSupported)
3244	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3245	else
3246	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3247	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3248	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3249	if (pVM->hm.s.vmx.fSupported)
3250	{
3251	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3252	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3253	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3254
3255	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3256	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3257	if (fRealOnV86Active)
3258	{
3259	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3260	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3261	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3262	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3263	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3264	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3265	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3266	}
3267	}
3268	}
3269	else
3270	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3271	}
3272
3273
3274	/**
3275	* Displays the HM Last-Branch-Record info. for the guest.
3276	*
3277	* @param pVM The cross context VM structure.
3278	* @param pHlp The info helper functions.
3279	* @param pszArgs Arguments, ignored.
3280	*/
3281	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3282	{
3283	NOREF(pszArgs);
3284	PVMCPU pVCpu = VMMGetCpu(pVM);
3285	if (!pVCpu)
3286	pVCpu = pVM->apCpusR3[0];
3287
3288	if (!HMIsEnabled(pVM))
3289	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3290
3291	if (HMIsVmxActive(pVM))
3292	{
3293	if (pVM->hm.s.vmx.fLbrCfg)
3294	{
3295	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3296	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3297
3298	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3299	* 0xf should cover everything we support thus far. Fix if necessary
3300	* later. */
3301	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3302	if (idxTopOfStack > cLbrStack)
3303	{
3304	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3305	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3306	return;
3307	}
3308
3309	/*
3310	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3311	*/
3312	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3313	uint32_t idxCurrent = idxTopOfStack;
3314	Assert(idxTopOfStack < cLbrStack);
3315	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3316	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3317	for (;;)
3318	{
3319	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3320	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3321	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3322	else
3323	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3324
3325	idxCurrent = (idxCurrent - 1) % cLbrStack;
3326	if (idxCurrent == idxTopOfStack)
3327	break;
3328	}
3329	}
3330	else
3331	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3332	}
3333	else
3334	{
3335	Assert(HMIsSvmActive(pVM));
3336	/** @todo SVM: LBRs (get them from VMCB if possible). */
3337	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented in VM debugger yet\n");
3338	}
3339	}
3340
3341
3342	/**
3343	* Displays the HM pending event.
3344	*
3345	* @param pVM The cross context VM structure.
3346	* @param pHlp The info helper functions.
3347	* @param pszArgs Arguments, ignored.
3348	*/
3349	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3350	{
3351	NOREF(pszArgs);
3352	PVMCPU pVCpu = VMMGetCpu(pVM);
3353	if (!pVCpu)
3354	pVCpu = pVM->apCpusR3[0];
3355
3356	if (HMIsEnabled(pVM))
3357	{
3358	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3359	if (pVCpu->hm.s.Event.fPending)
3360	{
3361	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3362	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3363	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3364	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3365	}
3366	}
3367	else
3368	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3369	}
3370
3371
3372	/**
3373	* Displays the SVM nested-guest VMCB cache.
3374	*
3375	* @param pVM The cross context VM structure.
3376	* @param pHlp The info helper functions.
3377	* @param pszArgs Arguments, ignored.
3378	*/
3379	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3380	{
3381	NOREF(pszArgs);
3382	PVMCPU pVCpu = VMMGetCpu(pVM);
3383	if (!pVCpu)
3384	pVCpu = pVM->apCpusR3[0];
3385
3386	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3387	if ( fSvmEnabled
3388	&& pVM->cpum.ro.GuestFeatures.fSvm)
3389	{
3390	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3391	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3392	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3393	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3394	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3395	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3396	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3397	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3398	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3399	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3400	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3401	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3402	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3403	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3404	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3405	}
3406	else
3407	{
3408	if (!fSvmEnabled)
3409	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3410	else
3411	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3412	}
3413	}
3414

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 91281

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