HM.cpp@ 80074

Last change on this file since 80074 was 80052, checked in by vboxsync, 6 years ago
Main: Kicking out 32-bit host support - Some HM bits using VMMSwitcher & CPUMHyper. bugref:9511
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 153.3 KB

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1	/* $Id: HM.cpp 80052 2019-07-29 20:36:52Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/mm.h>
44	#include <VBox/vmm/em.h>
45	#include <VBox/vmm/pdmapi.h>
46	#include <VBox/vmm/pgm.h>
47	#include <VBox/vmm/ssm.h>
48	#include <VBox/vmm/gim.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/selm.h>
54	#include <VBox/vmm/nem.h>
55	#ifdef VBOX_WITH_REM
56	# include <VBox/vmm/rem.h>
57	#endif
58	#include <VBox/vmm/hm_vmx.h>
59	#include <VBox/vmm/hm_svm.h>
60	#include "HMInternal.h"
61	#include <VBox/vmm/vm.h>
62	#include <VBox/vmm/uvm.h>
63	#include <VBox/err.h>
64	#include <VBox/param.h>
65
66	#include <iprt/assert.h>
67	#include <VBox/log.h>
68	#include <iprt/asm.h>
69	#include <iprt/asm-amd64-x86.h>
70	#include <iprt/env.h>
71	#include <iprt/thread.h>
72
73
74	/*********************************************************************************************************************************
75	* Defined Constants And Macros *
76	*********************************************************************************************************************************/
77	/** @def HMVMX_REPORT_FEAT
78	* Reports VT-x feature to the release log.
79	*
80	* @param a_uAllowed1 Mask of allowed-1 feature bits.
81	* @param a_uAllowed0 Mask of allowed-0 feature bits.
82	* @param a_StrDesc The description string to report.
83	* @param a_Featflag Mask of the feature to report.
84	*/
85	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
86	do { \
87	if ((a_uAllowed1) & (a_Featflag)) \
88	{ \
89	if ((a_uAllowed0) & (a_Featflag)) \
90	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
91	else \
92	LogRel(("HM: " a_StrDesc "\n")); \
93	} \
94	else \
95	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
96	} while (0)
97
98	/** @def HMVMX_REPORT_ALLOWED_FEAT
99	* Reports an allowed VT-x feature to the release log.
100	*
101	* @param a_uAllowed1 Mask of allowed-1 feature bits.
102	* @param a_StrDesc The description string to report.
103	* @param a_FeatFlag Mask of the feature to report.
104	*/
105	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
106	do { \
107	if ((a_uAllowed1) & (a_FeatFlag)) \
108	LogRel(("HM: " a_StrDesc "\n")); \
109	else \
110	LogRel(("HM: " a_StrDesc " not supported\n")); \
111	} while (0)
112
113	/** @def HMVMX_REPORT_MSR_CAP
114	* Reports MSR feature capability.
115	*
116	* @param a_MsrCaps Mask of MSR feature bits.
117	* @param a_StrDesc The description string to report.
118	* @param a_fCap Mask of the feature to report.
119	*/
120	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
121	do { \
122	if ((a_MsrCaps) & (a_fCap)) \
123	LogRel(("HM: " a_StrDesc "\n")); \
124	} while (0)
125
126	/** @def HMVMX_LOGREL_FEAT
127	* Dumps a feature flag from a bitmap of features to the release log.
128	*
129	* @param a_fVal The value of all the features.
130	* @param a_fMask The specific bitmask of the feature.
131	*/
132	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
133	do { \
134	if ((a_fVal) & (a_fMask)) \
135	LogRel(("HM: %s\n", #a_fMask)); \
136	} while (0)
137
138
139	/*********************************************************************************************************************************
140	* Internal Functions *
141	*********************************************************************************************************************************/
142	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
143	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
144	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
145	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
146	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
147	static int hmR3InitFinalizeR3(PVM pVM);
148	static int hmR3InitFinalizeR0(PVM pVM);
149	static int hmR3InitFinalizeR0Intel(PVM pVM);
150	static int hmR3InitFinalizeR0Amd(PVM pVM);
151	static int hmR3TermCPU(PVM pVM);
152
153
154
155	/**
156	* Initializes the HM.
157	*
158	* This is the very first component to really do init after CFGM so that we can
159	* establish the predominant execution engine for the VM prior to initializing
160	* other modules. It takes care of NEM initialization if needed (HM disabled or
161	* not available in HW).
162	*
163	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
164	* hypervisor API via NEM, and then back on raw-mode if that isn't available
165	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
166	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
167	* X, OS/2 and others).
168	*
169	* Note that a lot of the set up work is done in ring-0 and thus postponed till
170	* the ring-3 and ring-0 callback to HMR3InitCompleted.
171	*
172	* @returns VBox status code.
173	* @param pVM The cross context VM structure.
174	*
175	* @remarks Be careful with what we call here, since most of the VMM components
176	* are uninitialized.
177	*/
178	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
179	{
180	LogFlowFunc(("\n"));
181
182	/*
183	* Assert alignment and sizes.
184	*/
185	AssertCompileMemberAlignment(VM, hm.s, 32);
186	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
187
188	/*
189	* Register the saved state data unit.
190	*/
191	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
192	NULL, NULL, NULL,
193	NULL, hmR3Save, NULL,
194	NULL, hmR3Load, NULL);
195	if (RT_FAILURE(rc))
196	return rc;
197
198	/*
199	* Register info handlers.
200	*/
201	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
202	AssertRCReturn(rc, rc);
203
204	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
205	DBGFINFO_FLAGS_ALL_EMTS);
206	AssertRCReturn(rc, rc);
207
208	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
209	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
210	AssertRCReturn(rc, rc);
211
212	/*
213	* Read configuration.
214	*/
215	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
216
217	/*
218	* Validate the HM settings.
219	*/
220	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
221	"HMForced"
222	"\|UseNEMInstead"
223	"\|FallbackToNEM"
224	"\|EnableNestedPaging"
225	"\|EnableUX"
226	"\|EnableLargePages"
227	"\|EnableVPID"
228	"\|IBPBOnVMExit"
229	"\|IBPBOnVMEntry"
230	"\|SpecCtrlByHost"
231	"\|L1DFlushOnSched"
232	"\|L1DFlushOnVMEntry"
233	"\|MDSClearOnSched"
234	"\|MDSClearOnVMEntry"
235	"\|TPRPatchingEnabled"
236	"\|64bitEnabled"
237	"\|Exclusive"
238	"\|MaxResumeLoops"
239	"\|VmxPleGap"
240	"\|VmxPleWindow"
241	"\|UseVmxPreemptTimer"
242	"\|SvmPauseFilter"
243	"\|SvmPauseFilterThreshold"
244	"\|SvmVirtVmsaveVmload"
245	"\|SvmVGif"
246	"\|LovelyMesaDrvWorkaround",
247	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
248	if (RT_FAILURE(rc))
249	return rc;
250
251	/** @cfgm{/HM/HMForced, bool, false}
252	* Forces hardware virtualization, no falling back on raw-mode. HM must be
253	* enabled, i.e. /HMEnabled must be true. */
254	bool fHMForced;
255	#ifdef VBOX_WITH_RAW_MODE
256	rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
257	AssertRCReturn(rc, rc);
258	AssertLogRelMsgReturn(!fHMForced \|\| pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
259	VERR_INVALID_PARAMETER);
260	# if defined(RT_OS_DARWIN)
261	if (pVM->fHMEnabled)
262	fHMForced = true;
263	# endif
264	AssertLogRelMsgReturn(pVM->cCpus == 1 \|\| pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
265	VERR_INVALID_PARAMETER);
266	if (pVM->cCpus > 1)
267	fHMForced = true;
268	#else /* !VBOX_WITH_RAW_MODE */
269	AssertRelease(pVM->fHMEnabled);
270	fHMForced = true;
271	#endif /* !VBOX_WITH_RAW_MODE */
272
273	/** @cfgm{/HM/UseNEMInstead, bool, true}
274	* Don't use HM, use NEM instead. */
275	bool fUseNEMInstead = false;
276	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
277	AssertRCReturn(rc, rc);
278	if (fUseNEMInstead && pVM->fHMEnabled)
279	{
280	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
281	pVM->fHMEnabled = false;
282	}
283
284	/** @cfgm{/HM/FallbackToNEM, bool, true}
285	* Enables fallback on NEM. */
286	bool fFallbackToNEM = true;
287	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
288	AssertRCReturn(rc, rc);
289
290	/** @cfgm{/HM/EnableNestedPaging, bool, false}
291	* Enables nested paging (aka extended page tables). */
292	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
293	AssertRCReturn(rc, rc);
294
295	/** @cfgm{/HM/EnableUX, bool, true}
296	* Enables the VT-x unrestricted execution feature. */
297	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
298	AssertRCReturn(rc, rc);
299
300	/** @cfgm{/HM/EnableLargePages, bool, false}
301	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
302	* page table walking and maybe better TLB hit rate in some cases. */
303	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
304	AssertRCReturn(rc, rc);
305
306	/** @cfgm{/HM/EnableVPID, bool, false}
307	* Enables the VT-x VPID feature. */
308	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
309	AssertRCReturn(rc, rc);
310
311	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
312	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
313	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
314	AssertRCReturn(rc, rc);
315
316	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
317	* Enables AMD64 cpu features.
318	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
319	* already have the support. */
320	#ifdef VBOX_ENABLE_64_BITS_GUESTS
321	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
322	AssertLogRelRCReturn(rc, rc);
323	#else
324	pVM->hm.s.fAllow64BitGuests = false;
325	#endif
326
327	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
328	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
329	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
330	* latest PAUSE instruction to be start of a new PAUSE loop.
331	*/
332	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
333	AssertRCReturn(rc, rc);
334
335	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
336	* The pause-filter exiting window in TSC ticks. When the number of ticks
337	* between the current PAUSE instruction and first PAUSE of a loop exceeds
338	* VmxPleWindow, a VM-exit is triggered.
339	*
340	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
341	*/
342	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
343	AssertRCReturn(rc, rc);
344
345	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
346	* A counter that is decrement each time a PAUSE instruction is executed by the
347	* guest. When the counter is 0, a \#VMEXIT is triggered.
348	*
349	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
350	*/
351	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
352	AssertRCReturn(rc, rc);
353
354	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
355	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
356	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
357	* PauseFilter count is reset to its initial value. However, if PAUSE is
358	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
359	* be triggered.
360	*
361	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
362	* activated.
363	*/
364	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
365	AssertRCReturn(rc, rc);
366
367	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
368	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
369	* available. */
370	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
371	AssertRCReturn(rc, rc);
372
373	/** @cfgm{/HM/SvmVGif, bool, true}
374	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
375	* if it's available. */
376	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
377	AssertRCReturn(rc, rc);
378
379	/** @cfgm{/HM/Exclusive, bool}
380	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
381	* global init for each host CPU. If false, we do local init each time we wish
382	* to execute guest code.
383	*
384	* On Windows, default is false due to the higher risk of conflicts with other
385	* hypervisors.
386	*
387	* On Mac OS X, this setting is ignored since the code does not handle local
388	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
389	*/
390	#if defined(RT_OS_DARWIN)
391	pVM->hm.s.fGlobalInit = true;
392	#else
393	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
394	# if defined(RT_OS_WINDOWS)
395	false
396	# else
397	true
398	# endif
399	);
400	AssertLogRelRCReturn(rc, rc);
401	#endif
402
403	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
404	* The number of times to resume guest execution before we forcibly return to
405	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
406	* determines the default value. */
407	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
408	AssertLogRelRCReturn(rc, rc);
409
410	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
411	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
412	* available. */
413	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
414	AssertLogRelRCReturn(rc, rc);
415
416	/** @cfgm{/HM/IBPBOnVMExit, bool}
417	* Costly paranoia setting. */
418	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
419	AssertLogRelRCReturn(rc, rc);
420
421	/** @cfgm{/HM/IBPBOnVMEntry, bool}
422	* Costly paranoia setting. */
423	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
424	AssertLogRelRCReturn(rc, rc);
425
426	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
427	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
428	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
429	AssertLogRelRCReturn(rc, rc);
430
431	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
432	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
433	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
434	AssertLogRelRCReturn(rc, rc);
435
436	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
437	if (pVM->hm.s.fL1dFlushOnVmEntry)
438	pVM->hm.s.fL1dFlushOnSched = false;
439
440	/** @cfgm{/HM/SpecCtrlByHost, bool}
441	* Another expensive paranoia setting. */
442	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
443	AssertLogRelRCReturn(rc, rc);
444
445	/** @cfgm{/HM/MDSClearOnSched, bool, true}
446	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
447	* ignored on CPUs that aren't affected. */
448	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
449	AssertLogRelRCReturn(rc, rc);
450
451	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
452	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
453	* ignored on CPUs that aren't affected. */
454	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
455	AssertLogRelRCReturn(rc, rc);
456
457	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
458	if (pVM->hm.s.fMdsClearOnVmEntry)
459	pVM->hm.s.fMdsClearOnSched = false;
460
461	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
462	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
463	* the hypervisor it is running under. */
464	bool f;
465	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
466	AssertLogRelRCReturn(rc, rc);
467	for (VMCPUID i = 0; i < pVM->cCpus; i++)
468	pVM->aCpus[i].hm.s.fTrapXcptGpForLovelyMesaDrv = f;
469
470	/*
471	* Check if VT-x or AMD-v support according to the users wishes.
472	*/
473	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
474	* VERR_SVM_IN_USE. */
475	if (pVM->fHMEnabled)
476	{
477	uint32_t fCaps;
478	rc = SUPR3QueryVTCaps(&fCaps);
479	if (RT_SUCCESS(rc))
480	{
481	if (fCaps & SUPVTCAPS_AMD_V)
482	{
483	pVM->hm.s.svm.fSupported = true;
484	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
485	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
486	}
487	else if (fCaps & SUPVTCAPS_VT_X)
488	{
489	const char *pszWhy;
490	rc = SUPR3QueryVTxSupported(&pszWhy);
491	if (RT_SUCCESS(rc))
492	{
493	pVM->hm.s.vmx.fSupported = true;
494	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
495	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
496	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
497	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
498	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
499	}
500	else
501	{
502	/*
503	* Before failing, try fallback to NEM if we're allowed to do that.
504	*/
505	pVM->fHMEnabled = false;
506	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
507	if (fFallbackToNEM)
508	{
509	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
510	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
511
512	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
513	if ( RT_SUCCESS(rc2)
514	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
515	rc = VINF_SUCCESS;
516	}
517	if (RT_FAILURE(rc))
518	{
519	if (fHMForced)
520	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
521
522	/* Fall back to raw-mode. */
523	LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
524	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
525	}
526	}
527	}
528	else
529	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
530	VERR_INTERNAL_ERROR_5);
531
532	/*
533	* Do we require a little bit or raw-mode for 64-bit guest execution?
534	*/
535	pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
536	&& pVM->fHMEnabled
537	&& pVM->hm.s.fAllow64BitGuests;
538
539	/*
540	* Disable nested paging and unrestricted guest execution now if they're
541	* configured so that CPUM can make decisions based on our configuration.
542	*/
543	Assert(!pVM->hm.s.fNestedPaging);
544	if (pVM->hm.s.fAllowNestedPaging)
545	{
546	if (fCaps & SUPVTCAPS_NESTED_PAGING)
547	pVM->hm.s.fNestedPaging = true;
548	else
549	pVM->hm.s.fAllowNestedPaging = false;
550	}
551
552	if (fCaps & SUPVTCAPS_VT_X)
553	{
554	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
555	if (pVM->hm.s.vmx.fAllowUnrestricted)
556	{
557	if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
558	&& pVM->hm.s.fNestedPaging)
559	pVM->hm.s.vmx.fUnrestrictedGuest = true;
560	else
561	pVM->hm.s.vmx.fAllowUnrestricted = false;
562	}
563	}
564	}
565	else
566	{
567	const char *pszMsg;
568	switch (rc)
569	{
570	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
571	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
572	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
573	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
574	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
575	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
576	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
577	default:
578	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
579	}
580
581	/*
582	* Before failing, try fallback to NEM if we're allowed to do that.
583	*/
584	pVM->fHMEnabled = false;
585	if (fFallbackToNEM)
586	{
587	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
588	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
589	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
590	if ( RT_SUCCESS(rc2)
591	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
592	rc = VINF_SUCCESS;
593	}
594	if (RT_FAILURE(rc))
595	{
596	if (fHMForced)
597	return VM_SET_ERROR(pVM, rc, pszMsg);
598
599	LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
600	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
601	}
602	}
603	}
604	else
605	{
606	/*
607	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
608	*/
609	if (!fUseNEMInstead)
610	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
611	else
612	{
613	rc = NEMR3Init(pVM, false /fFallback/, true);
614	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
615	if (RT_FAILURE(rc))
616	return rc;
617	}
618	}
619
620	return VINF_SUCCESS;
621	}
622
623
624	/**
625	* Initializes HM components after ring-3 phase has been fully initialized.
626	*
627	* @returns VBox status code.
628	* @param pVM The cross context VM structure.
629	*/
630	static int hmR3InitFinalizeR3(PVM pVM)
631	{
632	LogFlowFunc(("\n"));
633
634	if (!HMIsEnabled(pVM))
635	return VINF_SUCCESS;
636
637	for (VMCPUID i = 0; i < pVM->cCpus; i++)
638	{
639	PVMCPU pVCpu = &pVM->aCpus[i];
640	pVCpu->hm.s.fActive = false;
641	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
642	}
643
644	#ifdef VBOX_WITH_STATISTICS
645	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
646	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
647	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
648	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
649	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
650	#endif
651
652	/*
653	* Statistics.
654	*/
655	for (VMCPUID i = 0; i < pVM->cCpus; i++)
656	{
657	PVMCPU pVCpu = &pVM->aCpus[i];
658	int rc;
659
660	#ifdef VBOX_WITH_STATISTICS
661	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
662	"Profiling of RTMpPokeCpu.",
663	"/PROF/CPU%d/HM/Poke", i);
664	AssertRC(rc);
665	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
666	"Profiling of poke wait.",
667	"/PROF/CPU%d/HM/PokeWait", i);
668	AssertRC(rc);
669	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
670	"Profiling of poke wait when RTMpPokeCpu fails.",
671	"/PROF/CPU%d/HM/PokeWaitFailed", i);
672	AssertRC(rc);
673	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
674	"Profiling of entry until entering GC.",
675	"/PROF/CPU%d/HM/Entry", i);
676	AssertRC(rc);
677	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
678	"Profiling of pre-exit processing after returning from GC.",
679	"/PROF/CPU%d/HM/SwitchFromGC_1", i);
680	AssertRC(rc);
681	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
682	"Profiling of exit handling (longjmps not included!)",
683	"/PROF/CPU%d/HM/SwitchFromGC_2", i);
684	AssertRC(rc);
685
686	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
687	"I/O.",
688	"/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
689	AssertRC(rc);
690	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
691	"MOV CRx.",
692	"/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
693	AssertRC(rc);
694	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
695	"Exceptions, NMIs.",
696	"/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
697	AssertRC(rc);
698	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitVmentry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
699	"VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.",
700	"/PROF/CPU%d/HM/SwitchFromGC_2/Vmentry", i);
701	AssertRC(rc);
702	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
703	"Profiling of importing guest state from hardware after VM-exit.",
704	"/PROF/CPU%d/HM/ImportGuestState", i);
705	AssertRC(rc);
706	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
707	"Profiling of exporting guest state to hardware before VM-entry.",
708	"/PROF/CPU%d/HM/ExportGuestState", i);
709	AssertRC(rc);
710	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
711	"Profiling of CPUMR0LoadGuestFPU.",
712	"/PROF/CPU%d/HM/LoadGuestFpuState", i);
713	AssertRC(rc);
714	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
715	"Profiling of execution of guest-code in hardware.",
716	"/PROF/CPU%d/HM/InGC", i);
717	AssertRC(rc);
718
719	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
720	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
721	STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
722	"/PROF/CPU%d/HM/Switcher3264", i);
723	AssertRC(rc);
724	# endif
725
726	# ifdef HM_PROFILE_EXIT_DISPATCH
727	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
728	STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
729	"/PROF/CPU%d/HM/ExitDispatch", i);
730	AssertRC(rc);
731	# endif
732
733	#endif
734	# define HM_REG_COUNTER(a, b, desc) \
735	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
736	AssertRC(rc);
737
738	#ifdef VBOX_WITH_STATISTICS
739	HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Total exits (including nested-guest exits).");
740	HM_REG_COUNTER(&pVCpu->hm.s.StatNestedExitAll, "/HM/CPU%d/Exit/NestedGuest/All", "Total nested-guest exits.");
741	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
742	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
743	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
744	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
745	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
746	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
747	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
748	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
749	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestTS, "/HM/CPU%d/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
750	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestOF, "/HM/CPU%d/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
751	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
752	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
753	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDF, "/HM/CPU%d/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
754	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBR, "/HM/CPU%d/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
755	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestAC, "/HM/CPU%d/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
756	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
757	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
758	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
759	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
760	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
761	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "MSR read.");
762	HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "MSR write.");
763	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
764	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
765	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
766	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
767	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
768	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
769	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
770	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
771	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
772	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
773	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
774	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
775	HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
776	HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
777	HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
778	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/Instr/IO/Write", "I/O write.");
779	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/Instr/IO/Read", "I/O read.");
780	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/Instr/IO/WriteString", "String I/O write.");
781	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/Instr/IO/ReadString", "String I/O read.");
782	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
783	HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
784	#endif
785	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
786	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGCIpi, "/HM/CPU%d/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
787	#ifdef VBOX_WITH_STATISTICS
788	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
789	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
790	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
791	HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
792
793	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
794	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
795	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
796	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
797	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchVmReq, "/HM/CPU%d/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
798	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPgmPoolFlush, "/HM/CPU%d/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
799	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchDma, "/HM/CPU%d/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
800	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
801	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
802	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
803	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
804	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
805	#endif
806	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
807	#ifdef VBOX_WITH_STATISTICS
808	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchNstGstVmexit, "/HM/CPU%d/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
809
810	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
811	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
812	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectReflect, "/HM/CPU%d/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
813	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectConvertDF, "/HM/CPU%d/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
814	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterpret, "/HM/CPU%d/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
815	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectReflectNPF, "/HM/CPU%d/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
816
817	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
818	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
819	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
820	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
821	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
822	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbNstGst, "/HM/CPU%d/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
823	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
824	HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
825	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
826	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
827	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
828	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
829	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
830	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
831	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
832
833	HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
834	HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
835	HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
836
837	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
838	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
839	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
840
841	HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
842	HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
843	HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
844	HM_REG_COUNTER(&pVCpu->hm.s.StatExportHostState, "/HM/CPU%d/Export/HostState", "VM-entry exporting host-state.");
845
846	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
847	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
848	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr, "/HM/CPU%d/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
849
850	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelBase, "/HM/CPU%d/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
851	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit, "/HM/CPU%d/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
852	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr, "/HM/CPU%d/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
853
854	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
855	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
856	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
857	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
858
859	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
860	HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
861	HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
862	#endif
863
864	#undef HM_REG_COUNTER
865
866	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
867
868	/*
869	* Guest Exit reason stats.
870	*/
871	pVCpu->hm.s.paStatExitReason = NULL;
872	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
873	(void **)&pVCpu->hm.s.paStatExitReason);
874	AssertRCReturn(rc, rc);
875
876	if (fCpuSupportsVmx)
877	{
878	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
879	{
880	const char *pszExitName = HMGetVmxExitName(j);
881	if (pszExitName)
882	{
883	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
884	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
885	AssertRCReturn(rc, rc);
886	}
887	}
888	}
889	else
890	{
891	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
892	{
893	const char *pszExitName = HMGetSvmExitName(j);
894	if (pszExitName)
895	{
896	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
897	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
898	AssertRCReturn(rc, rc);
899	}
900	}
901	}
902	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
903	"Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
904	AssertRCReturn(rc, rc);
905	pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
906	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
907	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
908	# else
909	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
910	# endif
911
912	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
913	/*
914	* Nested-guest VM-exit reason stats.
915	*/
916	pVCpu->hm.s.paStatNestedExitReason = NULL;
917	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatNestedExitReason), 0 / uAlignment */, MM_TAG_HM,
918	(void **)&pVCpu->hm.s.paStatNestedExitReason);
919	AssertRCReturn(rc, rc);
920	if (fCpuSupportsVmx)
921	{
922	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
923	{
924	const char *pszExitName = HMGetVmxExitName(j);
925	if (pszExitName)
926	{
927	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
928	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/NestedGuest/Reason/%02x", i, j);
929	AssertRC(rc);
930	}
931	}
932	}
933	else
934	{
935	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
936	{
937	const char *pszExitName = HMGetSvmExitName(j);
938	if (pszExitName)
939	{
940	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
941	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/NestedGuest/Reason/%02x", i, j);
942	AssertRC(rc);
943	}
944	}
945	}
946	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
947	STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/Exit/NestedGuest/Reason/#NPF", i);
948	AssertRCReturn(rc, rc);
949	pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
950	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
951	Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
952	# else
953	Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
954	# endif
955	#endif
956
957	/*
958	* Injected events stats.
959	*/
960	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
961	AssertRCReturn(rc, rc);
962	pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
963	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
964	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
965	# else
966	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
967	# endif
968	for (unsigned j = 0; j < 255; j++)
969	{
970	STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
971	"Injected event.",
972	(j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
973	}
974
975	#endif /* VBOX_WITH_STATISTICS */
976	}
977
978	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
979	/*
980	* Magic marker for searching in crash dumps.
981	*/
982	for (VMCPUID i = 0; i < pVM->cCpus; i++)
983	{
984	PVMCPU pVCpu = &pVM->aCpus[i];
985
986	PVMXVMCSCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsCache;
987	strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
988	pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
989	}
990	#endif
991
992	return VINF_SUCCESS;
993	}
994
995
996	/**
997	* Called when a init phase has completed.
998	*
999	* @returns VBox status code.
1000	* @param pVM The cross context VM structure.
1001	* @param enmWhat The phase that completed.
1002	*/
1003	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1004	{
1005	switch (enmWhat)
1006	{
1007	case VMINITCOMPLETED_RING3:
1008	return hmR3InitFinalizeR3(pVM);
1009	case VMINITCOMPLETED_RING0:
1010	return hmR3InitFinalizeR0(pVM);
1011	default:
1012	return VINF_SUCCESS;
1013	}
1014	}
1015
1016
1017	/**
1018	* Turns off normal raw mode features.
1019	*
1020	* @param pVM The cross context VM structure.
1021	*/
1022	static void hmR3DisableRawMode(PVM pVM)
1023	{
1024	/** @todo r=bird: HM shouldn't be doing this crap. */
1025	/* Reinit the paging mode to force the new shadow mode. */
1026	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1027	{
1028	PVMCPU pVCpu = &pVM->aCpus[i];
1029	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1030	}
1031	}
1032
1033
1034	/**
1035	* Initialize VT-x or AMD-V.
1036	*
1037	* @returns VBox status code.
1038	* @param pVM The cross context VM structure.
1039	*/
1040	static int hmR3InitFinalizeR0(PVM pVM)
1041	{
1042	int rc;
1043
1044	if (!HMIsEnabled(pVM))
1045	return VINF_SUCCESS;
1046
1047	/*
1048	* Hack to allow users to work around broken BIOSes that incorrectly set
1049	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1050	*/
1051	if ( !pVM->hm.s.vmx.fSupported
1052	&& !pVM->hm.s.svm.fSupported
1053	&& pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1054	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1055	{
1056	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1057	pVM->hm.s.svm.fSupported = true;
1058	pVM->hm.s.svm.fIgnoreInUseError = true;
1059	pVM->hm.s.rcInit = VINF_SUCCESS;
1060	}
1061
1062	/*
1063	* Report ring-0 init errors.
1064	*/
1065	if ( !pVM->hm.s.vmx.fSupported
1066	&& !pVM->hm.s.svm.fSupported)
1067	{
1068	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1069	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1070	switch (pVM->hm.s.rcInit)
1071	{
1072	case VERR_VMX_IN_VMX_ROOT_MODE:
1073	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1074	case VERR_VMX_NO_VMX:
1075	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1076	case VERR_VMX_MSR_VMX_DISABLED:
1077	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1078	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1079	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1080	case VERR_VMX_MSR_LOCKING_FAILED:
1081	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1082	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1083	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1084	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1085	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1086
1087	case VERR_SVM_IN_USE:
1088	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1089	case VERR_SVM_NO_SVM:
1090	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1091	case VERR_SVM_DISABLED:
1092	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1093	}
1094	return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1095	}
1096
1097	/*
1098	* Enable VT-x or AMD-V on all host CPUs.
1099	*/
1100	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1101	if (RT_FAILURE(rc))
1102	{
1103	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1104	HMR3CheckError(pVM, rc);
1105	return rc;
1106	}
1107
1108	/*
1109	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1110	* (Main should have taken care of this already)
1111	*/
1112	if (!PDMHasIoApic(pVM))
1113	{
1114	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1115	pVM->hm.s.fTprPatchingAllowed = false;
1116	}
1117
1118	/*
1119	* Check if L1D flush is needed/possible.
1120	*/
1121	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1122	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1123	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1124	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1125	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
1126	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1127
1128	/*
1129	* Check if MDS flush is needed/possible.
1130	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
1131	*/
1132	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
1133	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
1134	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1135	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
1136	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
1137	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
1138	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
1139	{
1140	if (!pVM->hm.s.fMdsClearOnSched)
1141	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
1142	pVM->hm.s.fMdsClearOnVmEntry = false;
1143	}
1144	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1145	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
1146	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1147
1148	/*
1149	* Sync options.
1150	*/
1151	/** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1152	* That will require a little bit of work, of course. */
1153	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1154	{
1155	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1156	PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1157	pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT \| CPUMCTX_WSF_IBPB_ENTRY);
1158	if (pVM->cpum.ro.HostFeatures.fIbpb)
1159	{
1160	if (pVM->hm.s.fIbpbOnVmExit)
1161	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_EXIT;
1162	if (pVM->hm.s.fIbpbOnVmEntry)
1163	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_ENTRY;
1164	}
1165	if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1166	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_L1D_ENTRY;
1167	if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
1168	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_MDS_ENTRY;
1169	if (iCpu == 0)
1170	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1171	pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1172	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1173	}
1174
1175	/*
1176	* Do the vendor specific initialization
1177	*
1178	* Note! We disable release log buffering here since we're doing relatively
1179	* lot of logging and doesn't want to hit the disk with each LogRel
1180	* statement.
1181	*/
1182	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1183	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1184	if (pVM->hm.s.vmx.fSupported)
1185	rc = hmR3InitFinalizeR0Intel(pVM);
1186	else
1187	rc = hmR3InitFinalizeR0Amd(pVM);
1188	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1189	: "HM: VT-x/AMD-V init method: Local\n"));
1190	RTLogRelSetBuffering(fOldBuffered);
1191	pVM->hm.s.fInitialized = true;
1192
1193	return rc;
1194	}
1195
1196
1197	/**
1198	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1199	*/
1200	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1201	{
1202	NOREF(pVM);
1203	NOREF(pvAllocation);
1204	NOREF(GCPhysAllocation);
1205	}
1206
1207
1208	/**
1209	* Returns a description of the VMCS (and associated regions') memory type given the
1210	* IA32_VMX_BASIC MSR.
1211	*
1212	* @returns The descriptive memory type.
1213	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1214	*/
1215	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1216	{
1217	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1218	switch (uMemType)
1219	{
1220	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1221	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1222	}
1223	return "Unknown";
1224	}
1225
1226
1227	/**
1228	* Returns a single-line description of all the activity-states supported by the CPU
1229	* given the IA32_VMX_MISC MSR.
1230	*
1231	* @returns All supported activity states.
1232	* @param uMsrMisc IA32_VMX_MISC MSR value.
1233	*/
1234	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1235	{
1236	static const char * const s_apszActStates[] =
1237	{
1238	"",
1239	" ( HLT )",
1240	" ( SHUTDOWN )",
1241	" ( HLT SHUTDOWN )",
1242	" ( SIPI_WAIT )",
1243	" ( HLT SIPI_WAIT )",
1244	" ( SHUTDOWN SIPI_WAIT )",
1245	" ( HLT SHUTDOWN SIPI_WAIT )"
1246	};
1247	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1248	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1249	return s_apszActStates[idxActStates];
1250	}
1251
1252
1253	/**
1254	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1255	*
1256	* @param fFeatMsr The feature control MSR value.
1257	*/
1258	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1259	{
1260	uint64_t const val = fFeatMsr;
1261	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1262	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1263	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1264	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1265	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1266	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1267	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1268	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1269	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1270	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1271	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1272	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1273	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1274	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1275	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1276	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1277	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1278	}
1279
1280
1281	/**
1282	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1283	*
1284	* @param uBasicMsr The VMX basic MSR value.
1285	*/
1286	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1287	{
1288	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1289	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1290	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1291	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1292	"< 4 GB" : "None"));
1293	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1294	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1295	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1296	LogRel(("HM: Supports true capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1297	}
1298
1299
1300	/**
1301	* Reports MSR_IA32_PINBASED_CTLS to the log.
1302	*
1303	* @param pVmxMsr Pointer to the VMX MSR.
1304	*/
1305	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1306	{
1307	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1308	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1309	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1314	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1315	}
1316
1317
1318	/**
1319	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1320	*
1321	* @param pVmxMsr Pointer to the VMX MSR.
1322	*/
1323	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1324	{
1325	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1326	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1327	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1349	}
1350
1351
1352	/**
1353	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1354	*
1355	* @param pVmxMsr Pointer to the VMX MSR.
1356	*/
1357	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1358	{
1359	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1360	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1361	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1362	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1363	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1365	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1366	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1367	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1368	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1369	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1387	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1388	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1389	}
1390
1391
1392	/**
1393	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1394	*
1395	* @param pVmxMsr Pointer to the VMX MSR.
1396	*/
1397	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1398	{
1399	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1400	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1401	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1408	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1409	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1410	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1411	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1412	}
1413
1414
1415	/**
1416	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1417	*
1418	* @param pVmxMsr Pointer to the VMX MSR.
1419	*/
1420	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1421	{
1422	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1423	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1424	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1425	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1426	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1427	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1428	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1429	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1430	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1431	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1432	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1433	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1434	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1435	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1436	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1437	}
1438
1439
1440	/**
1441	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1442	*
1443	* @param fCaps The VMX EPT/VPID capability MSR value.
1444	*/
1445	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1446	{
1447	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1448	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1449	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1450	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1451	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1452	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1453	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1454	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1455	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1456	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1457	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1458	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1459	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1460	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1461	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1462	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1463	}
1464
1465
1466	/**
1467	* Reports MSR_IA32_VMX_MISC MSR to the log.
1468	*
1469	* @param pVM Pointer to the VM.
1470	* @param fMisc The VMX misc. MSR value.
1471	*/
1472	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1473	{
1474	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1475	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1476	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1477	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1478	else
1479	{
1480	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1481	pVM->hm.s.vmx.cPreemptTimerShift));
1482	}
1483	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1484	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1485	hmR3VmxGetActivityStateAllDesc(fMisc)));
1486	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1487	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1488	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1489	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1490	VMX_MISC_MAX_MSRS(fMisc)));
1491	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1492	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1493	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1494	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1495	}
1496
1497
1498	/**
1499	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1500	*
1501	* @param uVmcsEnum The VMX VMCS enum MSR value.
1502	*/
1503	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1504	{
1505	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1506	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1507	}
1508
1509
1510	/**
1511	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1512	*
1513	* @param uVmFunc The VMX VMFUNC MSR value.
1514	*/
1515	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1516	{
1517	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1518	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1519	}
1520
1521
1522	/**
1523	* Reports VMX CR0, CR4 fixed MSRs.
1524	*
1525	* @param pMsrs Pointer to the VMX MSRs.
1526	*/
1527	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1528	{
1529	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1530	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1531	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1532	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1533	}
1534
1535
1536	/**
1537	* Finish VT-x initialization (after ring-0 init).
1538	*
1539	* @returns VBox status code.
1540	* @param pVM The cross context VM structure.
1541	*/
1542	static int hmR3InitFinalizeR0Intel(PVM pVM)
1543	{
1544	int rc;
1545
1546	Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1547	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1548
1549	LogRel(("HM: Using VT-x implementation 3.0\n"));
1550	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1551	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1552	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostMsrEfer));
1553	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1554
1555	hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1556	hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1557
1558	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1559	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1560	if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1561	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1562
1563	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1564	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1565
1566	if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1567	{
1568	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1569	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1570	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1571	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1572	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1573	}
1574
1575	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1576	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1577	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1578	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1579	if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1580	hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1581	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1582
1583	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1584	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1585	{
1586	PCVMXVMCSINFO pVmcsInfo = &pVM->aCpus[i].hm.s.vmx.VmcsInfo;
1587	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVmcsInfo->HCPhysMsrBitmap));
1588	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVmcsInfo->HCPhysVmcs));
1589	}
1590	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1591	if (pVM->cpum.ro.GuestFeatures.fVmx)
1592	{
1593	LogRel(("HM: Nested-guest:\n"));
1594	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1595	{
1596	PCVMXVMCSINFO pVmcsInfoNstGst = &pVM->aCpus[i].hm.s.vmx.VmcsInfoNstGst;
1597	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVmcsInfoNstGst->HCPhysMsrBitmap));
1598	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVmcsInfoNstGst->HCPhysVmcs));
1599	}
1600	}
1601	#endif
1602
1603	/*
1604	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1605	*/
1606	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1607	\|\| (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1608	VERR_HM_IPE_1);
1609	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1610	\|\| ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1611	&& pVM->hm.s.fNestedPaging),
1612	VERR_HM_IPE_1);
1613
1614	/*
1615	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1616	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1617	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1618	*/
1619	if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1620	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1621	{
1622	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1623	LogRel(("HM: Disabled RDTSCP\n"));
1624	}
1625
1626	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1627	{
1628	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1629	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1630	if (RT_SUCCESS(rc))
1631	{
1632	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1633	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1634	esp. Figure 20-5.*/
1635	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1636	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1637
1638	/* Bit set to 0 means software interrupts are redirected to the
1639	8086 program interrupt handler rather than switching to
1640	protected-mode handler. */
1641	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1642
1643	/* Allow all port IO, so that port IO instructions do not cause
1644	exceptions and would instead cause a VM-exit (based on VT-x's
1645	IO bitmap which we currently configure to always cause an exit). */
1646	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1647	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1648
1649	/*
1650	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1651	* page table used in real and protected mode without paging with EPT.
1652	*/
1653	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1654	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1655	{
1656	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1657	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1658	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1659	\| X86_PDE4M_G;
1660	}
1661
1662	/* We convert it here every time as PCI regions could be reconfigured. */
1663	if (PDMVmmDevHeapIsEnabled(pVM))
1664	{
1665	RTGCPHYS GCPhys;
1666	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1667	AssertRCReturn(rc, rc);
1668	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1669
1670	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1671	AssertRCReturn(rc, rc);
1672	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1673	}
1674	}
1675	else
1676	{
1677	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1678	pVM->hm.s.vmx.pRealModeTSS = NULL;
1679	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1680	return VMSetError(pVM, rc, RT_SRC_POS,
1681	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1682	}
1683	}
1684
1685	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1686	: "HM: Guest support: 32-bit only\n"));
1687
1688	/*
1689	* Call ring-0 to set up the VM.
1690	*/
1691	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1692	if (rc != VINF_SUCCESS)
1693	{
1694	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1695	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1696	{
1697	PVMCPU pVCpu = &pVM->aCpus[i];
1698	LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1699	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1700	}
1701	HMR3CheckError(pVM, rc);
1702	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1703	}
1704
1705	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1706	LogRel(("HM: Enabled VMX\n"));
1707	pVM->hm.s.vmx.fEnabled = true;
1708
1709	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1710
1711	/*
1712	* Change the CPU features.
1713	*/
1714	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1715	if (pVM->hm.s.fAllow64BitGuests)
1716	{
1717	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1718	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1719	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1720	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1721	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1722	}
1723	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1724	(we reuse the host EFER in the switcher). */
1725	/** @todo this needs to be fixed properly!! */
1726	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1727	{
1728	if (pVM->hm.s.vmx.u64HostMsrEfer & MSR_K6_EFER_NXE)
1729	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1730	else
1731	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1732	}
1733
1734	/*
1735	* Log configuration details.
1736	*/
1737	if (pVM->hm.s.fNestedPaging)
1738	{
1739	LogRel(("HM: Enabled nested paging\n"));
1740	if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1741	LogRel(("HM: EPT flush type = Single context\n"));
1742	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1743	LogRel(("HM: EPT flush type = All contexts\n"));
1744	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1745	LogRel(("HM: EPT flush type = Not supported\n"));
1746	else
1747	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1748
1749	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1750	LogRel(("HM: Enabled unrestricted guest execution\n"));
1751
1752	#if HC_ARCH_BITS == 64
1753	if (pVM->hm.s.fLargePages)
1754	{
1755	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1756	PGMSetLargePageUsage(pVM, true);
1757	LogRel(("HM: Enabled large page support\n"));
1758	}
1759	#endif
1760	}
1761	else
1762	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1763
1764	if (pVM->hm.s.vmx.fVpid)
1765	{
1766	LogRel(("HM: Enabled VPID\n"));
1767	if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1768	LogRel(("HM: VPID flush type = Individual addresses\n"));
1769	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1770	LogRel(("HM: VPID flush type = Single context\n"));
1771	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1772	LogRel(("HM: VPID flush type = All contexts\n"));
1773	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1774	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1775	else
1776	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1777	}
1778	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1779	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1780
1781	if (pVM->hm.s.vmx.fUsePreemptTimer)
1782	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1783	else
1784	LogRel(("HM: Disabled VMX-preemption timer\n"));
1785
1786	if (pVM->hm.s.fVirtApicRegs)
1787	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1788
1789	if (pVM->hm.s.fPostedIntrs)
1790	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1791
1792	if (pVM->hm.s.vmx.fUseVmcsShadowing)
1793	{
1794	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1795	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1796	}
1797
1798	return VINF_SUCCESS;
1799	}
1800
1801
1802	/**
1803	* Finish AMD-V initialization (after ring-0 init).
1804	*
1805	* @returns VBox status code.
1806	* @param pVM The cross context VM structure.
1807	*/
1808	static int hmR3InitFinalizeR0Amd(PVM pVM)
1809	{
1810	Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1811
1812	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1813
1814	uint32_t u32Family;
1815	uint32_t u32Model;
1816	uint32_t u32Stepping;
1817	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1818	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1819	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1820	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1821	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1822	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1823	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1824
1825	/*
1826	* Enumerate AMD-V features.
1827	*/
1828	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1829	{
1830	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1831	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1832	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1833	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1834	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1835	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1836	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1837	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1838	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1839	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1840	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1841	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1842	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1843	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1844	#undef HMSVM_REPORT_FEATURE
1845	};
1846
1847	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1848	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1849	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1850	{
1851	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1852	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1853	}
1854	if (fSvmFeatures)
1855	for (unsigned iBit = 0; iBit < 32; iBit++)
1856	if (RT_BIT_32(iBit) & fSvmFeatures)
1857	LogRel(("HM: Reserved bit %u\n", iBit));
1858
1859	/*
1860	* Nested paging is determined in HMR3Init, verify the sanity of that.
1861	*/
1862	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1863	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1864	VERR_HM_IPE_1);
1865
1866	#if 0
1867	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1868	* here. */
1869	if (RTR0IsPostIpiSupport())
1870	pVM->hm.s.fPostedIntrs = true;
1871	#endif
1872
1873	/*
1874	* Call ring-0 to set up the VM.
1875	*/
1876	int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1877	if (rc != VINF_SUCCESS)
1878	{
1879	AssertMsgFailed(("%Rrc\n", rc));
1880	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1881	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1882	}
1883
1884	LogRel(("HM: Enabled SVM\n"));
1885	pVM->hm.s.svm.fEnabled = true;
1886
1887	if (pVM->hm.s.fNestedPaging)
1888	{
1889	LogRel(("HM: Enabled nested paging\n"));
1890
1891	/*
1892	* Enable large pages (2 MB) if applicable.
1893	*/
1894	#if HC_ARCH_BITS == 64
1895	if (pVM->hm.s.fLargePages)
1896	{
1897	PGMSetLargePageUsage(pVM, true);
1898	LogRel(("HM: Enabled large page support\n"));
1899	}
1900	#endif
1901	}
1902
1903	if (pVM->hm.s.fVirtApicRegs)
1904	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1905
1906	if (pVM->hm.s.fPostedIntrs)
1907	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1908
1909	hmR3DisableRawMode(pVM);
1910
1911	/*
1912	* Change the CPU features.
1913	*/
1914	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1915	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1916	if (pVM->hm.s.fAllow64BitGuests)
1917	{
1918	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1919	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1920	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1921	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1922	}
1923	/* Turn on NXE if PAE has been enabled. */
1924	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1925	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1926
1927	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1928	: "HM: Disabled TPR patching\n"));
1929
1930	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1931	: "HM: Guest support: 32-bit only\n"));
1932	return VINF_SUCCESS;
1933	}
1934
1935
1936	/**
1937	* Applies relocations to data and code managed by this
1938	* component. This function will be called at init and
1939	* whenever the VMM need to relocate it self inside the GC.
1940	*
1941	* @param pVM The cross context VM structure.
1942	*/
1943	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1944	{
1945	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1946
1947	/* Fetch the current paging mode during the relocate callback during state loading. */
1948	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1949	{
1950	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1951	{
1952	PVMCPU pVCpu = &pVM->aCpus[i];
1953	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1954	}
1955	}
1956	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1957	if (HMIsEnabled(pVM))
1958	{
1959	switch (PGMGetHostMode(pVM))
1960	{
1961	case PGMMODE_32_BIT:
1962	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1963	break;
1964
1965	case PGMMODE_PAE:
1966	case PGMMODE_PAE_NX:
1967	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1968	break;
1969
1970	default:
1971	AssertFailed();
1972	break;
1973	}
1974	}
1975	#endif
1976	return;
1977	}
1978
1979
1980	/**
1981	* Terminates the HM.
1982	*
1983	* Termination means cleaning up and freeing all resources,
1984	* the VM itself is, at this point, powered off or suspended.
1985	*
1986	* @returns VBox status code.
1987	* @param pVM The cross context VM structure.
1988	*/
1989	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1990	{
1991	if (pVM->hm.s.vmx.pRealModeTSS)
1992	{
1993	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1994	pVM->hm.s.vmx.pRealModeTSS = 0;
1995	}
1996	hmR3TermCPU(pVM);
1997	return 0;
1998	}
1999
2000
2001	/**
2002	* Terminates the per-VCPU HM.
2003	*
2004	* @returns VBox status code.
2005	* @param pVM The cross context VM structure.
2006	*/
2007	static int hmR3TermCPU(PVM pVM)
2008	{
2009	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2010	{
2011	PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
2012
2013	#ifdef VBOX_WITH_STATISTICS
2014	if (pVCpu->hm.s.paStatExitReason)
2015	{
2016	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2017	pVCpu->hm.s.paStatExitReason = NULL;
2018	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2019	}
2020	if (pVCpu->hm.s.paStatInjectedIrqs)
2021	{
2022	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2023	pVCpu->hm.s.paStatInjectedIrqs = NULL;
2024	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2025	}
2026	# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
2027	if (pVCpu->hm.s.paStatNestedExitReason)
2028	{
2029	MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
2030	pVCpu->hm.s.paStatNestedExitReason = NULL;
2031	pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
2032	}
2033	# endif
2034	#endif
2035
2036	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2037	memset(pVCpu->hm.s.vmx.VmcsCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VmcsCache.aMagic));
2038	pVCpu->hm.s.vmx.VmcsCache.uMagic = 0;
2039	pVCpu->hm.s.vmx.VmcsCache.uPos = 0xffffffff;
2040	#endif
2041	}
2042	return 0;
2043	}
2044
2045
2046	/**
2047	* Resets a virtual CPU.
2048	*
2049	* Used by HMR3Reset and CPU hot plugging.
2050	*
2051	* @param pVCpu The cross context virtual CPU structure to reset.
2052	*/
2053	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2054	{
2055	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2056	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2057	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2058
2059	pVCpu->hm.s.fActive = false;
2060	pVCpu->hm.s.Event.fPending = false;
2061	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2062	pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32Obsolete = false;
2063	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2064	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2065	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2066	{
2067	pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32Obsolete = false;
2068	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2069	}
2070	#endif
2071
2072	/* Reset the contents of the read cache. */
2073	PVMXVMCSCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsCache;
2074	for (unsigned j = 0; j < pVmcsCache->Read.cValidEntries; j++)
2075	pVmcsCache->Read.aFieldVal[j] = 0;
2076
2077	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2078	/* Magic marker for searching in crash dumps. */
2079	strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
2080	pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2081	#endif
2082	}
2083
2084
2085	/**
2086	* The VM is being reset.
2087	*
2088	* For the HM component this means that any GDT/LDT/TSS monitors
2089	* needs to be removed.
2090	*
2091	* @param pVM The cross context VM structure.
2092	*/
2093	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2094	{
2095	LogFlow(("HMR3Reset:\n"));
2096
2097	if (HMIsEnabled(pVM))
2098	hmR3DisableRawMode(pVM);
2099
2100	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2101	{
2102	PVMCPU pVCpu = &pVM->aCpus[i];
2103
2104	HMR3ResetCpu(pVCpu);
2105	}
2106
2107	/* Clear all patch information. */
2108	pVM->hm.s.pGuestPatchMem = 0;
2109	pVM->hm.s.pFreeGuestPatchMem = 0;
2110	pVM->hm.s.cbGuestPatchMem = 0;
2111	pVM->hm.s.cPatches = 0;
2112	pVM->hm.s.PatchTree = 0;
2113	pVM->hm.s.fTPRPatchingActive = false;
2114	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2115	}
2116
2117
2118	/**
2119	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2120	*
2121	* @returns VBox strict status code.
2122	* @param pVM The cross context VM structure.
2123	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2124	* @param pvUser Unused.
2125	*/
2126	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2127	{
2128	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2129
2130	/* Only execute the handler on the VCPU the original patch request was issued. */
2131	if (pVCpu->idCpu != idCpu)
2132	return VINF_SUCCESS;
2133
2134	Log(("hmR3RemovePatches\n"));
2135	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2136	{
2137	uint8_t abInstr[15];
2138	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2139	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2140	int rc;
2141
2142	#ifdef LOG_ENABLED
2143	char szOutput[256];
2144	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2145	szOutput, sizeof(szOutput), NULL);
2146	if (RT_SUCCESS(rc))
2147	Log(("Patched instr: %s\n", szOutput));
2148	#endif
2149
2150	/* Check if the instruction is still the same. */
2151	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2152	if (rc != VINF_SUCCESS)
2153	{
2154	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2155	continue; /* swapped out or otherwise removed; skip it. */
2156	}
2157
2158	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2159	{
2160	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2161	continue; /* skip it. */
2162	}
2163
2164	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2165	AssertRC(rc);
2166
2167	#ifdef LOG_ENABLED
2168	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2169	szOutput, sizeof(szOutput), NULL);
2170	if (RT_SUCCESS(rc))
2171	Log(("Original instr: %s\n", szOutput));
2172	#endif
2173	}
2174	pVM->hm.s.cPatches = 0;
2175	pVM->hm.s.PatchTree = 0;
2176	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2177	pVM->hm.s.fTPRPatchingActive = false;
2178	return VINF_SUCCESS;
2179	}
2180
2181
2182	/**
2183	* Worker for enabling patching in a VT-x/AMD-V guest.
2184	*
2185	* @returns VBox status code.
2186	* @param pVM The cross context VM structure.
2187	* @param idCpu VCPU to execute hmR3RemovePatches on.
2188	* @param pPatchMem Patch memory range.
2189	* @param cbPatchMem Size of the memory range.
2190	*/
2191	static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2192	{
2193	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2194	AssertRC(rc);
2195
2196	pVM->hm.s.pGuestPatchMem = pPatchMem;
2197	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2198	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2199	return VINF_SUCCESS;
2200	}
2201
2202
2203	/**
2204	* Enable patching in a VT-x/AMD-V guest
2205	*
2206	* @returns VBox status code.
2207	* @param pVM The cross context VM structure.
2208	* @param pPatchMem Patch memory range.
2209	* @param cbPatchMem Size of the memory range.
2210	*/
2211	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2212	{
2213	VM_ASSERT_EMT(pVM);
2214	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2215	if (pVM->cCpus > 1)
2216	{
2217	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2218	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2219	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2220	AssertRC(rc);
2221	return rc;
2222	}
2223	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2224	}
2225
2226
2227	/**
2228	* Disable patching in a VT-x/AMD-V guest.
2229	*
2230	* @returns VBox status code.
2231	* @param pVM The cross context VM structure.
2232	* @param pPatchMem Patch memory range.
2233	* @param cbPatchMem Size of the memory range.
2234	*/
2235	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2236	{
2237	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2238	RT_NOREF2(pPatchMem, cbPatchMem);
2239
2240	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2241	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2242
2243	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2244	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2245	(void *)(uintptr_t)VMMGetCpuId(pVM));
2246	AssertRC(rc);
2247
2248	pVM->hm.s.pGuestPatchMem = 0;
2249	pVM->hm.s.pFreeGuestPatchMem = 0;
2250	pVM->hm.s.cbGuestPatchMem = 0;
2251	pVM->hm.s.fTPRPatchingActive = false;
2252	return VINF_SUCCESS;
2253	}
2254
2255
2256	/**
2257	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2258	*
2259	* @returns VBox strict status code.
2260	* @param pVM The cross context VM structure.
2261	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2262	* @param pvUser User specified CPU context.
2263	*
2264	*/
2265	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2266	{
2267	/*
2268	* Only execute the handler on the VCPU the original patch request was
2269	* issued. (The other CPU(s) might not yet have switched to protected
2270	* mode, nor have the correct memory context.)
2271	*/
2272	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2273	if (pVCpu->idCpu != idCpu)
2274	return VINF_SUCCESS;
2275
2276	/*
2277	* We're racing other VCPUs here, so don't try patch the instruction twice
2278	* and make sure there is still room for our patch record.
2279	*/
2280	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2281	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2282	if (pPatch)
2283	{
2284	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2285	return VINF_SUCCESS;
2286	}
2287	uint32_t const idx = pVM->hm.s.cPatches;
2288	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2289	{
2290	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2291	return VINF_SUCCESS;
2292	}
2293	pPatch = &pVM->hm.s.aPatches[idx];
2294
2295	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2296
2297	/*
2298	* Disassembler the instruction and get cracking.
2299	*/
2300	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2301	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2302	uint32_t cbOp;
2303	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2304	AssertRC(rc);
2305	if ( rc == VINF_SUCCESS
2306	&& pDis->pCurInstr->uOpcode == OP_MOV
2307	&& cbOp >= 3)
2308	{
2309	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2310
2311	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2312	AssertRC(rc);
2313
2314	pPatch->cbOp = cbOp;
2315
2316	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2317	{
2318	/* write. */
2319	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2320	{
2321	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2322	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2323	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2324	}
2325	else
2326	{
2327	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2328	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2329	pPatch->uSrcOperand = pDis->Param2.uValue;
2330	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2331	}
2332	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2333	AssertRC(rc);
2334
2335	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2336	pPatch->cbNewOp = sizeof(s_abVMMCall);
2337	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2338	}
2339	else
2340	{
2341	/*
2342	* TPR Read.
2343	*
2344	* Found:
2345	* mov eax, dword [fffe0080] (5 bytes)
2346	* Check if next instruction is:
2347	* shr eax, 4
2348	*/
2349	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2350
2351	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2352	uint8_t const cbOpMmio = cbOp;
2353	uint64_t const uSavedRip = pCtx->rip;
2354
2355	pCtx->rip += cbOp;
2356	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2357	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2358	pCtx->rip = uSavedRip;
2359
2360	if ( rc == VINF_SUCCESS
2361	&& pDis->pCurInstr->uOpcode == OP_SHR
2362	&& pDis->Param1.fUse == DISUSE_REG_GEN32
2363	&& pDis->Param1.Base.idxGenReg == idxMmioReg
2364	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
2365	&& pDis->Param2.uValue == 4
2366	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2367	{
2368	uint8_t abInstr[15];
2369
2370	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2371	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2372	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2373	AssertRC(rc);
2374
2375	pPatch->cbOp = cbOpMmio + cbOp;
2376
2377	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2378	abInstr[0] = 0xf0;
2379	abInstr[1] = 0x0f;
2380	abInstr[2] = 0x20;
2381	abInstr[3] = 0xc0 \| pDis->Param1.Base.idxGenReg;
2382	for (unsigned i = 4; i < pPatch->cbOp; i++)
2383	abInstr[i] = 0x90; /* nop */
2384
2385	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2386	AssertRC(rc);
2387
2388	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2389	pPatch->cbNewOp = pPatch->cbOp;
2390	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2391
2392	Log(("Acceptable read/shr candidate!\n"));
2393	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2394	}
2395	else
2396	{
2397	pPatch->enmType = HMTPRINSTR_READ;
2398	pPatch->uDstOperand = idxMmioReg;
2399
2400	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2401	AssertRC(rc);
2402
2403	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2404	pPatch->cbNewOp = sizeof(s_abVMMCall);
2405	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2406	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2407	}
2408	}
2409
2410	pPatch->Core.Key = pCtx->eip;
2411	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2412	AssertRC(rc);
2413
2414	pVM->hm.s.cPatches++;
2415	return VINF_SUCCESS;
2416	}
2417
2418	/*
2419	* Save invalid patch, so we will not try again.
2420	*/
2421	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2422	pPatch->Core.Key = pCtx->eip;
2423	pPatch->enmType = HMTPRINSTR_INVALID;
2424	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2425	AssertRC(rc);
2426	pVM->hm.s.cPatches++;
2427	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2428	return VINF_SUCCESS;
2429	}
2430
2431
2432	/**
2433	* Callback to patch a TPR instruction (jump to generated code).
2434	*
2435	* @returns VBox strict status code.
2436	* @param pVM The cross context VM structure.
2437	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2438	* @param pvUser User specified CPU context.
2439	*
2440	*/
2441	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2442	{
2443	/*
2444	* Only execute the handler on the VCPU the original patch request was
2445	* issued. (The other CPU(s) might not yet have switched to protected
2446	* mode, nor have the correct memory context.)
2447	*/
2448	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2449	if (pVCpu->idCpu != idCpu)
2450	return VINF_SUCCESS;
2451
2452	/*
2453	* We're racing other VCPUs here, so don't try patch the instruction twice
2454	* and make sure there is still room for our patch record.
2455	*/
2456	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2457	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2458	if (pPatch)
2459	{
2460	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2461	return VINF_SUCCESS;
2462	}
2463	uint32_t const idx = pVM->hm.s.cPatches;
2464	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2465	{
2466	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2467	return VINF_SUCCESS;
2468	}
2469	pPatch = &pVM->hm.s.aPatches[idx];
2470
2471	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2472	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2473
2474	/*
2475	* Disassemble the instruction and get cracking.
2476	*/
2477	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2478	uint32_t cbOp;
2479	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2480	AssertRC(rc);
2481	if ( rc == VINF_SUCCESS
2482	&& pDis->pCurInstr->uOpcode == OP_MOV
2483	&& cbOp >= 5)
2484	{
2485	uint8_t aPatch[64];
2486	uint32_t off = 0;
2487
2488	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2489	AssertRC(rc);
2490
2491	pPatch->cbOp = cbOp;
2492	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2493
2494	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2495	{
2496	/*
2497	* TPR write:
2498	*
2499	* push ECX [51]
2500	* push EDX [52]
2501	* push EAX [50]
2502	* xor EDX,EDX [31 D2]
2503	* mov EAX,EAX [89 C0]
2504	* or
2505	* mov EAX,0000000CCh [B8 CC 00 00 00]
2506	* mov ECX,0C0000082h [B9 82 00 00 C0]
2507	* wrmsr [0F 30]
2508	* pop EAX [58]
2509	* pop EDX [5A]
2510	* pop ECX [59]
2511	* jmp return_address [E9 return_address]
2512	*/
2513	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2514
2515	aPatch[off++] = 0x51; /* push ecx */
2516	aPatch[off++] = 0x52; /* push edx */
2517	if (!fUsesEax)
2518	aPatch[off++] = 0x50; /* push eax */
2519	aPatch[off++] = 0x31; /* xor edx, edx */
2520	aPatch[off++] = 0xd2;
2521	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2522	{
2523	if (!fUsesEax)
2524	{
2525	aPatch[off++] = 0x89; /* mov eax, src_reg */
2526	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2527	}
2528	}
2529	else
2530	{
2531	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2532	aPatch[off++] = 0xb8; /* mov eax, immediate */
2533	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2534	off += sizeof(uint32_t);
2535	}
2536	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2537	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2538	off += sizeof(uint32_t);
2539
2540	aPatch[off++] = 0x0f; /* wrmsr */
2541	aPatch[off++] = 0x30;
2542	if (!fUsesEax)
2543	aPatch[off++] = 0x58; /* pop eax */
2544	aPatch[off++] = 0x5a; /* pop edx */
2545	aPatch[off++] = 0x59; /* pop ecx */
2546	}
2547	else
2548	{
2549	/*
2550	* TPR read:
2551	*
2552	* push ECX [51]
2553	* push EDX [52]
2554	* push EAX [50]
2555	* mov ECX,0C0000082h [B9 82 00 00 C0]
2556	* rdmsr [0F 32]
2557	* mov EAX,EAX [89 C0]
2558	* pop EAX [58]
2559	* pop EDX [5A]
2560	* pop ECX [59]
2561	* jmp return_address [E9 return_address]
2562	*/
2563	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2564
2565	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2566	aPatch[off++] = 0x51; /* push ecx */
2567	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2568	aPatch[off++] = 0x52; /* push edx */
2569	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2570	aPatch[off++] = 0x50; /* push eax */
2571
2572	aPatch[off++] = 0x31; /* xor edx, edx */
2573	aPatch[off++] = 0xd2;
2574
2575	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2576	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2577	off += sizeof(uint32_t);
2578
2579	aPatch[off++] = 0x0f; /* rdmsr */
2580	aPatch[off++] = 0x32;
2581
2582	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2583	{
2584	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2585	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2586	}
2587
2588	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2589	aPatch[off++] = 0x58; /* pop eax */
2590	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2591	aPatch[off++] = 0x5a; /* pop edx */
2592	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2593	aPatch[off++] = 0x59; /* pop ecx */
2594	}
2595	aPatch[off++] = 0xe9; /* jmp return_address */
2596	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2597	off += sizeof(RTRCUINTPTR);
2598
2599	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2600	{
2601	/* Write new code to the patch buffer. */
2602	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2603	AssertRC(rc);
2604
2605	#ifdef LOG_ENABLED
2606	uint32_t cbCurInstr;
2607	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2608	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2609	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2610	{
2611	char szOutput[256];
2612	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2613	szOutput, sizeof(szOutput), &cbCurInstr);
2614	if (RT_SUCCESS(rc))
2615	Log(("Patch instr %s\n", szOutput));
2616	else
2617	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2618	}
2619	#endif
2620
2621	pPatch->aNewOpcode[0] = 0xE9;
2622	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2623
2624	/* Overwrite the TPR instruction with a jump. */
2625	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2626	AssertRC(rc);
2627
2628	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2629
2630	pVM->hm.s.pFreeGuestPatchMem += off;
2631	pPatch->cbNewOp = 5;
2632
2633	pPatch->Core.Key = pCtx->eip;
2634	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2635	AssertRC(rc);
2636
2637	pVM->hm.s.cPatches++;
2638	pVM->hm.s.fTPRPatchingActive = true;
2639	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2640	return VINF_SUCCESS;
2641	}
2642
2643	Log(("Ran out of space in our patch buffer!\n"));
2644	}
2645	else
2646	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2647
2648
2649	/*
2650	* Save invalid patch, so we will not try again.
2651	*/
2652	pPatch = &pVM->hm.s.aPatches[idx];
2653	pPatch->Core.Key = pCtx->eip;
2654	pPatch->enmType = HMTPRINSTR_INVALID;
2655	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2656	AssertRC(rc);
2657	pVM->hm.s.cPatches++;
2658	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2659	return VINF_SUCCESS;
2660	}
2661
2662
2663	/**
2664	* Attempt to patch TPR mmio instructions.
2665	*
2666	* @returns VBox status code.
2667	* @param pVM The cross context VM structure.
2668	* @param pVCpu The cross context virtual CPU structure.
2669	*/
2670	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2671	{
2672	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2673	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2674	(void *)(uintptr_t)pVCpu->idCpu);
2675	AssertRC(rc);
2676	return rc;
2677	}
2678
2679
2680	/**
2681	* Checks if we need to reschedule due to VMM device heap changes.
2682	*
2683	* @returns true if a reschedule is required, otherwise false.
2684	* @param pVM The cross context VM structure.
2685	* @param pCtx VM execution context.
2686	*/
2687	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2688	{
2689	/*
2690	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2691	* when the unrestricted guest execution feature is missing (VT-x only).
2692	*/
2693	if ( pVM->hm.s.vmx.fEnabled
2694	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2695	&& CPUMIsGuestInRealModeEx(pCtx)
2696	&& !PDMVmmDevHeapIsEnabled(pVM))
2697	return true;
2698
2699	return false;
2700	}
2701
2702
2703	/**
2704	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2705	* event settings changes.
2706	*
2707	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2708	* function is just updating the VM globals.
2709	*
2710	* @param pVM The VM cross context VM structure.
2711	* @thread EMT(0)
2712	*/
2713	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2714	{
2715	/* Interrupts. */
2716	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2717	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2718
2719	/* CPU Exceptions. */
2720	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2721	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2722	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2723	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2724
2725	/* Common VM exits. */
2726	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2727	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2728	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2729	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2730
2731	/* Vendor specific VM exits. */
2732	if (HMR3IsVmxEnabled(pVM->pUVM))
2733	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2734	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2735	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2736	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2737	else
2738	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2739	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2740	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2741	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2742
2743	/* Done. */
2744	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2745	}
2746
2747
2748	/**
2749	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2750	*
2751	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2752	* per CPU settings.
2753	*
2754	* @param pVM The VM cross context VM structure.
2755	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2756	*/
2757	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2758	{
2759	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2760	}
2761
2762
2763	/**
2764	* Checks if we are currently using hardware acceleration.
2765	*
2766	* @returns true if hardware acceleration is being used, otherwise false.
2767	* @param pVCpu The cross context virtual CPU structure.
2768	*/
2769	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2770	{
2771	return pVCpu->hm.s.fActive;
2772	}
2773
2774
2775	/**
2776	* External interface for querying whether hardware acceleration is enabled.
2777	*
2778	* @returns true if VT-x or AMD-V is being used, otherwise false.
2779	* @param pUVM The user mode VM handle.
2780	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2781	*/
2782	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2783	{
2784	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2785	PVM pVM = pUVM->pVM;
2786	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2787	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2788	}
2789
2790
2791	/**
2792	* External interface for querying whether VT-x is being used.
2793	*
2794	* @returns true if VT-x is being used, otherwise false.
2795	* @param pUVM The user mode VM handle.
2796	* @sa HMR3IsSvmEnabled, HMIsEnabled
2797	*/
2798	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2799	{
2800	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2801	PVM pVM = pUVM->pVM;
2802	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2803	return pVM->hm.s.vmx.fEnabled
2804	&& pVM->hm.s.vmx.fSupported
2805	&& pVM->fHMEnabled;
2806	}
2807
2808
2809	/**
2810	* External interface for querying whether AMD-V is being used.
2811	*
2812	* @returns true if VT-x is being used, otherwise false.
2813	* @param pUVM The user mode VM handle.
2814	* @sa HMR3IsVmxEnabled, HMIsEnabled
2815	*/
2816	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2817	{
2818	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2819	PVM pVM = pUVM->pVM;
2820	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2821	return pVM->hm.s.svm.fEnabled
2822	&& pVM->hm.s.svm.fSupported
2823	&& pVM->fHMEnabled;
2824	}
2825
2826
2827	/**
2828	* Checks if we are currently using nested paging.
2829	*
2830	* @returns true if nested paging is being used, otherwise false.
2831	* @param pUVM The user mode VM handle.
2832	*/
2833	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2834	{
2835	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2836	PVM pVM = pUVM->pVM;
2837	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2838	return pVM->hm.s.fNestedPaging;
2839	}
2840
2841
2842	/**
2843	* Checks if virtualized APIC registers is enabled.
2844	*
2845	* When enabled this feature allows the hardware to access most of the
2846	* APIC registers in the virtual-APIC page without causing VM-exits. See
2847	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2848	*
2849	* @returns true if virtualized APIC registers is enabled, otherwise
2850	* false.
2851	* @param pUVM The user mode VM handle.
2852	*/
2853	VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2854	{
2855	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2856	PVM pVM = pUVM->pVM;
2857	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2858	return pVM->hm.s.fVirtApicRegs;
2859	}
2860
2861
2862	/**
2863	* Checks if APIC posted-interrupt processing is enabled.
2864	*
2865	* This returns whether we can deliver interrupts to the guest without
2866	* leaving guest-context by updating APIC state from host-context.
2867	*
2868	* @returns true if APIC posted-interrupt processing is enabled,
2869	* otherwise false.
2870	* @param pUVM The user mode VM handle.
2871	*/
2872	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2873	{
2874	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2875	PVM pVM = pUVM->pVM;
2876	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2877	return pVM->hm.s.fPostedIntrs;
2878	}
2879
2880
2881	/**
2882	* Checks if we are currently using VPID in VT-x mode.
2883	*
2884	* @returns true if VPID is being used, otherwise false.
2885	* @param pUVM The user mode VM handle.
2886	*/
2887	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2888	{
2889	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2890	PVM pVM = pUVM->pVM;
2891	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2892	return pVM->hm.s.vmx.fVpid;
2893	}
2894
2895
2896	/**
2897	* Checks if we are currently using VT-x unrestricted execution,
2898	* aka UX.
2899	*
2900	* @returns true if UX is being used, otherwise false.
2901	* @param pUVM The user mode VM handle.
2902	*/
2903	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2904	{
2905	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2906	PVM pVM = pUVM->pVM;
2907	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2908	return pVM->hm.s.vmx.fUnrestrictedGuest
2909	\|\| pVM->hm.s.svm.fSupported;
2910	}
2911
2912
2913	/**
2914	* Checks if the VMX-preemption timer is being used.
2915	*
2916	* @returns true if the VMX-preemption timer is being used, otherwise false.
2917	* @param pVM The cross context VM structure.
2918	*/
2919	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2920	{
2921	return HMIsEnabled(pVM)
2922	&& pVM->hm.s.vmx.fEnabled
2923	&& pVM->hm.s.vmx.fUsePreemptTimer;
2924	}
2925
2926
2927	/**
2928	* Helper for HMR3CheckError to log VMCS controls to the release log.
2929	*
2930	* @param idCpu The Virtual CPU ID.
2931	* @param pVmcsInfo The VMCS info. object.
2932	*/
2933	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2934	{
2935	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2936	{
2937	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2943	}
2944	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2945	{
2946	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2966	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2967	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2968	}
2969	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2970	{
2971	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2975	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2976	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2977	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2978	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2989	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2990	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2993	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2994	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2995	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2996	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2997	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2998	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2999	}
3000	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
3001	{
3002	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
3003	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3004	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3005	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3006	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3007	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3008	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3009	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3010	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
3011	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
3012	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
3013	}
3014	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
3015	{
3016	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
3017	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3018	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3019	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3020	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3021	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3022	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3023	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3024	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3025	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3026	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3027	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3028	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3029	}
3030	}
3031
3032
3033	/**
3034	* Check fatal VT-x/AMD-V error and produce some meaningful
3035	* log release message.
3036	*
3037	* @param pVM The cross context VM structure.
3038	* @param iStatusCode VBox status code.
3039	*/
3040	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3041	{
3042	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3043	{
3044	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3045	* might be getting inaccurate values for non-guru'ing EMTs. */
3046	PVMCPU pVCpu = &pVM->aCpus[i];
3047	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3048	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3049	switch (iStatusCode)
3050	{
3051	case VERR_VMX_INVALID_VMCS_PTR:
3052	{
3053	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3054	LogRel(("HM: CPU[%u] %s VMCS active\n", i, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3055	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", i, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3056	pVmcsInfo->HCPhysVmcs));
3057	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3058	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3059	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3060	break;
3061	}
3062
3063	case VERR_VMX_UNABLE_TO_START_VM:
3064	{
3065	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3066	LogRel(("HM: CPU[%u] %s VMCS active\n", i, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3067	LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3068	LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3069
3070	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3071	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3072	{
3073	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3074	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3075	}
3076	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3077	{
3078	hmR3CheckErrorLogVmcsCtls(i, pVmcsInfo);
3079	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVmcsInfo->HCPhysMsrBitmap));
3080	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", i, pVmcsInfo->HCPhysGuestMsrLoad));
3081	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", i, pVmcsInfo->HCPhysGuestMsrStore));
3082	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", i, pVmcsInfo->HCPhysHostMsrLoad));
3083	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", i, pVmcsInfo->cEntryMsrLoad));
3084	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", i, pVmcsInfo->cExitMsrStore));
3085	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", i, pVmcsInfo->cExitMsrLoad));
3086	}
3087	/** @todo Log VM-entry event injection control fields
3088	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3089	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3090	break;
3091	}
3092
3093	case VERR_VMX_INVALID_GUEST_STATE:
3094	{
3095	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3096	hmR3CheckErrorLogVmcsCtls(i, pVmcsInfo);
3097	break;
3098	}
3099
3100	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3101	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3102	case VERR_VMX_INVALID_VMXON_PTR:
3103	case VERR_VMX_UNEXPECTED_EXIT:
3104	case VERR_VMX_INVALID_VMCS_FIELD:
3105	case VERR_SVM_UNKNOWN_EXIT:
3106	case VERR_SVM_UNEXPECTED_EXIT:
3107	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3108	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3109	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3110	break;
3111	}
3112	}
3113
3114	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3115	{
3116	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3117	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3118	}
3119	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3120	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3121	}
3122
3123
3124	/**
3125	* Execute state save operation.
3126	*
3127	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3128	* is because we always save the VM state from ring-3 and thus most HM state
3129	* will be re-synced dynamically at runtime and don't need to be part of the VM
3130	* saved state.
3131	*
3132	* @returns VBox status code.
3133	* @param pVM The cross context VM structure.
3134	* @param pSSM SSM operation handle.
3135	*/
3136	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3137	{
3138	int rc;
3139
3140	Log(("hmR3Save:\n"));
3141
3142	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3143	{
3144	Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3145	if (pVM->cpum.ro.GuestFeatures.fSvm)
3146	{
3147	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3148	rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3149	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3150	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3151	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3152	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3153	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3154	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3155	rc \|= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3156	rc \|= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3157	rc \|= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3158	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3159	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3160	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3161	AssertRCReturn(rc, rc);
3162	}
3163	}
3164
3165	/* Save the guest patch data. */
3166	rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3167	rc \|= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3168	rc \|= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3169
3170	/* Store all the guest patch records too. */
3171	rc \|= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3172	AssertRCReturn(rc, rc);
3173
3174	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3175	{
3176	AssertCompileSize(HMTPRINSTR, 4);
3177	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3178	rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3179	rc \|= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3180	rc \|= SSMR3PutU32(pSSM, pPatch->cbOp);
3181	rc \|= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3182	rc \|= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3183	rc \|= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3184	rc \|= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3185	rc \|= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3186	rc \|= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3187	rc \|= SSMR3PutU32(pSSM, pPatch->cFaults);
3188	AssertRCReturn(rc, rc);
3189	}
3190
3191	return VINF_SUCCESS;
3192	}
3193
3194
3195	/**
3196	* Execute state load operation.
3197	*
3198	* @returns VBox status code.
3199	* @param pVM The cross context VM structure.
3200	* @param pSSM SSM operation handle.
3201	* @param uVersion Data layout version.
3202	* @param uPass The data pass.
3203	*/
3204	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3205	{
3206	int rc;
3207
3208	LogFlowFunc(("uVersion=%u\n", uVersion));
3209	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3210
3211	/*
3212	* Validate version.
3213	*/
3214	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3215	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3216	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3217	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3218	{
3219	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3220	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3221	}
3222
3223	/*
3224	* Load per-VCPU state.
3225	*/
3226	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3227	{
3228	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3229	{
3230	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3231	if (pVM->cpum.ro.GuestFeatures.fSvm)
3232	{
3233	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3234	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3235	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3236	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3237	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3238	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3239	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3240	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3241	rc \|= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3242	rc \|= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3243	rc \|= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3244	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3245	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3246	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3247	AssertRCReturn(rc, rc);
3248	}
3249	}
3250	else
3251	{
3252	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3253	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3254	rc \|= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3255	rc \|= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3256
3257	/* VMX fWasInRealMode related data. */
3258	uint32_t uDummy;
3259	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3260	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3261	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3262	AssertRCReturn(rc, rc);
3263	}
3264	}
3265
3266	/*
3267	* Load TPR patching data.
3268	*/
3269	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3270	{
3271	rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3272	rc \|= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3273	rc \|= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3274
3275	/* Fetch all TPR patch records. */
3276	rc \|= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3277	AssertRCReturn(rc, rc);
3278	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3279	{
3280	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3281	rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3282	rc \|= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3283	rc \|= SSMR3GetU32(pSSM, &pPatch->cbOp);
3284	rc \|= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3285	rc \|= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3286	rc \|= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3287
3288	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3289	pVM->hm.s.fTPRPatchingActive = true;
3290	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3291
3292	rc \|= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3293	rc \|= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3294	rc \|= SSMR3GetU32(pSSM, &pPatch->cFaults);
3295	rc \|= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3296	AssertRCReturn(rc, rc);
3297
3298	LogFlow(("hmR3Load: patch %d\n", i));
3299	LogFlow(("Key = %x\n", pPatch->Core.Key));
3300	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3301	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3302	LogFlow(("type = %d\n", pPatch->enmType));
3303	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3304	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3305	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3306	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3307
3308	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3309	AssertRCReturn(rc, rc);
3310	}
3311	}
3312
3313	return VINF_SUCCESS;
3314	}
3315
3316
3317	/**
3318	* Displays HM info.
3319	*
3320	* @param pVM The cross context VM structure.
3321	* @param pHlp The info helper functions.
3322	* @param pszArgs Arguments, ignored.
3323	*/
3324	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3325	{
3326	NOREF(pszArgs);
3327	PVMCPU pVCpu = VMMGetCpu(pVM);
3328	if (!pVCpu)
3329	pVCpu = &pVM->aCpus[0];
3330
3331	if (HMIsEnabled(pVM))
3332	{
3333	if (pVM->hm.s.vmx.fSupported)
3334	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3335	else
3336	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3337	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3338	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3339	if (pVM->hm.s.vmx.fSupported)
3340	{
3341	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3342	bool const fRealOnV86Active = pVmcsInfo->RealMode.fRealOnV86Active;
3343	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3344
3345	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3346	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3347	if (fRealOnV86Active)
3348	{
3349	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfo->RealMode.Eflags.u32);
3350	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfo->RealMode.AttrCS.u);
3351	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfo->RealMode.AttrSS.u);
3352	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfo->RealMode.AttrDS.u);
3353	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfo->RealMode.AttrES.u);
3354	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfo->RealMode.AttrFS.u);
3355	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfo->RealMode.AttrGS.u);
3356	}
3357	}
3358	}
3359	else
3360	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3361	}
3362
3363
3364	/**
3365	* Displays the HM pending event.
3366	*
3367	* @param pVM The cross context VM structure.
3368	* @param pHlp The info helper functions.
3369	* @param pszArgs Arguments, ignored.
3370	*/
3371	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3372	{
3373	NOREF(pszArgs);
3374	PVMCPU pVCpu = VMMGetCpu(pVM);
3375	if (!pVCpu)
3376	pVCpu = &pVM->aCpus[0];
3377
3378	if (HMIsEnabled(pVM))
3379	{
3380	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3381	if (pVCpu->hm.s.Event.fPending)
3382	{
3383	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3384	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3385	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3386	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3387	}
3388	}
3389	else
3390	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3391	}
3392
3393
3394	/**
3395	* Displays the SVM nested-guest VMCB cache.
3396	*
3397	* @param pVM The cross context VM structure.
3398	* @param pHlp The info helper functions.
3399	* @param pszArgs Arguments, ignored.
3400	*/
3401	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3402	{
3403	NOREF(pszArgs);
3404	PVMCPU pVCpu = VMMGetCpu(pVM);
3405	if (!pVCpu)
3406	pVCpu = &pVM->aCpus[0];
3407
3408	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3409	if ( fSvmEnabled
3410	&& pVM->cpum.ro.GuestFeatures.fSvm)
3411	{
3412	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3413	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3414	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3415	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3416	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3417	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3418	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3419	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3420	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3421	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3422	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3423	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3424	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3425	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3426	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3427	}
3428	else
3429	{
3430	if (!fSvmEnabled)
3431	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3432	else
3433	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3434	}
3435	}
3436

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 80074

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