1 | /* $Id: HM.cpp 72555 2018-06-14 21:28:31Z vboxsync $ */
|
---|
2 | /** @file
|
---|
3 | * HM - Intel/AMD VM Hardware Support Manager.
|
---|
4 | */
|
---|
5 |
|
---|
6 | /*
|
---|
7 | * Copyright (C) 2006-2017 Oracle Corporation
|
---|
8 | *
|
---|
9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
---|
10 | * available from http://www.virtualbox.org. This file is free software;
|
---|
11 | * you can redistribute it and/or modify it under the terms of the GNU
|
---|
12 | * General Public License (GPL) as published by the Free Software
|
---|
13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
---|
14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
---|
15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
---|
16 | */
|
---|
17 |
|
---|
18 | /** @page pg_hm HM - Hardware Assisted Virtualization Manager
|
---|
19 | *
|
---|
20 | * The HM manages guest execution using the VT-x and AMD-V CPU hardware
|
---|
21 | * extensions.
|
---|
22 | *
|
---|
23 | * {summary of what HM does}
|
---|
24 | *
|
---|
25 | * Hardware assisted virtualization manager was originally abbreviated HWACCM,
|
---|
26 | * however that was cumbersome to write and parse for such a central component,
|
---|
27 | * so it was shortened to HM when refactoring the code in the 4.3 development
|
---|
28 | * cycle.
|
---|
29 | *
|
---|
30 | * {add sections with more details}
|
---|
31 | *
|
---|
32 | * @sa @ref grp_hm
|
---|
33 | */
|
---|
34 |
|
---|
35 |
|
---|
36 | /*********************************************************************************************************************************
|
---|
37 | * Header Files *
|
---|
38 | *********************************************************************************************************************************/
|
---|
39 | #define LOG_GROUP LOG_GROUP_HM
|
---|
40 | #include <VBox/vmm/cpum.h>
|
---|
41 | #include <VBox/vmm/stam.h>
|
---|
42 | #include <VBox/vmm/mm.h>
|
---|
43 | #include <VBox/vmm/pdmapi.h>
|
---|
44 | #include <VBox/vmm/pgm.h>
|
---|
45 | #include <VBox/vmm/ssm.h>
|
---|
46 | #include <VBox/vmm/trpm.h>
|
---|
47 | #include <VBox/vmm/dbgf.h>
|
---|
48 | #include <VBox/vmm/iom.h>
|
---|
49 | #include <VBox/vmm/iem.h>
|
---|
50 | #include <VBox/vmm/patm.h>
|
---|
51 | #include <VBox/vmm/csam.h>
|
---|
52 | #include <VBox/vmm/selm.h>
|
---|
53 | #include <VBox/vmm/nem.h>
|
---|
54 | #ifdef VBOX_WITH_REM
|
---|
55 | # include <VBox/vmm/rem.h>
|
---|
56 | #endif
|
---|
57 | #include <VBox/vmm/hm_vmx.h>
|
---|
58 | #include <VBox/vmm/hm_svm.h>
|
---|
59 | #include "HMInternal.h"
|
---|
60 | #include <VBox/vmm/vm.h>
|
---|
61 | #include <VBox/vmm/uvm.h>
|
---|
62 | #include <VBox/err.h>
|
---|
63 | #include <VBox/param.h>
|
---|
64 |
|
---|
65 | #include <iprt/assert.h>
|
---|
66 | #include <VBox/log.h>
|
---|
67 | #include <iprt/asm.h>
|
---|
68 | #include <iprt/asm-amd64-x86.h>
|
---|
69 | #include <iprt/env.h>
|
---|
70 | #include <iprt/thread.h>
|
---|
71 |
|
---|
72 |
|
---|
73 | /*********************************************************************************************************************************
|
---|
74 | * Global Variables *
|
---|
75 | *********************************************************************************************************************************/
|
---|
76 | #define EXIT_REASON(def, val, str) #def " - " #val " - " str
|
---|
77 | #define EXIT_REASON_NIL() NULL
|
---|
78 | /** Exit reason descriptions for VT-x, used to describe statistics. */
|
---|
79 | static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
|
---|
80 | {
|
---|
81 | EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
|
---|
82 | EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
|
---|
83 | EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
|
---|
84 | EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
|
---|
85 | EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
|
---|
86 | EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
|
---|
87 | EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
|
---|
88 | EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
|
---|
89 | EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
|
---|
90 | EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
|
---|
91 | EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
|
---|
92 | EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
|
---|
93 | EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
|
---|
94 | EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
|
---|
95 | EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
|
---|
96 | EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
|
---|
97 | EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
|
---|
98 | EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
|
---|
99 | EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
|
---|
100 | EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
|
---|
101 | EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
|
---|
102 | EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
|
---|
103 | EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
|
---|
104 | EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
|
---|
105 | EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
|
---|
106 | EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
|
---|
107 | EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
|
---|
108 | EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
|
---|
109 | EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
|
---|
110 | EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
|
---|
111 | EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
|
---|
112 | EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
|
---|
113 | EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
|
---|
114 | EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
|
---|
115 | EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
|
---|
116 | EXIT_REASON_NIL(),
|
---|
117 | EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
|
---|
118 | EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
|
---|
119 | EXIT_REASON_NIL(),
|
---|
120 | EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
|
---|
121 | EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
|
---|
122 | EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
|
---|
123 | EXIT_REASON_NIL(),
|
---|
124 | EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
|
---|
125 | EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
|
---|
126 | EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
|
---|
127 | EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
|
---|
128 | EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
|
---|
129 | EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
|
---|
130 | EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
|
---|
131 | EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
|
---|
132 | EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
|
---|
133 | EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
|
---|
134 | EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
|
---|
135 | EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
|
---|
136 | EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
|
---|
137 | EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
|
---|
138 | EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
|
---|
139 | EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
|
---|
140 | EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
|
---|
141 | EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
|
---|
142 | EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
|
---|
143 | EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
|
---|
144 | EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
|
---|
145 | EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
|
---|
146 | };
|
---|
147 | /** Array index of the last valid VT-x exit reason. */
|
---|
148 | #define MAX_EXITREASON_VTX 64
|
---|
149 |
|
---|
150 | /** A partial list of Exit reason descriptions for AMD-V, used to describe
|
---|
151 | * statistics.
|
---|
152 | *
|
---|
153 | * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
|
---|
154 | * this array doesn't contain the entire set of exit reasons, we
|
---|
155 | * handle them via hmSvmGetSpecialExitReasonDesc(). */
|
---|
156 | static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
|
---|
157 | {
|
---|
158 | EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
|
---|
159 | EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
|
---|
160 | EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
|
---|
161 | EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
|
---|
162 | EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
|
---|
163 | EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
|
---|
164 | EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
|
---|
165 | EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
|
---|
166 | EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
|
---|
167 | EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
|
---|
168 | EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
|
---|
169 | EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
|
---|
170 | EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
|
---|
171 | EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
|
---|
172 | EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
|
---|
173 | EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
|
---|
174 | EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
|
---|
175 | EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
|
---|
176 | EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
|
---|
177 | EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
|
---|
178 | EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
|
---|
179 | EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
|
---|
180 | EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
|
---|
181 | EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
|
---|
182 | EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
|
---|
183 | EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
|
---|
184 | EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
|
---|
185 | EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
|
---|
186 | EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
|
---|
187 | EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
|
---|
188 | EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
|
---|
189 | EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
|
---|
190 | EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
|
---|
191 | EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
|
---|
192 | EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
|
---|
193 | EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
|
---|
194 | EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
|
---|
195 | EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
|
---|
196 | EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
|
---|
197 | EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
|
---|
198 | EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
|
---|
199 | EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
|
---|
200 | EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
|
---|
201 | EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
|
---|
202 | EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
|
---|
203 | EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
|
---|
204 | EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
|
---|
205 | EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
|
---|
206 | EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
|
---|
207 | EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
|
---|
208 | EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
|
---|
209 | EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
|
---|
210 | EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
|
---|
211 | EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
|
---|
212 | EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
|
---|
213 | EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
|
---|
214 | EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
|
---|
215 | EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
|
---|
216 | EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
|
---|
217 | EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
|
---|
218 | EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
|
---|
219 | EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
|
---|
220 | EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
|
---|
221 | EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
|
---|
222 | EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
|
---|
223 | EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
|
---|
224 | EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
|
---|
225 | EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
|
---|
226 | EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
|
---|
227 | EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
|
---|
228 | EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
|
---|
229 | EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
|
---|
230 | EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
|
---|
231 | EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
|
---|
232 | EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
|
---|
233 | EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
|
---|
234 | EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
|
---|
235 | EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
|
---|
236 | EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
|
---|
237 | EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
|
---|
238 | EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
|
---|
239 | EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
|
---|
240 | EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
|
---|
241 | EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
|
---|
242 | EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
|
---|
243 | EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
|
---|
244 | EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
|
---|
245 | EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
|
---|
246 | EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
|
---|
247 | EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
|
---|
248 | EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1A)."),
|
---|
249 | EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1B)."),
|
---|
250 | EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1C)."),
|
---|
251 | EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1D)."),
|
---|
252 | EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
|
---|
253 | EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
|
---|
254 | EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
|
---|
255 | EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
|
---|
256 | EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
|
---|
257 | EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
|
---|
258 | EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
|
---|
259 | EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
|
---|
260 | EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
|
---|
261 | EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
|
---|
262 | EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
|
---|
263 | EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
|
---|
264 | EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
|
---|
265 | EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
|
---|
266 | EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
|
---|
267 | EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
|
---|
268 | EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
|
---|
269 | EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
|
---|
270 | EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
|
---|
271 | EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
|
---|
272 | EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
|
---|
273 | EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
|
---|
274 | EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
|
---|
275 | EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
|
---|
276 | EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
|
---|
277 | EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
|
---|
278 | EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
|
---|
279 | EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
|
---|
280 | EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
|
---|
281 | EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
|
---|
282 | EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
|
---|
283 | EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
|
---|
284 | EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
|
---|
285 | EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
|
---|
286 | EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
|
---|
287 | EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
|
---|
288 | EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
|
---|
289 | EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
|
---|
290 | EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
|
---|
291 | EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
|
---|
292 | EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
|
---|
293 | EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
|
---|
294 | EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
|
---|
295 | EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
|
---|
296 | EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
|
---|
297 | EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
|
---|
298 | EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
|
---|
299 | EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
|
---|
300 | };
|
---|
301 | /** Array index of the last valid AMD-V exit reason. */
|
---|
302 | #define MAX_EXITREASON_AMDV 141
|
---|
303 |
|
---|
304 | /** Special exit reasons not covered in the array above. */
|
---|
305 | #define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
|
---|
306 | #define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
|
---|
307 | #define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
|
---|
308 |
|
---|
309 | /**
|
---|
310 | * Gets the SVM exit reason if it's one of the reasons not present in the @c
|
---|
311 | * g_apszAmdVExitReasons array.
|
---|
312 | *
|
---|
313 | * @returns The exit reason or NULL if unknown.
|
---|
314 | * @param uExit The exit.
|
---|
315 | */
|
---|
316 | DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
|
---|
317 | {
|
---|
318 | switch (uExit)
|
---|
319 | {
|
---|
320 | case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
|
---|
321 | case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
|
---|
322 | case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
|
---|
323 | }
|
---|
324 | return EXIT_REASON_NIL();
|
---|
325 | }
|
---|
326 | #undef EXIT_REASON_NIL
|
---|
327 | #undef EXIT_REASON
|
---|
328 |
|
---|
329 | /** @def HMVMX_REPORT_FEATURE
|
---|
330 | * Reports VT-x feature to the release log.
|
---|
331 | *
|
---|
332 | * @param allowed1 Mask of allowed feature bits.
|
---|
333 | * @param disallowed0 Mask of disallowed feature bits.
|
---|
334 | * @param strdesc The description string to report.
|
---|
335 | * @param featflag Mask of the feature to report.
|
---|
336 | */
|
---|
337 | #define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
|
---|
338 | do { \
|
---|
339 | if ((allowed1) & (featflag)) \
|
---|
340 | { \
|
---|
341 | if ((disallowed0) & (featflag)) \
|
---|
342 | LogRel(("HM: " strdesc " (must be set)\n")); \
|
---|
343 | else \
|
---|
344 | LogRel(("HM: " strdesc "\n")); \
|
---|
345 | } \
|
---|
346 | else \
|
---|
347 | LogRel(("HM: " strdesc " (must be cleared)\n")); \
|
---|
348 | } while (0)
|
---|
349 |
|
---|
350 | /** @def HMVMX_REPORT_ALLOWED_FEATURE
|
---|
351 | * Reports an allowed VT-x feature to the release log.
|
---|
352 | *
|
---|
353 | * @param allowed1 Mask of allowed feature bits.
|
---|
354 | * @param strdesc The description string to report.
|
---|
355 | * @param featflag Mask of the feature to report.
|
---|
356 | */
|
---|
357 | #define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
|
---|
358 | do { \
|
---|
359 | if ((allowed1) & (featflag)) \
|
---|
360 | LogRel(("HM: " strdesc "\n")); \
|
---|
361 | else \
|
---|
362 | LogRel(("HM: " strdesc " not supported\n")); \
|
---|
363 | } while (0)
|
---|
364 |
|
---|
365 | /** @def HMVMX_REPORT_MSR_CAPABILITY
|
---|
366 | * Reports MSR feature capability.
|
---|
367 | *
|
---|
368 | * @param msrcaps Mask of MSR feature bits.
|
---|
369 | * @param strdesc The description string to report.
|
---|
370 | * @param cap Mask of the feature to report.
|
---|
371 | */
|
---|
372 | #define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
|
---|
373 | do { \
|
---|
374 | if ((msrcaps) & (cap)) \
|
---|
375 | LogRel(("HM: " strdesc "\n")); \
|
---|
376 | } while (0)
|
---|
377 |
|
---|
378 |
|
---|
379 | /*********************************************************************************************************************************
|
---|
380 | * Internal Functions *
|
---|
381 | *********************************************************************************************************************************/
|
---|
382 | static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
|
---|
383 | static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
|
---|
384 | static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
|
---|
385 | static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
|
---|
386 | static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
|
---|
387 | static int hmR3InitCPU(PVM pVM);
|
---|
388 | static int hmR3InitFinalizeR0(PVM pVM);
|
---|
389 | static int hmR3InitFinalizeR0Intel(PVM pVM);
|
---|
390 | static int hmR3InitFinalizeR0Amd(PVM pVM);
|
---|
391 | static int hmR3TermCPU(PVM pVM);
|
---|
392 |
|
---|
393 |
|
---|
394 |
|
---|
395 | /**
|
---|
396 | * Initializes the HM.
|
---|
397 | *
|
---|
398 | * This is the very first component to really do init after CFGM so that we can
|
---|
399 | * establish the predominat execution engine for the VM prior to initializing
|
---|
400 | * other modules. It takes care of NEM initialization if needed (HM disabled or
|
---|
401 | * not available in HW).
|
---|
402 | *
|
---|
403 | * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
|
---|
404 | * hypervisor API via NEM, and then back on raw-mode if that isn't available
|
---|
405 | * either. The fallback to raw-mode will not happen if /HM/HMForced is set
|
---|
406 | * (like for guest using SMP or 64-bit as well as for complicated guest like OS
|
---|
407 | * X, OS/2 and others).
|
---|
408 | *
|
---|
409 | * Note that a lot of the set up work is done in ring-0 and thus postponed till
|
---|
410 | * the ring-3 and ring-0 callback to HMR3InitCompleted.
|
---|
411 | *
|
---|
412 | * @returns VBox status code.
|
---|
413 | * @param pVM The cross context VM structure.
|
---|
414 | *
|
---|
415 | * @remarks Be careful with what we call here, since most of the VMM components
|
---|
416 | * are uninitialized.
|
---|
417 | */
|
---|
418 | VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
|
---|
419 | {
|
---|
420 | LogFlow(("HMR3Init\n"));
|
---|
421 |
|
---|
422 | /*
|
---|
423 | * Assert alignment and sizes.
|
---|
424 | */
|
---|
425 | AssertCompileMemberAlignment(VM, hm.s, 32);
|
---|
426 | AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
|
---|
427 |
|
---|
428 | /*
|
---|
429 | * Register the saved state data unit.
|
---|
430 | */
|
---|
431 | int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
|
---|
432 | NULL, NULL, NULL,
|
---|
433 | NULL, hmR3Save, NULL,
|
---|
434 | NULL, hmR3Load, NULL);
|
---|
435 | if (RT_FAILURE(rc))
|
---|
436 | return rc;
|
---|
437 |
|
---|
438 | /*
|
---|
439 | * Register info handlers.
|
---|
440 | */
|
---|
441 | rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
|
---|
442 | DBGFINFO_FLAGS_ALL_EMTS);
|
---|
443 | AssertRCReturn(rc, rc);
|
---|
444 |
|
---|
445 | rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
|
---|
446 | DBGFINFO_FLAGS_ALL_EMTS);
|
---|
447 | AssertRCReturn(rc, rc);
|
---|
448 |
|
---|
449 | rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
|
---|
450 | hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
|
---|
451 | AssertRCReturn(rc, rc);
|
---|
452 |
|
---|
453 | /*
|
---|
454 | * Read configuration.
|
---|
455 | */
|
---|
456 | PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
|
---|
457 |
|
---|
458 | /*
|
---|
459 | * Validate the HM settings.
|
---|
460 | */
|
---|
461 | rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
|
---|
462 | "HMForced"
|
---|
463 | "|UseNEMInstead"
|
---|
464 | "|FallbackToNEM"
|
---|
465 | "|EnableNestedPaging"
|
---|
466 | "|EnableUX"
|
---|
467 | "|EnableLargePages"
|
---|
468 | "|EnableVPID"
|
---|
469 | "|IBPBOnVMExit"
|
---|
470 | "|IBPBOnVMEntry"
|
---|
471 | "|SpecCtrlByHost"
|
---|
472 | "|TPRPatchingEnabled"
|
---|
473 | "|64bitEnabled"
|
---|
474 | "|Exclusive"
|
---|
475 | "|MaxResumeLoops"
|
---|
476 | "|VmxPleGap"
|
---|
477 | "|VmxPleWindow"
|
---|
478 | "|UseVmxPreemptTimer"
|
---|
479 | "|SvmPauseFilter"
|
---|
480 | "|SvmPauseFilterThreshold"
|
---|
481 | "|SvmVirtVmsaveVmload"
|
---|
482 | "|SvmVGif",
|
---|
483 | "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
|
---|
484 | if (RT_FAILURE(rc))
|
---|
485 | return rc;
|
---|
486 |
|
---|
487 | /** @cfgm{/HM/HMForced, bool, false}
|
---|
488 | * Forces hardware virtualization, no falling back on raw-mode. HM must be
|
---|
489 | * enabled, i.e. /HMEnabled must be true. */
|
---|
490 | bool fHMForced;
|
---|
491 | #ifdef VBOX_WITH_RAW_MODE
|
---|
492 | rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
|
---|
493 | AssertRCReturn(rc, rc);
|
---|
494 | AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
|
---|
495 | VERR_INVALID_PARAMETER);
|
---|
496 | # if defined(RT_OS_DARWIN)
|
---|
497 | if (pVM->fHMEnabled)
|
---|
498 | fHMForced = true;
|
---|
499 | # endif
|
---|
500 | AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
|
---|
501 | VERR_INVALID_PARAMETER);
|
---|
502 | if (pVM->cCpus > 1)
|
---|
503 | fHMForced = true;
|
---|
504 | #else /* !VBOX_WITH_RAW_MODE */
|
---|
505 | AssertRelease(pVM->fHMEnabled);
|
---|
506 | fHMForced = true;
|
---|
507 | #endif /* !VBOX_WITH_RAW_MODE */
|
---|
508 |
|
---|
509 | /** @cfgm{/HM/UseNEMInstead, bool, true}
|
---|
510 | * Don't use HM, use NEM instead. */
|
---|
511 | bool fUseNEMInstead = false;
|
---|
512 | rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
|
---|
513 | AssertRCReturn(rc, rc);
|
---|
514 | if (fUseNEMInstead && pVM->fHMEnabled)
|
---|
515 | {
|
---|
516 | LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
|
---|
517 | pVM->fHMEnabled = false;
|
---|
518 | }
|
---|
519 |
|
---|
520 | /** @cfgm{/HM/FallbackToNEM, bool, true}
|
---|
521 | * Enables fallback on NEM. */
|
---|
522 | bool fFallbackToNEM = true;
|
---|
523 | rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
|
---|
524 | AssertRCReturn(rc, rc);
|
---|
525 |
|
---|
526 | /** @cfgm{/HM/EnableNestedPaging, bool, false}
|
---|
527 | * Enables nested paging (aka extended page tables). */
|
---|
528 | rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
|
---|
529 | AssertRCReturn(rc, rc);
|
---|
530 |
|
---|
531 | /** @cfgm{/HM/EnableUX, bool, true}
|
---|
532 | * Enables the VT-x unrestricted execution feature. */
|
---|
533 | rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
|
---|
534 | AssertRCReturn(rc, rc);
|
---|
535 |
|
---|
536 | /** @cfgm{/HM/EnableLargePages, bool, false}
|
---|
537 | * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
|
---|
538 | * page table walking and maybe better TLB hit rate in some cases. */
|
---|
539 | rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
|
---|
540 | AssertRCReturn(rc, rc);
|
---|
541 |
|
---|
542 | /** @cfgm{/HM/EnableVPID, bool, false}
|
---|
543 | * Enables the VT-x VPID feature. */
|
---|
544 | rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
|
---|
545 | AssertRCReturn(rc, rc);
|
---|
546 |
|
---|
547 | /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
|
---|
548 | * Enables TPR patching for 32-bit windows guests with IO-APIC. */
|
---|
549 | rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
|
---|
550 | AssertRCReturn(rc, rc);
|
---|
551 |
|
---|
552 | /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
|
---|
553 | * Enables AMD64 cpu features.
|
---|
554 | * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
|
---|
555 | * already have the support. */
|
---|
556 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
557 | rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
|
---|
558 | AssertLogRelRCReturn(rc, rc);
|
---|
559 | #else
|
---|
560 | pVM->hm.s.fAllow64BitGuests = false;
|
---|
561 | #endif
|
---|
562 |
|
---|
563 | /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
|
---|
564 | * The pause-filter exiting gap in TSC ticks. When the number of ticks between
|
---|
565 | * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
|
---|
566 | * latest PAUSE instruction to be start of a new PAUSE loop.
|
---|
567 | */
|
---|
568 | rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
|
---|
569 | AssertRCReturn(rc, rc);
|
---|
570 |
|
---|
571 | /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
|
---|
572 | * The pause-filter exiting window in TSC ticks. When the number of ticks
|
---|
573 | * between the current PAUSE instruction and first PAUSE of a loop exceeds
|
---|
574 | * VmxPleWindow, a VM-exit is triggered.
|
---|
575 | *
|
---|
576 | * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
|
---|
577 | */
|
---|
578 | rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
|
---|
579 | AssertRCReturn(rc, rc);
|
---|
580 |
|
---|
581 | /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
|
---|
582 | * A counter that is decrement each time a PAUSE instruction is executed by the
|
---|
583 | * guest. When the counter is 0, a \#VMEXIT is triggered.
|
---|
584 | *
|
---|
585 | * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
|
---|
586 | */
|
---|
587 | rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
|
---|
588 | AssertRCReturn(rc, rc);
|
---|
589 |
|
---|
590 | /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
|
---|
591 | * The pause filter threshold in ticks. When the elapsed time (in ticks) between
|
---|
592 | * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
|
---|
593 | * PauseFilter count is reset to its initial value. However, if PAUSE is
|
---|
594 | * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
|
---|
595 | * be triggered.
|
---|
596 | *
|
---|
597 | * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
|
---|
598 | * activated.
|
---|
599 | */
|
---|
600 | rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
|
---|
601 | AssertRCReturn(rc, rc);
|
---|
602 |
|
---|
603 | /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
|
---|
604 | * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
|
---|
605 | * available. */
|
---|
606 | rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
|
---|
607 | AssertRCReturn(rc, rc);
|
---|
608 |
|
---|
609 | /** @cfgm{/HM/SvmVGif, bool, true}
|
---|
610 | * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
|
---|
611 | * if it's available. */
|
---|
612 | rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
|
---|
613 | AssertRCReturn(rc, rc);
|
---|
614 |
|
---|
615 | /** @cfgm{/HM/Exclusive, bool}
|
---|
616 | * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
|
---|
617 | * global init for each host CPU. If false, we do local init each time we wish
|
---|
618 | * to execute guest code.
|
---|
619 | *
|
---|
620 | * On Windows, default is false due to the higher risk of conflicts with other
|
---|
621 | * hypervisors.
|
---|
622 | *
|
---|
623 | * On Mac OS X, this setting is ignored since the code does not handle local
|
---|
624 | * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
|
---|
625 | */
|
---|
626 | #if defined(RT_OS_DARWIN)
|
---|
627 | pVM->hm.s.fGlobalInit = true;
|
---|
628 | #else
|
---|
629 | rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
|
---|
630 | # if defined(RT_OS_WINDOWS)
|
---|
631 | false
|
---|
632 | # else
|
---|
633 | true
|
---|
634 | # endif
|
---|
635 | );
|
---|
636 | AssertLogRelRCReturn(rc, rc);
|
---|
637 | #endif
|
---|
638 |
|
---|
639 | /** @cfgm{/HM/MaxResumeLoops, uint32_t}
|
---|
640 | * The number of times to resume guest execution before we forcibly return to
|
---|
641 | * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
|
---|
642 | * determines the default value. */
|
---|
643 | rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
|
---|
644 | AssertLogRelRCReturn(rc, rc);
|
---|
645 |
|
---|
646 | /** @cfgm{/HM/UseVmxPreemptTimer, bool}
|
---|
647 | * Whether to make use of the VMX-preemption timer feature of the CPU if it's
|
---|
648 | * available. */
|
---|
649 | rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
|
---|
650 | AssertLogRelRCReturn(rc, rc);
|
---|
651 |
|
---|
652 | /** @cfgm{/HM/IBPBOnVMExit, bool}
|
---|
653 | * Costly paranoia setting. */
|
---|
654 | rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
|
---|
655 | AssertLogRelRCReturn(rc, rc);
|
---|
656 |
|
---|
657 | /** @cfgm{/HM/IBPBOnVMEntry, bool}
|
---|
658 | * Costly paranoia setting. */
|
---|
659 | rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
|
---|
660 | AssertLogRelRCReturn(rc, rc);
|
---|
661 |
|
---|
662 | /** @cfgm{/HM/SpecCtrlByHost, bool}
|
---|
663 | * Another expensive paranoia setting. */
|
---|
664 | rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
|
---|
665 | AssertLogRelRCReturn(rc, rc);
|
---|
666 |
|
---|
667 | /*
|
---|
668 | * Check if VT-x or AMD-v support according to the users wishes.
|
---|
669 | */
|
---|
670 | /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
|
---|
671 | * VERR_SVM_IN_USE. */
|
---|
672 | if (pVM->fHMEnabled)
|
---|
673 | {
|
---|
674 | uint32_t fCaps;
|
---|
675 | rc = SUPR3QueryVTCaps(&fCaps);
|
---|
676 | if (RT_SUCCESS(rc))
|
---|
677 | {
|
---|
678 | if (fCaps & SUPVTCAPS_AMD_V)
|
---|
679 | {
|
---|
680 | LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
|
---|
681 | pVM->hm.s.svm.fSupported = true;
|
---|
682 | VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
|
---|
683 | }
|
---|
684 | else if (fCaps & SUPVTCAPS_VT_X)
|
---|
685 | {
|
---|
686 | const char *pszWhy;
|
---|
687 | rc = SUPR3QueryVTxSupported(&pszWhy);
|
---|
688 | if (RT_SUCCESS(rc))
|
---|
689 | {
|
---|
690 | LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
|
---|
691 | fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
|
---|
692 | fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
|
---|
693 | (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
|
---|
694 | pVM->hm.s.vmx.fSupported = true;
|
---|
695 | VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
|
---|
696 | }
|
---|
697 | else
|
---|
698 | {
|
---|
699 | /*
|
---|
700 | * Before failing, try fallback to NEM if we're allowed to do that.
|
---|
701 | */
|
---|
702 | pVM->fHMEnabled = false;
|
---|
703 | Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
|
---|
704 | if (fFallbackToNEM)
|
---|
705 | {
|
---|
706 | LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
|
---|
707 | int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
|
---|
708 |
|
---|
709 | ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
|
---|
710 | if ( RT_SUCCESS(rc2)
|
---|
711 | && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
|
---|
712 | rc = VINF_SUCCESS;
|
---|
713 | }
|
---|
714 | if (RT_FAILURE(rc))
|
---|
715 | {
|
---|
716 | if (fHMForced)
|
---|
717 | return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
|
---|
718 |
|
---|
719 | /* Fall back to raw-mode. */
|
---|
720 | LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
|
---|
721 | VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
|
---|
722 | }
|
---|
723 | }
|
---|
724 | }
|
---|
725 | else
|
---|
726 | AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
|
---|
727 | VERR_INTERNAL_ERROR_5);
|
---|
728 |
|
---|
729 | /*
|
---|
730 | * Do we require a little bit or raw-mode for 64-bit guest execution?
|
---|
731 | */
|
---|
732 | pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
|
---|
733 | && pVM->fHMEnabled
|
---|
734 | && pVM->hm.s.fAllow64BitGuests;
|
---|
735 |
|
---|
736 | /*
|
---|
737 | * Disable nested paging and unrestricted guest execution now if they're
|
---|
738 | * configured so that CPUM can make decisions based on our configuration.
|
---|
739 | */
|
---|
740 | Assert(!pVM->hm.s.fNestedPaging);
|
---|
741 | if (pVM->hm.s.fAllowNestedPaging)
|
---|
742 | {
|
---|
743 | if (fCaps & SUPVTCAPS_NESTED_PAGING)
|
---|
744 | pVM->hm.s.fNestedPaging = true;
|
---|
745 | else
|
---|
746 | pVM->hm.s.fAllowNestedPaging = false;
|
---|
747 | }
|
---|
748 |
|
---|
749 | if (fCaps & SUPVTCAPS_VT_X)
|
---|
750 | {
|
---|
751 | Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
|
---|
752 | if (pVM->hm.s.vmx.fAllowUnrestricted)
|
---|
753 | {
|
---|
754 | if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
|
---|
755 | && pVM->hm.s.fNestedPaging)
|
---|
756 | pVM->hm.s.vmx.fUnrestrictedGuest = true;
|
---|
757 | else
|
---|
758 | pVM->hm.s.vmx.fAllowUnrestricted = false;
|
---|
759 | }
|
---|
760 | }
|
---|
761 | }
|
---|
762 | else
|
---|
763 | {
|
---|
764 | const char *pszMsg;
|
---|
765 | switch (rc)
|
---|
766 | {
|
---|
767 | case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
|
---|
768 | case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
|
---|
769 | case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
|
---|
770 | case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
|
---|
771 | case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
|
---|
772 | case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
|
---|
773 | case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
|
---|
774 | default:
|
---|
775 | return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
|
---|
776 | }
|
---|
777 |
|
---|
778 | /*
|
---|
779 | * Before failing, try fallback to NEM if we're allowed to do that.
|
---|
780 | */
|
---|
781 | pVM->fHMEnabled = false;
|
---|
782 | if (fFallbackToNEM)
|
---|
783 | {
|
---|
784 | LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
|
---|
785 | int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
|
---|
786 | ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
|
---|
787 | if ( RT_SUCCESS(rc2)
|
---|
788 | && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
|
---|
789 | rc = VINF_SUCCESS;
|
---|
790 | }
|
---|
791 | if (RT_FAILURE(rc))
|
---|
792 | {
|
---|
793 | if (fHMForced)
|
---|
794 | return VM_SET_ERROR(pVM, rc, pszMsg);
|
---|
795 |
|
---|
796 | LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
|
---|
797 | VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
|
---|
798 | }
|
---|
799 | }
|
---|
800 | }
|
---|
801 | else
|
---|
802 | {
|
---|
803 | /*
|
---|
804 | * Disabled HM mean raw-mode, unless NEM is supposed to be used.
|
---|
805 | */
|
---|
806 | if (!fUseNEMInstead)
|
---|
807 | VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
|
---|
808 | else
|
---|
809 | {
|
---|
810 | rc = NEMR3Init(pVM, false /*fFallback*/, true);
|
---|
811 | ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
|
---|
812 | if (RT_FAILURE(rc))
|
---|
813 | return rc;
|
---|
814 | }
|
---|
815 | }
|
---|
816 |
|
---|
817 | return VINF_SUCCESS;
|
---|
818 | }
|
---|
819 |
|
---|
820 |
|
---|
821 | /**
|
---|
822 | * Initializes the per-VCPU HM.
|
---|
823 | *
|
---|
824 | * @returns VBox status code.
|
---|
825 | * @param pVM The cross context VM structure.
|
---|
826 | */
|
---|
827 | static int hmR3InitCPU(PVM pVM)
|
---|
828 | {
|
---|
829 | LogFlow(("HMR3InitCPU\n"));
|
---|
830 |
|
---|
831 | if (!HMIsEnabled(pVM))
|
---|
832 | return VINF_SUCCESS;
|
---|
833 |
|
---|
834 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
835 | {
|
---|
836 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
837 | pVCpu->hm.s.fActive = false;
|
---|
838 | }
|
---|
839 |
|
---|
840 | #ifdef VBOX_WITH_STATISTICS
|
---|
841 | STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
|
---|
842 | STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
|
---|
843 | STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
|
---|
844 | STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
|
---|
845 | STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
|
---|
846 | #endif
|
---|
847 |
|
---|
848 | /*
|
---|
849 | * Statistics.
|
---|
850 | */
|
---|
851 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
852 | {
|
---|
853 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
854 | int rc;
|
---|
855 |
|
---|
856 | #ifdef VBOX_WITH_STATISTICS
|
---|
857 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
858 | "Profiling of RTMpPokeCpu",
|
---|
859 | "/PROF/CPU%d/HM/Poke", i);
|
---|
860 | AssertRC(rc);
|
---|
861 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
862 | "Profiling of poke wait",
|
---|
863 | "/PROF/CPU%d/HM/PokeWait", i);
|
---|
864 | AssertRC(rc);
|
---|
865 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
866 | "Profiling of poke wait when RTMpPokeCpu fails",
|
---|
867 | "/PROF/CPU%d/HM/PokeWaitFailed", i);
|
---|
868 | AssertRC(rc);
|
---|
869 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
870 | "Profiling of VMXR0RunGuestCode entry",
|
---|
871 | "/PROF/CPU%d/HM/StatEntry", i);
|
---|
872 | AssertRC(rc);
|
---|
873 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
874 | "Profiling of VMXR0RunGuestCode exit part 1",
|
---|
875 | "/PROF/CPU%d/HM/SwitchFromGC_1", i);
|
---|
876 | AssertRC(rc);
|
---|
877 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
878 | "Profiling of VMXR0RunGuestCode exit part 2",
|
---|
879 | "/PROF/CPU%d/HM/SwitchFromGC_2", i);
|
---|
880 | AssertRC(rc);
|
---|
881 |
|
---|
882 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
883 | "I/O",
|
---|
884 | "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
|
---|
885 | AssertRC(rc);
|
---|
886 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
887 | "MOV CRx",
|
---|
888 | "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
|
---|
889 | AssertRC(rc);
|
---|
890 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
891 | "Exceptions, NMIs",
|
---|
892 | "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
|
---|
893 | AssertRC(rc);
|
---|
894 |
|
---|
895 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
896 | "Profiling of VMXR0LoadGuestState",
|
---|
897 | "/PROF/CPU%d/HM/StatLoadGuestState", i);
|
---|
898 | AssertRC(rc);
|
---|
899 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
900 | "Profiling of CPUMR0LoadGuestFPU",
|
---|
901 | "/PROF/CPU%d/HM/StatLoadGuestFpuState", i);
|
---|
902 | AssertRC(rc);
|
---|
903 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
|
---|
904 | "Profiling of VMLAUNCH/VMRESUME.",
|
---|
905 | "/PROF/CPU%d/HM/InGC", i);
|
---|
906 | AssertRC(rc);
|
---|
907 |
|
---|
908 | # if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
|
---|
909 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
|
---|
910 | STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
|
---|
911 | "/PROF/CPU%d/HM/Switcher3264", i);
|
---|
912 | AssertRC(rc);
|
---|
913 | # endif
|
---|
914 |
|
---|
915 | # ifdef HM_PROFILE_EXIT_DISPATCH
|
---|
916 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
|
---|
917 | STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
|
---|
918 | "/PROF/CPU%d/HM/ExitDispatch", i);
|
---|
919 | AssertRC(rc);
|
---|
920 | # endif
|
---|
921 |
|
---|
922 | #endif
|
---|
923 | # define HM_REG_COUNTER(a, b, desc) \
|
---|
924 | rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
|
---|
925 | AssertRC(rc);
|
---|
926 |
|
---|
927 | #ifdef VBOX_WITH_STATISTICS
|
---|
928 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
|
---|
929 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
|
---|
930 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
|
---|
931 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
|
---|
932 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
|
---|
933 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
|
---|
934 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
|
---|
935 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
|
---|
936 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
|
---|
937 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
|
---|
938 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
|
---|
939 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
|
---|
940 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
|
---|
941 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
|
---|
942 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
|
---|
943 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
|
---|
944 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
|
---|
945 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
|
---|
946 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
|
---|
947 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
|
---|
948 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
|
---|
949 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
|
---|
950 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
|
---|
951 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
|
---|
952 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
|
---|
953 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
|
---|
954 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
|
---|
955 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
|
---|
956 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
|
---|
957 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
|
---|
958 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
|
---|
959 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
|
---|
960 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
|
---|
961 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
|
---|
962 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
|
---|
963 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
|
---|
964 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
|
---|
965 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
|
---|
966 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
|
---|
967 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
|
---|
968 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
|
---|
969 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
|
---|
970 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
|
---|
971 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
|
---|
972 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
|
---|
973 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
|
---|
974 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
|
---|
975 | #endif
|
---|
976 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
|
---|
977 | #ifdef VBOX_WITH_STATISTICS
|
---|
978 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
|
---|
979 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
|
---|
980 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
|
---|
981 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
|
---|
982 | HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
|
---|
983 |
|
---|
984 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
|
---|
985 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
|
---|
986 | HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
|
---|
987 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
|
---|
988 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
|
---|
989 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
|
---|
990 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
|
---|
991 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
|
---|
992 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
|
---|
993 | #endif
|
---|
994 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
|
---|
995 | #ifdef VBOX_WITH_STATISTICS
|
---|
996 | HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
|
---|
997 |
|
---|
998 | HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
|
---|
999 | HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
|
---|
1000 | HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
|
---|
1001 | HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
|
---|
1002 |
|
---|
1003 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
|
---|
1004 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
|
---|
1005 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
|
---|
1006 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
|
---|
1007 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
|
---|
1008 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
|
---|
1009 | HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
|
---|
1010 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
|
---|
1011 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
|
---|
1012 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
|
---|
1013 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
|
---|
1014 | HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
|
---|
1015 | HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
|
---|
1016 | HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
|
---|
1017 |
|
---|
1018 | HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
|
---|
1019 | HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
|
---|
1020 | HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
|
---|
1021 |
|
---|
1022 | HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
|
---|
1023 | HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
|
---|
1024 | HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
|
---|
1025 |
|
---|
1026 | HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
|
---|
1027 | HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
|
---|
1028 | HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/GuestFpu", "VM-entry loading the guest-FPU state.");
|
---|
1029 |
|
---|
1030 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
|
---|
1031 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
|
---|
1032 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
|
---|
1033 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
|
---|
1034 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
|
---|
1035 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
|
---|
1036 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
|
---|
1037 | HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
|
---|
1038 |
|
---|
1039 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
|
---|
1040 | HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
|
---|
1041 | HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
|
---|
1042 | #endif
|
---|
1043 |
|
---|
1044 | for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
|
---|
1045 | {
|
---|
1046 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
|
---|
1047 | STAMUNIT_OCCURENCES, "Profiling of CRx writes",
|
---|
1048 | "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
|
---|
1049 | AssertRC(rc);
|
---|
1050 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
|
---|
1051 | STAMUNIT_OCCURENCES, "Profiling of CRx reads",
|
---|
1052 | "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
|
---|
1053 | AssertRC(rc);
|
---|
1054 | }
|
---|
1055 |
|
---|
1056 | #undef HM_REG_COUNTER
|
---|
1057 |
|
---|
1058 | const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVTxExitReasons[0]
|
---|
1059 | : &g_apszAmdVExitReasons[0];
|
---|
1060 |
|
---|
1061 | /*
|
---|
1062 | * Guest Exit reason stats.
|
---|
1063 | */
|
---|
1064 | pVCpu->hm.s.paStatExitReason = NULL;
|
---|
1065 | rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
|
---|
1066 | (void **)&pVCpu->hm.s.paStatExitReason);
|
---|
1067 | AssertRCReturn(rc, rc);
|
---|
1068 | for (int j = 0; j < MAX_EXITREASON_STAT; j++)
|
---|
1069 | {
|
---|
1070 | if (papszDesc[j])
|
---|
1071 | {
|
---|
1072 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
|
---|
1073 | STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
|
---|
1074 | AssertRCReturn(rc, rc);
|
---|
1075 | }
|
---|
1076 | }
|
---|
1077 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
|
---|
1078 | "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
|
---|
1079 | AssertRCReturn(rc, rc);
|
---|
1080 | pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
|
---|
1081 | # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
|
---|
1082 | Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
|
---|
1083 | # else
|
---|
1084 | Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
|
---|
1085 | # endif
|
---|
1086 |
|
---|
1087 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
|
---|
1088 | /*
|
---|
1089 | * Nested-guest Exit reason stats.
|
---|
1090 | */
|
---|
1091 | pVCpu->hm.s.paStatNestedExitReason = NULL;
|
---|
1092 | rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
|
---|
1093 | (void **)&pVCpu->hm.s.paStatNestedExitReason);
|
---|
1094 | AssertRCReturn(rc, rc);
|
---|
1095 | for (int j = 0; j < MAX_EXITREASON_STAT; j++)
|
---|
1096 | {
|
---|
1097 | if (papszDesc[j])
|
---|
1098 | {
|
---|
1099 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
|
---|
1100 | STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
|
---|
1101 | AssertRC(rc);
|
---|
1102 | }
|
---|
1103 | }
|
---|
1104 | rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
|
---|
1105 | STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
|
---|
1106 | AssertRCReturn(rc, rc);
|
---|
1107 | pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
|
---|
1108 | # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
|
---|
1109 | Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
|
---|
1110 | # else
|
---|
1111 | Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
|
---|
1112 | # endif
|
---|
1113 | #endif
|
---|
1114 |
|
---|
1115 | /*
|
---|
1116 | * Injected events stats.
|
---|
1117 | */
|
---|
1118 | rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
|
---|
1119 | AssertRCReturn(rc, rc);
|
---|
1120 | pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
|
---|
1121 | # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
|
---|
1122 | Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
|
---|
1123 | # else
|
---|
1124 | Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
|
---|
1125 | # endif
|
---|
1126 | for (unsigned j = 0; j < 255; j++)
|
---|
1127 | {
|
---|
1128 | STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
|
---|
1129 | "Injected event.",
|
---|
1130 | (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
|
---|
1131 | }
|
---|
1132 |
|
---|
1133 | #endif /* VBOX_WITH_STATISTICS */
|
---|
1134 | }
|
---|
1135 |
|
---|
1136 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
1137 | /*
|
---|
1138 | * Magic marker for searching in crash dumps.
|
---|
1139 | */
|
---|
1140 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
1141 | {
|
---|
1142 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
1143 |
|
---|
1144 | PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
|
---|
1145 | strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
|
---|
1146 | pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
|
---|
1147 | }
|
---|
1148 | #endif
|
---|
1149 |
|
---|
1150 | return VINF_SUCCESS;
|
---|
1151 | }
|
---|
1152 |
|
---|
1153 |
|
---|
1154 | /**
|
---|
1155 | * Called when a init phase has completed.
|
---|
1156 | *
|
---|
1157 | * @returns VBox status code.
|
---|
1158 | * @param pVM The cross context VM structure.
|
---|
1159 | * @param enmWhat The phase that completed.
|
---|
1160 | */
|
---|
1161 | VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
|
---|
1162 | {
|
---|
1163 | switch (enmWhat)
|
---|
1164 | {
|
---|
1165 | case VMINITCOMPLETED_RING3:
|
---|
1166 | return hmR3InitCPU(pVM);
|
---|
1167 | case VMINITCOMPLETED_RING0:
|
---|
1168 | return hmR3InitFinalizeR0(pVM);
|
---|
1169 | default:
|
---|
1170 | return VINF_SUCCESS;
|
---|
1171 | }
|
---|
1172 | }
|
---|
1173 |
|
---|
1174 |
|
---|
1175 | /**
|
---|
1176 | * Turns off normal raw mode features.
|
---|
1177 | *
|
---|
1178 | * @param pVM The cross context VM structure.
|
---|
1179 | */
|
---|
1180 | static void hmR3DisableRawMode(PVM pVM)
|
---|
1181 | {
|
---|
1182 | /* Reinit the paging mode to force the new shadow mode. */
|
---|
1183 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
1184 | {
|
---|
1185 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
1186 |
|
---|
1187 | PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
|
---|
1188 | }
|
---|
1189 | }
|
---|
1190 |
|
---|
1191 |
|
---|
1192 | /**
|
---|
1193 | * Initialize VT-x or AMD-V.
|
---|
1194 | *
|
---|
1195 | * @returns VBox status code.
|
---|
1196 | * @param pVM The cross context VM structure.
|
---|
1197 | */
|
---|
1198 | static int hmR3InitFinalizeR0(PVM pVM)
|
---|
1199 | {
|
---|
1200 | int rc;
|
---|
1201 |
|
---|
1202 | if (!HMIsEnabled(pVM))
|
---|
1203 | return VINF_SUCCESS;
|
---|
1204 |
|
---|
1205 | /*
|
---|
1206 | * Hack to allow users to work around broken BIOSes that incorrectly set
|
---|
1207 | * EFER.SVME, which makes us believe somebody else is already using AMD-V.
|
---|
1208 | */
|
---|
1209 | if ( !pVM->hm.s.vmx.fSupported
|
---|
1210 | && !pVM->hm.s.svm.fSupported
|
---|
1211 | && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
|
---|
1212 | && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
|
---|
1213 | {
|
---|
1214 | LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
|
---|
1215 | pVM->hm.s.svm.fSupported = true;
|
---|
1216 | pVM->hm.s.svm.fIgnoreInUseError = true;
|
---|
1217 | pVM->hm.s.lLastError = VINF_SUCCESS;
|
---|
1218 | }
|
---|
1219 |
|
---|
1220 | /*
|
---|
1221 | * Report ring-0 init errors.
|
---|
1222 | */
|
---|
1223 | if ( !pVM->hm.s.vmx.fSupported
|
---|
1224 | && !pVM->hm.s.svm.fSupported)
|
---|
1225 | {
|
---|
1226 | LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
|
---|
1227 | LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
|
---|
1228 | switch (pVM->hm.s.lLastError)
|
---|
1229 | {
|
---|
1230 | case VERR_VMX_IN_VMX_ROOT_MODE:
|
---|
1231 | return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
|
---|
1232 | case VERR_VMX_NO_VMX:
|
---|
1233 | return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
|
---|
1234 | case VERR_VMX_MSR_VMX_DISABLED:
|
---|
1235 | return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
|
---|
1236 | case VERR_VMX_MSR_ALL_VMX_DISABLED:
|
---|
1237 | return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
|
---|
1238 | case VERR_VMX_MSR_LOCKING_FAILED:
|
---|
1239 | return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
|
---|
1240 | case VERR_VMX_MSR_VMX_ENABLE_FAILED:
|
---|
1241 | return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
|
---|
1242 | case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
|
---|
1243 | return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
|
---|
1244 |
|
---|
1245 | case VERR_SVM_IN_USE:
|
---|
1246 | return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
|
---|
1247 | case VERR_SVM_NO_SVM:
|
---|
1248 | return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
|
---|
1249 | case VERR_SVM_DISABLED:
|
---|
1250 | return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
|
---|
1251 | }
|
---|
1252 | return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
|
---|
1253 | }
|
---|
1254 |
|
---|
1255 | /*
|
---|
1256 | * Enable VT-x or AMD-V on all host CPUs.
|
---|
1257 | */
|
---|
1258 | rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
|
---|
1259 | if (RT_FAILURE(rc))
|
---|
1260 | {
|
---|
1261 | LogRel(("HM: Failed to enable, error %Rrc\n", rc));
|
---|
1262 | HMR3CheckError(pVM, rc);
|
---|
1263 | return rc;
|
---|
1264 | }
|
---|
1265 |
|
---|
1266 | /*
|
---|
1267 | * No TPR patching is required when the IO-APIC is not enabled for this VM.
|
---|
1268 | * (Main should have taken care of this already)
|
---|
1269 | */
|
---|
1270 | if (!PDMHasIoApic(pVM))
|
---|
1271 | {
|
---|
1272 | Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
|
---|
1273 | pVM->hm.s.fTprPatchingAllowed = false;
|
---|
1274 | }
|
---|
1275 |
|
---|
1276 | /*
|
---|
1277 | * Sync options.
|
---|
1278 | */
|
---|
1279 | /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
|
---|
1280 | * That will require a little bit of work, of course. */
|
---|
1281 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
|
---|
1282 | {
|
---|
1283 | PVMCPU pVCpu = &pVM->aCpus[iCpu];
|
---|
1284 | PCPUMCTX pCpuCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
---|
1285 | pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
|
---|
1286 | if (pVM->cpum.ro.HostFeatures.fIbpb)
|
---|
1287 | {
|
---|
1288 | if (pVM->hm.s.fIbpbOnVmExit)
|
---|
1289 | pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
|
---|
1290 | if (pVM->hm.s.fIbpbOnVmEntry)
|
---|
1291 | pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
|
---|
1292 | }
|
---|
1293 | if (iCpu == 0)
|
---|
1294 | LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
|
---|
1295 | pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
|
---|
1296 | }
|
---|
1297 |
|
---|
1298 | /*
|
---|
1299 | * Do the vendor specific initialization
|
---|
1300 | *
|
---|
1301 | * Note! We disable release log buffering here since we're doing relatively
|
---|
1302 | * lot of logging and doesn't want to hit the disk with each LogRel
|
---|
1303 | * statement.
|
---|
1304 | */
|
---|
1305 | AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
|
---|
1306 | bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
|
---|
1307 | if (pVM->hm.s.vmx.fSupported)
|
---|
1308 | rc = hmR3InitFinalizeR0Intel(pVM);
|
---|
1309 | else
|
---|
1310 | rc = hmR3InitFinalizeR0Amd(pVM);
|
---|
1311 | LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
|
---|
1312 | RTLogRelSetBuffering(fOldBuffered);
|
---|
1313 | pVM->hm.s.fInitialized = true;
|
---|
1314 |
|
---|
1315 | return rc;
|
---|
1316 | }
|
---|
1317 |
|
---|
1318 |
|
---|
1319 | /**
|
---|
1320 | * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
|
---|
1321 | */
|
---|
1322 | static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
|
---|
1323 | {
|
---|
1324 | NOREF(pVM);
|
---|
1325 | NOREF(pvAllocation);
|
---|
1326 | NOREF(GCPhysAllocation);
|
---|
1327 | }
|
---|
1328 |
|
---|
1329 |
|
---|
1330 | /**
|
---|
1331 | * Finish VT-x initialization (after ring-0 init).
|
---|
1332 | *
|
---|
1333 | * @returns VBox status code.
|
---|
1334 | * @param pVM The cross context VM structure.
|
---|
1335 | */
|
---|
1336 | static int hmR3InitFinalizeR0Intel(PVM pVM)
|
---|
1337 | {
|
---|
1338 | int rc;
|
---|
1339 |
|
---|
1340 | Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
|
---|
1341 | AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
|
---|
1342 |
|
---|
1343 | uint64_t val;
|
---|
1344 | uint64_t zap;
|
---|
1345 |
|
---|
1346 | LogRel(("HM: Using VT-x implementation 2.0\n"));
|
---|
1347 | LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
|
---|
1348 | LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
|
---|
1349 | LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
|
---|
1350 | LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
|
---|
1351 | if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
|
---|
1352 | LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
|
---|
1353 | LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
|
---|
1354 | LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
|
---|
1355 | LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
|
---|
1356 | LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
|
---|
1357 | LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
|
---|
1358 | LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
|
---|
1359 | LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
|
---|
1360 | LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
|
---|
1361 | LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
|
---|
1362 |
|
---|
1363 | LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
|
---|
1364 | val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
|
---|
1365 | zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
|
---|
1366 | HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
|
---|
1367 | HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
|
---|
1368 | HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
|
---|
1369 | HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
|
---|
1370 | HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
|
---|
1371 |
|
---|
1372 | LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
|
---|
1373 | val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
|
---|
1374 | zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
|
---|
1375 | HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
|
---|
1376 | HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
|
---|
1377 | HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
|
---|
1378 | HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
|
---|
1379 | HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
|
---|
1380 | HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
|
---|
1381 | HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
|
---|
1382 | HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
|
---|
1383 | HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
|
---|
1384 | HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
|
---|
1385 | HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
|
---|
1386 | HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
|
---|
1387 | HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
|
---|
1388 | HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
|
---|
1389 | HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
|
---|
1390 | HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
|
---|
1391 | HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
|
---|
1392 | HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
|
---|
1393 | HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
|
---|
1394 | HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
|
---|
1395 | HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
|
---|
1396 | if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
1397 | {
|
---|
1398 | LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
|
---|
1399 | val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
|
---|
1400 | zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
|
---|
1401 | HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
|
---|
1402 | HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
|
---|
1403 | HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
|
---|
1404 | HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
|
---|
1405 | HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
|
---|
1406 | HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
|
---|
1407 | HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
|
---|
1408 | HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
|
---|
1409 | HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
|
---|
1410 | HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
|
---|
1411 | HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
|
---|
1412 | HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
|
---|
1413 | HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
|
---|
1414 | HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
|
---|
1415 | HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
|
---|
1416 | HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
|
---|
1417 | HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
|
---|
1418 | HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
|
---|
1419 | HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
|
---|
1420 | HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
|
---|
1421 | HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
|
---|
1422 | HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
|
---|
1423 | }
|
---|
1424 |
|
---|
1425 | LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
|
---|
1426 | val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
|
---|
1427 | zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
|
---|
1428 | HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
|
---|
1429 | HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
|
---|
1430 | HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
|
---|
1431 | HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
|
---|
1432 | HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
|
---|
1433 | HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
|
---|
1434 | HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
|
---|
1435 |
|
---|
1436 | LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
|
---|
1437 | val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
|
---|
1438 | zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
|
---|
1439 | HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
|
---|
1440 | HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
|
---|
1441 | HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
|
---|
1442 | HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
|
---|
1443 | HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
|
---|
1444 | HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
|
---|
1445 | HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
|
---|
1446 | HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
|
---|
1447 | HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
|
---|
1448 |
|
---|
1449 | if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
|
---|
1450 | {
|
---|
1451 | val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
|
---|
1452 | LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
|
---|
1453 | HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
|
---|
1454 | HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
|
---|
1455 | HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
|
---|
1456 | HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
|
---|
1457 | HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
|
---|
1458 | HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
|
---|
1459 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
|
---|
1460 | HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
|
---|
1461 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
|
---|
1462 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
|
---|
1463 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
|
---|
1464 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
|
---|
1465 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
|
---|
1466 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
|
---|
1467 | HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
|
---|
1468 | }
|
---|
1469 |
|
---|
1470 | val = pVM->hm.s.vmx.Msrs.u64Misc;
|
---|
1471 | LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
|
---|
1472 | if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
|
---|
1473 | LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
|
---|
1474 | else
|
---|
1475 | {
|
---|
1476 | LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
|
---|
1477 | MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
|
---|
1478 | }
|
---|
1479 |
|
---|
1480 | LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
|
---|
1481 | LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
|
---|
1482 | LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
|
---|
1483 | LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
|
---|
1484 | LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
|
---|
1485 | LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
|
---|
1486 | LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
|
---|
1487 | LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
|
---|
1488 |
|
---|
1489 | /* Paranoia */
|
---|
1490 | AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
|
---|
1491 |
|
---|
1492 | LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
|
---|
1493 | LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
|
---|
1494 | LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
|
---|
1495 | LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
|
---|
1496 |
|
---|
1497 | val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
|
---|
1498 | LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
|
---|
1499 | LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
|
---|
1500 |
|
---|
1501 | val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
|
---|
1502 | if (val)
|
---|
1503 | {
|
---|
1504 | LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
|
---|
1505 | HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
|
---|
1506 | }
|
---|
1507 |
|
---|
1508 | LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
|
---|
1509 |
|
---|
1510 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
1511 | {
|
---|
1512 | LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
|
---|
1513 | LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
|
---|
1514 | }
|
---|
1515 |
|
---|
1516 | /*
|
---|
1517 | * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
|
---|
1518 | */
|
---|
1519 | AssertLogRelReturn( !pVM->hm.s.fNestedPaging
|
---|
1520 | || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
|
---|
1521 | VERR_HM_IPE_1);
|
---|
1522 | AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
|
---|
1523 | || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
|
---|
1524 | && pVM->hm.s.fNestedPaging),
|
---|
1525 | VERR_HM_IPE_1);
|
---|
1526 |
|
---|
1527 | /*
|
---|
1528 | * Enable VPID if configured and supported.
|
---|
1529 | */
|
---|
1530 | if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
|
---|
1531 | pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
|
---|
1532 |
|
---|
1533 | #if 0
|
---|
1534 | /*
|
---|
1535 | * Enable APIC register virtualization and virtual-interrupt delivery if supported.
|
---|
1536 | */
|
---|
1537 | if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
|
---|
1538 | && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
|
---|
1539 | pVM->hm.s.fVirtApicRegs = true;
|
---|
1540 |
|
---|
1541 | /*
|
---|
1542 | * Enable posted-interrupt processing if supported.
|
---|
1543 | */
|
---|
1544 | /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
|
---|
1545 | * here. */
|
---|
1546 | if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
|
---|
1547 | && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
|
---|
1548 | pVM->hm.s.fPostedIntrs = true;
|
---|
1549 | #endif
|
---|
1550 |
|
---|
1551 | /*
|
---|
1552 | * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
|
---|
1553 | * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
|
---|
1554 | * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
|
---|
1555 | */
|
---|
1556 | if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
1557 | && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
|
---|
1558 | {
|
---|
1559 | CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
|
---|
1560 | LogRel(("HM: Disabled RDTSCP\n"));
|
---|
1561 | }
|
---|
1562 |
|
---|
1563 | if (!pVM->hm.s.vmx.fUnrestrictedGuest)
|
---|
1564 | {
|
---|
1565 | /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
|
---|
1566 | rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
|
---|
1567 | if (RT_SUCCESS(rc))
|
---|
1568 | {
|
---|
1569 | /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
|
---|
1570 | Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
|
---|
1571 | esp. Figure 20-5.*/
|
---|
1572 | ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
|
---|
1573 | pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
|
---|
1574 |
|
---|
1575 | /* Bit set to 0 means software interrupts are redirected to the
|
---|
1576 | 8086 program interrupt handler rather than switching to
|
---|
1577 | protected-mode handler. */
|
---|
1578 | memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
|
---|
1579 |
|
---|
1580 | /* Allow all port IO, so that port IO instructions do not cause
|
---|
1581 | exceptions and would instead cause a VM-exit (based on VT-x's
|
---|
1582 | IO bitmap which we currently configure to always cause an exit). */
|
---|
1583 | memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
|
---|
1584 | *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
|
---|
1585 |
|
---|
1586 | /*
|
---|
1587 | * Construct a 1024 element page directory with 4 MB pages for
|
---|
1588 | * the identity mapped page table used in real and protected mode
|
---|
1589 | * without paging with EPT.
|
---|
1590 | */
|
---|
1591 | pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
|
---|
1592 | for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
|
---|
1593 | {
|
---|
1594 | pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
|
---|
1595 | pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
|
---|
1596 | | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
|
---|
1597 | | X86_PDE4M_G;
|
---|
1598 | }
|
---|
1599 |
|
---|
1600 | /* We convert it here every time as PCI regions could be reconfigured. */
|
---|
1601 | if (PDMVmmDevHeapIsEnabled(pVM))
|
---|
1602 | {
|
---|
1603 | RTGCPHYS GCPhys;
|
---|
1604 | rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
|
---|
1605 | AssertRCReturn(rc, rc);
|
---|
1606 | LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
|
---|
1607 |
|
---|
1608 | rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
|
---|
1609 | AssertRCReturn(rc, rc);
|
---|
1610 | LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
|
---|
1611 | }
|
---|
1612 | }
|
---|
1613 | else
|
---|
1614 | {
|
---|
1615 | LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
|
---|
1616 | pVM->hm.s.vmx.pRealModeTSS = NULL;
|
---|
1617 | pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
|
---|
1618 | return VMSetError(pVM, rc, RT_SRC_POS,
|
---|
1619 | "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
|
---|
1620 | }
|
---|
1621 | }
|
---|
1622 |
|
---|
1623 | LogRel((pVM->hm.s.fAllow64BitGuests
|
---|
1624 | ? "HM: Guest support: 32-bit and 64-bit\n"
|
---|
1625 | : "HM: Guest support: 32-bit only\n"));
|
---|
1626 |
|
---|
1627 | /*
|
---|
1628 | * Call ring-0 to set up the VM.
|
---|
1629 | */
|
---|
1630 | rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
|
---|
1631 | if (rc != VINF_SUCCESS)
|
---|
1632 | {
|
---|
1633 | AssertMsgFailed(("%Rrc\n", rc));
|
---|
1634 | LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
|
---|
1635 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
1636 | {
|
---|
1637 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
1638 | LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
|
---|
1639 | LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
|
---|
1640 | }
|
---|
1641 | HMR3CheckError(pVM, rc);
|
---|
1642 | return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
|
---|
1643 | }
|
---|
1644 |
|
---|
1645 | LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
|
---|
1646 | LogRel(("HM: Enabled VMX\n"));
|
---|
1647 | pVM->hm.s.vmx.fEnabled = true;
|
---|
1648 |
|
---|
1649 | hmR3DisableRawMode(pVM); /** @todo make this go away! */
|
---|
1650 |
|
---|
1651 | /*
|
---|
1652 | * Change the CPU features.
|
---|
1653 | */
|
---|
1654 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
1655 | if (pVM->hm.s.fAllow64BitGuests)
|
---|
1656 | {
|
---|
1657 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
1658 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
1659 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
|
---|
1660 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
1661 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
|
---|
1662 | }
|
---|
1663 | /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
|
---|
1664 | (we reuse the host EFER in the switcher). */
|
---|
1665 | /** @todo this needs to be fixed properly!! */
|
---|
1666 | else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
|
---|
1667 | {
|
---|
1668 | if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
|
---|
1669 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
|
---|
1670 | else
|
---|
1671 | LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
|
---|
1672 | }
|
---|
1673 |
|
---|
1674 | /*
|
---|
1675 | * Log configuration details.
|
---|
1676 | */
|
---|
1677 | if (pVM->hm.s.fNestedPaging)
|
---|
1678 | {
|
---|
1679 | LogRel(("HM: Enabled nested paging\n"));
|
---|
1680 | if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
|
---|
1681 | LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
|
---|
1682 | else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
|
---|
1683 | LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
|
---|
1684 | else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
|
---|
1685 | LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
|
---|
1686 | else
|
---|
1687 | LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
|
---|
1688 |
|
---|
1689 | if (pVM->hm.s.vmx.fUnrestrictedGuest)
|
---|
1690 | LogRel(("HM: Enabled unrestricted guest execution\n"));
|
---|
1691 |
|
---|
1692 | #if HC_ARCH_BITS == 64
|
---|
1693 | if (pVM->hm.s.fLargePages)
|
---|
1694 | {
|
---|
1695 | /* Use large (2 MB) pages for our EPT PDEs where possible. */
|
---|
1696 | PGMSetLargePageUsage(pVM, true);
|
---|
1697 | LogRel(("HM: Enabled large page support\n"));
|
---|
1698 | }
|
---|
1699 | #endif
|
---|
1700 | }
|
---|
1701 | else
|
---|
1702 | Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
|
---|
1703 |
|
---|
1704 | if (pVM->hm.s.fVirtApicRegs)
|
---|
1705 | LogRel(("HM: Enabled APIC-register virtualization support\n"));
|
---|
1706 |
|
---|
1707 | if (pVM->hm.s.fPostedIntrs)
|
---|
1708 | LogRel(("HM: Enabled posted-interrupt processing support\n"));
|
---|
1709 |
|
---|
1710 | if (pVM->hm.s.vmx.fVpid)
|
---|
1711 | {
|
---|
1712 | LogRel(("HM: Enabled VPID\n"));
|
---|
1713 | if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
|
---|
1714 | LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
|
---|
1715 | else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
|
---|
1716 | LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
|
---|
1717 | else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
|
---|
1718 | LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
|
---|
1719 | else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
|
---|
1720 | LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
|
---|
1721 | else
|
---|
1722 | LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
|
---|
1723 | }
|
---|
1724 | else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
|
---|
1725 | LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
|
---|
1726 |
|
---|
1727 | if (pVM->hm.s.vmx.fUsePreemptTimer)
|
---|
1728 | LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
|
---|
1729 | else
|
---|
1730 | LogRel(("HM: Disabled VMX-preemption timer\n"));
|
---|
1731 |
|
---|
1732 | return VINF_SUCCESS;
|
---|
1733 | }
|
---|
1734 |
|
---|
1735 |
|
---|
1736 | /**
|
---|
1737 | * Finish AMD-V initialization (after ring-0 init).
|
---|
1738 | *
|
---|
1739 | * @returns VBox status code.
|
---|
1740 | * @param pVM The cross context VM structure.
|
---|
1741 | */
|
---|
1742 | static int hmR3InitFinalizeR0Amd(PVM pVM)
|
---|
1743 | {
|
---|
1744 | Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
|
---|
1745 |
|
---|
1746 | LogRel(("HM: Using AMD-V implementation 2.0\n"));
|
---|
1747 |
|
---|
1748 | uint32_t u32Family;
|
---|
1749 | uint32_t u32Model;
|
---|
1750 | uint32_t u32Stepping;
|
---|
1751 | if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
|
---|
1752 | LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
|
---|
1753 | LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
|
---|
1754 | LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
|
---|
1755 | LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
|
---|
1756 | LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
|
---|
1757 | LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
|
---|
1758 | LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
|
---|
1759 | LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
|
---|
1760 |
|
---|
1761 | /*
|
---|
1762 | * Enumerate AMD-V features.
|
---|
1763 | */
|
---|
1764 | static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
|
---|
1765 | {
|
---|
1766 | #define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
|
---|
1767 | HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
|
---|
1768 | HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
|
---|
1769 | HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
|
---|
1770 | HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
|
---|
1771 | HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
|
---|
1772 | HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
|
---|
1773 | HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
|
---|
1774 | HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
|
---|
1775 | HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
|
---|
1776 | HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
|
---|
1777 | HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
|
---|
1778 | HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
|
---|
1779 | HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
|
---|
1780 | #undef HMSVM_REPORT_FEATURE
|
---|
1781 | };
|
---|
1782 |
|
---|
1783 | uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
|
---|
1784 | for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
|
---|
1785 | if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
|
---|
1786 | {
|
---|
1787 | LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
|
---|
1788 | fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
|
---|
1789 | }
|
---|
1790 | if (fSvmFeatures)
|
---|
1791 | for (unsigned iBit = 0; iBit < 32; iBit++)
|
---|
1792 | if (RT_BIT_32(iBit) & fSvmFeatures)
|
---|
1793 | LogRel(("HM: Reserved bit %u\n", iBit));
|
---|
1794 |
|
---|
1795 | /*
|
---|
1796 | * Nested paging is determined in HMR3Init, verify the sanity of that.
|
---|
1797 | */
|
---|
1798 | AssertLogRelReturn( !pVM->hm.s.fNestedPaging
|
---|
1799 | || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
|
---|
1800 | VERR_HM_IPE_1);
|
---|
1801 |
|
---|
1802 | #if 0
|
---|
1803 | /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
|
---|
1804 | * here. */
|
---|
1805 | if (RTR0IsPostIpiSupport())
|
---|
1806 | pVM->hm.s.fPostedIntrs = true;
|
---|
1807 | #endif
|
---|
1808 |
|
---|
1809 | /*
|
---|
1810 | * Call ring-0 to set up the VM.
|
---|
1811 | */
|
---|
1812 | int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
|
---|
1813 | if (rc != VINF_SUCCESS)
|
---|
1814 | {
|
---|
1815 | AssertMsgFailed(("%Rrc\n", rc));
|
---|
1816 | LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
|
---|
1817 | return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
|
---|
1818 | }
|
---|
1819 |
|
---|
1820 | LogRel(("HM: Enabled SVM\n"));
|
---|
1821 | pVM->hm.s.svm.fEnabled = true;
|
---|
1822 |
|
---|
1823 | if (pVM->hm.s.fNestedPaging)
|
---|
1824 | {
|
---|
1825 | LogRel(("HM: Enabled nested paging\n"));
|
---|
1826 |
|
---|
1827 | /*
|
---|
1828 | * Enable large pages (2 MB) if applicable.
|
---|
1829 | */
|
---|
1830 | #if HC_ARCH_BITS == 64
|
---|
1831 | if (pVM->hm.s.fLargePages)
|
---|
1832 | {
|
---|
1833 | PGMSetLargePageUsage(pVM, true);
|
---|
1834 | LogRel(("HM: Enabled large page support\n"));
|
---|
1835 | }
|
---|
1836 | #endif
|
---|
1837 | }
|
---|
1838 |
|
---|
1839 | if (pVM->hm.s.fVirtApicRegs)
|
---|
1840 | LogRel(("HM: Enabled APIC-register virtualization support\n"));
|
---|
1841 |
|
---|
1842 | if (pVM->hm.s.fPostedIntrs)
|
---|
1843 | LogRel(("HM: Enabled posted-interrupt processing support\n"));
|
---|
1844 |
|
---|
1845 | hmR3DisableRawMode(pVM);
|
---|
1846 |
|
---|
1847 | /*
|
---|
1848 | * Change the CPU features.
|
---|
1849 | */
|
---|
1850 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
1851 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
|
---|
1852 | if (pVM->hm.s.fAllow64BitGuests)
|
---|
1853 | {
|
---|
1854 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
1855 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
1856 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
|
---|
1857 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
1858 | }
|
---|
1859 | /* Turn on NXE if PAE has been enabled. */
|
---|
1860 | else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
|
---|
1861 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
|
---|
1862 |
|
---|
1863 | LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
|
---|
1864 |
|
---|
1865 | LogRel((pVM->hm.s.fAllow64BitGuests
|
---|
1866 | ? "HM: Guest support: 32-bit and 64-bit\n"
|
---|
1867 | : "HM: Guest support: 32-bit only\n"));
|
---|
1868 |
|
---|
1869 | return VINF_SUCCESS;
|
---|
1870 | }
|
---|
1871 |
|
---|
1872 |
|
---|
1873 | /**
|
---|
1874 | * Applies relocations to data and code managed by this
|
---|
1875 | * component. This function will be called at init and
|
---|
1876 | * whenever the VMM need to relocate it self inside the GC.
|
---|
1877 | *
|
---|
1878 | * @param pVM The cross context VM structure.
|
---|
1879 | */
|
---|
1880 | VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
|
---|
1881 | {
|
---|
1882 | Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
|
---|
1883 |
|
---|
1884 | /* Fetch the current paging mode during the relocate callback during state loading. */
|
---|
1885 | if (VMR3GetState(pVM) == VMSTATE_LOADING)
|
---|
1886 | {
|
---|
1887 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
1888 | {
|
---|
1889 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
1890 | pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
|
---|
1891 | }
|
---|
1892 | }
|
---|
1893 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
|
---|
1894 | if (HMIsEnabled(pVM))
|
---|
1895 | {
|
---|
1896 | switch (PGMGetHostMode(pVM))
|
---|
1897 | {
|
---|
1898 | case PGMMODE_32_BIT:
|
---|
1899 | pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
|
---|
1900 | break;
|
---|
1901 |
|
---|
1902 | case PGMMODE_PAE:
|
---|
1903 | case PGMMODE_PAE_NX:
|
---|
1904 | pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
|
---|
1905 | break;
|
---|
1906 |
|
---|
1907 | default:
|
---|
1908 | AssertFailed();
|
---|
1909 | break;
|
---|
1910 | }
|
---|
1911 | }
|
---|
1912 | #endif
|
---|
1913 | return;
|
---|
1914 | }
|
---|
1915 |
|
---|
1916 |
|
---|
1917 | /**
|
---|
1918 | * Notification callback which is called whenever there is a chance that a CR3
|
---|
1919 | * value might have changed.
|
---|
1920 | *
|
---|
1921 | * This is called by PGM.
|
---|
1922 | *
|
---|
1923 | * @param pVM The cross context VM structure.
|
---|
1924 | * @param pVCpu The cross context virtual CPU structure.
|
---|
1925 | * @param enmShadowMode New shadow paging mode.
|
---|
1926 | * @param enmGuestMode New guest paging mode.
|
---|
1927 | */
|
---|
1928 | VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
|
---|
1929 | {
|
---|
1930 | RT_NOREF_PV(pVM);
|
---|
1931 |
|
---|
1932 | /* Ignore page mode changes during state loading. */
|
---|
1933 | if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
|
---|
1934 | return;
|
---|
1935 |
|
---|
1936 | pVCpu->hm.s.enmShadowMode = enmShadowMode;
|
---|
1937 |
|
---|
1938 | /*
|
---|
1939 | * If the guest left protected mode VMX execution, we'll have to be
|
---|
1940 | * extra careful if/when the guest switches back to protected mode.
|
---|
1941 | */
|
---|
1942 | if (enmGuestMode == PGMMODE_REAL)
|
---|
1943 | pVCpu->hm.s.vmx.fWasInRealMode = true;
|
---|
1944 |
|
---|
1945 | Log4(("HMR3PagingModeChanged: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
|
---|
1946 | PGMGetModeName(enmShadowMode)));
|
---|
1947 | }
|
---|
1948 |
|
---|
1949 |
|
---|
1950 | /**
|
---|
1951 | * Terminates the HM.
|
---|
1952 | *
|
---|
1953 | * Termination means cleaning up and freeing all resources,
|
---|
1954 | * the VM itself is, at this point, powered off or suspended.
|
---|
1955 | *
|
---|
1956 | * @returns VBox status code.
|
---|
1957 | * @param pVM The cross context VM structure.
|
---|
1958 | */
|
---|
1959 | VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
|
---|
1960 | {
|
---|
1961 | if (pVM->hm.s.vmx.pRealModeTSS)
|
---|
1962 | {
|
---|
1963 | PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
|
---|
1964 | pVM->hm.s.vmx.pRealModeTSS = 0;
|
---|
1965 | }
|
---|
1966 | hmR3TermCPU(pVM);
|
---|
1967 | return 0;
|
---|
1968 | }
|
---|
1969 |
|
---|
1970 |
|
---|
1971 | /**
|
---|
1972 | * Terminates the per-VCPU HM.
|
---|
1973 | *
|
---|
1974 | * @returns VBox status code.
|
---|
1975 | * @param pVM The cross context VM structure.
|
---|
1976 | */
|
---|
1977 | static int hmR3TermCPU(PVM pVM)
|
---|
1978 | {
|
---|
1979 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
1980 | {
|
---|
1981 | PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
|
---|
1982 |
|
---|
1983 | #ifdef VBOX_WITH_STATISTICS
|
---|
1984 | if (pVCpu->hm.s.paStatExitReason)
|
---|
1985 | {
|
---|
1986 | MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
|
---|
1987 | pVCpu->hm.s.paStatExitReason = NULL;
|
---|
1988 | pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
|
---|
1989 | }
|
---|
1990 | if (pVCpu->hm.s.paStatInjectedIrqs)
|
---|
1991 | {
|
---|
1992 | MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
|
---|
1993 | pVCpu->hm.s.paStatInjectedIrqs = NULL;
|
---|
1994 | pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
|
---|
1995 | }
|
---|
1996 | #endif
|
---|
1997 |
|
---|
1998 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
1999 | memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
|
---|
2000 | pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
|
---|
2001 | pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
|
---|
2002 | #endif
|
---|
2003 | }
|
---|
2004 | return 0;
|
---|
2005 | }
|
---|
2006 |
|
---|
2007 |
|
---|
2008 | /**
|
---|
2009 | * Resets a virtual CPU.
|
---|
2010 | *
|
---|
2011 | * Used by HMR3Reset and CPU hot plugging.
|
---|
2012 | *
|
---|
2013 | * @param pVCpu The cross context virtual CPU structure to reset.
|
---|
2014 | */
|
---|
2015 | VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
|
---|
2016 | {
|
---|
2017 | /* Sync. entire state on VM reset R0-reentry. It's safe to reset
|
---|
2018 | the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
|
---|
2019 | HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
|
---|
2020 |
|
---|
2021 | pVCpu->hm.s.vmx.u32CR0Mask = 0;
|
---|
2022 | pVCpu->hm.s.vmx.u32CR4Mask = 0;
|
---|
2023 | pVCpu->hm.s.fActive = false;
|
---|
2024 | pVCpu->hm.s.Event.fPending = false;
|
---|
2025 | pVCpu->hm.s.vmx.fWasInRealMode = true;
|
---|
2026 | pVCpu->hm.s.vmx.u64MsrApicBase = 0;
|
---|
2027 | pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
|
---|
2028 |
|
---|
2029 | /* Reset the contents of the read cache. */
|
---|
2030 | PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
|
---|
2031 | for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
|
---|
2032 | pCache->Read.aFieldVal[j] = 0;
|
---|
2033 |
|
---|
2034 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
2035 | /* Magic marker for searching in crash dumps. */
|
---|
2036 | strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
|
---|
2037 | pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
|
---|
2038 | #endif
|
---|
2039 | }
|
---|
2040 |
|
---|
2041 |
|
---|
2042 | /**
|
---|
2043 | * The VM is being reset.
|
---|
2044 | *
|
---|
2045 | * For the HM component this means that any GDT/LDT/TSS monitors
|
---|
2046 | * needs to be removed.
|
---|
2047 | *
|
---|
2048 | * @param pVM The cross context VM structure.
|
---|
2049 | */
|
---|
2050 | VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
|
---|
2051 | {
|
---|
2052 | LogFlow(("HMR3Reset:\n"));
|
---|
2053 |
|
---|
2054 | if (HMIsEnabled(pVM))
|
---|
2055 | hmR3DisableRawMode(pVM);
|
---|
2056 |
|
---|
2057 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
2058 | {
|
---|
2059 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
2060 |
|
---|
2061 | HMR3ResetCpu(pVCpu);
|
---|
2062 | }
|
---|
2063 |
|
---|
2064 | /* Clear all patch information. */
|
---|
2065 | pVM->hm.s.pGuestPatchMem = 0;
|
---|
2066 | pVM->hm.s.pFreeGuestPatchMem = 0;
|
---|
2067 | pVM->hm.s.cbGuestPatchMem = 0;
|
---|
2068 | pVM->hm.s.cPatches = 0;
|
---|
2069 | pVM->hm.s.PatchTree = 0;
|
---|
2070 | pVM->hm.s.fTPRPatchingActive = false;
|
---|
2071 | ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
|
---|
2072 | }
|
---|
2073 |
|
---|
2074 |
|
---|
2075 | /**
|
---|
2076 | * Callback to patch a TPR instruction (vmmcall or mov cr8).
|
---|
2077 | *
|
---|
2078 | * @returns VBox strict status code.
|
---|
2079 | * @param pVM The cross context VM structure.
|
---|
2080 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
2081 | * @param pvUser Unused.
|
---|
2082 | */
|
---|
2083 | static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
|
---|
2084 | {
|
---|
2085 | VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
|
---|
2086 |
|
---|
2087 | /* Only execute the handler on the VCPU the original patch request was issued. */
|
---|
2088 | if (pVCpu->idCpu != idCpu)
|
---|
2089 | return VINF_SUCCESS;
|
---|
2090 |
|
---|
2091 | Log(("hmR3RemovePatches\n"));
|
---|
2092 | for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
|
---|
2093 | {
|
---|
2094 | uint8_t abInstr[15];
|
---|
2095 | PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
|
---|
2096 | RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
|
---|
2097 | int rc;
|
---|
2098 |
|
---|
2099 | #ifdef LOG_ENABLED
|
---|
2100 | char szOutput[256];
|
---|
2101 |
|
---|
2102 | rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
|
---|
2103 | szOutput, sizeof(szOutput), NULL);
|
---|
2104 | if (RT_SUCCESS(rc))
|
---|
2105 | Log(("Patched instr: %s\n", szOutput));
|
---|
2106 | #endif
|
---|
2107 |
|
---|
2108 | /* Check if the instruction is still the same. */
|
---|
2109 | rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
|
---|
2110 | if (rc != VINF_SUCCESS)
|
---|
2111 | {
|
---|
2112 | Log(("Patched code removed? (rc=%Rrc0\n", rc));
|
---|
2113 | continue; /* swapped out or otherwise removed; skip it. */
|
---|
2114 | }
|
---|
2115 |
|
---|
2116 | if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
|
---|
2117 | {
|
---|
2118 | Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
|
---|
2119 | continue; /* skip it. */
|
---|
2120 | }
|
---|
2121 |
|
---|
2122 | rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
|
---|
2123 | AssertRC(rc);
|
---|
2124 |
|
---|
2125 | #ifdef LOG_ENABLED
|
---|
2126 | rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
|
---|
2127 | szOutput, sizeof(szOutput), NULL);
|
---|
2128 | if (RT_SUCCESS(rc))
|
---|
2129 | Log(("Original instr: %s\n", szOutput));
|
---|
2130 | #endif
|
---|
2131 | }
|
---|
2132 | pVM->hm.s.cPatches = 0;
|
---|
2133 | pVM->hm.s.PatchTree = 0;
|
---|
2134 | pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
|
---|
2135 | pVM->hm.s.fTPRPatchingActive = false;
|
---|
2136 | return VINF_SUCCESS;
|
---|
2137 | }
|
---|
2138 |
|
---|
2139 |
|
---|
2140 | /**
|
---|
2141 | * Worker for enabling patching in a VT-x/AMD-V guest.
|
---|
2142 | *
|
---|
2143 | * @returns VBox status code.
|
---|
2144 | * @param pVM The cross context VM structure.
|
---|
2145 | * @param idCpu VCPU to execute hmR3RemovePatches on.
|
---|
2146 | * @param pPatchMem Patch memory range.
|
---|
2147 | * @param cbPatchMem Size of the memory range.
|
---|
2148 | */
|
---|
2149 | static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
|
---|
2150 | {
|
---|
2151 | int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
|
---|
2152 | AssertRC(rc);
|
---|
2153 |
|
---|
2154 | pVM->hm.s.pGuestPatchMem = pPatchMem;
|
---|
2155 | pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
|
---|
2156 | pVM->hm.s.cbGuestPatchMem = cbPatchMem;
|
---|
2157 | return VINF_SUCCESS;
|
---|
2158 | }
|
---|
2159 |
|
---|
2160 |
|
---|
2161 | /**
|
---|
2162 | * Enable patching in a VT-x/AMD-V guest
|
---|
2163 | *
|
---|
2164 | * @returns VBox status code.
|
---|
2165 | * @param pVM The cross context VM structure.
|
---|
2166 | * @param pPatchMem Patch memory range.
|
---|
2167 | * @param cbPatchMem Size of the memory range.
|
---|
2168 | */
|
---|
2169 | VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
|
---|
2170 | {
|
---|
2171 | VM_ASSERT_EMT(pVM);
|
---|
2172 | Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
|
---|
2173 | if (pVM->cCpus > 1)
|
---|
2174 | {
|
---|
2175 | /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
|
---|
2176 | int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
|
---|
2177 | (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
|
---|
2178 | AssertRC(rc);
|
---|
2179 | return rc;
|
---|
2180 | }
|
---|
2181 | return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
|
---|
2182 | }
|
---|
2183 |
|
---|
2184 |
|
---|
2185 | /**
|
---|
2186 | * Disable patching in a VT-x/AMD-V guest.
|
---|
2187 | *
|
---|
2188 | * @returns VBox status code.
|
---|
2189 | * @param pVM The cross context VM structure.
|
---|
2190 | * @param pPatchMem Patch memory range.
|
---|
2191 | * @param cbPatchMem Size of the memory range.
|
---|
2192 | */
|
---|
2193 | VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
|
---|
2194 | {
|
---|
2195 | Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
|
---|
2196 | RT_NOREF2(pPatchMem, cbPatchMem);
|
---|
2197 |
|
---|
2198 | Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
|
---|
2199 | Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
|
---|
2200 |
|
---|
2201 | /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
|
---|
2202 | int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
|
---|
2203 | (void *)(uintptr_t)VMMGetCpuId(pVM));
|
---|
2204 | AssertRC(rc);
|
---|
2205 |
|
---|
2206 | pVM->hm.s.pGuestPatchMem = 0;
|
---|
2207 | pVM->hm.s.pFreeGuestPatchMem = 0;
|
---|
2208 | pVM->hm.s.cbGuestPatchMem = 0;
|
---|
2209 | pVM->hm.s.fTPRPatchingActive = false;
|
---|
2210 | return VINF_SUCCESS;
|
---|
2211 | }
|
---|
2212 |
|
---|
2213 |
|
---|
2214 | /**
|
---|
2215 | * Callback to patch a TPR instruction (vmmcall or mov cr8).
|
---|
2216 | *
|
---|
2217 | * @returns VBox strict status code.
|
---|
2218 | * @param pVM The cross context VM structure.
|
---|
2219 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
2220 | * @param pvUser User specified CPU context.
|
---|
2221 | *
|
---|
2222 | */
|
---|
2223 | static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
|
---|
2224 | {
|
---|
2225 | /*
|
---|
2226 | * Only execute the handler on the VCPU the original patch request was
|
---|
2227 | * issued. (The other CPU(s) might not yet have switched to protected
|
---|
2228 | * mode, nor have the correct memory context.)
|
---|
2229 | */
|
---|
2230 | VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
|
---|
2231 | if (pVCpu->idCpu != idCpu)
|
---|
2232 | return VINF_SUCCESS;
|
---|
2233 |
|
---|
2234 | /*
|
---|
2235 | * We're racing other VCPUs here, so don't try patch the instruction twice
|
---|
2236 | * and make sure there is still room for our patch record.
|
---|
2237 | */
|
---|
2238 | PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
---|
2239 | PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
|
---|
2240 | if (pPatch)
|
---|
2241 | {
|
---|
2242 | Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
|
---|
2243 | return VINF_SUCCESS;
|
---|
2244 | }
|
---|
2245 | uint32_t const idx = pVM->hm.s.cPatches;
|
---|
2246 | if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
|
---|
2247 | {
|
---|
2248 | Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
|
---|
2249 | return VINF_SUCCESS;
|
---|
2250 | }
|
---|
2251 | pPatch = &pVM->hm.s.aPatches[idx];
|
---|
2252 |
|
---|
2253 | Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
|
---|
2254 |
|
---|
2255 | /*
|
---|
2256 | * Disassembler the instruction and get cracking.
|
---|
2257 | */
|
---|
2258 | DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
|
---|
2259 | PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
|
---|
2260 | uint32_t cbOp;
|
---|
2261 | int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
|
---|
2262 | AssertRC(rc);
|
---|
2263 | if ( rc == VINF_SUCCESS
|
---|
2264 | && pDis->pCurInstr->uOpcode == OP_MOV
|
---|
2265 | && cbOp >= 3)
|
---|
2266 | {
|
---|
2267 | static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
|
---|
2268 |
|
---|
2269 | rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
|
---|
2270 | AssertRC(rc);
|
---|
2271 |
|
---|
2272 | pPatch->cbOp = cbOp;
|
---|
2273 |
|
---|
2274 | if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
|
---|
2275 | {
|
---|
2276 | /* write. */
|
---|
2277 | if (pDis->Param2.fUse == DISUSE_REG_GEN32)
|
---|
2278 | {
|
---|
2279 | pPatch->enmType = HMTPRINSTR_WRITE_REG;
|
---|
2280 | pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
|
---|
2281 | Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
|
---|
2282 | }
|
---|
2283 | else
|
---|
2284 | {
|
---|
2285 | Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
|
---|
2286 | pPatch->enmType = HMTPRINSTR_WRITE_IMM;
|
---|
2287 | pPatch->uSrcOperand = pDis->Param2.uValue;
|
---|
2288 | Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
|
---|
2289 | }
|
---|
2290 | rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
|
---|
2291 | AssertRC(rc);
|
---|
2292 |
|
---|
2293 | memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
|
---|
2294 | pPatch->cbNewOp = sizeof(s_abVMMCall);
|
---|
2295 | STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
|
---|
2296 | }
|
---|
2297 | else
|
---|
2298 | {
|
---|
2299 | /*
|
---|
2300 | * TPR Read.
|
---|
2301 | *
|
---|
2302 | * Found:
|
---|
2303 | * mov eax, dword [fffe0080] (5 bytes)
|
---|
2304 | * Check if next instruction is:
|
---|
2305 | * shr eax, 4
|
---|
2306 | */
|
---|
2307 | Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
|
---|
2308 |
|
---|
2309 | uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
|
---|
2310 | uint8_t const cbOpMmio = cbOp;
|
---|
2311 | uint64_t const uSavedRip = pCtx->rip;
|
---|
2312 |
|
---|
2313 | pCtx->rip += cbOp;
|
---|
2314 | rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
|
---|
2315 | DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
|
---|
2316 | pCtx->rip = uSavedRip;
|
---|
2317 |
|
---|
2318 | if ( rc == VINF_SUCCESS
|
---|
2319 | && pDis->pCurInstr->uOpcode == OP_SHR
|
---|
2320 | && pDis->Param1.fUse == DISUSE_REG_GEN32
|
---|
2321 | && pDis->Param1.Base.idxGenReg == idxMmioReg
|
---|
2322 | && pDis->Param2.fUse == DISUSE_IMMEDIATE8
|
---|
2323 | && pDis->Param2.uValue == 4
|
---|
2324 | && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
|
---|
2325 | {
|
---|
2326 | uint8_t abInstr[15];
|
---|
2327 |
|
---|
2328 | /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
|
---|
2329 | access CR8 in 32-bit mode and not cause a #VMEXIT. */
|
---|
2330 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
|
---|
2331 | AssertRC(rc);
|
---|
2332 |
|
---|
2333 | pPatch->cbOp = cbOpMmio + cbOp;
|
---|
2334 |
|
---|
2335 | /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
|
---|
2336 | abInstr[0] = 0xF0;
|
---|
2337 | abInstr[1] = 0x0F;
|
---|
2338 | abInstr[2] = 0x20;
|
---|
2339 | abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
|
---|
2340 | for (unsigned i = 4; i < pPatch->cbOp; i++)
|
---|
2341 | abInstr[i] = 0x90; /* nop */
|
---|
2342 |
|
---|
2343 | rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
|
---|
2344 | AssertRC(rc);
|
---|
2345 |
|
---|
2346 | memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
|
---|
2347 | pPatch->cbNewOp = pPatch->cbOp;
|
---|
2348 | STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
|
---|
2349 |
|
---|
2350 | Log(("Acceptable read/shr candidate!\n"));
|
---|
2351 | pPatch->enmType = HMTPRINSTR_READ_SHR4;
|
---|
2352 | }
|
---|
2353 | else
|
---|
2354 | {
|
---|
2355 | pPatch->enmType = HMTPRINSTR_READ;
|
---|
2356 | pPatch->uDstOperand = idxMmioReg;
|
---|
2357 |
|
---|
2358 | rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
|
---|
2359 | AssertRC(rc);
|
---|
2360 |
|
---|
2361 | memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
|
---|
2362 | pPatch->cbNewOp = sizeof(s_abVMMCall);
|
---|
2363 | STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
|
---|
2364 | Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
|
---|
2365 | }
|
---|
2366 | }
|
---|
2367 |
|
---|
2368 | pPatch->Core.Key = pCtx->eip;
|
---|
2369 | rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
|
---|
2370 | AssertRC(rc);
|
---|
2371 |
|
---|
2372 | pVM->hm.s.cPatches++;
|
---|
2373 | return VINF_SUCCESS;
|
---|
2374 | }
|
---|
2375 |
|
---|
2376 | /*
|
---|
2377 | * Save invalid patch, so we will not try again.
|
---|
2378 | */
|
---|
2379 | Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
|
---|
2380 | pPatch->Core.Key = pCtx->eip;
|
---|
2381 | pPatch->enmType = HMTPRINSTR_INVALID;
|
---|
2382 | rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
|
---|
2383 | AssertRC(rc);
|
---|
2384 | pVM->hm.s.cPatches++;
|
---|
2385 | STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
|
---|
2386 | return VINF_SUCCESS;
|
---|
2387 | }
|
---|
2388 |
|
---|
2389 |
|
---|
2390 | /**
|
---|
2391 | * Callback to patch a TPR instruction (jump to generated code).
|
---|
2392 | *
|
---|
2393 | * @returns VBox strict status code.
|
---|
2394 | * @param pVM The cross context VM structure.
|
---|
2395 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
2396 | * @param pvUser User specified CPU context.
|
---|
2397 | *
|
---|
2398 | */
|
---|
2399 | static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
|
---|
2400 | {
|
---|
2401 | /*
|
---|
2402 | * Only execute the handler on the VCPU the original patch request was
|
---|
2403 | * issued. (The other CPU(s) might not yet have switched to protected
|
---|
2404 | * mode, nor have the correct memory context.)
|
---|
2405 | */
|
---|
2406 | VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
|
---|
2407 | if (pVCpu->idCpu != idCpu)
|
---|
2408 | return VINF_SUCCESS;
|
---|
2409 |
|
---|
2410 | /*
|
---|
2411 | * We're racing other VCPUs here, so don't try patch the instruction twice
|
---|
2412 | * and make sure there is still room for our patch record.
|
---|
2413 | */
|
---|
2414 | PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
---|
2415 | PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
|
---|
2416 | if (pPatch)
|
---|
2417 | {
|
---|
2418 | Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
|
---|
2419 | return VINF_SUCCESS;
|
---|
2420 | }
|
---|
2421 | uint32_t const idx = pVM->hm.s.cPatches;
|
---|
2422 | if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
|
---|
2423 | {
|
---|
2424 | Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
|
---|
2425 | return VINF_SUCCESS;
|
---|
2426 | }
|
---|
2427 | pPatch = &pVM->hm.s.aPatches[idx];
|
---|
2428 |
|
---|
2429 | Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
|
---|
2430 | DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
|
---|
2431 |
|
---|
2432 | /*
|
---|
2433 | * Disassemble the instruction and get cracking.
|
---|
2434 | */
|
---|
2435 | PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
|
---|
2436 | uint32_t cbOp;
|
---|
2437 | int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
|
---|
2438 | AssertRC(rc);
|
---|
2439 | if ( rc == VINF_SUCCESS
|
---|
2440 | && pDis->pCurInstr->uOpcode == OP_MOV
|
---|
2441 | && cbOp >= 5)
|
---|
2442 | {
|
---|
2443 | uint8_t aPatch[64];
|
---|
2444 | uint32_t off = 0;
|
---|
2445 |
|
---|
2446 | rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
|
---|
2447 | AssertRC(rc);
|
---|
2448 |
|
---|
2449 | pPatch->cbOp = cbOp;
|
---|
2450 | pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
|
---|
2451 |
|
---|
2452 | if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
|
---|
2453 | {
|
---|
2454 | /*
|
---|
2455 | * TPR write:
|
---|
2456 | *
|
---|
2457 | * push ECX [51]
|
---|
2458 | * push EDX [52]
|
---|
2459 | * push EAX [50]
|
---|
2460 | * xor EDX,EDX [31 D2]
|
---|
2461 | * mov EAX,EAX [89 C0]
|
---|
2462 | * or
|
---|
2463 | * mov EAX,0000000CCh [B8 CC 00 00 00]
|
---|
2464 | * mov ECX,0C0000082h [B9 82 00 00 C0]
|
---|
2465 | * wrmsr [0F 30]
|
---|
2466 | * pop EAX [58]
|
---|
2467 | * pop EDX [5A]
|
---|
2468 | * pop ECX [59]
|
---|
2469 | * jmp return_address [E9 return_address]
|
---|
2470 | *
|
---|
2471 | */
|
---|
2472 | bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
|
---|
2473 |
|
---|
2474 | aPatch[off++] = 0x51; /* push ecx */
|
---|
2475 | aPatch[off++] = 0x52; /* push edx */
|
---|
2476 | if (!fUsesEax)
|
---|
2477 | aPatch[off++] = 0x50; /* push eax */
|
---|
2478 | aPatch[off++] = 0x31; /* xor edx, edx */
|
---|
2479 | aPatch[off++] = 0xD2;
|
---|
2480 | if (pDis->Param2.fUse == DISUSE_REG_GEN32)
|
---|
2481 | {
|
---|
2482 | if (!fUsesEax)
|
---|
2483 | {
|
---|
2484 | aPatch[off++] = 0x89; /* mov eax, src_reg */
|
---|
2485 | aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
|
---|
2486 | }
|
---|
2487 | }
|
---|
2488 | else
|
---|
2489 | {
|
---|
2490 | Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
|
---|
2491 | aPatch[off++] = 0xB8; /* mov eax, immediate */
|
---|
2492 | *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
|
---|
2493 | off += sizeof(uint32_t);
|
---|
2494 | }
|
---|
2495 | aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
|
---|
2496 | *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
|
---|
2497 | off += sizeof(uint32_t);
|
---|
2498 |
|
---|
2499 | aPatch[off++] = 0x0F; /* wrmsr */
|
---|
2500 | aPatch[off++] = 0x30;
|
---|
2501 | if (!fUsesEax)
|
---|
2502 | aPatch[off++] = 0x58; /* pop eax */
|
---|
2503 | aPatch[off++] = 0x5A; /* pop edx */
|
---|
2504 | aPatch[off++] = 0x59; /* pop ecx */
|
---|
2505 | }
|
---|
2506 | else
|
---|
2507 | {
|
---|
2508 | /*
|
---|
2509 | * TPR read:
|
---|
2510 | *
|
---|
2511 | * push ECX [51]
|
---|
2512 | * push EDX [52]
|
---|
2513 | * push EAX [50]
|
---|
2514 | * mov ECX,0C0000082h [B9 82 00 00 C0]
|
---|
2515 | * rdmsr [0F 32]
|
---|
2516 | * mov EAX,EAX [89 C0]
|
---|
2517 | * pop EAX [58]
|
---|
2518 | * pop EDX [5A]
|
---|
2519 | * pop ECX [59]
|
---|
2520 | * jmp return_address [E9 return_address]
|
---|
2521 | *
|
---|
2522 | */
|
---|
2523 | Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
|
---|
2524 |
|
---|
2525 | if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
|
---|
2526 | aPatch[off++] = 0x51; /* push ecx */
|
---|
2527 | if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
|
---|
2528 | aPatch[off++] = 0x52; /* push edx */
|
---|
2529 | if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
|
---|
2530 | aPatch[off++] = 0x50; /* push eax */
|
---|
2531 |
|
---|
2532 | aPatch[off++] = 0x31; /* xor edx, edx */
|
---|
2533 | aPatch[off++] = 0xD2;
|
---|
2534 |
|
---|
2535 | aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
|
---|
2536 | *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
|
---|
2537 | off += sizeof(uint32_t);
|
---|
2538 |
|
---|
2539 | aPatch[off++] = 0x0F; /* rdmsr */
|
---|
2540 | aPatch[off++] = 0x32;
|
---|
2541 |
|
---|
2542 | if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
|
---|
2543 | {
|
---|
2544 | aPatch[off++] = 0x89; /* mov dst_reg, eax */
|
---|
2545 | aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
|
---|
2546 | }
|
---|
2547 |
|
---|
2548 | if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
|
---|
2549 | aPatch[off++] = 0x58; /* pop eax */
|
---|
2550 | if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
|
---|
2551 | aPatch[off++] = 0x5A; /* pop edx */
|
---|
2552 | if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
|
---|
2553 | aPatch[off++] = 0x59; /* pop ecx */
|
---|
2554 | }
|
---|
2555 | aPatch[off++] = 0xE9; /* jmp return_address */
|
---|
2556 | *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
|
---|
2557 | off += sizeof(RTRCUINTPTR);
|
---|
2558 |
|
---|
2559 | if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
|
---|
2560 | {
|
---|
2561 | /* Write new code to the patch buffer. */
|
---|
2562 | rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
|
---|
2563 | AssertRC(rc);
|
---|
2564 |
|
---|
2565 | #ifdef LOG_ENABLED
|
---|
2566 | uint32_t cbCurInstr;
|
---|
2567 | for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
|
---|
2568 | GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
|
---|
2569 | GCPtrInstr += RT_MAX(cbCurInstr, 1))
|
---|
2570 | {
|
---|
2571 | char szOutput[256];
|
---|
2572 | rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
|
---|
2573 | szOutput, sizeof(szOutput), &cbCurInstr);
|
---|
2574 | if (RT_SUCCESS(rc))
|
---|
2575 | Log(("Patch instr %s\n", szOutput));
|
---|
2576 | else
|
---|
2577 | Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
|
---|
2578 | }
|
---|
2579 | #endif
|
---|
2580 |
|
---|
2581 | pPatch->aNewOpcode[0] = 0xE9;
|
---|
2582 | *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
|
---|
2583 |
|
---|
2584 | /* Overwrite the TPR instruction with a jump. */
|
---|
2585 | rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
|
---|
2586 | AssertRC(rc);
|
---|
2587 |
|
---|
2588 | DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
|
---|
2589 |
|
---|
2590 | pVM->hm.s.pFreeGuestPatchMem += off;
|
---|
2591 | pPatch->cbNewOp = 5;
|
---|
2592 |
|
---|
2593 | pPatch->Core.Key = pCtx->eip;
|
---|
2594 | rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
|
---|
2595 | AssertRC(rc);
|
---|
2596 |
|
---|
2597 | pVM->hm.s.cPatches++;
|
---|
2598 | pVM->hm.s.fTPRPatchingActive = true;
|
---|
2599 | STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
|
---|
2600 | return VINF_SUCCESS;
|
---|
2601 | }
|
---|
2602 |
|
---|
2603 | Log(("Ran out of space in our patch buffer!\n"));
|
---|
2604 | }
|
---|
2605 | else
|
---|
2606 | Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
|
---|
2607 |
|
---|
2608 |
|
---|
2609 | /*
|
---|
2610 | * Save invalid patch, so we will not try again.
|
---|
2611 | */
|
---|
2612 | pPatch = &pVM->hm.s.aPatches[idx];
|
---|
2613 | pPatch->Core.Key = pCtx->eip;
|
---|
2614 | pPatch->enmType = HMTPRINSTR_INVALID;
|
---|
2615 | rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
|
---|
2616 | AssertRC(rc);
|
---|
2617 | pVM->hm.s.cPatches++;
|
---|
2618 | STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
|
---|
2619 | return VINF_SUCCESS;
|
---|
2620 | }
|
---|
2621 |
|
---|
2622 |
|
---|
2623 | /**
|
---|
2624 | * Attempt to patch TPR mmio instructions.
|
---|
2625 | *
|
---|
2626 | * @returns VBox status code.
|
---|
2627 | * @param pVM The cross context VM structure.
|
---|
2628 | * @param pVCpu The cross context virtual CPU structure.
|
---|
2629 | * @param pCtx Pointer to the guest CPU context.
|
---|
2630 | */
|
---|
2631 | VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
|
---|
2632 | {
|
---|
2633 | NOREF(pCtx);
|
---|
2634 | int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
|
---|
2635 | pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
|
---|
2636 | (void *)(uintptr_t)pVCpu->idCpu);
|
---|
2637 | AssertRC(rc);
|
---|
2638 | return rc;
|
---|
2639 | }
|
---|
2640 |
|
---|
2641 |
|
---|
2642 | /**
|
---|
2643 | * Checks if a code selector (CS) is suitable for execution
|
---|
2644 | * within VMX when unrestricted execution isn't available.
|
---|
2645 | *
|
---|
2646 | * @returns true if selector is suitable for VMX, otherwise
|
---|
2647 | * false.
|
---|
2648 | * @param pSel Pointer to the selector to check (CS).
|
---|
2649 | * @param uStackDpl The CPL, aka the DPL of the stack segment.
|
---|
2650 | */
|
---|
2651 | static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
|
---|
2652 | {
|
---|
2653 | /*
|
---|
2654 | * Segment must be an accessed code segment, it must be present and it must
|
---|
2655 | * be usable.
|
---|
2656 | * Note! These are all standard requirements and if CS holds anything else
|
---|
2657 | * we've got buggy code somewhere!
|
---|
2658 | */
|
---|
2659 | AssertCompile(X86DESCATTR_TYPE == 0xf);
|
---|
2660 | AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
|
---|
2661 | == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
|
---|
2662 | ("%#x\n", pSel->Attr.u),
|
---|
2663 | false);
|
---|
2664 |
|
---|
2665 | /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
|
---|
2666 | must equal SS.DPL for non-confroming segments.
|
---|
2667 | Note! This is also a hard requirement like above. */
|
---|
2668 | AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
|
---|
2669 | ? pSel->Attr.n.u2Dpl <= uStackDpl
|
---|
2670 | : pSel->Attr.n.u2Dpl == uStackDpl,
|
---|
2671 | ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
|
---|
2672 | false);
|
---|
2673 |
|
---|
2674 | /*
|
---|
2675 | * The following two requirements are VT-x specific:
|
---|
2676 | * - G bit must be set if any high limit bits are set.
|
---|
2677 | * - G bit must be clear if any low limit bits are clear.
|
---|
2678 | */
|
---|
2679 | if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
|
---|
2680 | && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
|
---|
2681 | return true;
|
---|
2682 | return false;
|
---|
2683 | }
|
---|
2684 |
|
---|
2685 |
|
---|
2686 | /**
|
---|
2687 | * Checks if a data selector (DS/ES/FS/GS) is suitable for
|
---|
2688 | * execution within VMX when unrestricted execution isn't
|
---|
2689 | * available.
|
---|
2690 | *
|
---|
2691 | * @returns true if selector is suitable for VMX, otherwise
|
---|
2692 | * false.
|
---|
2693 | * @param pSel Pointer to the selector to check
|
---|
2694 | * (DS/ES/FS/GS).
|
---|
2695 | */
|
---|
2696 | static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
|
---|
2697 | {
|
---|
2698 | /*
|
---|
2699 | * Unusable segments are OK. These days they should be marked as such, as
|
---|
2700 | * but as an alternative we for old saved states and AMD<->VT-x migration
|
---|
2701 | * we also treat segments with all the attributes cleared as unusable.
|
---|
2702 | */
|
---|
2703 | if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
|
---|
2704 | return true;
|
---|
2705 |
|
---|
2706 | /** @todo tighten these checks. Will require CPUM load adjusting. */
|
---|
2707 |
|
---|
2708 | /* Segment must be accessed. */
|
---|
2709 | if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
|
---|
2710 | {
|
---|
2711 | /* Code segments must also be readable. */
|
---|
2712 | if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
|
---|
2713 | || (pSel->Attr.u & X86_SEL_TYPE_READ))
|
---|
2714 | {
|
---|
2715 | /* The S bit must be set. */
|
---|
2716 | if (pSel->Attr.n.u1DescType)
|
---|
2717 | {
|
---|
2718 | /* Except for conforming segments, DPL >= RPL. */
|
---|
2719 | if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
|
---|
2720 | || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
|
---|
2721 | {
|
---|
2722 | /* Segment must be present. */
|
---|
2723 | if (pSel->Attr.n.u1Present)
|
---|
2724 | {
|
---|
2725 | /*
|
---|
2726 | * The following two requirements are VT-x specific:
|
---|
2727 | * - G bit must be set if any high limit bits are set.
|
---|
2728 | * - G bit must be clear if any low limit bits are clear.
|
---|
2729 | */
|
---|
2730 | if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
|
---|
2731 | && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
|
---|
2732 | return true;
|
---|
2733 | }
|
---|
2734 | }
|
---|
2735 | }
|
---|
2736 | }
|
---|
2737 | }
|
---|
2738 |
|
---|
2739 | return false;
|
---|
2740 | }
|
---|
2741 |
|
---|
2742 |
|
---|
2743 | /**
|
---|
2744 | * Checks if the stack selector (SS) is suitable for execution
|
---|
2745 | * within VMX when unrestricted execution isn't available.
|
---|
2746 | *
|
---|
2747 | * @returns true if selector is suitable for VMX, otherwise
|
---|
2748 | * false.
|
---|
2749 | * @param pSel Pointer to the selector to check (SS).
|
---|
2750 | */
|
---|
2751 | static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
|
---|
2752 | {
|
---|
2753 | /*
|
---|
2754 | * Unusable segments are OK. These days they should be marked as such, as
|
---|
2755 | * but as an alternative we for old saved states and AMD<->VT-x migration
|
---|
2756 | * we also treat segments with all the attributes cleared as unusable.
|
---|
2757 | */
|
---|
2758 | /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
|
---|
2759 | if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
|
---|
2760 | return true;
|
---|
2761 |
|
---|
2762 | /*
|
---|
2763 | * Segment must be an accessed writable segment, it must be present.
|
---|
2764 | * Note! These are all standard requirements and if SS holds anything else
|
---|
2765 | * we've got buggy code somewhere!
|
---|
2766 | */
|
---|
2767 | AssertCompile(X86DESCATTR_TYPE == 0xf);
|
---|
2768 | AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
|
---|
2769 | == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
|
---|
2770 | ("%#x\n", pSel->Attr.u),
|
---|
2771 | false);
|
---|
2772 |
|
---|
2773 | /* DPL must equal RPL.
|
---|
2774 | Note! This is also a hard requirement like above. */
|
---|
2775 | AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
|
---|
2776 | ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
|
---|
2777 | false);
|
---|
2778 |
|
---|
2779 | /*
|
---|
2780 | * The following two requirements are VT-x specific:
|
---|
2781 | * - G bit must be set if any high limit bits are set.
|
---|
2782 | * - G bit must be clear if any low limit bits are clear.
|
---|
2783 | */
|
---|
2784 | if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
|
---|
2785 | && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
|
---|
2786 | return true;
|
---|
2787 | return false;
|
---|
2788 | }
|
---|
2789 |
|
---|
2790 |
|
---|
2791 | /**
|
---|
2792 | * Force execution of the current IO code in the recompiler.
|
---|
2793 | *
|
---|
2794 | * @returns VBox status code.
|
---|
2795 | * @param pVM The cross context VM structure.
|
---|
2796 | * @param pCtx Partial VM execution context.
|
---|
2797 | */
|
---|
2798 | VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
|
---|
2799 | {
|
---|
2800 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
2801 |
|
---|
2802 | Assert(HMIsEnabled(pVM));
|
---|
2803 | Log(("HMR3EmulateIoBlock\n"));
|
---|
2804 |
|
---|
2805 | /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
|
---|
2806 | if (HMCanEmulateIoBlockEx(pCtx))
|
---|
2807 | {
|
---|
2808 | Log(("HMR3EmulateIoBlock -> enabled\n"));
|
---|
2809 | pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
|
---|
2810 | pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
|
---|
2811 | pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
|
---|
2812 | return VINF_EM_RESCHEDULE_REM;
|
---|
2813 | }
|
---|
2814 | return VINF_SUCCESS;
|
---|
2815 | }
|
---|
2816 |
|
---|
2817 |
|
---|
2818 | /**
|
---|
2819 | * Checks if we can currently use hardware accelerated raw mode.
|
---|
2820 | *
|
---|
2821 | * @returns true if we can currently use hardware acceleration, otherwise false.
|
---|
2822 | * @param pVM The cross context VM structure.
|
---|
2823 | * @param pCtx Partial VM execution context.
|
---|
2824 | */
|
---|
2825 | VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
|
---|
2826 | {
|
---|
2827 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
2828 |
|
---|
2829 | Assert(HMIsEnabled(pVM));
|
---|
2830 |
|
---|
2831 | #ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
|
---|
2832 | if (CPUMIsGuestInNestedHwVirtMode(pCtx))
|
---|
2833 | {
|
---|
2834 | Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
|
---|
2835 | return false;
|
---|
2836 | }
|
---|
2837 | #endif
|
---|
2838 |
|
---|
2839 | /* If we're still executing the IO code, then return false. */
|
---|
2840 | if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
|
---|
2841 | && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
|
---|
2842 | && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
|
---|
2843 | && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
|
---|
2844 | return false;
|
---|
2845 |
|
---|
2846 | pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
|
---|
2847 |
|
---|
2848 | /* AMD-V supports real & protected mode with or without paging. */
|
---|
2849 | if (pVM->hm.s.svm.fEnabled)
|
---|
2850 | {
|
---|
2851 | pVCpu->hm.s.fActive = true;
|
---|
2852 | return true;
|
---|
2853 | }
|
---|
2854 |
|
---|
2855 | pVCpu->hm.s.fActive = false;
|
---|
2856 |
|
---|
2857 | /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
|
---|
2858 | Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
|
---|
2859 | || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
|
---|
2860 |
|
---|
2861 | bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
|
---|
2862 | if (!pVM->hm.s.vmx.fUnrestrictedGuest)
|
---|
2863 | {
|
---|
2864 | /*
|
---|
2865 | * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
|
---|
2866 | * guest execution feature is missing (VT-x only).
|
---|
2867 | */
|
---|
2868 | if (fSupportsRealMode)
|
---|
2869 | {
|
---|
2870 | if (CPUMIsGuestInRealModeEx(pCtx))
|
---|
2871 | {
|
---|
2872 | /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
|
---|
2873 | * bases and limits, i.e. limit must be 64K and base must be selector * 16.
|
---|
2874 | * If this is not true, we cannot execute real mode as V86 and have to fall
|
---|
2875 | * back to emulation.
|
---|
2876 | */
|
---|
2877 | if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
|
---|
2878 | || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
|
---|
2879 | || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
|
---|
2880 | || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
|
---|
2881 | || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
|
---|
2882 | || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
|
---|
2883 | {
|
---|
2884 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
|
---|
2885 | return false;
|
---|
2886 | }
|
---|
2887 | if ( (pCtx->cs.u32Limit != 0xffff)
|
---|
2888 | || (pCtx->ds.u32Limit != 0xffff)
|
---|
2889 | || (pCtx->es.u32Limit != 0xffff)
|
---|
2890 | || (pCtx->ss.u32Limit != 0xffff)
|
---|
2891 | || (pCtx->fs.u32Limit != 0xffff)
|
---|
2892 | || (pCtx->gs.u32Limit != 0xffff))
|
---|
2893 | {
|
---|
2894 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
|
---|
2895 | return false;
|
---|
2896 | }
|
---|
2897 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
|
---|
2898 | }
|
---|
2899 | else
|
---|
2900 | {
|
---|
2901 | /* Verify the requirements for executing code in protected
|
---|
2902 | mode. VT-x can't handle the CPU state right after a switch
|
---|
2903 | from real to protected mode. (all sorts of RPL & DPL assumptions). */
|
---|
2904 | if (pVCpu->hm.s.vmx.fWasInRealMode)
|
---|
2905 | {
|
---|
2906 | /** @todo If guest is in V86 mode, these checks should be different! */
|
---|
2907 | if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
|
---|
2908 | {
|
---|
2909 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
|
---|
2910 | return false;
|
---|
2911 | }
|
---|
2912 | if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
|
---|
2913 | || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
|
---|
2914 | || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
|
---|
2915 | || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
|
---|
2916 | || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
|
---|
2917 | || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
|
---|
2918 | {
|
---|
2919 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
|
---|
2920 | return false;
|
---|
2921 | }
|
---|
2922 | }
|
---|
2923 | /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
|
---|
2924 | if (pCtx->gdtr.cbGdt)
|
---|
2925 | {
|
---|
2926 | if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
|
---|
2927 | {
|
---|
2928 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
|
---|
2929 | return false;
|
---|
2930 | }
|
---|
2931 | else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
|
---|
2932 | {
|
---|
2933 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
|
---|
2934 | return false;
|
---|
2935 | }
|
---|
2936 | }
|
---|
2937 | STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
|
---|
2938 | }
|
---|
2939 | }
|
---|
2940 | else
|
---|
2941 | {
|
---|
2942 | if ( !CPUMIsGuestInLongModeEx(pCtx)
|
---|
2943 | && !pVM->hm.s.vmx.fUnrestrictedGuest)
|
---|
2944 | {
|
---|
2945 | if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
|
---|
2946 | || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
|
---|
2947 | return false;
|
---|
2948 |
|
---|
2949 | /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
|
---|
2950 | if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
|
---|
2951 | return false;
|
---|
2952 |
|
---|
2953 | /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
|
---|
2954 | /* Windows XP; switch to protected mode; all selectors are marked not present in the
|
---|
2955 | * hidden registers (possible recompiler bug; see load_seg_vm) */
|
---|
2956 | if (pCtx->cs.Attr.n.u1Present == 0)
|
---|
2957 | return false;
|
---|
2958 | if (pCtx->ss.Attr.n.u1Present == 0)
|
---|
2959 | return false;
|
---|
2960 |
|
---|
2961 | /* Windows XP: possible same as above, but new recompiler requires new heuristics?
|
---|
2962 | VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
|
---|
2963 | /** @todo This check is actually wrong, it doesn't take the direction of the
|
---|
2964 | * stack segment into account. But, it does the job for now. */
|
---|
2965 | if (pCtx->rsp >= pCtx->ss.u32Limit)
|
---|
2966 | return false;
|
---|
2967 | }
|
---|
2968 | }
|
---|
2969 | }
|
---|
2970 |
|
---|
2971 | if (pVM->hm.s.vmx.fEnabled)
|
---|
2972 | {
|
---|
2973 | uint32_t mask;
|
---|
2974 |
|
---|
2975 | /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
|
---|
2976 | mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
|
---|
2977 | /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
|
---|
2978 | mask &= ~X86_CR0_NE;
|
---|
2979 |
|
---|
2980 | if (fSupportsRealMode)
|
---|
2981 | {
|
---|
2982 | /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
|
---|
2983 | mask &= ~(X86_CR0_PG|X86_CR0_PE);
|
---|
2984 | }
|
---|
2985 | else
|
---|
2986 | {
|
---|
2987 | /* We support protected mode without paging using identity mapping. */
|
---|
2988 | mask &= ~X86_CR0_PG;
|
---|
2989 | }
|
---|
2990 | if ((pCtx->cr0 & mask) != mask)
|
---|
2991 | return false;
|
---|
2992 |
|
---|
2993 | /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
|
---|
2994 | mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
|
---|
2995 | if ((pCtx->cr0 & mask) != 0)
|
---|
2996 | return false;
|
---|
2997 |
|
---|
2998 | /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
|
---|
2999 | mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
|
---|
3000 | mask &= ~X86_CR4_VMXE;
|
---|
3001 | if ((pCtx->cr4 & mask) != mask)
|
---|
3002 | return false;
|
---|
3003 |
|
---|
3004 | /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
|
---|
3005 | mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
|
---|
3006 | if ((pCtx->cr4 & mask) != 0)
|
---|
3007 | return false;
|
---|
3008 |
|
---|
3009 | pVCpu->hm.s.fActive = true;
|
---|
3010 | return true;
|
---|
3011 | }
|
---|
3012 |
|
---|
3013 | return false;
|
---|
3014 | }
|
---|
3015 |
|
---|
3016 |
|
---|
3017 | /**
|
---|
3018 | * Checks if we need to reschedule due to VMM device heap changes.
|
---|
3019 | *
|
---|
3020 | * @returns true if a reschedule is required, otherwise false.
|
---|
3021 | * @param pVM The cross context VM structure.
|
---|
3022 | * @param pCtx VM execution context.
|
---|
3023 | */
|
---|
3024 | VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
|
---|
3025 | {
|
---|
3026 | /*
|
---|
3027 | * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
|
---|
3028 | * when the unrestricted guest execution feature is missing (VT-x only).
|
---|
3029 | */
|
---|
3030 | if ( pVM->hm.s.vmx.fEnabled
|
---|
3031 | && !pVM->hm.s.vmx.fUnrestrictedGuest
|
---|
3032 | && CPUMIsGuestInRealModeEx(pCtx)
|
---|
3033 | && !PDMVmmDevHeapIsEnabled(pVM))
|
---|
3034 | {
|
---|
3035 | return true;
|
---|
3036 | }
|
---|
3037 |
|
---|
3038 | return false;
|
---|
3039 | }
|
---|
3040 |
|
---|
3041 |
|
---|
3042 | /**
|
---|
3043 | * Noticiation callback from DBGF when interrupt breakpoints or generic debug
|
---|
3044 | * event settings changes.
|
---|
3045 | *
|
---|
3046 | * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
|
---|
3047 | * function is just updating the VM globals.
|
---|
3048 | *
|
---|
3049 | * @param pVM The VM cross context VM structure.
|
---|
3050 | * @thread EMT(0)
|
---|
3051 | */
|
---|
3052 | VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
|
---|
3053 | {
|
---|
3054 | /* Interrupts. */
|
---|
3055 | bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
|
---|
3056 | || pVM->dbgf.ro.cHardIntBreakpoints > 0;
|
---|
3057 |
|
---|
3058 | /* CPU Exceptions. */
|
---|
3059 | for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
|
---|
3060 | !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
|
---|
3061 | enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
|
---|
3062 | fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
|
---|
3063 |
|
---|
3064 | /* Common VM exits. */
|
---|
3065 | for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
|
---|
3066 | !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
|
---|
3067 | enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
|
---|
3068 | fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
|
---|
3069 |
|
---|
3070 | /* Vendor specific VM exits. */
|
---|
3071 | if (HMR3IsVmxEnabled(pVM->pUVM))
|
---|
3072 | for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
|
---|
3073 | !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
|
---|
3074 | enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
|
---|
3075 | fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
|
---|
3076 | else
|
---|
3077 | for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
|
---|
3078 | !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
|
---|
3079 | enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
|
---|
3080 | fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
|
---|
3081 |
|
---|
3082 | /* Done. */
|
---|
3083 | pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
|
---|
3084 | }
|
---|
3085 |
|
---|
3086 |
|
---|
3087 | /**
|
---|
3088 | * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
|
---|
3089 | *
|
---|
3090 | * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
|
---|
3091 | * per CPU settings.
|
---|
3092 | *
|
---|
3093 | * @param pVM The VM cross context VM structure.
|
---|
3094 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
3095 | */
|
---|
3096 | VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
|
---|
3097 | {
|
---|
3098 | pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
|
---|
3099 | }
|
---|
3100 |
|
---|
3101 |
|
---|
3102 | /**
|
---|
3103 | * Notification from EM about a rescheduling into hardware assisted execution
|
---|
3104 | * mode.
|
---|
3105 | *
|
---|
3106 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
3107 | */
|
---|
3108 | VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
|
---|
3109 | {
|
---|
3110 | HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
|
---|
3111 | }
|
---|
3112 |
|
---|
3113 |
|
---|
3114 | /**
|
---|
3115 | * Notification from EM about returning from instruction emulation (REM / EM).
|
---|
3116 | *
|
---|
3117 | * @param pVCpu The cross context virtual CPU structure.
|
---|
3118 | */
|
---|
3119 | VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
|
---|
3120 | {
|
---|
3121 | HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
|
---|
3122 | }
|
---|
3123 |
|
---|
3124 |
|
---|
3125 | /**
|
---|
3126 | * Checks if we are currently using hardware acceleration.
|
---|
3127 | *
|
---|
3128 | * @returns true if hardware acceleration is being used, otherwise false.
|
---|
3129 | * @param pVCpu The cross context virtual CPU structure.
|
---|
3130 | */
|
---|
3131 | VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
|
---|
3132 | {
|
---|
3133 | return pVCpu->hm.s.fActive;
|
---|
3134 | }
|
---|
3135 |
|
---|
3136 |
|
---|
3137 | /**
|
---|
3138 | * External interface for querying whether hardware acceleration is enabled.
|
---|
3139 | *
|
---|
3140 | * @returns true if VT-x or AMD-V is being used, otherwise false.
|
---|
3141 | * @param pUVM The user mode VM handle.
|
---|
3142 | * @sa HMIsEnabled, HMIsEnabledNotMacro.
|
---|
3143 | */
|
---|
3144 | VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
|
---|
3145 | {
|
---|
3146 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3147 | PVM pVM = pUVM->pVM;
|
---|
3148 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3149 | return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
|
---|
3150 | }
|
---|
3151 |
|
---|
3152 |
|
---|
3153 | /**
|
---|
3154 | * External interface for querying whether VT-x is being used.
|
---|
3155 | *
|
---|
3156 | * @returns true if VT-x is being used, otherwise false.
|
---|
3157 | * @param pUVM The user mode VM handle.
|
---|
3158 | * @sa HMR3IsSvmEnabled, HMIsEnabled
|
---|
3159 | */
|
---|
3160 | VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
|
---|
3161 | {
|
---|
3162 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3163 | PVM pVM = pUVM->pVM;
|
---|
3164 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3165 | return pVM->hm.s.vmx.fEnabled
|
---|
3166 | && pVM->hm.s.vmx.fSupported
|
---|
3167 | && pVM->fHMEnabled;
|
---|
3168 | }
|
---|
3169 |
|
---|
3170 |
|
---|
3171 | /**
|
---|
3172 | * External interface for querying whether AMD-V is being used.
|
---|
3173 | *
|
---|
3174 | * @returns true if VT-x is being used, otherwise false.
|
---|
3175 | * @param pUVM The user mode VM handle.
|
---|
3176 | * @sa HMR3IsVmxEnabled, HMIsEnabled
|
---|
3177 | */
|
---|
3178 | VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
|
---|
3179 | {
|
---|
3180 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3181 | PVM pVM = pUVM->pVM;
|
---|
3182 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3183 | return pVM->hm.s.svm.fEnabled
|
---|
3184 | && pVM->hm.s.svm.fSupported
|
---|
3185 | && pVM->fHMEnabled;
|
---|
3186 | }
|
---|
3187 |
|
---|
3188 |
|
---|
3189 | /**
|
---|
3190 | * Checks if we are currently using nested paging.
|
---|
3191 | *
|
---|
3192 | * @returns true if nested paging is being used, otherwise false.
|
---|
3193 | * @param pUVM The user mode VM handle.
|
---|
3194 | */
|
---|
3195 | VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
|
---|
3196 | {
|
---|
3197 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3198 | PVM pVM = pUVM->pVM;
|
---|
3199 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3200 | return pVM->hm.s.fNestedPaging;
|
---|
3201 | }
|
---|
3202 |
|
---|
3203 |
|
---|
3204 | /**
|
---|
3205 | * Checks if virtualized APIC registers is enabled.
|
---|
3206 | *
|
---|
3207 | * When enabled this feature allows the hardware to access most of the
|
---|
3208 | * APIC registers in the virtual-APIC page without causing VM-exits. See
|
---|
3209 | * Intel spec. 29.1.1 "Virtualized APIC Registers".
|
---|
3210 | *
|
---|
3211 | * @returns true if virtualized APIC registers is enabled, otherwise
|
---|
3212 | * false.
|
---|
3213 | * @param pUVM The user mode VM handle.
|
---|
3214 | */
|
---|
3215 | VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
|
---|
3216 | {
|
---|
3217 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3218 | PVM pVM = pUVM->pVM;
|
---|
3219 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3220 | return pVM->hm.s.fVirtApicRegs;
|
---|
3221 | }
|
---|
3222 |
|
---|
3223 |
|
---|
3224 | /**
|
---|
3225 | * Checks if APIC posted-interrupt processing is enabled.
|
---|
3226 | *
|
---|
3227 | * This returns whether we can deliver interrupts to the guest without
|
---|
3228 | * leaving guest-context by updating APIC state from host-context.
|
---|
3229 | *
|
---|
3230 | * @returns true if APIC posted-interrupt processing is enabled,
|
---|
3231 | * otherwise false.
|
---|
3232 | * @param pUVM The user mode VM handle.
|
---|
3233 | */
|
---|
3234 | VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
|
---|
3235 | {
|
---|
3236 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3237 | PVM pVM = pUVM->pVM;
|
---|
3238 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3239 | return pVM->hm.s.fPostedIntrs;
|
---|
3240 | }
|
---|
3241 |
|
---|
3242 |
|
---|
3243 | /**
|
---|
3244 | * Checks if we are currently using VPID in VT-x mode.
|
---|
3245 | *
|
---|
3246 | * @returns true if VPID is being used, otherwise false.
|
---|
3247 | * @param pUVM The user mode VM handle.
|
---|
3248 | */
|
---|
3249 | VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
|
---|
3250 | {
|
---|
3251 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3252 | PVM pVM = pUVM->pVM;
|
---|
3253 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3254 | return pVM->hm.s.vmx.fVpid;
|
---|
3255 | }
|
---|
3256 |
|
---|
3257 |
|
---|
3258 | /**
|
---|
3259 | * Checks if we are currently using VT-x unrestricted execution,
|
---|
3260 | * aka UX.
|
---|
3261 | *
|
---|
3262 | * @returns true if UX is being used, otherwise false.
|
---|
3263 | * @param pUVM The user mode VM handle.
|
---|
3264 | */
|
---|
3265 | VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
|
---|
3266 | {
|
---|
3267 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
|
---|
3268 | PVM pVM = pUVM->pVM;
|
---|
3269 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
|
---|
3270 | return pVM->hm.s.vmx.fUnrestrictedGuest;
|
---|
3271 | }
|
---|
3272 |
|
---|
3273 |
|
---|
3274 | /**
|
---|
3275 | * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
|
---|
3276 | *
|
---|
3277 | * @returns true if an internal event is pending, otherwise false.
|
---|
3278 | * @param pVCpu The cross context virtual CPU structure.
|
---|
3279 | */
|
---|
3280 | VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
|
---|
3281 | {
|
---|
3282 | return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
|
---|
3283 | }
|
---|
3284 |
|
---|
3285 |
|
---|
3286 | /**
|
---|
3287 | * Checks if the VMX-preemption timer is being used.
|
---|
3288 | *
|
---|
3289 | * @returns true if the VMX-preemption timer is being used, otherwise false.
|
---|
3290 | * @param pVM The cross context VM structure.
|
---|
3291 | */
|
---|
3292 | VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
|
---|
3293 | {
|
---|
3294 | return HMIsEnabled(pVM)
|
---|
3295 | && pVM->hm.s.vmx.fEnabled
|
---|
3296 | && pVM->hm.s.vmx.fUsePreemptTimer;
|
---|
3297 | }
|
---|
3298 |
|
---|
3299 |
|
---|
3300 | /**
|
---|
3301 | * Restart an I/O instruction that was refused in ring-0
|
---|
3302 | *
|
---|
3303 | * @returns Strict VBox status code. Informational status codes other than the one documented
|
---|
3304 | * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
|
---|
3305 | * @retval VINF_SUCCESS Success.
|
---|
3306 | * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
|
---|
3307 | * status code must be passed on to EM.
|
---|
3308 | * @retval VERR_NOT_FOUND if no pending I/O instruction.
|
---|
3309 | *
|
---|
3310 | * @param pVM The cross context VM structure.
|
---|
3311 | * @param pVCpu The cross context virtual CPU structure.
|
---|
3312 | * @param pCtx Pointer to the guest CPU context.
|
---|
3313 | */
|
---|
3314 | VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
|
---|
3315 | {
|
---|
3316 | /*
|
---|
3317 | * Check if we've got relevant data pending.
|
---|
3318 | */
|
---|
3319 | HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
|
---|
3320 | if (enmType == HMPENDINGIO_INVALID)
|
---|
3321 | return VERR_NOT_FOUND;
|
---|
3322 | pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
|
---|
3323 | if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
|
---|
3324 | return VERR_NOT_FOUND;
|
---|
3325 |
|
---|
3326 | /*
|
---|
3327 | * Execute pending I/O.
|
---|
3328 | */
|
---|
3329 | VBOXSTRICTRC rcStrict;
|
---|
3330 | switch (enmType)
|
---|
3331 | {
|
---|
3332 | case HMPENDINGIO_PORT_READ:
|
---|
3333 | {
|
---|
3334 | uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
|
---|
3335 | uint32_t u32Val = 0;
|
---|
3336 |
|
---|
3337 | rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
|
---|
3338 | pVCpu->hm.s.PendingIO.s.Port.cbSize);
|
---|
3339 | if (IOM_SUCCESS(rcStrict))
|
---|
3340 | {
|
---|
3341 | /* Write back to the EAX register. */
|
---|
3342 | pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
|
---|
3343 | pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
|
---|
3344 | }
|
---|
3345 | break;
|
---|
3346 | }
|
---|
3347 |
|
---|
3348 | default:
|
---|
3349 | AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
|
---|
3350 | }
|
---|
3351 |
|
---|
3352 | if (IOM_SUCCESS(rcStrict))
|
---|
3353 | {
|
---|
3354 | /*
|
---|
3355 | * Check for I/O breakpoints.
|
---|
3356 | */
|
---|
3357 | uint32_t const uDr7 = pCtx->dr[7];
|
---|
3358 | if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
|
---|
3359 | && X86_DR7_ANY_RW_IO(uDr7)
|
---|
3360 | && (pCtx->cr4 & X86_CR4_DE))
|
---|
3361 | || DBGFBpIsHwIoArmed(pVM))
|
---|
3362 | {
|
---|
3363 | VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
|
---|
3364 | pVCpu->hm.s.PendingIO.s.Port.cbSize);
|
---|
3365 | if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
|
---|
3366 | rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
|
---|
3367 | /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
|
---|
3368 | else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
|
---|
3369 | rcStrict = rcStrict2;
|
---|
3370 | }
|
---|
3371 | }
|
---|
3372 | return rcStrict;
|
---|
3373 | }
|
---|
3374 |
|
---|
3375 |
|
---|
3376 | /**
|
---|
3377 | * Check fatal VT-x/AMD-V error and produce some meaningful
|
---|
3378 | * log release message.
|
---|
3379 | *
|
---|
3380 | * @param pVM The cross context VM structure.
|
---|
3381 | * @param iStatusCode VBox status code.
|
---|
3382 | */
|
---|
3383 | VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
|
---|
3384 | {
|
---|
3385 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
3386 | {
|
---|
3387 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
3388 | switch (iStatusCode)
|
---|
3389 | {
|
---|
3390 | /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
|
---|
3391 | * might be getting inaccurate values for non-guru'ing EMTs. */
|
---|
3392 | case VERR_VMX_INVALID_VMCS_FIELD:
|
---|
3393 | break;
|
---|
3394 |
|
---|
3395 | case VERR_VMX_INVALID_VMCS_PTR:
|
---|
3396 | LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
|
---|
3397 | LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
|
---|
3398 | pVCpu->hm.s.vmx.HCPhysVmcs));
|
---|
3399 | LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
|
---|
3400 | LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
|
---|
3401 | LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
|
---|
3402 | break;
|
---|
3403 |
|
---|
3404 | case VERR_VMX_UNABLE_TO_START_VM:
|
---|
3405 | LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
|
---|
3406 | LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
|
---|
3407 | LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
|
---|
3408 |
|
---|
3409 | if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
|
---|
3410 | || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
|
---|
3411 | {
|
---|
3412 | LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
|
---|
3413 | LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
|
---|
3414 | }
|
---|
3415 | else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
|
---|
3416 | {
|
---|
3417 | LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
|
---|
3418 | LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
|
---|
3419 | LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
|
---|
3420 | LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
|
---|
3421 | LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
|
---|
3422 | LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
|
---|
3423 | LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
|
---|
3424 | LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
|
---|
3425 | LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
|
---|
3426 | }
|
---|
3427 | /** @todo Log VM-entry event injection control fields
|
---|
3428 | * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
|
---|
3429 | * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
|
---|
3430 | break;
|
---|
3431 |
|
---|
3432 | /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
|
---|
3433 | case VERR_VMX_INVALID_VMXON_PTR:
|
---|
3434 | case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
|
---|
3435 | case VERR_VMX_INVALID_GUEST_STATE:
|
---|
3436 | case VERR_VMX_UNEXPECTED_EXIT:
|
---|
3437 | case VERR_SVM_UNKNOWN_EXIT:
|
---|
3438 | case VERR_SVM_UNEXPECTED_EXIT:
|
---|
3439 | case VERR_SVM_UNEXPECTED_PATCH_TYPE:
|
---|
3440 | case VERR_SVM_UNEXPECTED_XCPT_EXIT:
|
---|
3441 | case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
|
---|
3442 | break;
|
---|
3443 | }
|
---|
3444 | }
|
---|
3445 |
|
---|
3446 | if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
|
---|
3447 | {
|
---|
3448 | LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
|
---|
3449 | LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
|
---|
3450 | }
|
---|
3451 | else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
|
---|
3452 | LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
|
---|
3453 | }
|
---|
3454 |
|
---|
3455 |
|
---|
3456 | /**
|
---|
3457 | * Execute state save operation.
|
---|
3458 | *
|
---|
3459 | * Save only data that cannot be re-loaded while entering HM ring-0 code. This
|
---|
3460 | * is because we always save the VM state from ring-3 and thus most HM state
|
---|
3461 | * will be re-synced dynamically at runtime and don't need to be part of the VM
|
---|
3462 | * saved state.
|
---|
3463 | *
|
---|
3464 | * @returns VBox status code.
|
---|
3465 | * @param pVM The cross context VM structure.
|
---|
3466 | * @param pSSM SSM operation handle.
|
---|
3467 | */
|
---|
3468 | static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
3469 | {
|
---|
3470 | int rc;
|
---|
3471 |
|
---|
3472 | Log(("hmR3Save:\n"));
|
---|
3473 |
|
---|
3474 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
3475 | {
|
---|
3476 | Assert(!pVM->aCpus[i].hm.s.Event.fPending);
|
---|
3477 | if (pVM->cpum.ro.GuestFeatures.fSvm)
|
---|
3478 | {
|
---|
3479 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
|
---|
3480 | rc = SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
|
---|
3481 | rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
|
---|
3482 | rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
|
---|
3483 | rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
|
---|
3484 | rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
|
---|
3485 | rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
|
---|
3486 | rc |= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
|
---|
3487 | rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
|
---|
3488 | rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
|
---|
3489 | rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
|
---|
3490 | rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
|
---|
3491 | rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
|
---|
3492 | AssertRCReturn(rc, rc);
|
---|
3493 | }
|
---|
3494 | }
|
---|
3495 |
|
---|
3496 | /* Save the guest patch data. */
|
---|
3497 | rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
|
---|
3498 | rc |= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
|
---|
3499 | rc |= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
|
---|
3500 |
|
---|
3501 | /* Store all the guest patch records too. */
|
---|
3502 | rc |= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
|
---|
3503 | AssertRCReturn(rc, rc);
|
---|
3504 |
|
---|
3505 | for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
|
---|
3506 | {
|
---|
3507 | AssertCompileSize(HMTPRINSTR, 4);
|
---|
3508 | PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
|
---|
3509 | rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
|
---|
3510 | rc |= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
|
---|
3511 | rc |= SSMR3PutU32(pSSM, pPatch->cbOp);
|
---|
3512 | rc |= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
|
---|
3513 | rc |= SSMR3PutU32(pSSM, pPatch->cbNewOp);
|
---|
3514 | rc |= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
|
---|
3515 | rc |= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
|
---|
3516 | rc |= SSMR3PutU32(pSSM, pPatch->uDstOperand);
|
---|
3517 | rc |= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
|
---|
3518 | rc |= SSMR3PutU32(pSSM, pPatch->cFaults);
|
---|
3519 | AssertRCReturn(rc, rc);
|
---|
3520 | }
|
---|
3521 |
|
---|
3522 | return VINF_SUCCESS;
|
---|
3523 | }
|
---|
3524 |
|
---|
3525 |
|
---|
3526 | /**
|
---|
3527 | * Execute state load operation.
|
---|
3528 | *
|
---|
3529 | * @returns VBox status code.
|
---|
3530 | * @param pVM The cross context VM structure.
|
---|
3531 | * @param pSSM SSM operation handle.
|
---|
3532 | * @param uVersion Data layout version.
|
---|
3533 | * @param uPass The data pass.
|
---|
3534 | */
|
---|
3535 | static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
3536 | {
|
---|
3537 | int rc;
|
---|
3538 |
|
---|
3539 | LogFlowFunc(("uVersion=%u\n", uVersion));
|
---|
3540 | Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
|
---|
3541 |
|
---|
3542 | /*
|
---|
3543 | * Validate version.
|
---|
3544 | */
|
---|
3545 | if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
|
---|
3546 | && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
|
---|
3547 | && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
|
---|
3548 | && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
|
---|
3549 | {
|
---|
3550 | AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
|
---|
3551 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
3552 | }
|
---|
3553 |
|
---|
3554 | /*
|
---|
3555 | * Load per-VCPU state.
|
---|
3556 | */
|
---|
3557 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
3558 | {
|
---|
3559 | if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
|
---|
3560 | {
|
---|
3561 | /* Load the SVM nested hw.virt state if the VM is configured for it. */
|
---|
3562 | if (pVM->cpum.ro.GuestFeatures.fSvm)
|
---|
3563 | {
|
---|
3564 | PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
|
---|
3565 | rc = SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
|
---|
3566 | rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
|
---|
3567 | rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
|
---|
3568 | rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
|
---|
3569 | rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
|
---|
3570 | rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
|
---|
3571 | rc |= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
|
---|
3572 | rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
|
---|
3573 | rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
|
---|
3574 | rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
|
---|
3575 | rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
|
---|
3576 | rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
|
---|
3577 | AssertRCReturn(rc, rc);
|
---|
3578 | }
|
---|
3579 | }
|
---|
3580 | else
|
---|
3581 | {
|
---|
3582 | /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
|
---|
3583 | rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
|
---|
3584 | rc |= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
|
---|
3585 | rc |= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
|
---|
3586 |
|
---|
3587 | /* VMX fWasInRealMode related data. */
|
---|
3588 | uint32_t uDummy;
|
---|
3589 | rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
|
---|
3590 | rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
|
---|
3591 | rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
|
---|
3592 | AssertRCReturn(rc, rc);
|
---|
3593 | }
|
---|
3594 | }
|
---|
3595 |
|
---|
3596 | /*
|
---|
3597 | * Load TPR patching data.
|
---|
3598 | */
|
---|
3599 | if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
|
---|
3600 | {
|
---|
3601 | rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
|
---|
3602 | rc |= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
|
---|
3603 | rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
|
---|
3604 |
|
---|
3605 | /* Fetch all TPR patch records. */
|
---|
3606 | rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
|
---|
3607 | AssertRCReturn(rc, rc);
|
---|
3608 | for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
|
---|
3609 | {
|
---|
3610 | PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
|
---|
3611 | rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
|
---|
3612 | rc |= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
|
---|
3613 | rc |= SSMR3GetU32(pSSM, &pPatch->cbOp);
|
---|
3614 | rc |= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
|
---|
3615 | rc |= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
|
---|
3616 | rc |= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
|
---|
3617 |
|
---|
3618 | if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
|
---|
3619 | pVM->hm.s.fTPRPatchingActive = true;
|
---|
3620 | Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
|
---|
3621 |
|
---|
3622 | rc |= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
|
---|
3623 | rc |= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
|
---|
3624 | rc |= SSMR3GetU32(pSSM, &pPatch->cFaults);
|
---|
3625 | rc |= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
|
---|
3626 | AssertRCReturn(rc, rc);
|
---|
3627 |
|
---|
3628 | LogFlow(("hmR3Load: patch %d\n", i));
|
---|
3629 | LogFlow(("Key = %x\n", pPatch->Core.Key));
|
---|
3630 | LogFlow(("cbOp = %d\n", pPatch->cbOp));
|
---|
3631 | LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
|
---|
3632 | LogFlow(("type = %d\n", pPatch->enmType));
|
---|
3633 | LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
|
---|
3634 | LogFlow(("dstop = %d\n", pPatch->uDstOperand));
|
---|
3635 | LogFlow(("cFaults = %d\n", pPatch->cFaults));
|
---|
3636 | LogFlow(("target = %x\n", pPatch->pJumpTarget));
|
---|
3637 |
|
---|
3638 | rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
|
---|
3639 | AssertRCReturn(rc, rc);
|
---|
3640 | }
|
---|
3641 | }
|
---|
3642 |
|
---|
3643 | return VINF_SUCCESS;
|
---|
3644 | }
|
---|
3645 |
|
---|
3646 |
|
---|
3647 | /**
|
---|
3648 | * Gets the name of a VT-x exit code.
|
---|
3649 | *
|
---|
3650 | * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
|
---|
3651 | * @param uExit The VT-x exit to name.
|
---|
3652 | */
|
---|
3653 | VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit)
|
---|
3654 | {
|
---|
3655 | if (uExit < RT_ELEMENTS(g_apszVTxExitReasons))
|
---|
3656 | return g_apszVTxExitReasons[uExit];
|
---|
3657 | return NULL;
|
---|
3658 | }
|
---|
3659 |
|
---|
3660 |
|
---|
3661 | /**
|
---|
3662 | * Gets the name of an AMD-V exit code.
|
---|
3663 | *
|
---|
3664 | * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
|
---|
3665 | * @param uExit The AMD-V exit to name.
|
---|
3666 | */
|
---|
3667 | VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit)
|
---|
3668 | {
|
---|
3669 | if (uExit < RT_ELEMENTS(g_apszAmdVExitReasons))
|
---|
3670 | return g_apszAmdVExitReasons[uExit];
|
---|
3671 | return hmSvmGetSpecialExitReasonDesc(uExit);
|
---|
3672 | }
|
---|
3673 |
|
---|
3674 |
|
---|
3675 | /**
|
---|
3676 | * Displays the guest VM-exit history.
|
---|
3677 | *
|
---|
3678 | * @param pVM The cross context VM structure.
|
---|
3679 | * @param pHlp The info helper functions.
|
---|
3680 | * @param pszArgs Arguments, ignored.
|
---|
3681 | */
|
---|
3682 | static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
3683 | {
|
---|
3684 | NOREF(pszArgs);
|
---|
3685 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
3686 | if (!pVCpu)
|
---|
3687 | pVCpu = &pVM->aCpus[0];
|
---|
3688 |
|
---|
3689 | if (HMIsEnabled(pVM))
|
---|
3690 | {
|
---|
3691 | bool const fIsVtx = pVM->hm.s.vmx.fSupported;
|
---|
3692 | const char * const *papszDesc;
|
---|
3693 | unsigned cMaxExitDesc;
|
---|
3694 | if (fIsVtx)
|
---|
3695 | {
|
---|
3696 | cMaxExitDesc = MAX_EXITREASON_VTX;
|
---|
3697 | papszDesc = &g_apszVTxExitReasons[0];
|
---|
3698 | pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
|
---|
3699 | }
|
---|
3700 | else
|
---|
3701 | {
|
---|
3702 | cMaxExitDesc = MAX_EXITREASON_AMDV;
|
---|
3703 | papszDesc = &g_apszAmdVExitReasons[0];
|
---|
3704 | pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
|
---|
3705 | }
|
---|
3706 |
|
---|
3707 | pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
|
---|
3708 | unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
|
---|
3709 | pVCpu->hm.s.idxExitHistoryFree - 1 :
|
---|
3710 | RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
|
---|
3711 | for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
|
---|
3712 | {
|
---|
3713 | uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
|
---|
3714 | const char *pszExit = NULL;
|
---|
3715 | if (uExit <= cMaxExitDesc)
|
---|
3716 | pszExit = papszDesc[uExit];
|
---|
3717 | else if (!fIsVtx)
|
---|
3718 | pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
|
---|
3719 | else
|
---|
3720 | pszExit = NULL;
|
---|
3721 |
|
---|
3722 | pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
|
---|
3723 | idxLast == i ? "<-- Latest exit" : "");
|
---|
3724 | }
|
---|
3725 | pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
|
---|
3726 | }
|
---|
3727 | else
|
---|
3728 | pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
|
---|
3729 | }
|
---|
3730 |
|
---|
3731 |
|
---|
3732 | /**
|
---|
3733 | * Displays the HM pending event.
|
---|
3734 | *
|
---|
3735 | * @param pVM The cross context VM structure.
|
---|
3736 | * @param pHlp The info helper functions.
|
---|
3737 | * @param pszArgs Arguments, ignored.
|
---|
3738 | */
|
---|
3739 | static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
3740 | {
|
---|
3741 | NOREF(pszArgs);
|
---|
3742 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
3743 | if (!pVCpu)
|
---|
3744 | pVCpu = &pVM->aCpus[0];
|
---|
3745 |
|
---|
3746 | if (HMIsEnabled(pVM))
|
---|
3747 | {
|
---|
3748 | pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
|
---|
3749 | if (pVCpu->hm.s.Event.fPending)
|
---|
3750 | {
|
---|
3751 | pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
|
---|
3752 | pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
|
---|
3753 | pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
|
---|
3754 | pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
|
---|
3755 | }
|
---|
3756 | }
|
---|
3757 | else
|
---|
3758 | pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
|
---|
3759 | }
|
---|
3760 |
|
---|
3761 |
|
---|
3762 | /**
|
---|
3763 | * Displays the SVM nested-guest VMCB cache.
|
---|
3764 | *
|
---|
3765 | * @param pVM The cross context VM structure.
|
---|
3766 | * @param pHlp The info helper functions.
|
---|
3767 | * @param pszArgs Arguments, ignored.
|
---|
3768 | */
|
---|
3769 | static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
3770 | {
|
---|
3771 | NOREF(pszArgs);
|
---|
3772 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
3773 | if (!pVCpu)
|
---|
3774 | pVCpu = &pVM->aCpus[0];
|
---|
3775 |
|
---|
3776 | bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
|
---|
3777 | if ( fSvmEnabled
|
---|
3778 | && pVM->cpum.ro.GuestFeatures.fSvm)
|
---|
3779 | {
|
---|
3780 | PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
---|
3781 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
|
---|
3782 | pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
|
---|
3783 | pHlp->pfnPrintf(pHlp, " fHMCachedVmcb = %#RTbool\n", pCtx->hwvirt.svm.fHMCachedVmcb);
|
---|
3784 | pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
|
---|
3785 | pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
|
---|
3786 | pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
|
---|
3787 | pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
|
---|
3788 | pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
|
---|
3789 | pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
|
---|
3790 | pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
|
---|
3791 | pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
|
---|
3792 | pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
|
---|
3793 | pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
|
---|
3794 | pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
|
---|
3795 | pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
|
---|
3796 | }
|
---|
3797 | else
|
---|
3798 | {
|
---|
3799 | if (!fSvmEnabled)
|
---|
3800 | pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
|
---|
3801 | else
|
---|
3802 | pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
|
---|
3803 | }
|
---|
3804 | }
|
---|
3805 |
|
---|