VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 65697

Last change on this file since 65697 was 65447, checked in by vboxsync, 8 years ago

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1/* $Id: HM.cpp 65447 2017-01-26 09:38:50Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#include <VBox/vmm/cpum.h>
41#include <VBox/vmm/stam.h>
42#include <VBox/vmm/mm.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/vmm/pgm.h>
45#include <VBox/vmm/ssm.h>
46#include <VBox/vmm/trpm.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/iom.h>
49#include <VBox/vmm/patm.h>
50#include <VBox/vmm/csam.h>
51#include <VBox/vmm/selm.h>
52#ifdef VBOX_WITH_REM
53# include <VBox/vmm/rem.h>
54#endif
55#include <VBox/vmm/hm_vmx.h>
56#include <VBox/vmm/hm_svm.h>
57#include "HMInternal.h"
58#include <VBox/vmm/vm.h>
59#include <VBox/vmm/uvm.h>
60#include <VBox/err.h>
61#include <VBox/param.h>
62
63#include <iprt/assert.h>
64#include <VBox/log.h>
65#include <iprt/asm.h>
66#include <iprt/asm-amd64-x86.h>
67#include <iprt/env.h>
68#include <iprt/thread.h>
69
70
71/*********************************************************************************************************************************
72* Global Variables *
73*********************************************************************************************************************************/
74#define EXIT_REASON(def, val, str) #def " - " #val " - " str
75#define EXIT_REASON_NIL() NULL
76/** Exit reason descriptions for VT-x, used to describe statistics. */
77static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
78{
79 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
80 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
81 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
82 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
83 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
84 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
85 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
86 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
87 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
88 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
89 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
90 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
91 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
92 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
93 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
94 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
95 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
96 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
97 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
98 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
99 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
100 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
101 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
102 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
103 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
104 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
105 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
106 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
107 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
108 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
109 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
110 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
111 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
112 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
113 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
114 EXIT_REASON_NIL(),
115 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
116 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
117 EXIT_REASON_NIL(),
118 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
119 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
120 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
121 EXIT_REASON_NIL(),
122 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
123 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
124 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
125 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
126 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
127 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
128 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
129 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
130 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
131 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
132 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
133 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
134 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
135 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
136 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
137 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
138 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
139 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
140 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
141 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
142 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
143};
144/** Array index of the last valid VT-x exit reason. */
145#define MAX_EXITREASON_VTX 64
146
147/** A partial list of Exit reason descriptions for AMD-V, used to describe
148 * statistics.
149 *
150 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
151 * this array doesn't contain the entire set of exit reasons, we
152 * handle them via hmSvmGetSpecialExitReasonDesc(). */
153static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
154{
155 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
156 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
157 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
158 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
159 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
160 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
161 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
162 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
163 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
164 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
165 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
166 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
167 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
168 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
169 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
170 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
171 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
172 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
173 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
174 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
187 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
188 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
189 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
190 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
191 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
192 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
193 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
194 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
195 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
196 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
197 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
198 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
199 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
200 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
201 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
202 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
203 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
204 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
205 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
206 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
233 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
234 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
235 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
236 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
237 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
238 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
239 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
240 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
241 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
242 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
243 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
244 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
245 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
246 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
247 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
248 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
249 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
250 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
251 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
252 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
253 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
254 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
255 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
256 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
257 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
258 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
259 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
260 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
261 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
262 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
263 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
264 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
265 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
266 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
267 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
268 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
269 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
270 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
271 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
272 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
273 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
274 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
275 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
276 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
277 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
278 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
279 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
280 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
281 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
282 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
283 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
284 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
285 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
286 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
287 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
288 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
289 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
290 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
291 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
292 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
293 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
294 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
295 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
296 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
297};
298/** Array index of the last valid AMD-V exit reason. */
299#define MAX_EXITREASON_AMDV 141
300
301/** Special exit reasons not covered in the array above. */
302#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
303#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
304#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
305
306/**
307 * Gets the SVM exit reason if it's one of the reasons not present in the @c
308 * g_apszAmdVExitReasons array.
309 *
310 * @returns The exit reason or NULL if unknown.
311 * @param uExit The exit.
312 */
313DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
314{
315 switch (uExit)
316 {
317 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
318 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
319 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
320 }
321 return EXIT_REASON_NIL();
322}
323#undef EXIT_REASON_NIL
324#undef EXIT_REASON
325
326/** @def HMVMX_REPORT_FEATURE
327 * Reports VT-x feature to the release log.
328 *
329 * @param allowed1 Mask of allowed feature bits.
330 * @param disallowed0 Mask of disallowed feature bits.
331 * @param strdesc The description string to report.
332 * @param featflag Mask of the feature to report.
333 */
334#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
335 do { \
336 if ((allowed1) & (featflag)) \
337 { \
338 if ((disallowed0) & (featflag)) \
339 LogRel(("HM: " strdesc " (must be set)\n")); \
340 else \
341 LogRel(("HM: " strdesc "\n")); \
342 } \
343 else \
344 LogRel(("HM: " strdesc " (must be cleared)\n")); \
345 } while (0)
346
347/** @def HMVMX_REPORT_ALLOWED_FEATURE
348 * Reports an allowed VT-x feature to the release log.
349 *
350 * @param allowed1 Mask of allowed feature bits.
351 * @param strdesc The description string to report.
352 * @param featflag Mask of the feature to report.
353 */
354#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
355 do { \
356 if ((allowed1) & (featflag)) \
357 LogRel(("HM: " strdesc "\n")); \
358 else \
359 LogRel(("HM: " strdesc " not supported\n")); \
360 } while (0)
361
362/** @def HMVMX_REPORT_MSR_CAPABILITY
363 * Reports MSR feature capability.
364 *
365 * @param msrcaps Mask of MSR feature bits.
366 * @param strdesc The description string to report.
367 * @param cap Mask of the feature to report.
368 */
369#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
370 do { \
371 if ((msrcaps) & (cap)) \
372 LogRel(("HM: " strdesc "\n")); \
373 } while (0)
374
375
376/*********************************************************************************************************************************
377* Internal Functions *
378*********************************************************************************************************************************/
379static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
380static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
381static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
382static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
383static int hmR3InitCPU(PVM pVM);
384static int hmR3InitFinalizeR0(PVM pVM);
385static int hmR3InitFinalizeR0Intel(PVM pVM);
386static int hmR3InitFinalizeR0Amd(PVM pVM);
387static int hmR3TermCPU(PVM pVM);
388
389
390
391/**
392 * Initializes the HM.
393 *
394 * This reads the config and check whether VT-x or AMD-V hardware is available
395 * if configured to use it. This is one of the very first components to be
396 * initialized after CFGM, so that we can fall back to raw-mode early in the
397 * initialization process.
398 *
399 * Note that a lot of the set up work is done in ring-0 and thus postponed till
400 * the ring-3 and ring-0 callback to HMR3InitCompleted.
401 *
402 * @returns VBox status code.
403 * @param pVM The cross context VM structure.
404 *
405 * @remarks Be careful with what we call here, since most of the VMM components
406 * are uninitialized.
407 */
408VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
409{
410 LogFlow(("HMR3Init\n"));
411
412 /*
413 * Assert alignment and sizes.
414 */
415 AssertCompileMemberAlignment(VM, hm.s, 32);
416 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
417
418 /*
419 * Register the saved state data unit.
420 */
421 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
422 NULL, NULL, NULL,
423 NULL, hmR3Save, NULL,
424 NULL, hmR3Load, NULL);
425 if (RT_FAILURE(rc))
426 return rc;
427
428 /*
429 * Register info handlers.
430 */
431 rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
432 DBGFINFO_FLAGS_ALL_EMTS);
433 AssertRCReturn(rc, rc);
434
435 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
436 DBGFINFO_FLAGS_ALL_EMTS);
437 AssertRCReturn(rc, rc);
438
439 /*
440 * Read configuration.
441 */
442 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
443
444 /*
445 * Validate the HM settings.
446 */
447 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
448 "HMForced"
449 "|EnableNestedPaging"
450 "|EnableUX"
451 "|EnableLargePages"
452 "|EnableVPID"
453 "|TPRPatchingEnabled"
454 "|64bitEnabled"
455 "|VmxPleGap"
456 "|VmxPleWindow"
457 "|SvmPauseFilter"
458 "|SvmPauseFilterThreshold"
459 "|Exclusive"
460 "|MaxResumeLoops"
461 "|UseVmxPreemptTimer",
462 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
463 if (RT_FAILURE(rc))
464 return rc;
465
466 /** @cfgm{/HM/HMForced, bool, false}
467 * Forces hardware virtualization, no falling back on raw-mode. HM must be
468 * enabled, i.e. /HMEnabled must be true. */
469 bool fHMForced;
470#ifdef VBOX_WITH_RAW_MODE
471 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
472 AssertRCReturn(rc, rc);
473 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
474 VERR_INVALID_PARAMETER);
475# if defined(RT_OS_DARWIN)
476 if (pVM->fHMEnabled)
477 fHMForced = true;
478# endif
479 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
480 VERR_INVALID_PARAMETER);
481 if (pVM->cCpus > 1)
482 fHMForced = true;
483#else /* !VBOX_WITH_RAW_MODE */
484 AssertRelease(pVM->fHMEnabled);
485 fHMForced = true;
486#endif /* !VBOX_WITH_RAW_MODE */
487
488 /** @cfgm{/HM/EnableNestedPaging, bool, false}
489 * Enables nested paging (aka extended page tables). */
490 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
491 AssertRCReturn(rc, rc);
492
493 /** @cfgm{/HM/EnableUX, bool, true}
494 * Enables the VT-x unrestricted execution feature. */
495 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
496 AssertRCReturn(rc, rc);
497
498 /** @cfgm{/HM/EnableLargePages, bool, false}
499 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
500 * page table walking and maybe better TLB hit rate in some cases. */
501 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
502 AssertRCReturn(rc, rc);
503
504 /** @cfgm{/HM/EnableVPID, bool, false}
505 * Enables the VT-x VPID feature. */
506 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
507 AssertRCReturn(rc, rc);
508
509 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
510 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
511 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
512 AssertRCReturn(rc, rc);
513
514 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
515 * Enables AMD64 cpu features.
516 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
517 * already have the support. */
518#ifdef VBOX_ENABLE_64_BITS_GUESTS
519 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
520 AssertLogRelRCReturn(rc, rc);
521#else
522 pVM->hm.s.fAllow64BitGuests = false;
523#endif
524
525 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
526 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
527 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
528 * latest PAUSE instruction to be start of a new PAUSE loop.
529 */
530 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
531 AssertRCReturn(rc, rc);
532
533 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
534 * The pause-filter exiting window in TSC ticks. When the number of ticks
535 * between the current PAUSE instruction and first PAUSE of a loop exceeds
536 * VmxPleWindow, a VM-exit is triggered.
537 *
538 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
539 */
540 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
541 AssertRCReturn(rc, rc);
542
543 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
544 * A counter that is decrement each time a PAUSE instruction is executed by the
545 * guest. When the counter is 0, a \#VMEXIT is triggered.
546 */
547 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
548 AssertRCReturn(rc, rc);
549
550 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
551 * The pause filter threshold in ticks. When the elapsed time between two
552 * successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
553 * count is reset to its initial value. However, if PAUSE is executed PauseFilter
554 * times within PauseFilterThreshold ticks, a VM-exit will be triggered.
555 *
556 * Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
557 * pause-filter exiting.
558 */
559 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
560 AssertRCReturn(rc, rc);
561
562 /** @cfgm{/HM/Exclusive, bool}
563 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
564 * global init for each host CPU. If false, we do local init each time we wish
565 * to execute guest code.
566 *
567 * On Windows, default is false due to the higher risk of conflicts with other
568 * hypervisors.
569 *
570 * On Mac OS X, this setting is ignored since the code does not handle local
571 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
572 */
573#if defined(RT_OS_DARWIN)
574 pVM->hm.s.fGlobalInit = true;
575#else
576 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
577# if defined(RT_OS_WINDOWS)
578 false
579# else
580 true
581# endif
582 );
583 AssertLogRelRCReturn(rc, rc);
584#endif
585
586 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
587 * The number of times to resume guest execution before we forcibly return to
588 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
589 * determines the default value. */
590 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
591 AssertLogRelRCReturn(rc, rc);
592
593 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
594 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
595 * available. */
596 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
597 AssertLogRelRCReturn(rc, rc);
598
599 /*
600 * Check if VT-x or AMD-v support according to the users wishes.
601 */
602 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
603 * VERR_SVM_IN_USE. */
604 if (pVM->fHMEnabled)
605 {
606 uint32_t fCaps;
607 rc = SUPR3QueryVTCaps(&fCaps);
608 if (RT_SUCCESS(rc))
609 {
610 if (fCaps & SUPVTCAPS_AMD_V)
611 {
612 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
613 pVM->hm.s.svm.fSupported = true;
614 }
615 else if (fCaps & SUPVTCAPS_VT_X)
616 {
617 rc = SUPR3QueryVTxSupported();
618 if (RT_SUCCESS(rc))
619 {
620 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
621 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
622 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
623 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
624 pVM->hm.s.vmx.fSupported = true;
625 }
626 else
627 {
628#ifdef RT_OS_LINUX
629 const char *pszMinReq = " Linux 2.6.13 or newer required!";
630#else
631 const char *pszMinReq = "";
632#endif
633 if (fHMForced)
634 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
635
636 /* Fall back to raw-mode. */
637 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
638 pVM->fHMEnabled = false;
639 }
640 }
641 else
642 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
643 VERR_INTERNAL_ERROR_5);
644
645 /*
646 * Do we require a little bit or raw-mode for 64-bit guest execution?
647 */
648 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
649 && pVM->fHMEnabled
650 && pVM->hm.s.fAllow64BitGuests;
651
652 /*
653 * Disable nested paging and unrestricted guest execution now if they're
654 * configured so that CPUM can make decisions based on our configuration.
655 */
656 Assert(!pVM->hm.s.fNestedPaging);
657 if (pVM->hm.s.fAllowNestedPaging)
658 {
659 if (fCaps & SUPVTCAPS_NESTED_PAGING)
660 pVM->hm.s.fNestedPaging = true;
661 else
662 pVM->hm.s.fAllowNestedPaging = false;
663 }
664
665 if (fCaps & SUPVTCAPS_VT_X)
666 {
667 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
668 if (pVM->hm.s.vmx.fAllowUnrestricted)
669 {
670 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
671 && pVM->hm.s.fNestedPaging)
672 pVM->hm.s.vmx.fUnrestrictedGuest = true;
673 else
674 pVM->hm.s.vmx.fAllowUnrestricted = false;
675 }
676 }
677 }
678 else
679 {
680 const char *pszMsg;
681 switch (rc)
682 {
683 case VERR_UNSUPPORTED_CPU:
684 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained";
685 break;
686
687 case VERR_VMX_NO_VMX:
688 pszMsg = "VT-x is not available";
689 break;
690
691 case VERR_VMX_MSR_VMX_DISABLED:
692 pszMsg = "VT-x is disabled in the BIOS";
693 break;
694
695 case VERR_VMX_MSR_ALL_VMX_DISABLED:
696 pszMsg = "VT-x is disabled in the BIOS for all CPU modes";
697 break;
698
699 case VERR_VMX_MSR_LOCKING_FAILED:
700 pszMsg = "Failed to enable and lock VT-x features";
701 break;
702
703 case VERR_SVM_NO_SVM:
704 pszMsg = "AMD-V is not available";
705 break;
706
707 case VERR_SVM_DISABLED:
708 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)";
709 break;
710
711 default:
712 pszMsg = NULL;
713 break;
714 }
715 if (fHMForced && pszMsg)
716 return VM_SET_ERROR(pVM, rc, pszMsg);
717 if (!pszMsg)
718 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
719
720 /* Fall back to raw-mode. */
721 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
722 pVM->fHMEnabled = false;
723 }
724 }
725
726 /* It's now OK to use the predicate function. */
727 pVM->fHMEnabledFixed = true;
728 return VINF_SUCCESS;
729}
730
731
732/**
733 * Initializes the per-VCPU HM.
734 *
735 * @returns VBox status code.
736 * @param pVM The cross context VM structure.
737 */
738static int hmR3InitCPU(PVM pVM)
739{
740 LogFlow(("HMR3InitCPU\n"));
741
742 if (!HMIsEnabled(pVM))
743 return VINF_SUCCESS;
744
745 for (VMCPUID i = 0; i < pVM->cCpus; i++)
746 {
747 PVMCPU pVCpu = &pVM->aCpus[i];
748 pVCpu->hm.s.fActive = false;
749 }
750
751#ifdef VBOX_WITH_STATISTICS
752 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
753 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
754 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
755 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
756 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
757#endif
758
759 /*
760 * Statistics.
761 */
762 for (VMCPUID i = 0; i < pVM->cCpus; i++)
763 {
764 PVMCPU pVCpu = &pVM->aCpus[i];
765 int rc;
766
767#ifdef VBOX_WITH_STATISTICS
768 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
769 "Profiling of RTMpPokeCpu",
770 "/PROF/CPU%d/HM/Poke", i);
771 AssertRC(rc);
772 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
773 "Profiling of poke wait",
774 "/PROF/CPU%d/HM/PokeWait", i);
775 AssertRC(rc);
776 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
777 "Profiling of poke wait when RTMpPokeCpu fails",
778 "/PROF/CPU%d/HM/PokeWaitFailed", i);
779 AssertRC(rc);
780 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
781 "Profiling of VMXR0RunGuestCode entry",
782 "/PROF/CPU%d/HM/StatEntry", i);
783 AssertRC(rc);
784 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
785 "Profiling of VMXR0RunGuestCode exit part 1",
786 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
787 AssertRC(rc);
788 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
789 "Profiling of VMXR0RunGuestCode exit part 2",
790 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
791 AssertRC(rc);
792
793 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
794 "I/O",
795 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
796 AssertRC(rc);
797 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
798 "MOV CRx",
799 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
800 AssertRC(rc);
801 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
802 "Exceptions, NMIs",
803 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
804 AssertRC(rc);
805
806 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
807 "Profiling of VMXR0LoadGuestState",
808 "/PROF/CPU%d/HM/StatLoadGuestState", i);
809 AssertRC(rc);
810 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
811 "Profiling of VMLAUNCH/VMRESUME.",
812 "/PROF/CPU%d/HM/InGC", i);
813 AssertRC(rc);
814
815# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
816 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
817 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
818 "/PROF/CPU%d/HM/Switcher3264", i);
819 AssertRC(rc);
820# endif
821
822# ifdef HM_PROFILE_EXIT_DISPATCH
823 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
824 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
825 "/PROF/CPU%d/HM/ExitDispatch", i);
826 AssertRC(rc);
827# endif
828
829#endif
830# define HM_REG_COUNTER(a, b, desc) \
831 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
832 AssertRC(rc);
833
834#ifdef VBOX_WITH_STATISTICS
835 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
836 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
837 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
838 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
839 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
840 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
841 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
842 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
843 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
844 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
845 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
846 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
847 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
848 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
849 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
850 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
851 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
852 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
853 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
854 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
855 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
856 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
857 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
858 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
859 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
860 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
861 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
862 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
863 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
864 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
865 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
866 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
867 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
868 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
869 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
870 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
871 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
872 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
873 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
874 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
875 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
876 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
877 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
878 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
879 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
880 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
881 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
882#endif
883 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
884#ifdef VBOX_WITH_STATISTICS
885 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
886 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
887 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
888 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
889 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
890
891 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
892 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
893 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
894 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
895 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
896 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
897 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
898 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
899 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
900#endif
901 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
902#ifdef VBOX_WITH_STATISTICS
903 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
904
905 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
906 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
907 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
908 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
909
910 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
911 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
912 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
913 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
914 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
915 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
916 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
917 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
918 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
919 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
920 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
921 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
922 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
923 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
924
925 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
926 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
927 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
928
929 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
930 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
931 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
932
933 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
934 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
935
936 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
937 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
938 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
939 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
940 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
941 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
942 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
943 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
944
945#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
946 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
947 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
948#endif
949
950 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
951 {
952 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
953 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
954 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
955 AssertRC(rc);
956 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
957 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
958 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
959 AssertRC(rc);
960 }
961
962#undef HM_REG_COUNTER
963
964 pVCpu->hm.s.paStatExitReason = NULL;
965
966 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
967 (void **)&pVCpu->hm.s.paStatExitReason);
968 AssertRC(rc);
969 if (RT_SUCCESS(rc))
970 {
971 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ?
972 &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
973 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
974 {
975 if (papszDesc[j])
976 {
977 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
978 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
979 AssertRC(rc);
980 }
981 }
982 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
983 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
984 AssertRC(rc);
985 }
986 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
987# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
988 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
989# else
990 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
991# endif
992
993 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
994 AssertRCReturn(rc, rc);
995 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
996# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
997 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
998# else
999 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1000# endif
1001 for (unsigned j = 0; j < 255; j++)
1002 {
1003 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1004 "Injected event.",
1005 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1006 }
1007
1008#endif /* VBOX_WITH_STATISTICS */
1009 }
1010
1011#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1012 /*
1013 * Magic marker for searching in crash dumps.
1014 */
1015 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1016 {
1017 PVMCPU pVCpu = &pVM->aCpus[i];
1018
1019 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1020 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1021 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1022 }
1023#endif
1024
1025 return VINF_SUCCESS;
1026}
1027
1028
1029/**
1030 * Called when a init phase has completed.
1031 *
1032 * @returns VBox status code.
1033 * @param pVM The cross context VM structure.
1034 * @param enmWhat The phase that completed.
1035 */
1036VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1037{
1038 switch (enmWhat)
1039 {
1040 case VMINITCOMPLETED_RING3:
1041 return hmR3InitCPU(pVM);
1042 case VMINITCOMPLETED_RING0:
1043 return hmR3InitFinalizeR0(pVM);
1044 default:
1045 return VINF_SUCCESS;
1046 }
1047}
1048
1049
1050/**
1051 * Turns off normal raw mode features.
1052 *
1053 * @param pVM The cross context VM structure.
1054 */
1055static void hmR3DisableRawMode(PVM pVM)
1056{
1057 /* Reinit the paging mode to force the new shadow mode. */
1058 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1059 {
1060 PVMCPU pVCpu = &pVM->aCpus[i];
1061
1062 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1063 }
1064}
1065
1066
1067/**
1068 * Initialize VT-x or AMD-V.
1069 *
1070 * @returns VBox status code.
1071 * @param pVM The cross context VM structure.
1072 */
1073static int hmR3InitFinalizeR0(PVM pVM)
1074{
1075 int rc;
1076
1077 if (!HMIsEnabled(pVM))
1078 return VINF_SUCCESS;
1079
1080 /*
1081 * Hack to allow users to work around broken BIOSes that incorrectly set
1082 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1083 */
1084 if ( !pVM->hm.s.vmx.fSupported
1085 && !pVM->hm.s.svm.fSupported
1086 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1087 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1088 {
1089 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1090 pVM->hm.s.svm.fSupported = true;
1091 pVM->hm.s.svm.fIgnoreInUseError = true;
1092 pVM->hm.s.lLastError = VINF_SUCCESS;
1093 }
1094
1095 /*
1096 * Report ring-0 init errors.
1097 */
1098 if ( !pVM->hm.s.vmx.fSupported
1099 && !pVM->hm.s.svm.fSupported)
1100 {
1101 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1102 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1103 switch (pVM->hm.s.lLastError)
1104 {
1105 case VERR_VMX_IN_VMX_ROOT_MODE:
1106 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1107 case VERR_VMX_NO_VMX:
1108 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1109 case VERR_VMX_MSR_VMX_DISABLED:
1110 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1111 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1112 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1113 case VERR_VMX_MSR_LOCKING_FAILED:
1114 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1115 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1116 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1117 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1118 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1119
1120 case VERR_SVM_IN_USE:
1121 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1122 case VERR_SVM_NO_SVM:
1123 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1124 case VERR_SVM_DISABLED:
1125 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1126 }
1127 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1128 }
1129
1130 /*
1131 * Enable VT-x or AMD-V on all host CPUs.
1132 */
1133 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1134 if (RT_FAILURE(rc))
1135 {
1136 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1137 HMR3CheckError(pVM, rc);
1138 return rc;
1139 }
1140
1141 /*
1142 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1143 * (Main should have taken care of this already)
1144 */
1145 if (!PDMHasIoApic(pVM))
1146 {
1147 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1148 pVM->hm.s.fTprPatchingAllowed = false;
1149 }
1150
1151 /*
1152 * Do the vendor specific initialization .
1153 * .
1154 * Note! We disable release log buffering here since we're doing relatively .
1155 * lot of logging and doesn't want to hit the disk with each LogRel .
1156 * statement.
1157 */
1158 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1159 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1160 if (pVM->hm.s.vmx.fSupported)
1161 rc = hmR3InitFinalizeR0Intel(pVM);
1162 else
1163 rc = hmR3InitFinalizeR0Amd(pVM);
1164 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1165 RTLogRelSetBuffering(fOldBuffered);
1166 pVM->hm.s.fInitialized = true;
1167
1168 return rc;
1169}
1170
1171
1172/**
1173 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1174 */
1175static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1176{
1177 NOREF(pVM);
1178 NOREF(pvAllocation);
1179 NOREF(GCPhysAllocation);
1180}
1181
1182
1183/**
1184 * Finish VT-x initialization (after ring-0 init).
1185 *
1186 * @returns VBox status code.
1187 * @param pVM The cross context VM structure.
1188 */
1189static int hmR3InitFinalizeR0Intel(PVM pVM)
1190{
1191 int rc;
1192
1193 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1194 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1195
1196 uint64_t val;
1197 uint64_t zap;
1198
1199 LogRel(("HM: Using VT-x implementation 2.0\n"));
1200 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1201 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1202 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1203 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1204 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1205 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1206 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1207 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1208 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1209 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1210 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1211 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1212 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1213 LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1214 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1215
1216 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1217 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1218 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1219 HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1220 HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1221 HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1222 HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1223 HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1224
1225 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1226 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1227 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1228 HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1229 HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1230 HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1231 HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1232 HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1233 HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1234 HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1235 HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1236 HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1237 HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1238 HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1239 HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1240 HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1241 HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1242 HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1243 HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1244 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1245 HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1246 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1247 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1248 HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1249 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1250 {
1251 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1252 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1253 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1254 HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1255 HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1256 HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1257 HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1258 HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1259 HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1260 HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1261 HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1262 HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1263 HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1264 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1265 HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1266 HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1267 HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1268 HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1269 HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1270 HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1271 HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1272 HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1273 HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1274 HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1275 HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1276 }
1277
1278 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1279 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1280 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1281 HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1282 HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1283 HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1284 HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1285 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1286 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1287 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1288
1289 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1290 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1291 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1292 HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1293 HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1294 HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1295 HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1296 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1297 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1298 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1299 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1300 HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1301
1302 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1303 {
1304 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1305 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1306 HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1307 HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1308 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1309 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1310 HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1311 HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1312 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1313 HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1314 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1315 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1316 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1317 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1318 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1319 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1320 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1321 }
1322
1323 val = pVM->hm.s.vmx.Msrs.u64Misc;
1324 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1325 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1326 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1327 else
1328 {
1329 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1330 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1331 }
1332
1333 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1334 LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1335 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1336 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1337 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1338 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1339 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1340 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1341
1342 /* Paranoia */
1343 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1344
1345 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1346 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1347 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1348 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1349
1350 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1351 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1352 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1353
1354 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1355 if (val)
1356 {
1357 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1358 HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1359 }
1360
1361 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1362
1363 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1364 {
1365 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1366 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1367 }
1368
1369 /*
1370 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1371 */
1372 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1373 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1374 VERR_HM_IPE_1);
1375 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1376 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1377 && pVM->hm.s.fNestedPaging),
1378 VERR_HM_IPE_1);
1379
1380 /*
1381 * Enable VPID if configured and supported.
1382 */
1383 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1384 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1385
1386#if 0
1387 /*
1388 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1389 */
1390 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1391 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1392 pVM->hm.s.fVirtApicRegs = true;
1393
1394 /*
1395 * Enable posted-interrupt processing if supported.
1396 */
1397 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1398 * here. */
1399 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1400 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1401 pVM->hm.s.fPostedIntrs = true;
1402#endif
1403
1404 /*
1405 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1406 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1407 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1408 */
1409 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1410 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1411 {
1412 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1413 LogRel(("HM: Disabled RDTSCP\n"));
1414 }
1415
1416 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1417 {
1418 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1419 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1420 if (RT_SUCCESS(rc))
1421 {
1422 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1423 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1424 esp. Figure 20-5.*/
1425 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1426 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1427
1428 /* Bit set to 0 means software interrupts are redirected to the
1429 8086 program interrupt handler rather than switching to
1430 protected-mode handler. */
1431 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1432
1433 /* Allow all port IO, so that port IO instructions do not cause
1434 exceptions and would instead cause a VM-exit (based on VT-x's
1435 IO bitmap which we currently configure to always cause an exit). */
1436 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1437 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1438
1439 /*
1440 * Construct a 1024 element page directory with 4 MB pages for
1441 * the identity mapped page table used in real and protected mode
1442 * without paging with EPT.
1443 */
1444 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1445 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1446 {
1447 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1448 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1449 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1450 | X86_PDE4M_G;
1451 }
1452
1453 /* We convert it here every time as PCI regions could be reconfigured. */
1454 if (PDMVmmDevHeapIsEnabled(pVM))
1455 {
1456 RTGCPHYS GCPhys;
1457 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1458 AssertRCReturn(rc, rc);
1459 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1460
1461 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1462 AssertRCReturn(rc, rc);
1463 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1464 }
1465 }
1466 else
1467 {
1468 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1469 pVM->hm.s.vmx.pRealModeTSS = NULL;
1470 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1471 return VMSetError(pVM, rc, RT_SRC_POS,
1472 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1473 }
1474 }
1475
1476 LogRel((pVM->hm.s.fAllow64BitGuests
1477 ? "HM: Guest support: 32-bit and 64-bit\n"
1478 : "HM: Guest support: 32-bit only\n"));
1479
1480 /*
1481 * Call ring-0 to set up the VM.
1482 */
1483 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1484 if (rc != VINF_SUCCESS)
1485 {
1486 AssertMsgFailed(("%Rrc\n", rc));
1487 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1488 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1489 {
1490 PVMCPU pVCpu = &pVM->aCpus[i];
1491 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1492 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1493 }
1494 HMR3CheckError(pVM, rc);
1495 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1496 }
1497
1498 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1499 LogRel(("HM: Enabled VMX\n"));
1500 pVM->hm.s.vmx.fEnabled = true;
1501
1502 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1503
1504 /*
1505 * Change the CPU features.
1506 */
1507 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1508 if (pVM->hm.s.fAllow64BitGuests)
1509 {
1510 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1511 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1512 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1513 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1514 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1515 }
1516 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1517 (we reuse the host EFER in the switcher). */
1518 /** @todo this needs to be fixed properly!! */
1519 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1520 {
1521 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1522 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1523 else
1524 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1525 }
1526
1527 /*
1528 * Log configuration details.
1529 */
1530 if (pVM->hm.s.fNestedPaging)
1531 {
1532 LogRel(("HM: Enabled nested paging\n"));
1533 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1534 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1535 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1536 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1537 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1538 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1539 else
1540 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1541
1542 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1543 LogRel(("HM: Enabled unrestricted guest execution\n"));
1544
1545#if HC_ARCH_BITS == 64
1546 if (pVM->hm.s.fLargePages)
1547 {
1548 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1549 PGMSetLargePageUsage(pVM, true);
1550 LogRel(("HM: Enabled large page support\n"));
1551 }
1552#endif
1553 }
1554 else
1555 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1556
1557 if (pVM->hm.s.fVirtApicRegs)
1558 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1559
1560 if (pVM->hm.s.fPostedIntrs)
1561 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1562
1563 if (pVM->hm.s.vmx.fVpid)
1564 {
1565 LogRel(("HM: Enabled VPID\n"));
1566 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1567 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1568 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1569 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1570 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1571 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1572 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1573 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1574 else
1575 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1576 }
1577 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1578 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1579
1580 if (pVM->hm.s.vmx.fUsePreemptTimer)
1581 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1582 else
1583 LogRel(("HM: Disabled VMX-preemption timer\n"));
1584
1585 return VINF_SUCCESS;
1586}
1587
1588
1589/**
1590 * Finish AMD-V initialization (after ring-0 init).
1591 *
1592 * @returns VBox status code.
1593 * @param pVM The cross context VM structure.
1594 */
1595static int hmR3InitFinalizeR0Amd(PVM pVM)
1596{
1597 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1598
1599 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1600
1601 uint32_t u32Family;
1602 uint32_t u32Model;
1603 uint32_t u32Stepping;
1604 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1605 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1606 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1607 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1608 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1609 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1610 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1611 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1612 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1613
1614 /*
1615 * Enumerate AMD-V features.
1616 */
1617 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1618 {
1619#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1620 HMSVM_REPORT_FEATURE("NESTED_PAGING", AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1621 HMSVM_REPORT_FEATURE("LBR_VIRT", AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1622 HMSVM_REPORT_FEATURE("SVM_LOCK", AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1623 HMSVM_REPORT_FEATURE("NRIP_SAVE", AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1624 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1625 HMSVM_REPORT_FEATURE("VMCB_CLEAN", AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1626 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1627 HMSVM_REPORT_FEATURE("DECODE_ASSIST", AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1628 HMSVM_REPORT_FEATURE("PAUSE_FILTER", AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1629 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1630 HMSVM_REPORT_FEATURE("AVIC", AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1631#undef HMSVM_REPORT_FEATURE
1632 };
1633
1634 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1635 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1636 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1637 {
1638 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1639 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1640 }
1641 if (fSvmFeatures)
1642 for (unsigned iBit = 0; iBit < 32; iBit++)
1643 if (RT_BIT_32(iBit) & fSvmFeatures)
1644 LogRel(("HM: Reserved bit %u\n", iBit));
1645
1646 /*
1647 * Nested paging is determined in HMR3Init, verify the sanity of that.
1648 */
1649 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1650 || (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1651 VERR_HM_IPE_1);
1652
1653#if 0
1654 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1655 * here. */
1656 if (RTR0IsPostIpiSupport())
1657 pVM->hm.s.fPostedIntrs = true;
1658#endif
1659
1660 /*
1661 * Call ring-0 to set up the VM.
1662 */
1663 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1664 if (rc != VINF_SUCCESS)
1665 {
1666 AssertMsgFailed(("%Rrc\n", rc));
1667 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1668 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1669 }
1670
1671 LogRel(("HM: Enabled SVM\n"));
1672 pVM->hm.s.svm.fEnabled = true;
1673
1674 if (pVM->hm.s.fNestedPaging)
1675 {
1676 LogRel(("HM: Enabled nested paging\n"));
1677
1678 /*
1679 * Enable large pages (2 MB) if applicable.
1680 */
1681#if HC_ARCH_BITS == 64
1682 if (pVM->hm.s.fLargePages)
1683 {
1684 PGMSetLargePageUsage(pVM, true);
1685 LogRel(("HM: Enabled large page support\n"));
1686 }
1687#endif
1688 }
1689
1690 if (pVM->hm.s.fVirtApicRegs)
1691 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1692
1693 if (pVM->hm.s.fPostedIntrs)
1694 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1695
1696 hmR3DisableRawMode(pVM);
1697
1698 /*
1699 * Change the CPU features.
1700 */
1701 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1702 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1703 if (pVM->hm.s.fAllow64BitGuests)
1704 {
1705 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1706 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1707 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1708 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1709 }
1710 /* Turn on NXE if PAE has been enabled. */
1711 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1712 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1713
1714 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1715
1716 LogRel((pVM->hm.s.fAllow64BitGuests
1717 ? "HM: Guest support: 32-bit and 64-bit\n"
1718 : "HM: Guest support: 32-bit only\n"));
1719
1720 return VINF_SUCCESS;
1721}
1722
1723
1724/**
1725 * Applies relocations to data and code managed by this
1726 * component. This function will be called at init and
1727 * whenever the VMM need to relocate it self inside the GC.
1728 *
1729 * @param pVM The cross context VM structure.
1730 */
1731VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1732{
1733 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1734
1735 /* Fetch the current paging mode during the relocate callback during state loading. */
1736 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1737 {
1738 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1739 {
1740 PVMCPU pVCpu = &pVM->aCpus[i];
1741 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1742 }
1743 }
1744#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1745 if (HMIsEnabled(pVM))
1746 {
1747 switch (PGMGetHostMode(pVM))
1748 {
1749 case PGMMODE_32_BIT:
1750 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1751 break;
1752
1753 case PGMMODE_PAE:
1754 case PGMMODE_PAE_NX:
1755 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1756 break;
1757
1758 default:
1759 AssertFailed();
1760 break;
1761 }
1762 }
1763#endif
1764 return;
1765}
1766
1767
1768/**
1769 * Notification callback which is called whenever there is a chance that a CR3
1770 * value might have changed.
1771 *
1772 * This is called by PGM.
1773 *
1774 * @param pVM The cross context VM structure.
1775 * @param pVCpu The cross context virtual CPU structure.
1776 * @param enmShadowMode New shadow paging mode.
1777 * @param enmGuestMode New guest paging mode.
1778 */
1779VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1780{
1781 RT_NOREF_PV(pVM);
1782
1783 /* Ignore page mode changes during state loading. */
1784 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1785 return;
1786
1787 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1788
1789 /*
1790 * If the guest left protected mode VMX execution, we'll have to be
1791 * extra careful if/when the guest switches back to protected mode.
1792 */
1793 if (enmGuestMode == PGMMODE_REAL)
1794 {
1795 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1796 pVCpu->hm.s.vmx.fWasInRealMode = true;
1797 }
1798}
1799
1800
1801/**
1802 * Terminates the HM.
1803 *
1804 * Termination means cleaning up and freeing all resources,
1805 * the VM itself is, at this point, powered off or suspended.
1806 *
1807 * @returns VBox status code.
1808 * @param pVM The cross context VM structure.
1809 */
1810VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1811{
1812 if (pVM->hm.s.vmx.pRealModeTSS)
1813 {
1814 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1815 pVM->hm.s.vmx.pRealModeTSS = 0;
1816 }
1817 hmR3TermCPU(pVM);
1818 return 0;
1819}
1820
1821
1822/**
1823 * Terminates the per-VCPU HM.
1824 *
1825 * @returns VBox status code.
1826 * @param pVM The cross context VM structure.
1827 */
1828static int hmR3TermCPU(PVM pVM)
1829{
1830 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1831 {
1832 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1833
1834#ifdef VBOX_WITH_STATISTICS
1835 if (pVCpu->hm.s.paStatExitReason)
1836 {
1837 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1838 pVCpu->hm.s.paStatExitReason = NULL;
1839 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1840 }
1841 if (pVCpu->hm.s.paStatInjectedIrqs)
1842 {
1843 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1844 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1845 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1846 }
1847#endif
1848
1849#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1850 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1851 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1852 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1853#endif
1854 }
1855 return 0;
1856}
1857
1858
1859/**
1860 * Resets a virtual CPU.
1861 *
1862 * Used by HMR3Reset and CPU hot plugging.
1863 *
1864 * @param pVCpu The cross context virtual CPU structure to reset.
1865 */
1866VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1867{
1868 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1869 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1870 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1871
1872 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1873 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1874 pVCpu->hm.s.fActive = false;
1875 pVCpu->hm.s.Event.fPending = false;
1876 pVCpu->hm.s.vmx.fWasInRealMode = true;
1877 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1878 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
1879
1880 /* Reset the contents of the read cache. */
1881 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1882 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1883 pCache->Read.aFieldVal[j] = 0;
1884
1885#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1886 /* Magic marker for searching in crash dumps. */
1887 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1888 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1889#endif
1890}
1891
1892
1893/**
1894 * The VM is being reset.
1895 *
1896 * For the HM component this means that any GDT/LDT/TSS monitors
1897 * needs to be removed.
1898 *
1899 * @param pVM The cross context VM structure.
1900 */
1901VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1902{
1903 LogFlow(("HMR3Reset:\n"));
1904
1905 if (HMIsEnabled(pVM))
1906 hmR3DisableRawMode(pVM);
1907
1908 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1909 {
1910 PVMCPU pVCpu = &pVM->aCpus[i];
1911
1912 HMR3ResetCpu(pVCpu);
1913 }
1914
1915 /* Clear all patch information. */
1916 pVM->hm.s.pGuestPatchMem = 0;
1917 pVM->hm.s.pFreeGuestPatchMem = 0;
1918 pVM->hm.s.cbGuestPatchMem = 0;
1919 pVM->hm.s.cPatches = 0;
1920 pVM->hm.s.PatchTree = 0;
1921 pVM->hm.s.fTPRPatchingActive = false;
1922 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1923}
1924
1925
1926/**
1927 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1928 *
1929 * @returns VBox strict status code.
1930 * @param pVM The cross context VM structure.
1931 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1932 * @param pvUser Unused.
1933 */
1934static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1935{
1936 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1937
1938 /* Only execute the handler on the VCPU the original patch request was issued. */
1939 if (pVCpu->idCpu != idCpu)
1940 return VINF_SUCCESS;
1941
1942 Log(("hmR3RemovePatches\n"));
1943 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1944 {
1945 uint8_t abInstr[15];
1946 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1947 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1948 int rc;
1949
1950#ifdef LOG_ENABLED
1951 char szOutput[256];
1952
1953 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1954 szOutput, sizeof(szOutput), NULL);
1955 if (RT_SUCCESS(rc))
1956 Log(("Patched instr: %s\n", szOutput));
1957#endif
1958
1959 /* Check if the instruction is still the same. */
1960 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1961 if (rc != VINF_SUCCESS)
1962 {
1963 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1964 continue; /* swapped out or otherwise removed; skip it. */
1965 }
1966
1967 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1968 {
1969 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1970 continue; /* skip it. */
1971 }
1972
1973 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1974 AssertRC(rc);
1975
1976#ifdef LOG_ENABLED
1977 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1978 szOutput, sizeof(szOutput), NULL);
1979 if (RT_SUCCESS(rc))
1980 Log(("Original instr: %s\n", szOutput));
1981#endif
1982 }
1983 pVM->hm.s.cPatches = 0;
1984 pVM->hm.s.PatchTree = 0;
1985 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1986 pVM->hm.s.fTPRPatchingActive = false;
1987 return VINF_SUCCESS;
1988}
1989
1990
1991/**
1992 * Worker for enabling patching in a VT-x/AMD-V guest.
1993 *
1994 * @returns VBox status code.
1995 * @param pVM The cross context VM structure.
1996 * @param idCpu VCPU to execute hmR3RemovePatches on.
1997 * @param pPatchMem Patch memory range.
1998 * @param cbPatchMem Size of the memory range.
1999 */
2000static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2001{
2002 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2003 AssertRC(rc);
2004
2005 pVM->hm.s.pGuestPatchMem = pPatchMem;
2006 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2007 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2008 return VINF_SUCCESS;
2009}
2010
2011
2012/**
2013 * Enable patching in a VT-x/AMD-V guest
2014 *
2015 * @returns VBox status code.
2016 * @param pVM The cross context VM structure.
2017 * @param pPatchMem Patch memory range.
2018 * @param cbPatchMem Size of the memory range.
2019 */
2020VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2021{
2022 VM_ASSERT_EMT(pVM);
2023 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2024 if (pVM->cCpus > 1)
2025 {
2026 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2027 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2028 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2029 AssertRC(rc);
2030 return rc;
2031 }
2032 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2033}
2034
2035
2036/**
2037 * Disable patching in a VT-x/AMD-V guest.
2038 *
2039 * @returns VBox status code.
2040 * @param pVM The cross context VM structure.
2041 * @param pPatchMem Patch memory range.
2042 * @param cbPatchMem Size of the memory range.
2043 */
2044VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2045{
2046 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2047 RT_NOREF2(pPatchMem, cbPatchMem);
2048
2049 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2050 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2051
2052 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2053 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2054 (void *)(uintptr_t)VMMGetCpuId(pVM));
2055 AssertRC(rc);
2056
2057 pVM->hm.s.pGuestPatchMem = 0;
2058 pVM->hm.s.pFreeGuestPatchMem = 0;
2059 pVM->hm.s.cbGuestPatchMem = 0;
2060 pVM->hm.s.fTPRPatchingActive = false;
2061 return VINF_SUCCESS;
2062}
2063
2064
2065/**
2066 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2067 *
2068 * @returns VBox strict status code.
2069 * @param pVM The cross context VM structure.
2070 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2071 * @param pvUser User specified CPU context.
2072 *
2073 */
2074static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2075{
2076 /*
2077 * Only execute the handler on the VCPU the original patch request was
2078 * issued. (The other CPU(s) might not yet have switched to protected
2079 * mode, nor have the correct memory context.)
2080 */
2081 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2082 if (pVCpu->idCpu != idCpu)
2083 return VINF_SUCCESS;
2084
2085 /*
2086 * We're racing other VCPUs here, so don't try patch the instruction twice
2087 * and make sure there is still room for our patch record.
2088 */
2089 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2090 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2091 if (pPatch)
2092 {
2093 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2094 return VINF_SUCCESS;
2095 }
2096 uint32_t const idx = pVM->hm.s.cPatches;
2097 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2098 {
2099 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2100 return VINF_SUCCESS;
2101 }
2102 pPatch = &pVM->hm.s.aPatches[idx];
2103
2104 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2105
2106 /*
2107 * Disassembler the instruction and get cracking.
2108 */
2109 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2110 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2111 uint32_t cbOp;
2112 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2113 AssertRC(rc);
2114 if ( rc == VINF_SUCCESS
2115 && pDis->pCurInstr->uOpcode == OP_MOV
2116 && cbOp >= 3)
2117 {
2118 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2119
2120 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2121 AssertRC(rc);
2122
2123 pPatch->cbOp = cbOp;
2124
2125 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2126 {
2127 /* write. */
2128 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2129 {
2130 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2131 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2132 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2133 }
2134 else
2135 {
2136 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2137 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2138 pPatch->uSrcOperand = pDis->Param2.uValue;
2139 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2140 }
2141 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2142 AssertRC(rc);
2143
2144 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2145 pPatch->cbNewOp = sizeof(s_abVMMCall);
2146 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2147 }
2148 else
2149 {
2150 /*
2151 * TPR Read.
2152 *
2153 * Found:
2154 * mov eax, dword [fffe0080] (5 bytes)
2155 * Check if next instruction is:
2156 * shr eax, 4
2157 */
2158 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2159
2160 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2161 uint8_t const cbOpMmio = cbOp;
2162 uint64_t const uSavedRip = pCtx->rip;
2163
2164 pCtx->rip += cbOp;
2165 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2166 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2167 pCtx->rip = uSavedRip;
2168
2169 if ( rc == VINF_SUCCESS
2170 && pDis->pCurInstr->uOpcode == OP_SHR
2171 && pDis->Param1.fUse == DISUSE_REG_GEN32
2172 && pDis->Param1.Base.idxGenReg == idxMmioReg
2173 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2174 && pDis->Param2.uValue == 4
2175 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2176 {
2177 uint8_t abInstr[15];
2178
2179 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2180 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2181 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2182 AssertRC(rc);
2183
2184 pPatch->cbOp = cbOpMmio + cbOp;
2185
2186 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2187 abInstr[0] = 0xF0;
2188 abInstr[1] = 0x0F;
2189 abInstr[2] = 0x20;
2190 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2191 for (unsigned i = 4; i < pPatch->cbOp; i++)
2192 abInstr[i] = 0x90; /* nop */
2193
2194 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2195 AssertRC(rc);
2196
2197 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2198 pPatch->cbNewOp = pPatch->cbOp;
2199 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2200
2201 Log(("Acceptable read/shr candidate!\n"));
2202 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2203 }
2204 else
2205 {
2206 pPatch->enmType = HMTPRINSTR_READ;
2207 pPatch->uDstOperand = idxMmioReg;
2208
2209 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2210 AssertRC(rc);
2211
2212 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2213 pPatch->cbNewOp = sizeof(s_abVMMCall);
2214 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2215 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2216 }
2217 }
2218
2219 pPatch->Core.Key = pCtx->eip;
2220 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2221 AssertRC(rc);
2222
2223 pVM->hm.s.cPatches++;
2224 return VINF_SUCCESS;
2225 }
2226
2227 /*
2228 * Save invalid patch, so we will not try again.
2229 */
2230 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2231 pPatch->Core.Key = pCtx->eip;
2232 pPatch->enmType = HMTPRINSTR_INVALID;
2233 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2234 AssertRC(rc);
2235 pVM->hm.s.cPatches++;
2236 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2237 return VINF_SUCCESS;
2238}
2239
2240
2241/**
2242 * Callback to patch a TPR instruction (jump to generated code).
2243 *
2244 * @returns VBox strict status code.
2245 * @param pVM The cross context VM structure.
2246 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2247 * @param pvUser User specified CPU context.
2248 *
2249 */
2250static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2251{
2252 /*
2253 * Only execute the handler on the VCPU the original patch request was
2254 * issued. (The other CPU(s) might not yet have switched to protected
2255 * mode, nor have the correct memory context.)
2256 */
2257 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2258 if (pVCpu->idCpu != idCpu)
2259 return VINF_SUCCESS;
2260
2261 /*
2262 * We're racing other VCPUs here, so don't try patch the instruction twice
2263 * and make sure there is still room for our patch record.
2264 */
2265 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2266 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2267 if (pPatch)
2268 {
2269 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2270 return VINF_SUCCESS;
2271 }
2272 uint32_t const idx = pVM->hm.s.cPatches;
2273 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2274 {
2275 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2276 return VINF_SUCCESS;
2277 }
2278 pPatch = &pVM->hm.s.aPatches[idx];
2279
2280 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2281 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2282
2283 /*
2284 * Disassemble the instruction and get cracking.
2285 */
2286 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2287 uint32_t cbOp;
2288 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2289 AssertRC(rc);
2290 if ( rc == VINF_SUCCESS
2291 && pDis->pCurInstr->uOpcode == OP_MOV
2292 && cbOp >= 5)
2293 {
2294 uint8_t aPatch[64];
2295 uint32_t off = 0;
2296
2297 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2298 AssertRC(rc);
2299
2300 pPatch->cbOp = cbOp;
2301 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2302
2303 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2304 {
2305 /*
2306 * TPR write:
2307 *
2308 * push ECX [51]
2309 * push EDX [52]
2310 * push EAX [50]
2311 * xor EDX,EDX [31 D2]
2312 * mov EAX,EAX [89 C0]
2313 * or
2314 * mov EAX,0000000CCh [B8 CC 00 00 00]
2315 * mov ECX,0C0000082h [B9 82 00 00 C0]
2316 * wrmsr [0F 30]
2317 * pop EAX [58]
2318 * pop EDX [5A]
2319 * pop ECX [59]
2320 * jmp return_address [E9 return_address]
2321 *
2322 */
2323 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2324
2325 aPatch[off++] = 0x51; /* push ecx */
2326 aPatch[off++] = 0x52; /* push edx */
2327 if (!fUsesEax)
2328 aPatch[off++] = 0x50; /* push eax */
2329 aPatch[off++] = 0x31; /* xor edx, edx */
2330 aPatch[off++] = 0xD2;
2331 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2332 {
2333 if (!fUsesEax)
2334 {
2335 aPatch[off++] = 0x89; /* mov eax, src_reg */
2336 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2337 }
2338 }
2339 else
2340 {
2341 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2342 aPatch[off++] = 0xB8; /* mov eax, immediate */
2343 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2344 off += sizeof(uint32_t);
2345 }
2346 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2347 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2348 off += sizeof(uint32_t);
2349
2350 aPatch[off++] = 0x0F; /* wrmsr */
2351 aPatch[off++] = 0x30;
2352 if (!fUsesEax)
2353 aPatch[off++] = 0x58; /* pop eax */
2354 aPatch[off++] = 0x5A; /* pop edx */
2355 aPatch[off++] = 0x59; /* pop ecx */
2356 }
2357 else
2358 {
2359 /*
2360 * TPR read:
2361 *
2362 * push ECX [51]
2363 * push EDX [52]
2364 * push EAX [50]
2365 * mov ECX,0C0000082h [B9 82 00 00 C0]
2366 * rdmsr [0F 32]
2367 * mov EAX,EAX [89 C0]
2368 * pop EAX [58]
2369 * pop EDX [5A]
2370 * pop ECX [59]
2371 * jmp return_address [E9 return_address]
2372 *
2373 */
2374 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2375
2376 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2377 aPatch[off++] = 0x51; /* push ecx */
2378 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2379 aPatch[off++] = 0x52; /* push edx */
2380 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2381 aPatch[off++] = 0x50; /* push eax */
2382
2383 aPatch[off++] = 0x31; /* xor edx, edx */
2384 aPatch[off++] = 0xD2;
2385
2386 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2387 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2388 off += sizeof(uint32_t);
2389
2390 aPatch[off++] = 0x0F; /* rdmsr */
2391 aPatch[off++] = 0x32;
2392
2393 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2394 {
2395 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2396 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2397 }
2398
2399 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2400 aPatch[off++] = 0x58; /* pop eax */
2401 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2402 aPatch[off++] = 0x5A; /* pop edx */
2403 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2404 aPatch[off++] = 0x59; /* pop ecx */
2405 }
2406 aPatch[off++] = 0xE9; /* jmp return_address */
2407 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2408 off += sizeof(RTRCUINTPTR);
2409
2410 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2411 {
2412 /* Write new code to the patch buffer. */
2413 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2414 AssertRC(rc);
2415
2416#ifdef LOG_ENABLED
2417 uint32_t cbCurInstr;
2418 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2419 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2420 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2421 {
2422 char szOutput[256];
2423 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2424 szOutput, sizeof(szOutput), &cbCurInstr);
2425 if (RT_SUCCESS(rc))
2426 Log(("Patch instr %s\n", szOutput));
2427 else
2428 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2429 }
2430#endif
2431
2432 pPatch->aNewOpcode[0] = 0xE9;
2433 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2434
2435 /* Overwrite the TPR instruction with a jump. */
2436 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2437 AssertRC(rc);
2438
2439 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2440
2441 pVM->hm.s.pFreeGuestPatchMem += off;
2442 pPatch->cbNewOp = 5;
2443
2444 pPatch->Core.Key = pCtx->eip;
2445 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2446 AssertRC(rc);
2447
2448 pVM->hm.s.cPatches++;
2449 pVM->hm.s.fTPRPatchingActive = true;
2450 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2451 return VINF_SUCCESS;
2452 }
2453
2454 Log(("Ran out of space in our patch buffer!\n"));
2455 }
2456 else
2457 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2458
2459
2460 /*
2461 * Save invalid patch, so we will not try again.
2462 */
2463 pPatch = &pVM->hm.s.aPatches[idx];
2464 pPatch->Core.Key = pCtx->eip;
2465 pPatch->enmType = HMTPRINSTR_INVALID;
2466 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2467 AssertRC(rc);
2468 pVM->hm.s.cPatches++;
2469 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2470 return VINF_SUCCESS;
2471}
2472
2473
2474/**
2475 * Attempt to patch TPR mmio instructions.
2476 *
2477 * @returns VBox status code.
2478 * @param pVM The cross context VM structure.
2479 * @param pVCpu The cross context virtual CPU structure.
2480 * @param pCtx Pointer to the guest CPU context.
2481 */
2482VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2483{
2484 NOREF(pCtx);
2485 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2486 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2487 (void *)(uintptr_t)pVCpu->idCpu);
2488 AssertRC(rc);
2489 return rc;
2490}
2491
2492
2493/**
2494 * Checks if a code selector (CS) is suitable for execution
2495 * within VMX when unrestricted execution isn't available.
2496 *
2497 * @returns true if selector is suitable for VMX, otherwise
2498 * false.
2499 * @param pSel Pointer to the selector to check (CS).
2500 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2501 */
2502static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2503{
2504 /*
2505 * Segment must be an accessed code segment, it must be present and it must
2506 * be usable.
2507 * Note! These are all standard requirements and if CS holds anything else
2508 * we've got buggy code somewhere!
2509 */
2510 AssertCompile(X86DESCATTR_TYPE == 0xf);
2511 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2512 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2513 ("%#x\n", pSel->Attr.u),
2514 false);
2515
2516 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2517 must equal SS.DPL for non-confroming segments.
2518 Note! This is also a hard requirement like above. */
2519 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2520 ? pSel->Attr.n.u2Dpl <= uStackDpl
2521 : pSel->Attr.n.u2Dpl == uStackDpl,
2522 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2523 false);
2524
2525 /*
2526 * The following two requirements are VT-x specific:
2527 * - G bit must be set if any high limit bits are set.
2528 * - G bit must be clear if any low limit bits are clear.
2529 */
2530 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2531 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2532 return true;
2533 return false;
2534}
2535
2536
2537/**
2538 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2539 * execution within VMX when unrestricted execution isn't
2540 * available.
2541 *
2542 * @returns true if selector is suitable for VMX, otherwise
2543 * false.
2544 * @param pSel Pointer to the selector to check
2545 * (DS/ES/FS/GS).
2546 */
2547static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2548{
2549 /*
2550 * Unusable segments are OK. These days they should be marked as such, as
2551 * but as an alternative we for old saved states and AMD<->VT-x migration
2552 * we also treat segments with all the attributes cleared as unusable.
2553 */
2554 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2555 return true;
2556
2557 /** @todo tighten these checks. Will require CPUM load adjusting. */
2558
2559 /* Segment must be accessed. */
2560 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2561 {
2562 /* Code segments must also be readable. */
2563 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2564 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2565 {
2566 /* The S bit must be set. */
2567 if (pSel->Attr.n.u1DescType)
2568 {
2569 /* Except for conforming segments, DPL >= RPL. */
2570 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2571 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2572 {
2573 /* Segment must be present. */
2574 if (pSel->Attr.n.u1Present)
2575 {
2576 /*
2577 * The following two requirements are VT-x specific:
2578 * - G bit must be set if any high limit bits are set.
2579 * - G bit must be clear if any low limit bits are clear.
2580 */
2581 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2582 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2583 return true;
2584 }
2585 }
2586 }
2587 }
2588 }
2589
2590 return false;
2591}
2592
2593
2594/**
2595 * Checks if the stack selector (SS) is suitable for execution
2596 * within VMX when unrestricted execution isn't available.
2597 *
2598 * @returns true if selector is suitable for VMX, otherwise
2599 * false.
2600 * @param pSel Pointer to the selector to check (SS).
2601 */
2602static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2603{
2604 /*
2605 * Unusable segments are OK. These days they should be marked as such, as
2606 * but as an alternative we for old saved states and AMD<->VT-x migration
2607 * we also treat segments with all the attributes cleared as unusable.
2608 */
2609 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2610 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2611 return true;
2612
2613 /*
2614 * Segment must be an accessed writable segment, it must be present.
2615 * Note! These are all standard requirements and if SS holds anything else
2616 * we've got buggy code somewhere!
2617 */
2618 AssertCompile(X86DESCATTR_TYPE == 0xf);
2619 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2620 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2621 ("%#x\n", pSel->Attr.u),
2622 false);
2623
2624 /* DPL must equal RPL.
2625 Note! This is also a hard requirement like above. */
2626 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2627 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2628 false);
2629
2630 /*
2631 * The following two requirements are VT-x specific:
2632 * - G bit must be set if any high limit bits are set.
2633 * - G bit must be clear if any low limit bits are clear.
2634 */
2635 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2636 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2637 return true;
2638 return false;
2639}
2640
2641
2642/**
2643 * Force execution of the current IO code in the recompiler.
2644 *
2645 * @returns VBox status code.
2646 * @param pVM The cross context VM structure.
2647 * @param pCtx Partial VM execution context.
2648 */
2649VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2650{
2651 PVMCPU pVCpu = VMMGetCpu(pVM);
2652
2653 Assert(HMIsEnabled(pVM));
2654 Log(("HMR3EmulateIoBlock\n"));
2655
2656 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2657 if (HMCanEmulateIoBlockEx(pCtx))
2658 {
2659 Log(("HMR3EmulateIoBlock -> enabled\n"));
2660 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2661 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2662 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2663 return VINF_EM_RESCHEDULE_REM;
2664 }
2665 return VINF_SUCCESS;
2666}
2667
2668
2669/**
2670 * Checks if we can currently use hardware accelerated raw mode.
2671 *
2672 * @returns true if we can currently use hardware acceleration, otherwise false.
2673 * @param pVM The cross context VM structure.
2674 * @param pCtx Partial VM execution context.
2675 */
2676VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2677{
2678 PVMCPU pVCpu = VMMGetCpu(pVM);
2679
2680 Assert(HMIsEnabled(pVM));
2681
2682 /* If we're still executing the IO code, then return false. */
2683 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2684 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2685 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2686 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2687 return false;
2688
2689 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2690
2691 /* AMD-V supports real & protected mode with or without paging. */
2692 if (pVM->hm.s.svm.fEnabled)
2693 {
2694 pVCpu->hm.s.fActive = true;
2695 return true;
2696 }
2697
2698 pVCpu->hm.s.fActive = false;
2699
2700 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2701 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2702 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2703
2704 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2705 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2706 {
2707 /*
2708 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2709 * guest execution feature is missing (VT-x only).
2710 */
2711 if (fSupportsRealMode)
2712 {
2713 if (CPUMIsGuestInRealModeEx(pCtx))
2714 {
2715 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2716 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2717 * If this is not true, we cannot execute real mode as V86 and have to fall
2718 * back to emulation.
2719 */
2720 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2721 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2722 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2723 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2724 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2725 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2726 {
2727 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2728 return false;
2729 }
2730 if ( (pCtx->cs.u32Limit != 0xffff)
2731 || (pCtx->ds.u32Limit != 0xffff)
2732 || (pCtx->es.u32Limit != 0xffff)
2733 || (pCtx->ss.u32Limit != 0xffff)
2734 || (pCtx->fs.u32Limit != 0xffff)
2735 || (pCtx->gs.u32Limit != 0xffff))
2736 {
2737 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2738 return false;
2739 }
2740 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2741 }
2742 else
2743 {
2744 /* Verify the requirements for executing code in protected
2745 mode. VT-x can't handle the CPU state right after a switch
2746 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2747 if (pVCpu->hm.s.vmx.fWasInRealMode)
2748 {
2749 /** @todo If guest is in V86 mode, these checks should be different! */
2750 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2751 {
2752 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2753 return false;
2754 }
2755 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2756 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2757 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2758 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2759 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2760 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2761 {
2762 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2763 return false;
2764 }
2765 }
2766 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2767 if (pCtx->gdtr.cbGdt)
2768 {
2769 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2770 {
2771 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2772 return false;
2773 }
2774 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2775 {
2776 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2777 return false;
2778 }
2779 }
2780 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2781 }
2782 }
2783 else
2784 {
2785 if ( !CPUMIsGuestInLongModeEx(pCtx)
2786 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2787 {
2788 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2789 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2790 return false;
2791
2792 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2793 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2794 return false;
2795
2796 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2797 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2798 * hidden registers (possible recompiler bug; see load_seg_vm) */
2799 if (pCtx->cs.Attr.n.u1Present == 0)
2800 return false;
2801 if (pCtx->ss.Attr.n.u1Present == 0)
2802 return false;
2803
2804 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2805 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2806 /** @todo This check is actually wrong, it doesn't take the direction of the
2807 * stack segment into account. But, it does the job for now. */
2808 if (pCtx->rsp >= pCtx->ss.u32Limit)
2809 return false;
2810 }
2811 }
2812 }
2813
2814 if (pVM->hm.s.vmx.fEnabled)
2815 {
2816 uint32_t mask;
2817
2818 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2819 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2820 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2821 mask &= ~X86_CR0_NE;
2822
2823 if (fSupportsRealMode)
2824 {
2825 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2826 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2827 }
2828 else
2829 {
2830 /* We support protected mode without paging using identity mapping. */
2831 mask &= ~X86_CR0_PG;
2832 }
2833 if ((pCtx->cr0 & mask) != mask)
2834 return false;
2835
2836 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2837 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2838 if ((pCtx->cr0 & mask) != 0)
2839 return false;
2840
2841 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2842 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2843 mask &= ~X86_CR4_VMXE;
2844 if ((pCtx->cr4 & mask) != mask)
2845 return false;
2846
2847 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2848 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2849 if ((pCtx->cr4 & mask) != 0)
2850 return false;
2851
2852 pVCpu->hm.s.fActive = true;
2853 return true;
2854 }
2855
2856 return false;
2857}
2858
2859
2860/**
2861 * Checks if we need to reschedule due to VMM device heap changes.
2862 *
2863 * @returns true if a reschedule is required, otherwise false.
2864 * @param pVM The cross context VM structure.
2865 * @param pCtx VM execution context.
2866 */
2867VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2868{
2869 /*
2870 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2871 * when the unrestricted guest execution feature is missing (VT-x only).
2872 */
2873 if ( pVM->hm.s.vmx.fEnabled
2874 && !pVM->hm.s.vmx.fUnrestrictedGuest
2875 && CPUMIsGuestInRealModeEx(pCtx)
2876 && !PDMVmmDevHeapIsEnabled(pVM))
2877 {
2878 return true;
2879 }
2880
2881 return false;
2882}
2883
2884
2885/**
2886 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2887 * event settings changes.
2888 *
2889 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2890 * function is just updating the VM globals.
2891 *
2892 * @param pVM The VM cross context VM structure.
2893 * @thread EMT(0)
2894 */
2895VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2896{
2897 /* Interrupts. */
2898 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2899 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2900
2901 /* CPU Exceptions. */
2902 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2903 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2904 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2905 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2906
2907 /* Common VM exits. */
2908 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2909 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2910 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2911 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2912
2913 /* Vendor specific VM exits. */
2914 if (HMR3IsVmxEnabled(pVM->pUVM))
2915 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2916 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2917 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2918 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2919 else
2920 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2921 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2922 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2923 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2924
2925 /* Done. */
2926 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2927}
2928
2929
2930/**
2931 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2932 *
2933 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2934 * per CPU settings.
2935 *
2936 * @param pVM The VM cross context VM structure.
2937 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2938 */
2939VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2940{
2941 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2942}
2943
2944
2945/**
2946 * Notification from EM about a rescheduling into hardware assisted execution
2947 * mode.
2948 *
2949 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2950 */
2951VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2952{
2953 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2954}
2955
2956
2957/**
2958 * Notification from EM about returning from instruction emulation (REM / EM).
2959 *
2960 * @param pVCpu The cross context virtual CPU structure.
2961 */
2962VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2963{
2964 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2965}
2966
2967
2968/**
2969 * Checks if we are currently using hardware acceleration.
2970 *
2971 * @returns true if hardware acceleration is being used, otherwise false.
2972 * @param pVCpu The cross context virtual CPU structure.
2973 */
2974VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2975{
2976 return pVCpu->hm.s.fActive;
2977}
2978
2979
2980/**
2981 * External interface for querying whether hardware acceleration is enabled.
2982 *
2983 * @returns true if VT-x or AMD-V is being used, otherwise false.
2984 * @param pUVM The user mode VM handle.
2985 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2986 */
2987VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2988{
2989 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2990 PVM pVM = pUVM->pVM;
2991 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2992 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2993}
2994
2995
2996/**
2997 * External interface for querying whether VT-x is being used.
2998 *
2999 * @returns true if VT-x is being used, otherwise false.
3000 * @param pUVM The user mode VM handle.
3001 * @sa HMR3IsSvmEnabled, HMIsEnabled
3002 */
3003VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3004{
3005 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3006 PVM pVM = pUVM->pVM;
3007 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3008 return pVM->hm.s.vmx.fEnabled
3009 && pVM->hm.s.vmx.fSupported
3010 && pVM->fHMEnabled;
3011}
3012
3013
3014/**
3015 * External interface for querying whether AMD-V is being used.
3016 *
3017 * @returns true if VT-x is being used, otherwise false.
3018 * @param pUVM The user mode VM handle.
3019 * @sa HMR3IsVmxEnabled, HMIsEnabled
3020 */
3021VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3022{
3023 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3024 PVM pVM = pUVM->pVM;
3025 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3026 return pVM->hm.s.svm.fEnabled
3027 && pVM->hm.s.svm.fSupported
3028 && pVM->fHMEnabled;
3029}
3030
3031
3032/**
3033 * Checks if we are currently using nested paging.
3034 *
3035 * @returns true if nested paging is being used, otherwise false.
3036 * @param pUVM The user mode VM handle.
3037 */
3038VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3039{
3040 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3041 PVM pVM = pUVM->pVM;
3042 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3043 return pVM->hm.s.fNestedPaging;
3044}
3045
3046
3047/**
3048 * Checks if virtualized APIC registers is enabled.
3049 *
3050 * When enabled this feature allows the hardware to access most of the
3051 * APIC registers in the virtual-APIC page without causing VM-exits. See
3052 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3053 *
3054 * @returns true if virtualized APIC registers is enabled, otherwise
3055 * false.
3056 * @param pUVM The user mode VM handle.
3057 */
3058VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3059{
3060 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3061 PVM pVM = pUVM->pVM;
3062 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3063 return pVM->hm.s.fVirtApicRegs;
3064}
3065
3066
3067/**
3068 * Checks if APIC posted-interrupt processing is enabled.
3069 *
3070 * This returns whether we can deliver interrupts to the guest without
3071 * leaving guest-context by updating APIC state from host-context.
3072 *
3073 * @returns true if APIC posted-interrupt processing is enabled,
3074 * otherwise false.
3075 * @param pUVM The user mode VM handle.
3076 */
3077VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3078{
3079 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3080 PVM pVM = pUVM->pVM;
3081 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3082 return pVM->hm.s.fPostedIntrs;
3083}
3084
3085
3086/**
3087 * Checks if we are currently using VPID in VT-x mode.
3088 *
3089 * @returns true if VPID is being used, otherwise false.
3090 * @param pUVM The user mode VM handle.
3091 */
3092VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3093{
3094 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3095 PVM pVM = pUVM->pVM;
3096 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3097 return pVM->hm.s.vmx.fVpid;
3098}
3099
3100
3101/**
3102 * Checks if we are currently using VT-x unrestricted execution,
3103 * aka UX.
3104 *
3105 * @returns true if UX is being used, otherwise false.
3106 * @param pUVM The user mode VM handle.
3107 */
3108VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3109{
3110 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3111 PVM pVM = pUVM->pVM;
3112 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3113 return pVM->hm.s.vmx.fUnrestrictedGuest;
3114}
3115
3116
3117/**
3118 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3119 *
3120 * @returns true if an internal event is pending, otherwise false.
3121 * @param pVCpu The cross context virtual CPU structure.
3122 */
3123VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3124{
3125 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3126}
3127
3128
3129/**
3130 * Checks if the VMX-preemption timer is being used.
3131 *
3132 * @returns true if the VMX-preemption timer is being used, otherwise false.
3133 * @param pVM The cross context VM structure.
3134 */
3135VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3136{
3137 return HMIsEnabled(pVM)
3138 && pVM->hm.s.vmx.fEnabled
3139 && pVM->hm.s.vmx.fUsePreemptTimer;
3140}
3141
3142
3143/**
3144 * Restart an I/O instruction that was refused in ring-0
3145 *
3146 * @returns Strict VBox status code. Informational status codes other than the one documented
3147 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3148 * @retval VINF_SUCCESS Success.
3149 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3150 * status code must be passed on to EM.
3151 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3152 *
3153 * @param pVM The cross context VM structure.
3154 * @param pVCpu The cross context virtual CPU structure.
3155 * @param pCtx Pointer to the guest CPU context.
3156 */
3157VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3158{
3159 /*
3160 * Check if we've got relevant data pending.
3161 */
3162 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3163 if (enmType == HMPENDINGIO_INVALID)
3164 return VERR_NOT_FOUND;
3165 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3166 if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3167 return VERR_NOT_FOUND;
3168
3169 /*
3170 * Execute pending I/O.
3171 */
3172 VBOXSTRICTRC rcStrict;
3173 switch (enmType)
3174 {
3175 case HMPENDINGIO_PORT_READ:
3176 {
3177 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3178 uint32_t u32Val = 0;
3179
3180 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3181 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3182 if (IOM_SUCCESS(rcStrict))
3183 {
3184 /* Write back to the EAX register. */
3185 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3186 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3187 }
3188 break;
3189 }
3190
3191 default:
3192 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3193 }
3194
3195 if (IOM_SUCCESS(rcStrict))
3196 {
3197 /*
3198 * Check for I/O breakpoints.
3199 */
3200 uint32_t const uDr7 = pCtx->dr[7];
3201 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3202 && X86_DR7_ANY_RW_IO(uDr7)
3203 && (pCtx->cr4 & X86_CR4_DE))
3204 || DBGFBpIsHwIoArmed(pVM))
3205 {
3206 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3207 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3208 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3209 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3210 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3211 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3212 rcStrict = rcStrict2;
3213 }
3214 }
3215 return rcStrict;
3216}
3217
3218
3219/**
3220 * Check fatal VT-x/AMD-V error and produce some meaningful
3221 * log release message.
3222 *
3223 * @param pVM The cross context VM structure.
3224 * @param iStatusCode VBox status code.
3225 */
3226VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3227{
3228 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3229 {
3230 PVMCPU pVCpu = &pVM->aCpus[i];
3231 switch (iStatusCode)
3232 {
3233 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3234 * might be getting inaccurate values for non-guru'ing EMTs. */
3235 case VERR_VMX_INVALID_VMCS_FIELD:
3236 break;
3237
3238 case VERR_VMX_INVALID_VMCS_PTR:
3239 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3240 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3241 pVCpu->hm.s.vmx.HCPhysVmcs));
3242 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3243 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3244 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3245 break;
3246
3247 case VERR_VMX_UNABLE_TO_START_VM:
3248 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3249 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3250 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3251
3252 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3253 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3254 {
3255 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3256 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3257 }
3258 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3259 {
3260 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3261 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3262 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3263 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3264 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3265 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3266 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3267 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3268 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3269 }
3270 /** @todo Log VM-entry event injection control fields
3271 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3272 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3273 break;
3274
3275 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3276 case VERR_VMX_INVALID_VMXON_PTR:
3277 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3278 case VERR_VMX_INVALID_GUEST_STATE:
3279 case VERR_VMX_UNEXPECTED_EXIT:
3280 case VERR_SVM_UNKNOWN_EXIT:
3281 case VERR_SVM_UNEXPECTED_EXIT:
3282 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3283 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3284 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3285 break;
3286 }
3287 }
3288
3289 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3290 {
3291 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3292 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3293 }
3294 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3295 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3296}
3297
3298
3299/**
3300 * Execute state save operation.
3301 *
3302 * @returns VBox status code.
3303 * @param pVM The cross context VM structure.
3304 * @param pSSM SSM operation handle.
3305 */
3306static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3307{
3308 int rc;
3309
3310 Log(("hmR3Save:\n"));
3311
3312 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3313 {
3314 /*
3315 * Save the basic bits - fortunately all the other things can be resynced on load.
3316 */
3317 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3318 AssertRCReturn(rc, rc);
3319 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3320 AssertRCReturn(rc, rc);
3321 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3322 AssertRCReturn(rc, rc);
3323 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3324
3325 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3326 * perhaps not even that (the initial value of @c true is safe. */
3327 uint32_t u32Dummy = PGMMODE_REAL;
3328 rc = SSMR3PutU32(pSSM, u32Dummy);
3329 AssertRCReturn(rc, rc);
3330 rc = SSMR3PutU32(pSSM, u32Dummy);
3331 AssertRCReturn(rc, rc);
3332 rc = SSMR3PutU32(pSSM, u32Dummy);
3333 AssertRCReturn(rc, rc);
3334 }
3335
3336#ifdef VBOX_HM_WITH_GUEST_PATCHING
3337 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3338 AssertRCReturn(rc, rc);
3339 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3340 AssertRCReturn(rc, rc);
3341 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3342 AssertRCReturn(rc, rc);
3343
3344 /* Store all the guest patch records too. */
3345 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3346 AssertRCReturn(rc, rc);
3347
3348 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3349 {
3350 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3351
3352 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3353 AssertRCReturn(rc, rc);
3354
3355 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3356 AssertRCReturn(rc, rc);
3357
3358 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3359 AssertRCReturn(rc, rc);
3360
3361 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3362 AssertRCReturn(rc, rc);
3363
3364 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3365 AssertRCReturn(rc, rc);
3366
3367 AssertCompileSize(HMTPRINSTR, 4);
3368 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3369 AssertRCReturn(rc, rc);
3370
3371 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3372 AssertRCReturn(rc, rc);
3373
3374 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3375 AssertRCReturn(rc, rc);
3376
3377 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3378 AssertRCReturn(rc, rc);
3379
3380 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3381 AssertRCReturn(rc, rc);
3382 }
3383#endif
3384 return VINF_SUCCESS;
3385}
3386
3387
3388/**
3389 * Execute state load operation.
3390 *
3391 * @returns VBox status code.
3392 * @param pVM The cross context VM structure.
3393 * @param pSSM SSM operation handle.
3394 * @param uVersion Data layout version.
3395 * @param uPass The data pass.
3396 */
3397static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3398{
3399 int rc;
3400
3401 Log(("hmR3Load:\n"));
3402 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3403
3404 /*
3405 * Validate version.
3406 */
3407 if ( uVersion != HM_SAVED_STATE_VERSION
3408 && uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3409 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3410 {
3411 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3412 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3413 }
3414 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3415 {
3416 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3417 AssertRCReturn(rc, rc);
3418 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3419 AssertRCReturn(rc, rc);
3420 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3421 AssertRCReturn(rc, rc);
3422
3423 if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3424 {
3425 uint32_t val;
3426 /** @todo See note in hmR3Save(). */
3427 rc = SSMR3GetU32(pSSM, &val);
3428 AssertRCReturn(rc, rc);
3429 rc = SSMR3GetU32(pSSM, &val);
3430 AssertRCReturn(rc, rc);
3431 rc = SSMR3GetU32(pSSM, &val);
3432 AssertRCReturn(rc, rc);
3433 }
3434 }
3435#ifdef VBOX_HM_WITH_GUEST_PATCHING
3436 if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3437 {
3438 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3439 AssertRCReturn(rc, rc);
3440 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3441 AssertRCReturn(rc, rc);
3442 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3443 AssertRCReturn(rc, rc);
3444
3445 /* Fetch all TPR patch records. */
3446 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3447 AssertRCReturn(rc, rc);
3448
3449 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3450 {
3451 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3452
3453 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3454 AssertRCReturn(rc, rc);
3455
3456 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3457 AssertRCReturn(rc, rc);
3458
3459 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3460 AssertRCReturn(rc, rc);
3461
3462 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3463 AssertRCReturn(rc, rc);
3464
3465 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3466 AssertRCReturn(rc, rc);
3467
3468 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3469 AssertRCReturn(rc, rc);
3470
3471 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3472 pVM->hm.s.fTPRPatchingActive = true;
3473
3474 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3475
3476 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3477 AssertRCReturn(rc, rc);
3478
3479 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3480 AssertRCReturn(rc, rc);
3481
3482 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3483 AssertRCReturn(rc, rc);
3484
3485 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3486 AssertRCReturn(rc, rc);
3487
3488 Log(("hmR3Load: patch %d\n", i));
3489 Log(("Key = %x\n", pPatch->Core.Key));
3490 Log(("cbOp = %d\n", pPatch->cbOp));
3491 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3492 Log(("type = %d\n", pPatch->enmType));
3493 Log(("srcop = %d\n", pPatch->uSrcOperand));
3494 Log(("dstop = %d\n", pPatch->uDstOperand));
3495 Log(("cFaults = %d\n", pPatch->cFaults));
3496 Log(("target = %x\n", pPatch->pJumpTarget));
3497 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3498 AssertRC(rc);
3499 }
3500 }
3501#endif
3502
3503 return VINF_SUCCESS;
3504}
3505
3506
3507/**
3508 * Displays the guest VM-exit history.
3509 *
3510 * @param pVM The cross context VM structure.
3511 * @param pHlp The info helper functions.
3512 * @param pszArgs Arguments, ignored.
3513 */
3514static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3515{
3516 NOREF(pszArgs);
3517 PVMCPU pVCpu = VMMGetCpu(pVM);
3518 if (!pVCpu)
3519 pVCpu = &pVM->aCpus[0];
3520
3521 if (HMIsEnabled(pVM))
3522 {
3523 bool const fIsVtx = pVM->hm.s.vmx.fSupported;
3524 const char * const *papszDesc;
3525 unsigned cMaxExitDesc;
3526 if (fIsVtx)
3527 {
3528 cMaxExitDesc = MAX_EXITREASON_VTX;
3529 papszDesc = &g_apszVTxExitReasons[0];
3530 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
3531 }
3532 else
3533 {
3534 cMaxExitDesc = MAX_EXITREASON_AMDV;
3535 papszDesc = &g_apszAmdVExitReasons[0];
3536 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
3537 }
3538
3539 pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
3540 unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3541 pVCpu->hm.s.idxExitHistoryFree - 1 :
3542 RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3543 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
3544 {
3545 uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
3546 const char *pszExit = NULL;
3547 if (uExit <= cMaxExitDesc)
3548 pszExit = papszDesc[uExit];
3549 else if (!fIsVtx)
3550 pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
3551 else
3552 pszExit = NULL;
3553
3554 pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
3555 idxLast == i ? "<-- Latest exit" : "");
3556 }
3557 pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3558 }
3559 else
3560 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3561}
3562
3563
3564/**
3565 * Displays the HM pending event.
3566 *
3567 * @param pVM The cross context VM structure.
3568 * @param pHlp The info helper functions.
3569 * @param pszArgs Arguments, ignored.
3570 */
3571static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3572{
3573 NOREF(pszArgs);
3574 PVMCPU pVCpu = VMMGetCpu(pVM);
3575 if (!pVCpu)
3576 pVCpu = &pVM->aCpus[0];
3577
3578 if (HMIsEnabled(pVM))
3579 {
3580 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3581 if (pVCpu->hm.s.Event.fPending)
3582 {
3583 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3584 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3585 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3586 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3587 }
3588 }
3589 else
3590 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3591}
3592
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