VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 45530

Last change on this file since 45530 was 45528, checked in by vboxsync, 11 years ago

VBOX_WITH_RAW_MODE changes.
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1/* $Id: HM.cpp 45528 2013-04-12 17:32:57Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/vmm/uvm.h>
42#include <VBox/err.h>
43#include <VBox/param.h>
44
45#include <iprt/assert.h>
46#include <VBox/log.h>
47#include <iprt/asm.h>
48#include <iprt/asm-amd64-x86.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
114 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL(),
119 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND. Guest software attempted to execute RDRAND."),
120 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID. Guest software attempted to execute INVPCID."),
121 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC. Guest software attempted to execute VMFUNC.")
122};
123/** Exit reason descriptions for AMD-V, used to describe statistics. */
124static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
125{
126 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
127 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
128 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
129 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
130 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
131 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
132 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
133 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
134 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
135 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
136 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
137 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
138 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
139 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
140 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
141 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
158 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
159 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
160 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
161 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
162 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
163 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
164 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
165 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
166 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
167 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
168 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
169 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
170 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
171 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
172 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
173 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
222 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
223 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
224 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
225 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
226 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
227 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
228 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
229 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
230 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
232 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
236 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
237 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
238 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
239 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
240 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
241 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
242 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
243 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
244 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
245 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
246 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
247 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
248 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
249 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
250 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
251 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
252 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
253 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
254 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
255 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
256 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
257 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
258 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
259 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
260 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
261 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
262 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
263 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
264 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
265 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
266 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
267 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
268 EXIT_REASON_NIL()
269};
270# undef EXIT_REASON
271# undef EXIT_REASON_NIL
272#endif /* VBOX_WITH_STATISTICS */
273
274#define VMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
275 do { \
276 if ((allowed1) & (featflag)) \
277 LogRel(("HM: " #featflag "\n")); \
278 else \
279 LogRel(("HM: " #featflag " *must* be cleared\n")); \
280 if ((disallowed0) & (featflag)) \
281 LogRel(("HM: " #featflag " *must* be set\n")); \
282 } while(0)
283
284#define VMX_REPORT_CAPABILITY(msrcaps, cap) \
285 do { \
286 if ((msrcaps) & (cap)) \
287 LogRel(("HM: " #cap "\n")); \
288 } while(0)
289
290/*******************************************************************************
291* Internal Functions *
292*******************************************************************************/
293static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
294static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
295static int hmR3InitCPU(PVM pVM);
296static int hmR3InitFinalizeR0(PVM pVM);
297static int hmR3TermCPU(PVM pVM);
298
299
300/**
301 * Initializes the HM.
302 *
303 * @returns VBox status code.
304 * @param pVM Pointer to the VM.
305 */
306VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
307{
308 LogFlow(("HMR3Init\n"));
309
310 /*
311 * Assert alignment and sizes.
312 */
313 AssertCompileMemberAlignment(VM, hm.s, 32);
314 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
315
316 /* Some structure checks. */
317 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
318 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
319 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
320
321 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
322 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
323 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
324 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
325 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
326 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
327 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
328 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
329 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
330 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
331 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
332
333 /*
334 * Register the saved state data unit.
335 */
336 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
337 NULL, NULL, NULL,
338 NULL, hmR3Save, NULL,
339 NULL, hmR3Load, NULL);
340 if (RT_FAILURE(rc))
341 return rc;
342
343 /* Misc initialisation. */
344 pVM->hm.s.vmx.fSupported = false;
345 pVM->hm.s.svm.fSupported = false;
346 pVM->hm.s.vmx.fEnabled = false;
347 pVM->hm.s.svm.fEnabled = false;
348
349 pVM->hm.s.fNestedPaging = false;
350 pVM->hm.s.fLargePages = false;
351
352 /* Disabled by default. */
353 pVM->fHMEnabled = false;
354
355 /*
356 * Check CFGM options.
357 */
358 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
359 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
360 /* Nested paging: disabled by default. */
361 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
362 AssertRC(rc);
363
364 /* Large pages: disabled by default. */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
366 AssertRC(rc);
367
368 /* VT-x VPID: disabled by default. */
369 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
370 AssertRC(rc);
371
372 /* HM support must be explicitely enabled in the configuration file. */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
374 AssertRC(rc);
375
376 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
377 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
378 AssertRC(rc);
379
380#ifdef RT_OS_DARWIN
381 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
382#else
383 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
384#endif
385 {
386 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
387 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
388 return VERR_HM_CONFIG_MISMATCH;
389 }
390
391 if (VMMIsHwVirtExtForced(pVM))
392 pVM->fHMEnabled = true;
393
394#if HC_ARCH_BITS == 32
395 /*
396 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
397 * (To use the default, don't set 64bitEnabled in CFGM.)
398 */
399 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
400 AssertLogRelRCReturn(rc, rc);
401 if (pVM->hm.s.fAllow64BitGuests)
402 {
403# ifdef RT_OS_DARWIN
404 if (!VMMIsHwVirtExtForced(pVM))
405# else
406 if (!pVM->hm.s.fAllowed)
407# endif
408 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
409 }
410#else
411 /*
412 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
413 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
414 */
415 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
416 AssertLogRelRCReturn(rc, rc);
417#endif
418
419
420 /*
421 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
422 * or local init each time we wish to execute guest code.
423 *
424 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
425 */
426 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
427#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
428 false
429#else
430 true
431#endif
432 );
433
434 /* Max number of resume loops. */
435 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
436 AssertRC(rc);
437
438 return rc;
439}
440
441
442/**
443 * Initializes the per-VCPU HM.
444 *
445 * @returns VBox status code.
446 * @param pVM Pointer to the VM.
447 */
448static int hmR3InitCPU(PVM pVM)
449{
450 LogFlow(("HMR3InitCPU\n"));
451
452 for (VMCPUID i = 0; i < pVM->cCpus; i++)
453 {
454 PVMCPU pVCpu = &pVM->aCpus[i];
455
456 pVCpu->hm.s.fActive = false;
457 }
458
459#ifdef VBOX_WITH_STATISTICS
460 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
461 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
462 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
463 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
464
465 /*
466 * Statistics.
467 */
468 for (VMCPUID i = 0; i < pVM->cCpus; i++)
469 {
470 PVMCPU pVCpu = &pVM->aCpus[i];
471 int rc;
472
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
474 "Profiling of RTMpPokeCpu",
475 "/PROF/CPU%d/HM/Poke", i);
476 AssertRC(rc);
477 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
478 "Profiling of poke wait",
479 "/PROF/CPU%d/HM/PokeWait", i);
480 AssertRC(rc);
481 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
482 "Profiling of poke wait when RTMpPokeCpu fails",
483 "/PROF/CPU%d/HM/PokeWaitFailed", i);
484 AssertRC(rc);
485 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
486 "Profiling of VMXR0RunGuestCode entry",
487 "/PROF/CPU%d/HM/StatEntry", i);
488 AssertRC(rc);
489 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
490 "Profiling of VMXR0RunGuestCode exit part 1",
491 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
492 AssertRC(rc);
493 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
494 "Profiling of VMXR0RunGuestCode exit part 2",
495 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
496 AssertRC(rc);
497
498 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
499 "I/O",
500 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
501 AssertRC(rc);
502 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
503 "MOV CRx",
504 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
505 AssertRC(rc);
506 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
507 "Exceptions, NMIs",
508 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
509 AssertRC(rc);
510
511 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
512 "Profiling of VMXR0LoadGuestState",
513 "/PROF/CPU%d/HM/StatLoadGuestState", i);
514 AssertRC(rc);
515 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
516 "Profiling of vmlaunch/vmresume",
517 "/PROF/CPU%d/HM/InGC", i);
518 AssertRC(rc);
519
520# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
521 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
522 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
523 "/PROF/CPU%d/HM/Switcher3264", i);
524 AssertRC(rc);
525# endif
526
527# define HM_REG_COUNTER(a, b) \
528 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of HM", b, i); \
529 AssertRC(rc);
530
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
559 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
560 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
563 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
564 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
567 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
568 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
571 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
572 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
574 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
575 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt");
578 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
579 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
580 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
581 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
582 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
583
584 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
585 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF");
586 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3");
587 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3");
588
589 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
590 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
591 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
592
593 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
594 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
595 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
596 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
597 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
598 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch");
599 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
600 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
601 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
602 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt");
603 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys");
604 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
605 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
606
607 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
608 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
609 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
610
611 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
612 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
613 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
614
615 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
616 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
617
618#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
619 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
620 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
621#endif
622
623 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
624 {
625 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
626 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
627 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
628 AssertRC(rc);
629 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
630 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
631 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
632 AssertRC(rc);
633 }
634
635#undef HM_REG_COUNTER
636
637 pVCpu->hm.s.paStatExitReason = NULL;
638
639 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
640 (void **)&pVCpu->hm.s.paStatExitReason);
641 AssertRC(rc);
642 if (RT_SUCCESS(rc))
643 {
644 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
645 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
646 {
647 if (papszDesc[j])
648 {
649 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
650 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
651 AssertRC(rc);
652 }
653 }
654 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
655 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
656 AssertRC(rc);
657 }
658 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
659# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
660 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
661# else
662 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
663# endif
664
665 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
666 AssertRCReturn(rc, rc);
667 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
668# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
669 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
670# else
671 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
672# endif
673 for (unsigned j = 0; j < 255; j++)
674 {
675 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
676 "Forwarded interrupts.",
677 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
678 }
679
680 }
681#endif /* VBOX_WITH_STATISTICS */
682
683#ifdef VBOX_WITH_CRASHDUMP_MAGIC
684 /* Magic marker for searching in crash dumps. */
685 for (VMCPUID i = 0; i < pVM->cCpus; i++)
686 {
687 PVMCPU pVCpu = &pVM->aCpus[i];
688
689 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
690 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
691 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
692 }
693#endif
694 return VINF_SUCCESS;
695}
696
697
698/**
699 * Called when a init phase has completed.
700 *
701 * @returns VBox status code.
702 * @param pVM The VM.
703 * @param enmWhat The phase that completed.
704 */
705VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
706{
707 switch (enmWhat)
708 {
709 case VMINITCOMPLETED_RING3:
710 return hmR3InitCPU(pVM);
711 case VMINITCOMPLETED_RING0:
712 return hmR3InitFinalizeR0(pVM);
713 default:
714 return VINF_SUCCESS;
715 }
716}
717
718
719/**
720 * Turns off normal raw mode features.
721 *
722 * @param pVM Pointer to the VM.
723 */
724static void hmR3DisableRawMode(PVM pVM)
725{
726#ifdef VBOX_WITH_RAW_MODE
727 /* Disable PATM & CSAM. */
728 PATMR3AllowPatching(pVM->pUVM, false);
729 CSAMDisableScanning(pVM);
730#endif
731
732 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
733 SELMR3DisableMonitoring(pVM);
734 TRPMR3DisableMonitoring(pVM);
735
736 /* Disable the switcher code (safety precaution). */
737 VMMR3DisableSwitcher(pVM);
738
739 /* Disable mapping of the hypervisor into the shadow page table. */
740 PGMR3MappingsDisable(pVM);
741
742 /* Disable the switcher */
743 VMMR3DisableSwitcher(pVM);
744
745 /* Reinit the paging mode to force the new shadow mode. */
746 for (VMCPUID i = 0; i < pVM->cCpus; i++)
747 {
748 PVMCPU pVCpu = &pVM->aCpus[i];
749
750 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
751 }
752}
753
754
755/**
756 * Initialize VT-x or AMD-V.
757 *
758 * @returns VBox status code.
759 * @param pVM Pointer to the VM.
760 */
761static int hmR3InitFinalizeR0(PVM pVM)
762{
763 int rc;
764
765 /*
766 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
767 * is already using AMD-V.
768 */
769 if ( !pVM->hm.s.vmx.fSupported
770 && !pVM->hm.s.svm.fSupported
771 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
772 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
773 {
774 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
775 pVM->hm.s.svm.fSupported = true;
776 pVM->hm.s.svm.fIgnoreInUseError = true;
777 }
778 else
779 if ( !pVM->hm.s.vmx.fSupported
780 && !pVM->hm.s.svm.fSupported)
781 {
782 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
783 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
784
785 if (VMMIsHwVirtExtForced(pVM))
786 {
787 switch (pVM->hm.s.lLastError)
788 {
789 case VERR_VMX_NO_VMX:
790 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
791 case VERR_VMX_IN_VMX_ROOT_MODE:
792 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
793 case VERR_SVM_IN_USE:
794 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
795 case VERR_SVM_NO_SVM:
796 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
797 case VERR_SVM_DISABLED:
798 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
799 default:
800 return pVM->hm.s.lLastError;
801 }
802 }
803 return VINF_SUCCESS;
804 }
805
806 if (pVM->hm.s.vmx.fSupported)
807 {
808 rc = SUPR3QueryVTxSupported();
809 if (RT_FAILURE(rc))
810 {
811#ifdef RT_OS_LINUX
812 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
813#else
814 LogRel(("HM: The host kernel does not support VT-x!\n"));
815#endif
816 if ( pVM->cCpus > 1
817 || VMMIsHwVirtExtForced(pVM))
818 return rc;
819
820 /* silently fall back to raw mode */
821 return VINF_SUCCESS;
822 }
823 }
824
825 if (!pVM->hm.s.fAllowed)
826 return VINF_SUCCESS; /* nothing to do */
827
828 /* Enable VT-x or AMD-V on all host CPUs. */
829 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
830 if (RT_FAILURE(rc))
831 {
832 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
833 return rc;
834 }
835 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
836
837 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
838 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
839 if (!pVM->hm.s.fHasIoApic)
840 {
841 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
842 pVM->hm.s.fTRPPatchingAllowed = false;
843 }
844
845 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
846 if (pVM->hm.s.vmx.fSupported)
847 {
848 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
849
850 if ( pVM->hm.s.fInitialized == false
851 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
852 {
853 uint64_t val;
854 uint64_t zap;
855 RTGCPHYS GCPhys = 0;
856
857#ifndef VBOX_WITH_OLD_VTX_CODE
858 LogRel(("HM: Using VT-x implementation 2.0!\n"));
859#endif
860 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
861 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
862 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
863 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
864 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
865 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
866 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
867 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
868 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
869
870 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
871 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
872 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
873 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT);
874 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT);
875 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI);
876 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER);
877
878 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
879 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
880 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
881 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT);
882 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TSC_OFFSETTING);
883 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT);
884 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT);
885 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT);
886 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT);
887 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT);
888 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT);
889 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
890 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT);
891 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT);
892 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW);
893 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT);
894 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
895 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT);
896 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS);
897 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG);
898 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS);
899 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT);
900 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT);
901 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
902 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
903 {
904 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
905 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
906 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
907 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
908 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
909 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
910 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
911 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
912 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
913 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
914 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
915 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
916 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
917 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
918 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
919 }
920
921 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
922 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
923 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
924 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG);
925 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST);
926 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM);
927 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON);
928 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR);
929 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR);
930 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR);
931
932 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
933 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
934 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
935 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG);
936 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE);
937 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR);
938 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT);
939 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR);
940 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR);
941 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR);
942 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR);
943 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER);
944
945 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
946 {
947 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
948 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", val));
949 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
950 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
951 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
952 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
953 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
954 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
955 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
956 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
957 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
958 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
959 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
960 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
961 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
962 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
963 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
964 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
965 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
966 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
967 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
968 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
969 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
970 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
971 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
972 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
973 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
974 }
975
976 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
977 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
978 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
979 else
980 {
981 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
982 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
983 }
984
985 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
986 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
987 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
988 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
989
990 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
991 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
992 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
993 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
994 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
995
996 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
997
998 /* Paranoia */
999 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1000
1001 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1002 {
1003 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1004 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1005 }
1006
1007 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1008 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1009
1010 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1011 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1012
1013 /*
1014 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1015 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1016 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1017 */
1018 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1019 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1020 {
1021 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1022 LogRel(("HM: Disabled RDTSCP\n"));
1023 }
1024
1025 /* Unrestricted guest execution relies on EPT. */
1026 if ( pVM->hm.s.fNestedPaging
1027 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1028 {
1029 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1030 }
1031
1032 /* Only try once. */
1033 pVM->hm.s.fInitialized = true;
1034
1035 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1036 {
1037 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1038 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1039 if (RT_SUCCESS(rc))
1040 {
1041 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1042 /* Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode" esp. Figure 20-5.*/
1043 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1044 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1045 /* Bit set to 0 means software interrupts are redirected to the 8086 program interrupt handler rather than
1046 switching to protected-mode handler. */
1047 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1048 /* Allow all port IO, so that port IO instructions do not cause exceptions and would instead
1049 cause a VM-exit (based on VT-x's IO bitmap which we currently configure to always cause an exit). */
1050 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1051 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1052
1053 /*
1054 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1055 * real and protected mode without paging with EPT.
1056 */
1057 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1058 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1059 {
1060 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1061 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1062 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1063 | X86_PDE4M_G;
1064 }
1065
1066 /* We convert it here every time as pci regions could be reconfigured. */
1067 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1068 AssertRC(rc);
1069 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1070
1071 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1072 AssertRC(rc);
1073 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1074 }
1075 else
1076 {
1077 /** @todo This cannot possibly work, there are other places which assumes
1078 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1079 * a failure case. */
1080 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1081 pVM->hm.s.vmx.pRealModeTSS = NULL;
1082 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1083 }
1084 }
1085
1086 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1087 AssertRC(rc);
1088 if (rc == VINF_SUCCESS)
1089 {
1090 pVM->fHMEnabled = true;
1091 pVM->hm.s.vmx.fEnabled = true;
1092 hmR3DisableRawMode(pVM);
1093
1094 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1095#ifdef VBOX_ENABLE_64_BITS_GUESTS
1096 if (pVM->hm.s.fAllow64BitGuests)
1097 {
1098 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1099 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1100 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1101 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1102 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1103# if RT_ARCH_X86
1104 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1105 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1106 LogRel(("NX is only supported for 64-bit guests!\n"));
1107# endif
1108 }
1109 else
1110 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1111 /* Todo: this needs to be fixed properly!! */
1112 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1113 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1114 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1115 else
1116 LogRel(("HM: NX not supported by the host\n"));
1117
1118 LogRel((pVM->hm.s.fAllow64BitGuests
1119 ? "HM: 32-bit and 64-bit guests supported.\n"
1120 : "HM: 32-bit guests supported.\n"));
1121#else
1122 LogRel(("HM: 32-bit guests supported.\n"));
1123#endif
1124 LogRel(("HM: VMX enabled!\n"));
1125 if (pVM->hm.s.fNestedPaging)
1126 {
1127 LogRel(("HM: Nested paging enabled!\n"));
1128 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1129 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1130 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1131 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1132 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1133 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1134 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1135 else
1136 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1137
1138 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1139 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1140
1141#if HC_ARCH_BITS == 64
1142 if (pVM->hm.s.fLargePages)
1143 {
1144 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1145 PGMSetLargePageUsage(pVM, true);
1146 LogRel(("HM: Large page support enabled!\n"));
1147 }
1148#endif
1149 }
1150 else
1151 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1152
1153 if (pVM->hm.s.vmx.fVpid)
1154 {
1155 LogRel(("HM: VPID enabled!\n"));
1156 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1157 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1158 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1159 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1160 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1161 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1162 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1163 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1164 else
1165 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1166 }
1167 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1168 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1169
1170 /* TPR patching status logging. */
1171 if (pVM->hm.s.fTRPPatchingAllowed)
1172 {
1173 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1174 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1175 {
1176 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1177 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1178 }
1179 else
1180 {
1181 uint32_t u32Eax, u32Dummy;
1182
1183 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1184 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1185 if ( u32Eax < 0x80000001
1186 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1187 {
1188 pVM->hm.s.fTRPPatchingAllowed = false;
1189 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1190 }
1191 }
1192 }
1193 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1194
1195 /*
1196 * Check for preemption timer config override and log the state of it.
1197 */
1198 if (pVM->hm.s.vmx.fUsePreemptTimer)
1199 {
1200 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1201 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1202 AssertLogRelRC(rc2);
1203 }
1204 if (pVM->hm.s.vmx.fUsePreemptTimer)
1205 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1206 }
1207 else
1208 {
1209 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1210 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1211 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1212 pVM->fHMEnabled = false;
1213 }
1214 }
1215 }
1216 else
1217 if (pVM->hm.s.svm.fSupported)
1218 {
1219 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1220
1221 if (pVM->hm.s.fInitialized == false)
1222 {
1223 /* Erratum 170 which requires a forced TLB flush for each world switch:
1224 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1225 *
1226 * All BH-G1/2 and DH-G1/2 models include a fix:
1227 * Athlon X2: 0x6b 1/2
1228 * 0x68 1/2
1229 * Athlon 64: 0x7f 1
1230 * 0x6f 2
1231 * Sempron: 0x7f 1/2
1232 * 0x6f 2
1233 * 0x6c 2
1234 * 0x7c 2
1235 * Turion 64: 0x68 2
1236 *
1237 */
1238 uint32_t u32Dummy;
1239 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1240 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1241 u32BaseFamily= (u32Version >> 8) & 0xf;
1242 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1243 u32Model = ((u32Version >> 4) & 0xf);
1244 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1245 u32Stepping = u32Version & 0xf;
1246 if ( u32Family == 0xf
1247 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1248 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1249 {
1250 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1251 }
1252
1253 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1254 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1255 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1256 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1257 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1258 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1259 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1260 {
1261#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1262 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1263 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1264 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1265 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1266 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1267 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1268 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1269 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1270 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1271 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1272 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1273#undef FLAG_NAME
1274 };
1275 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1276 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1277 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1278 {
1279 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1280 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1281 }
1282 if (fSvmFeatures)
1283 for (unsigned iBit = 0; iBit < 32; iBit++)
1284 if (RT_BIT_32(iBit) & fSvmFeatures)
1285 LogRel(("HM: Reserved bit %u\n", iBit));
1286
1287 /* Only try once. */
1288 pVM->hm.s.fInitialized = true;
1289
1290 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1291 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1292
1293 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1294 AssertRC(rc);
1295 if (rc == VINF_SUCCESS)
1296 {
1297 pVM->fHMEnabled = true;
1298 pVM->hm.s.svm.fEnabled = true;
1299
1300 if (pVM->hm.s.fNestedPaging)
1301 {
1302 LogRel(("HM: Enabled nested paging!\n"));
1303#if HC_ARCH_BITS == 64
1304 if (pVM->hm.s.fLargePages)
1305 {
1306 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1307 PGMSetLargePageUsage(pVM, true);
1308 LogRel(("HM: Large page support enabled!\n"));
1309 }
1310#endif
1311 }
1312
1313 hmR3DisableRawMode(pVM);
1314 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1315 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1316#ifdef VBOX_ENABLE_64_BITS_GUESTS
1317 if (pVM->hm.s.fAllow64BitGuests)
1318 {
1319 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1320 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1321 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1322 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1323 }
1324 else
1325 /* Turn on NXE if PAE has been enabled. */
1326 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1327 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1328#endif
1329
1330 LogRel((pVM->hm.s.fAllow64BitGuests
1331 ? "HM: 32-bit and 64-bit guest supported.\n"
1332 : "HM: 32-bit guest supported.\n"));
1333
1334 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1335 }
1336 else
1337 {
1338 pVM->fHMEnabled = false;
1339 }
1340 }
1341 }
1342 if (pVM->fHMEnabled)
1343 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1344 RTLogRelSetBuffering(fOldBuffered);
1345 return VINF_SUCCESS;
1346}
1347
1348
1349/**
1350 * Applies relocations to data and code managed by this
1351 * component. This function will be called at init and
1352 * whenever the VMM need to relocate it self inside the GC.
1353 *
1354 * @param pVM The VM.
1355 */
1356VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1357{
1358 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1359
1360 /* Fetch the current paging mode during the relocate callback during state loading. */
1361 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1362 {
1363 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1364 {
1365 PVMCPU pVCpu = &pVM->aCpus[i];
1366
1367 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1368 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1369 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1370 }
1371 }
1372#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1373 if (pVM->fHMEnabled)
1374 {
1375 int rc;
1376 switch (PGMGetHostMode(pVM))
1377 {
1378 case PGMMODE_32_BIT:
1379 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1380 break;
1381
1382 case PGMMODE_PAE:
1383 case PGMMODE_PAE_NX:
1384 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1385 break;
1386
1387 default:
1388 AssertFailed();
1389 break;
1390 }
1391 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1392 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1393
1394 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1395 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1396
1397 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1398 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1399
1400 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1401 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1402
1403# ifdef DEBUG
1404 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1405 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1406# endif
1407 }
1408#endif
1409 return;
1410}
1411
1412
1413/**
1414 * Checks if hardware accelerated raw mode is allowed.
1415 *
1416 * @returns true if hardware acceleration is allowed, otherwise false.
1417 * @param pVM Pointer to the VM.
1418 */
1419VMMR3_INT_DECL(bool) HMR3IsAllowed(PVM pVM)
1420{
1421 return pVM->hm.s.fAllowed;
1422}
1423
1424
1425/**
1426 * Notification callback which is called whenever there is a chance that a CR3
1427 * value might have changed.
1428 *
1429 * This is called by PGM.
1430 *
1431 * @param pVM Pointer to the VM.
1432 * @param pVCpu Pointer to the VMCPU.
1433 * @param enmShadowMode New shadow paging mode.
1434 * @param enmGuestMode New guest paging mode.
1435 */
1436VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1437{
1438 /* Ignore page mode changes during state loading. */
1439 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1440 return;
1441
1442 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1443
1444#ifdef VBOX_WITH_OLD_VTX_CODE
1445 if ( pVM->hm.s.vmx.fEnabled
1446 && pVM->fHMEnabled)
1447 {
1448 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1449 && enmGuestMode >= PGMMODE_PROTECTED)
1450 {
1451 PCPUMCTX pCtx;
1452
1453 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1454
1455 /* After a real mode switch to protected mode we must force
1456 CPL to 0. Our real mode emulation had to set it to 3. */
1457 pCtx->ss.Attr.n.u2Dpl = 0;
1458 }
1459 }
1460#endif
1461
1462 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1463 {
1464 /* Keep track of paging mode changes. */
1465 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1466 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1467
1468 /* Did we miss a change, because all code was executed in the recompiler? */
1469 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1470 {
1471 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1472 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1473 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1474 }
1475 }
1476
1477 /** @todo r=ramshankar: Why do we need to do this? Most likely
1478 * VBOX_WITH_OLD_VTX_CODE only. */
1479 /* Reset the contents of the read cache. */
1480 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1481 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1482 pCache->Read.aFieldVal[j] = 0;
1483}
1484
1485
1486/**
1487 * Terminates the HM.
1488 *
1489 * Termination means cleaning up and freeing all resources,
1490 * the VM itself is, at this point, powered off or suspended.
1491 *
1492 * @returns VBox status code.
1493 * @param pVM Pointer to the VM.
1494 */
1495VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1496{
1497 if (pVM->hm.s.vmx.pRealModeTSS)
1498 {
1499 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1500 pVM->hm.s.vmx.pRealModeTSS = 0;
1501 }
1502 hmR3TermCPU(pVM);
1503 return 0;
1504}
1505
1506
1507/**
1508 * Terminates the per-VCPU HM.
1509 *
1510 * @returns VBox status code.
1511 * @param pVM Pointer to the VM.
1512 */
1513static int hmR3TermCPU(PVM pVM)
1514{
1515 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1516 {
1517 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1518
1519#ifdef VBOX_WITH_STATISTICS
1520 if (pVCpu->hm.s.paStatExitReason)
1521 {
1522 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1523 pVCpu->hm.s.paStatExitReason = NULL;
1524 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1525 }
1526 if (pVCpu->hm.s.paStatInjectedIrqs)
1527 {
1528 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1529 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1530 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1531 }
1532#endif
1533
1534#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1535 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1536 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1537 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1538#endif
1539 }
1540 return 0;
1541}
1542
1543
1544/**
1545 * Resets a virtual CPU.
1546 *
1547 * Used by HMR3Reset and CPU hot plugging.
1548 *
1549 * @param pVCpu The CPU to reset.
1550 */
1551VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1552{
1553 /* On first entry we'll sync everything. */
1554 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1555
1556 pVCpu->hm.s.vmx.cr0_mask = 0;
1557 pVCpu->hm.s.vmx.cr4_mask = 0;
1558
1559 pVCpu->hm.s.fActive = false;
1560 pVCpu->hm.s.Event.fPending = false;
1561
1562 /* Reset state information for real-mode emulation in VT-x. */
1563 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1564 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1565 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1566
1567 /* Reset the contents of the read cache. */
1568 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1569 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1570 pCache->Read.aFieldVal[j] = 0;
1571
1572#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1573 /* Magic marker for searching in crash dumps. */
1574 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1575 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1576#endif
1577}
1578
1579
1580/**
1581 * The VM is being reset.
1582 *
1583 * For the HM component this means that any GDT/LDT/TSS monitors
1584 * needs to be removed.
1585 *
1586 * @param pVM Pointer to the VM.
1587 */
1588VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1589{
1590 LogFlow(("HMR3Reset:\n"));
1591
1592 if (pVM->fHMEnabled)
1593 hmR3DisableRawMode(pVM);
1594
1595 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1596 {
1597 PVMCPU pVCpu = &pVM->aCpus[i];
1598
1599 HMR3ResetCpu(pVCpu);
1600 }
1601
1602 /* Clear all patch information. */
1603 pVM->hm.s.pGuestPatchMem = 0;
1604 pVM->hm.s.pFreeGuestPatchMem = 0;
1605 pVM->hm.s.cbGuestPatchMem = 0;
1606 pVM->hm.s.cPatches = 0;
1607 pVM->hm.s.PatchTree = 0;
1608 pVM->hm.s.fTPRPatchingActive = false;
1609 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1610}
1611
1612
1613/**
1614 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1615 *
1616 * @returns VBox strict status code.
1617 * @param pVM Pointer to the VM.
1618 * @param pVCpu The VMCPU for the EMT we're being called on.
1619 * @param pvUser Unused.
1620 */
1621DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1622{
1623 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1624
1625 /* Only execute the handler on the VCPU the original patch request was issued. */
1626 if (pVCpu->idCpu != idCpu)
1627 return VINF_SUCCESS;
1628
1629 Log(("hmR3RemovePatches\n"));
1630 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1631 {
1632 uint8_t abInstr[15];
1633 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1634 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1635 int rc;
1636
1637#ifdef LOG_ENABLED
1638 char szOutput[256];
1639
1640 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1641 szOutput, sizeof(szOutput), NULL);
1642 if (RT_SUCCESS(rc))
1643 Log(("Patched instr: %s\n", szOutput));
1644#endif
1645
1646 /* Check if the instruction is still the same. */
1647 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1648 if (rc != VINF_SUCCESS)
1649 {
1650 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1651 continue; /* swapped out or otherwise removed; skip it. */
1652 }
1653
1654 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1655 {
1656 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1657 continue; /* skip it. */
1658 }
1659
1660 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1661 AssertRC(rc);
1662
1663#ifdef LOG_ENABLED
1664 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1665 szOutput, sizeof(szOutput), NULL);
1666 if (RT_SUCCESS(rc))
1667 Log(("Original instr: %s\n", szOutput));
1668#endif
1669 }
1670 pVM->hm.s.cPatches = 0;
1671 pVM->hm.s.PatchTree = 0;
1672 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1673 pVM->hm.s.fTPRPatchingActive = false;
1674 return VINF_SUCCESS;
1675}
1676
1677
1678/**
1679 * Worker for enabling patching in a VT-x/AMD-V guest.
1680 *
1681 * @returns VBox status code.
1682 * @param pVM Pointer to the VM.
1683 * @param idCpu VCPU to execute hmR3RemovePatches on.
1684 * @param pPatchMem Patch memory range.
1685 * @param cbPatchMem Size of the memory range.
1686 */
1687static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1688{
1689 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1690 AssertRC(rc);
1691
1692 pVM->hm.s.pGuestPatchMem = pPatchMem;
1693 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1694 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1695 return VINF_SUCCESS;
1696}
1697
1698
1699/**
1700 * Enable patching in a VT-x/AMD-V guest
1701 *
1702 * @returns VBox status code.
1703 * @param pVM Pointer to the VM.
1704 * @param pPatchMem Patch memory range.
1705 * @param cbPatchMem Size of the memory range.
1706 */
1707VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1708{
1709 VM_ASSERT_EMT(pVM);
1710 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1711 if (pVM->cCpus > 1)
1712 {
1713 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1714 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1715 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1716 AssertRC(rc);
1717 return rc;
1718 }
1719 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1720}
1721
1722
1723/**
1724 * Disable patching in a VT-x/AMD-V guest.
1725 *
1726 * @returns VBox status code.
1727 * @param pVM Pointer to the VM.
1728 * @param pPatchMem Patch memory range.
1729 * @param cbPatchMem Size of the memory range.
1730 */
1731VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1732{
1733 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1734
1735 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1736 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1737
1738 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1739 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1740 (void *)(uintptr_t)VMMGetCpuId(pVM));
1741 AssertRC(rc);
1742
1743 pVM->hm.s.pGuestPatchMem = 0;
1744 pVM->hm.s.pFreeGuestPatchMem = 0;
1745 pVM->hm.s.cbGuestPatchMem = 0;
1746 pVM->hm.s.fTPRPatchingActive = false;
1747 return VINF_SUCCESS;
1748}
1749
1750
1751/**
1752 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1753 *
1754 * @returns VBox strict status code.
1755 * @param pVM Pointer to the VM.
1756 * @param pVCpu The VMCPU for the EMT we're being called on.
1757 * @param pvUser User specified CPU context.
1758 *
1759 */
1760DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1761{
1762 /*
1763 * Only execute the handler on the VCPU the original patch request was
1764 * issued. (The other CPU(s) might not yet have switched to protected
1765 * mode, nor have the correct memory context.)
1766 */
1767 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1768 if (pVCpu->idCpu != idCpu)
1769 return VINF_SUCCESS;
1770
1771 /*
1772 * We're racing other VCPUs here, so don't try patch the instruction twice
1773 * and make sure there is still room for our patch record.
1774 */
1775 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1776 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1777 if (pPatch)
1778 {
1779 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1780 return VINF_SUCCESS;
1781 }
1782 uint32_t const idx = pVM->hm.s.cPatches;
1783 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1784 {
1785 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1786 return VINF_SUCCESS;
1787 }
1788 pPatch = &pVM->hm.s.aPatches[idx];
1789
1790 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1791
1792 /*
1793 * Disassembler the instruction and get cracking.
1794 */
1795 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1796 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1797 uint32_t cbOp;
1798 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1799 AssertRC(rc);
1800 if ( rc == VINF_SUCCESS
1801 && pDis->pCurInstr->uOpcode == OP_MOV
1802 && cbOp >= 3)
1803 {
1804 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1805
1806 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1807 AssertRC(rc);
1808
1809 pPatch->cbOp = cbOp;
1810
1811 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1812 {
1813 /* write. */
1814 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1815 {
1816 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1817 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1818 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1819 }
1820 else
1821 {
1822 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1823 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1824 pPatch->uSrcOperand = pDis->Param2.uValue;
1825 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1826 }
1827 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1828 AssertRC(rc);
1829
1830 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1831 pPatch->cbNewOp = sizeof(s_abVMMCall);
1832 }
1833 else
1834 {
1835 /*
1836 * TPR Read.
1837 *
1838 * Found:
1839 * mov eax, dword [fffe0080] (5 bytes)
1840 * Check if next instruction is:
1841 * shr eax, 4
1842 */
1843 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1844
1845 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1846 uint8_t const cbOpMmio = cbOp;
1847 uint64_t const uSavedRip = pCtx->rip;
1848
1849 pCtx->rip += cbOp;
1850 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1851 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1852 pCtx->rip = uSavedRip;
1853
1854 if ( rc == VINF_SUCCESS
1855 && pDis->pCurInstr->uOpcode == OP_SHR
1856 && pDis->Param1.fUse == DISUSE_REG_GEN32
1857 && pDis->Param1.Base.idxGenReg == idxMmioReg
1858 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1859 && pDis->Param2.uValue == 4
1860 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1861 {
1862 uint8_t abInstr[15];
1863
1864 /* Replacing two instructions now. */
1865 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1866 AssertRC(rc);
1867
1868 pPatch->cbOp = cbOpMmio + cbOp;
1869
1870 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1871 abInstr[0] = 0xF0;
1872 abInstr[1] = 0x0F;
1873 abInstr[2] = 0x20;
1874 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1875 for (unsigned i = 4; i < pPatch->cbOp; i++)
1876 abInstr[i] = 0x90; /* nop */
1877
1878 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1879 AssertRC(rc);
1880
1881 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1882 pPatch->cbNewOp = pPatch->cbOp;
1883
1884 Log(("Acceptable read/shr candidate!\n"));
1885 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1886 }
1887 else
1888 {
1889 pPatch->enmType = HMTPRINSTR_READ;
1890 pPatch->uDstOperand = idxMmioReg;
1891
1892 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1893 AssertRC(rc);
1894
1895 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1896 pPatch->cbNewOp = sizeof(s_abVMMCall);
1897 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1898 }
1899 }
1900
1901 pPatch->Core.Key = pCtx->eip;
1902 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1903 AssertRC(rc);
1904
1905 pVM->hm.s.cPatches++;
1906 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1907 return VINF_SUCCESS;
1908 }
1909
1910 /*
1911 * Save invalid patch, so we will not try again.
1912 */
1913 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1914 pPatch->Core.Key = pCtx->eip;
1915 pPatch->enmType = HMTPRINSTR_INVALID;
1916 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1917 AssertRC(rc);
1918 pVM->hm.s.cPatches++;
1919 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1920 return VINF_SUCCESS;
1921}
1922
1923
1924/**
1925 * Callback to patch a TPR instruction (jump to generated code).
1926 *
1927 * @returns VBox strict status code.
1928 * @param pVM Pointer to the VM.
1929 * @param pVCpu The VMCPU for the EMT we're being called on.
1930 * @param pvUser User specified CPU context.
1931 *
1932 */
1933DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1934{
1935 /*
1936 * Only execute the handler on the VCPU the original patch request was
1937 * issued. (The other CPU(s) might not yet have switched to protected
1938 * mode, nor have the correct memory context.)
1939 */
1940 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1941 if (pVCpu->idCpu != idCpu)
1942 return VINF_SUCCESS;
1943
1944 /*
1945 * We're racing other VCPUs here, so don't try patch the instruction twice
1946 * and make sure there is still room for our patch record.
1947 */
1948 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1949 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1950 if (pPatch)
1951 {
1952 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1953 return VINF_SUCCESS;
1954 }
1955 uint32_t const idx = pVM->hm.s.cPatches;
1956 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1957 {
1958 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1959 return VINF_SUCCESS;
1960 }
1961 pPatch = &pVM->hm.s.aPatches[idx];
1962
1963 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1964 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
1965
1966 /*
1967 * Disassemble the instruction and get cracking.
1968 */
1969 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1970 uint32_t cbOp;
1971 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1972 AssertRC(rc);
1973 if ( rc == VINF_SUCCESS
1974 && pDis->pCurInstr->uOpcode == OP_MOV
1975 && cbOp >= 5)
1976 {
1977 uint8_t aPatch[64];
1978 uint32_t off = 0;
1979
1980 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1981 AssertRC(rc);
1982
1983 pPatch->cbOp = cbOp;
1984 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
1985
1986 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1987 {
1988 /*
1989 * TPR write:
1990 *
1991 * push ECX [51]
1992 * push EDX [52]
1993 * push EAX [50]
1994 * xor EDX,EDX [31 D2]
1995 * mov EAX,EAX [89 C0]
1996 * or
1997 * mov EAX,0000000CCh [B8 CC 00 00 00]
1998 * mov ECX,0C0000082h [B9 82 00 00 C0]
1999 * wrmsr [0F 30]
2000 * pop EAX [58]
2001 * pop EDX [5A]
2002 * pop ECX [59]
2003 * jmp return_address [E9 return_address]
2004 *
2005 */
2006 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2007
2008 aPatch[off++] = 0x51; /* push ecx */
2009 aPatch[off++] = 0x52; /* push edx */
2010 if (!fUsesEax)
2011 aPatch[off++] = 0x50; /* push eax */
2012 aPatch[off++] = 0x31; /* xor edx, edx */
2013 aPatch[off++] = 0xD2;
2014 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2015 {
2016 if (!fUsesEax)
2017 {
2018 aPatch[off++] = 0x89; /* mov eax, src_reg */
2019 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2020 }
2021 }
2022 else
2023 {
2024 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2025 aPatch[off++] = 0xB8; /* mov eax, immediate */
2026 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2027 off += sizeof(uint32_t);
2028 }
2029 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2030 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2031 off += sizeof(uint32_t);
2032
2033 aPatch[off++] = 0x0F; /* wrmsr */
2034 aPatch[off++] = 0x30;
2035 if (!fUsesEax)
2036 aPatch[off++] = 0x58; /* pop eax */
2037 aPatch[off++] = 0x5A; /* pop edx */
2038 aPatch[off++] = 0x59; /* pop ecx */
2039 }
2040 else
2041 {
2042 /*
2043 * TPR read:
2044 *
2045 * push ECX [51]
2046 * push EDX [52]
2047 * push EAX [50]
2048 * mov ECX,0C0000082h [B9 82 00 00 C0]
2049 * rdmsr [0F 32]
2050 * mov EAX,EAX [89 C0]
2051 * pop EAX [58]
2052 * pop EDX [5A]
2053 * pop ECX [59]
2054 * jmp return_address [E9 return_address]
2055 *
2056 */
2057 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2058
2059 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2060 aPatch[off++] = 0x51; /* push ecx */
2061 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2062 aPatch[off++] = 0x52; /* push edx */
2063 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2064 aPatch[off++] = 0x50; /* push eax */
2065
2066 aPatch[off++] = 0x31; /* xor edx, edx */
2067 aPatch[off++] = 0xD2;
2068
2069 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2070 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2071 off += sizeof(uint32_t);
2072
2073 aPatch[off++] = 0x0F; /* rdmsr */
2074 aPatch[off++] = 0x32;
2075
2076 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2077 {
2078 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2079 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2080 }
2081
2082 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2083 aPatch[off++] = 0x58; /* pop eax */
2084 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2085 aPatch[off++] = 0x5A; /* pop edx */
2086 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2087 aPatch[off++] = 0x59; /* pop ecx */
2088 }
2089 aPatch[off++] = 0xE9; /* jmp return_address */
2090 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2091 off += sizeof(RTRCUINTPTR);
2092
2093 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2094 {
2095 /* Write new code to the patch buffer. */
2096 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2097 AssertRC(rc);
2098
2099#ifdef LOG_ENABLED
2100 uint32_t cbCurInstr;
2101 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2102 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2103 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2104 {
2105 char szOutput[256];
2106 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2107 szOutput, sizeof(szOutput), &cbCurInstr);
2108 if (RT_SUCCESS(rc))
2109 Log(("Patch instr %s\n", szOutput));
2110 else
2111 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2112 }
2113#endif
2114
2115 pPatch->aNewOpcode[0] = 0xE9;
2116 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2117
2118 /* Overwrite the TPR instruction with a jump. */
2119 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2120 AssertRC(rc);
2121
2122 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2123
2124 pVM->hm.s.pFreeGuestPatchMem += off;
2125 pPatch->cbNewOp = 5;
2126
2127 pPatch->Core.Key = pCtx->eip;
2128 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2129 AssertRC(rc);
2130
2131 pVM->hm.s.cPatches++;
2132 pVM->hm.s.fTPRPatchingActive = true;
2133 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2134 return VINF_SUCCESS;
2135 }
2136
2137 Log(("Ran out of space in our patch buffer!\n"));
2138 }
2139 else
2140 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2141
2142
2143 /*
2144 * Save invalid patch, so we will not try again.
2145 */
2146 pPatch = &pVM->hm.s.aPatches[idx];
2147 pPatch->Core.Key = pCtx->eip;
2148 pPatch->enmType = HMTPRINSTR_INVALID;
2149 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2150 AssertRC(rc);
2151 pVM->hm.s.cPatches++;
2152 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2153 return VINF_SUCCESS;
2154}
2155
2156
2157/**
2158 * Attempt to patch TPR mmio instructions.
2159 *
2160 * @returns VBox status code.
2161 * @param pVM Pointer to the VM.
2162 * @param pVCpu Pointer to the VMCPU.
2163 * @param pCtx Pointer to the guest CPU context.
2164 */
2165VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2166{
2167 NOREF(pCtx);
2168 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2169 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2170 (void *)(uintptr_t)pVCpu->idCpu);
2171 AssertRC(rc);
2172 return rc;
2173}
2174
2175
2176/**
2177 * Force execution of the current IO code in the recompiler.
2178 *
2179 * @returns VBox status code.
2180 * @param pVM Pointer to the VM.
2181 * @param pCtx Partial VM execution context.
2182 */
2183VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2184{
2185 PVMCPU pVCpu = VMMGetCpu(pVM);
2186
2187 Assert(pVM->fHMEnabled);
2188 Log(("HMR3EmulateIoBlock\n"));
2189
2190 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2191 if (HMCanEmulateIoBlockEx(pCtx))
2192 {
2193 Log(("HMR3EmulateIoBlock -> enabled\n"));
2194 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2195 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2196 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2197 return VINF_EM_RESCHEDULE_REM;
2198 }
2199 return VINF_SUCCESS;
2200}
2201
2202
2203/**
2204 * Checks if we can currently use hardware accelerated raw mode.
2205 *
2206 * @returns true if we can currently use hardware acceleration, otherwise false.
2207 * @param pVM Pointer to the VM.
2208 * @param pCtx Partial VM execution context.
2209 */
2210VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2211{
2212 PVMCPU pVCpu = VMMGetCpu(pVM);
2213
2214 Assert(pVM->fHMEnabled);
2215
2216 /* If we're still executing the IO code, then return false. */
2217 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2218 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2219 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2220 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2221 return false;
2222
2223 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2224
2225 /* AMD-V supports real & protected mode with or without paging. */
2226 if (pVM->hm.s.svm.fEnabled)
2227 {
2228 pVCpu->hm.s.fActive = true;
2229 return true;
2230 }
2231
2232 pVCpu->hm.s.fActive = false;
2233
2234 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2235 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2236 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2237
2238 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2239 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2240 {
2241 /*
2242 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2243 * guest execution feature i missing (VT-x only).
2244 */
2245 if (fSupportsRealMode)
2246 {
2247 if (CPUMIsGuestInRealModeEx(pCtx))
2248 {
2249 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2250 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2251 * If this is not true, we cannot execute real mode as V86 and have to fall
2252 * back to emulation.
2253 */
2254 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2255 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2256 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2257 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2258 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2259 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2260 || (pCtx->cs.u32Limit != 0xffff)
2261 || (pCtx->ds.u32Limit != 0xffff)
2262 || (pCtx->es.u32Limit != 0xffff)
2263 || (pCtx->ss.u32Limit != 0xffff)
2264 || (pCtx->fs.u32Limit != 0xffff)
2265 || (pCtx->gs.u32Limit != 0xffff))
2266 {
2267 return false;
2268 }
2269 }
2270 else
2271 {
2272 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2273 /* Verify the requirements for executing code in protected
2274 mode. VT-x can't handle the CPU state right after a switch
2275 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2276 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2277 && enmGuestMode >= PGMMODE_PROTECTED)
2278 {
2279 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2280 || (pCtx->ds.Sel & X86_SEL_RPL)
2281 || (pCtx->es.Sel & X86_SEL_RPL)
2282 || (pCtx->fs.Sel & X86_SEL_RPL)
2283 || (pCtx->gs.Sel & X86_SEL_RPL)
2284 || (pCtx->ss.Sel & X86_SEL_RPL))
2285 {
2286 return false;
2287 }
2288 }
2289 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2290 if ( pCtx->gdtr.cbGdt
2291 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2292 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2293 {
2294 return false;
2295 }
2296 }
2297 }
2298 else
2299 {
2300 if ( !CPUMIsGuestInLongModeEx(pCtx)
2301 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2302 {
2303 /** @todo This should (probably) be set on every excursion to the REM,
2304 * however it's too risky right now. So, only apply it when we go
2305 * back to REM for real mode execution. (The XP hack below doesn't
2306 * work reliably without this.)
2307 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2308 for (uint32_t i = 0; i < pVM->cCpus; i++)
2309 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2310
2311 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2312 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2313 return false;
2314
2315 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2316 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2317 return false;
2318
2319 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2320 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2321 * hidden registers (possible recompiler bug; see load_seg_vm) */
2322 if (pCtx->cs.Attr.n.u1Present == 0)
2323 return false;
2324 if (pCtx->ss.Attr.n.u1Present == 0)
2325 return false;
2326
2327 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2328 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2329 /** @todo This check is actually wrong, it doesn't take the direction of the
2330 * stack segment into account. But, it does the job for now. */
2331 if (pCtx->rsp >= pCtx->ss.u32Limit)
2332 return false;
2333#if 0
2334 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2335 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2336 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2337 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2338 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2339 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2340 return false;
2341#endif
2342 }
2343 }
2344 }
2345
2346 if (pVM->hm.s.vmx.fEnabled)
2347 {
2348 uint32_t mask;
2349
2350 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2351 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2352 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2353 mask &= ~X86_CR0_NE;
2354
2355 if (fSupportsRealMode)
2356 {
2357 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2358 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2359 }
2360 else
2361 {
2362 /* We support protected mode without paging using identity mapping. */
2363 mask &= ~X86_CR0_PG;
2364 }
2365 if ((pCtx->cr0 & mask) != mask)
2366 return false;
2367
2368 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2369 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2370 if ((pCtx->cr0 & mask) != 0)
2371 return false;
2372
2373 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2374 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2375 mask &= ~X86_CR4_VMXE;
2376 if ((pCtx->cr4 & mask) != mask)
2377 return false;
2378
2379 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2380 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2381 if ((pCtx->cr4 & mask) != 0)
2382 return false;
2383
2384 pVCpu->hm.s.fActive = true;
2385 return true;
2386 }
2387
2388 return false;
2389}
2390
2391
2392/**
2393 * Checks if we need to reschedule due to VMM device heap changes.
2394 *
2395 * @returns true if a reschedule is required, otherwise false.
2396 * @param pVM Pointer to the VM.
2397 * @param pCtx VM execution context.
2398 */
2399VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2400{
2401 /*
2402 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2403 * when the unrestricted guest execution feature is missing (VT-x only).
2404 */
2405#ifdef VBOX_WITH_OLD_VTX_CODE
2406 if ( pVM->hm.s.vmx.fEnabled
2407 && !pVM->hm.s.vmx.fUnrestrictedGuest
2408 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2409 && !PDMVmmDevHeapIsEnabled(pVM)
2410 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2411 return true;
2412#else
2413 if ( pVM->hm.s.vmx.fEnabled
2414 && !pVM->hm.s.vmx.fUnrestrictedGuest
2415 && CPUMIsGuestInRealModeEx(pCtx)
2416 && !PDMVmmDevHeapIsEnabled(pVM))
2417 return true;
2418#endif
2419
2420 return false;
2421}
2422
2423
2424/**
2425 * Notification from EM about a rescheduling into hardware assisted execution
2426 * mode.
2427 *
2428 * @param pVCpu Pointer to the current VMCPU.
2429 */
2430VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2431{
2432 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2433}
2434
2435
2436/**
2437 * Notification from EM about returning from instruction emulation (REM / EM).
2438 *
2439 * @param pVCpu Pointer to the VMCPU.
2440 */
2441VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2442{
2443 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2444}
2445
2446
2447/**
2448 * Checks if we are currently using hardware accelerated raw mode.
2449 *
2450 * @returns true if hardware acceleration is being used, otherwise false.
2451 * @param pVCpu Pointer to the VMCPU.
2452 */
2453VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2454{
2455 return pVCpu->hm.s.fActive;
2456}
2457
2458
2459/**
2460 * Checks if we are currently using nested paging.
2461 *
2462 * @returns true if nested paging is being used, otherwise false.
2463 * @param pUVM The user mode VM handle.
2464 */
2465VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2466{
2467 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2468 PVM pVM = pUVM->pVM;
2469 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2470 return HMIsEnabled(pVM);
2471}
2472
2473
2474/**
2475 * Checks if we are currently using nested paging.
2476 *
2477 * @returns true if nested paging is being used, otherwise false.
2478 * @param pUVM The user mode VM handle.
2479 */
2480VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2481{
2482 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2483 PVM pVM = pUVM->pVM;
2484 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2485 return pVM->hm.s.fNestedPaging;
2486}
2487
2488
2489/**
2490 * Checks if we are currently using VPID in VT-x mode.
2491 *
2492 * @returns true if VPID is being used, otherwise false.
2493 * @param pUVM The user mode VM handle.
2494 */
2495VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2496{
2497 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2498 PVM pVM = pUVM->pVM;
2499 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2500 return pVM->hm.s.vmx.fVpid;
2501}
2502
2503
2504/**
2505 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2506 *
2507 * @returns true if an internal event is pending, otherwise false.
2508 * @param pVM Pointer to the VM.
2509 */
2510VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2511{
2512 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2513}
2514
2515
2516/**
2517 * Checks if the VMX-preemption timer is being used.
2518 *
2519 * @returns true if the VMX-preemption timer is being used, otherwise false.
2520 * @param pVM Pointer to the VM.
2521 */
2522VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2523{
2524 return HMIsEnabled(pVM)
2525 && pVM->hm.s.vmx.fEnabled
2526 && pVM->hm.s.vmx.fUsePreemptTimer;
2527}
2528
2529
2530/**
2531 * Restart an I/O instruction that was refused in ring-0
2532 *
2533 * @returns Strict VBox status code. Informational status codes other than the one documented
2534 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2535 * @retval VINF_SUCCESS Success.
2536 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2537 * status code must be passed on to EM.
2538 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2539 *
2540 * @param pVM Pointer to the VM.
2541 * @param pVCpu Pointer to the VMCPU.
2542 * @param pCtx Pointer to the guest CPU context.
2543 */
2544VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2545{
2546 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2547
2548 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2549
2550 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2551 || enmType == HMPENDINGIO_INVALID)
2552 return VERR_NOT_FOUND;
2553
2554 VBOXSTRICTRC rcStrict;
2555 switch (enmType)
2556 {
2557 case HMPENDINGIO_PORT_READ:
2558 {
2559 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2560 uint32_t u32Val = 0;
2561
2562 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2563 &u32Val,
2564 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2565 if (IOM_SUCCESS(rcStrict))
2566 {
2567 /* Write back to the EAX register. */
2568 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2569 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2570 }
2571 break;
2572 }
2573
2574 case HMPENDINGIO_PORT_WRITE:
2575 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2576 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2577 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2578 if (IOM_SUCCESS(rcStrict))
2579 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2580 break;
2581
2582 default:
2583 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2584 }
2585
2586 return rcStrict;
2587}
2588
2589
2590/**
2591 * Check fatal VT-x/AMD-V error and produce some meaningful
2592 * log release message.
2593 *
2594 * @param pVM Pointer to the VM.
2595 * @param iStatusCode VBox status code.
2596 */
2597VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2598{
2599 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2600 {
2601 switch (iStatusCode)
2602 {
2603 case VERR_VMX_INVALID_VMCS_FIELD:
2604 break;
2605
2606 case VERR_VMX_INVALID_VMCS_PTR:
2607 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2608 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2609 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2610 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2611 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2612 break;
2613
2614 case VERR_VMX_UNABLE_TO_START_VM:
2615 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2616 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2617 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2618 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2619 {
2620 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2621 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2622 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2623 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2624 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2625 LogRel(("HM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2626#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2627 LogRel(("HM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2628 LogRel(("HM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2629 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2630#endif
2631 }
2632 /** @todo Log VM-entry event injection control fields
2633 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2634 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2635 break;
2636
2637 case VERR_VMX_INVALID_VMXON_PTR:
2638 break;
2639 }
2640 }
2641
2642 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2643 {
2644 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2645 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2646 }
2647}
2648
2649
2650/**
2651 * Execute state save operation.
2652 *
2653 * @returns VBox status code.
2654 * @param pVM Pointer to the VM.
2655 * @param pSSM SSM operation handle.
2656 */
2657static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2658{
2659 int rc;
2660
2661 Log(("hmR3Save:\n"));
2662
2663 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2664 {
2665 /*
2666 * Save the basic bits - fortunately all the other things can be resynced on load.
2667 */
2668 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2669 AssertRCReturn(rc, rc);
2670 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2671 AssertRCReturn(rc, rc);
2672 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2673 AssertRCReturn(rc, rc);
2674
2675 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2676 AssertRCReturn(rc, rc);
2677 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2678 AssertRCReturn(rc, rc);
2679 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2680 AssertRCReturn(rc, rc);
2681 }
2682#ifdef VBOX_HM_WITH_GUEST_PATCHING
2683 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2684 AssertRCReturn(rc, rc);
2685 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2686 AssertRCReturn(rc, rc);
2687 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2688 AssertRCReturn(rc, rc);
2689
2690 /* Store all the guest patch records too. */
2691 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2692 AssertRCReturn(rc, rc);
2693
2694 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2695 {
2696 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2697
2698 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2699 AssertRCReturn(rc, rc);
2700
2701 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2702 AssertRCReturn(rc, rc);
2703
2704 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2705 AssertRCReturn(rc, rc);
2706
2707 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2708 AssertRCReturn(rc, rc);
2709
2710 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2711 AssertRCReturn(rc, rc);
2712
2713 AssertCompileSize(HMTPRINSTR, 4);
2714 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2715 AssertRCReturn(rc, rc);
2716
2717 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2718 AssertRCReturn(rc, rc);
2719
2720 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2721 AssertRCReturn(rc, rc);
2722
2723 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2724 AssertRCReturn(rc, rc);
2725
2726 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2727 AssertRCReturn(rc, rc);
2728 }
2729#endif
2730 return VINF_SUCCESS;
2731}
2732
2733
2734/**
2735 * Execute state load operation.
2736 *
2737 * @returns VBox status code.
2738 * @param pVM Pointer to the VM.
2739 * @param pSSM SSM operation handle.
2740 * @param uVersion Data layout version.
2741 * @param uPass The data pass.
2742 */
2743static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2744{
2745 int rc;
2746
2747 Log(("hmR3Load:\n"));
2748 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2749
2750 /*
2751 * Validate version.
2752 */
2753 if ( uVersion != HM_SSM_VERSION
2754 && uVersion != HM_SSM_VERSION_NO_PATCHING
2755 && uVersion != HM_SSM_VERSION_2_0_X)
2756 {
2757 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2758 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2759 }
2760 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2761 {
2762 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2763 AssertRCReturn(rc, rc);
2764 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2765 AssertRCReturn(rc, rc);
2766 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2767 AssertRCReturn(rc, rc);
2768
2769 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2770 {
2771 uint32_t val;
2772
2773 rc = SSMR3GetU32(pSSM, &val);
2774 AssertRCReturn(rc, rc);
2775 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2776
2777 rc = SSMR3GetU32(pSSM, &val);
2778 AssertRCReturn(rc, rc);
2779 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2780
2781 rc = SSMR3GetU32(pSSM, &val);
2782 AssertRCReturn(rc, rc);
2783 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2784 }
2785 }
2786#ifdef VBOX_HM_WITH_GUEST_PATCHING
2787 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2788 {
2789 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2790 AssertRCReturn(rc, rc);
2791 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2792 AssertRCReturn(rc, rc);
2793 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2794 AssertRCReturn(rc, rc);
2795
2796 /* Fetch all TPR patch records. */
2797 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2798 AssertRCReturn(rc, rc);
2799
2800 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2801 {
2802 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2803
2804 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2805 AssertRCReturn(rc, rc);
2806
2807 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2808 AssertRCReturn(rc, rc);
2809
2810 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2811 AssertRCReturn(rc, rc);
2812
2813 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2814 AssertRCReturn(rc, rc);
2815
2816 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2817 AssertRCReturn(rc, rc);
2818
2819 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2820 AssertRCReturn(rc, rc);
2821
2822 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2823 pVM->hm.s.fTPRPatchingActive = true;
2824
2825 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2826
2827 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2828 AssertRCReturn(rc, rc);
2829
2830 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2831 AssertRCReturn(rc, rc);
2832
2833 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2834 AssertRCReturn(rc, rc);
2835
2836 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2837 AssertRCReturn(rc, rc);
2838
2839 Log(("hmR3Load: patch %d\n", i));
2840 Log(("Key = %x\n", pPatch->Core.Key));
2841 Log(("cbOp = %d\n", pPatch->cbOp));
2842 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2843 Log(("type = %d\n", pPatch->enmType));
2844 Log(("srcop = %d\n", pPatch->uSrcOperand));
2845 Log(("dstop = %d\n", pPatch->uDstOperand));
2846 Log(("cFaults = %d\n", pPatch->cFaults));
2847 Log(("target = %x\n", pPatch->pJumpTarget));
2848 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2849 AssertRC(rc);
2850 }
2851 }
2852#endif
2853
2854 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2855 if (HMIsEnabled(pVM))
2856 {
2857 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2858 {
2859 PVMCPU pVCpu = &pVM->aCpus[i];
2860
2861 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2862 }
2863 }
2864 return VINF_SUCCESS;
2865}
2866
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