VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 44399

Last change on this file since 44399 was 44399, checked in by vboxsync, 12 years ago

DBGF,DBGC,++: PVM -> PUVM. Some refactoring and cleanup as well.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 137.7 KB
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1/* $Id: HM.cpp 44399 2013-01-27 21:12:53Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/vmm/uvm.h>
42#include <VBox/err.h>
43#include <VBox/param.h>
44
45#include <iprt/assert.h>
46#include <VBox/log.h>
47#include <iprt/asm.h>
48#include <iprt/asm-amd64-x86.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL()
119};
120/** Exit reason descriptions for AMD-V, used to describe statistics. */
121static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
122{
123 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
124 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
125 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
126 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
127 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
128 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
129 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
130 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
131 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
132 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
133 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
134 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
135 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
136 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
137 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
138 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
155 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
156 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
157 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
158 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
159 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
160 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
161 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
162 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
163 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
164 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
165 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
166 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
167 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
168 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
169 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
170 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
219 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
221 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
222 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
223 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
224 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
225 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
226 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
227 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
232 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
233 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
234 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
235 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
236 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
237 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
238 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
239 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
240 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
241 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
242 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
243 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
245 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
246 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
247 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
248 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
249 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
250 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
251 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
252 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
253 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
254 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
255 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
256 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
257 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
258 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
259 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
260 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
261 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
262 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
263 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
264 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
265 EXIT_REASON_NIL()
266};
267# undef EXIT_REASON
268# undef EXIT_REASON_NIL
269#endif /* VBOX_WITH_STATISTICS */
270
271/*******************************************************************************
272* Internal Functions *
273*******************************************************************************/
274static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
275static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
276static int hmR3InitCPU(PVM pVM);
277static int hmR3InitFinalizeR0(PVM pVM);
278static int hmR3TermCPU(PVM pVM);
279
280
281/**
282 * Initializes the HM.
283 *
284 * @returns VBox status code.
285 * @param pVM Pointer to the VM.
286 */
287VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
288{
289 LogFlow(("HMR3Init\n"));
290
291 /*
292 * Assert alignment and sizes.
293 */
294 AssertCompileMemberAlignment(VM, hm.s, 32);
295 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
296
297 /* Some structure checks. */
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
301
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
306 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
307 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
308 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
311 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
312 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
313
314 /*
315 * Register the saved state data unit.
316 */
317 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
318 NULL, NULL, NULL,
319 NULL, hmR3Save, NULL,
320 NULL, hmR3Load, NULL);
321 if (RT_FAILURE(rc))
322 return rc;
323
324 /* Misc initialisation. */
325 pVM->hm.s.vmx.fSupported = false;
326 pVM->hm.s.svm.fSupported = false;
327 pVM->hm.s.vmx.fEnabled = false;
328 pVM->hm.s.svm.fEnabled = false;
329
330 pVM->hm.s.fNestedPaging = false;
331 pVM->hm.s.fLargePages = false;
332
333 /* Disabled by default. */
334 pVM->fHMEnabled = false;
335
336 /*
337 * Check CFGM options.
338 */
339 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
340 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
341 /* Nested paging: disabled by default. */
342 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
343 AssertRC(rc);
344
345 /* Large pages: disabled by default. */
346 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
347 AssertRC(rc);
348
349 /* VT-x VPID: disabled by default. */
350 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
351 AssertRC(rc);
352
353 /* HM support must be explicitely enabled in the configuration file. */
354 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
355 AssertRC(rc);
356
357 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
358 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
359 AssertRC(rc);
360
361#ifdef RT_OS_DARWIN
362 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
363#else
364 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
365#endif
366 {
367 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
368 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
369 return VERR_HM_CONFIG_MISMATCH;
370 }
371
372 if (VMMIsHwVirtExtForced(pVM))
373 pVM->fHMEnabled = true;
374
375#if HC_ARCH_BITS == 32
376 /*
377 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
378 * (To use the default, don't set 64bitEnabled in CFGM.)
379 */
380 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
381 AssertLogRelRCReturn(rc, rc);
382 if (pVM->hm.s.fAllow64BitGuests)
383 {
384# ifdef RT_OS_DARWIN
385 if (!VMMIsHwVirtExtForced(pVM))
386# else
387 if (!pVM->hm.s.fAllowed)
388# endif
389 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
390 }
391#else
392 /*
393 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
394 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
395 */
396 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
397 AssertLogRelRCReturn(rc, rc);
398#endif
399
400
401 /*
402 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
403 * or local init each time we wish to execute guest code.
404 *
405 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
406 */
407 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
408#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
409 false
410#else
411 true
412#endif
413 );
414
415 /* Max number of resume loops. */
416 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
417 AssertRC(rc);
418
419 return rc;
420}
421
422
423/**
424 * Initializes the per-VCPU HM.
425 *
426 * @returns VBox status code.
427 * @param pVM Pointer to the VM.
428 */
429static int hmR3InitCPU(PVM pVM)
430{
431 LogFlow(("HMR3InitCPU\n"));
432
433 for (VMCPUID i = 0; i < pVM->cCpus; i++)
434 {
435 PVMCPU pVCpu = &pVM->aCpus[i];
436
437 pVCpu->hm.s.fActive = false;
438 }
439
440#ifdef VBOX_WITH_STATISTICS
441 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
442 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
443 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
444 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
445
446 /*
447 * Statistics.
448 */
449 for (VMCPUID i = 0; i < pVM->cCpus; i++)
450 {
451 PVMCPU pVCpu = &pVM->aCpus[i];
452 int rc;
453
454 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
455 "Profiling of RTMpPokeCpu",
456 "/PROF/HM/CPU%d/Poke", i);
457 AssertRC(rc);
458 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
459 "Profiling of poke wait",
460 "/PROF/HM/CPU%d/PokeWait", i);
461 AssertRC(rc);
462 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
463 "Profiling of poke wait when RTMpPokeCpu fails",
464 "/PROF/HM/CPU%d/PokeWaitFailed", i);
465 AssertRC(rc);
466 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
467 "Profiling of VMXR0RunGuestCode entry",
468 "/PROF/HM/CPU%d/SwitchToGC", i);
469 AssertRC(rc);
470 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
471 "Profiling of VMXR0RunGuestCode exit part 1",
472 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
473 AssertRC(rc);
474 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
475 "Profiling of VMXR0RunGuestCode exit part 2",
476 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
477 AssertRC(rc);
478# if 1 /* temporary for tracking down darwin holdup. */
479 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
480 "Temporary - I/O",
481 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
482 AssertRC(rc);
483 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
484 "Temporary - CRx RWs",
485 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
486 AssertRC(rc);
487 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
488 "Temporary - Exceptions",
489 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
490 AssertRC(rc);
491# endif
492 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
493 "Profiling of vmlaunch",
494 "/PROF/HM/CPU%d/InGC", i);
495 AssertRC(rc);
496
497# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
498 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
499 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
500 "/PROF/HM/CPU%d/Switcher3264", i);
501 AssertRC(rc);
502# endif
503
504# define HM_REG_COUNTER(a, b) \
505 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
506 AssertRC(rc);
507
508 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
509 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
510 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
511 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
512 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
513 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
514 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
515 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
516 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
517 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
518 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
519 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
520 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
521 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
522 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
523 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
524 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
525 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
526 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
527 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
528 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
529 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
530 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptPending, "/HM/CPU%d/Exit/PreemptPending");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
559 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
560
561 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchToR3, "/HM/CPU%d/Switch/ToR3");
563
564 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
567
568 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
571 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
572 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbCRxChange, "/HM/CPU%d/Flush/TLB/CRx");
574 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageInvlpg, "/HM/CPU%d/Flush/Page/Invlpg");
575 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
578 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
579 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpga, "/HM/CPU%d/Flush/TLB/PhysInvl");
580 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
581 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
582
583 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
584 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
585 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
586
587 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
588 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
589 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
590
591 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
592 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
593
594#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
595 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
596 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
597#endif
598
599 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
600 {
601 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
602 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
603 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
604 AssertRC(rc);
605 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
606 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
607 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
608 AssertRC(rc);
609 }
610
611#undef HM_REG_COUNTER
612
613 pVCpu->hm.s.paStatExitReason = NULL;
614
615 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
616 (void **)&pVCpu->hm.s.paStatExitReason);
617 AssertRC(rc);
618 if (RT_SUCCESS(rc))
619 {
620 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
621 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
622 {
623 if (papszDesc[j])
624 {
625 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
626 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
627 AssertRC(rc);
628 }
629 }
630 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
631 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
632 AssertRC(rc);
633 }
634 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
635# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
636 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
637# else
638 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
639# endif
640
641 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
642 AssertRCReturn(rc, rc);
643 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
644# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
645 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
646# else
647 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
648# endif
649 for (unsigned j = 0; j < 255; j++)
650 {
651 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
652 "Forwarded interrupts.",
653 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
654 }
655
656 }
657#endif /* VBOX_WITH_STATISTICS */
658
659#ifdef VBOX_WITH_CRASHDUMP_MAGIC
660 /* Magic marker for searching in crash dumps. */
661 for (VMCPUID i = 0; i < pVM->cCpus; i++)
662 {
663 PVMCPU pVCpu = &pVM->aCpus[i];
664
665 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
666 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
667 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
668 }
669#endif
670 return VINF_SUCCESS;
671}
672
673
674/**
675 * Called when a init phase has completed.
676 *
677 * @returns VBox status code.
678 * @param pVM The VM.
679 * @param enmWhat The phase that completed.
680 */
681VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
682{
683 switch (enmWhat)
684 {
685 case VMINITCOMPLETED_RING3:
686 return hmR3InitCPU(pVM);
687 case VMINITCOMPLETED_RING0:
688 return hmR3InitFinalizeR0(pVM);
689 default:
690 return VINF_SUCCESS;
691 }
692}
693
694
695/**
696 * Turns off normal raw mode features.
697 *
698 * @param pVM Pointer to the VM.
699 */
700static void hmR3DisableRawMode(PVM pVM)
701{
702 /* Disable PATM & CSAM. */
703 PATMR3AllowPatching(pVM->pUVM, false);
704 CSAMDisableScanning(pVM);
705
706 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
707 SELMR3DisableMonitoring(pVM);
708 TRPMR3DisableMonitoring(pVM);
709
710 /* Disable the switcher code (safety precaution). */
711 VMMR3DisableSwitcher(pVM);
712
713 /* Disable mapping of the hypervisor into the shadow page table. */
714 PGMR3MappingsDisable(pVM);
715
716 /* Disable the switcher */
717 VMMR3DisableSwitcher(pVM);
718
719 /* Reinit the paging mode to force the new shadow mode. */
720 for (VMCPUID i = 0; i < pVM->cCpus; i++)
721 {
722 PVMCPU pVCpu = &pVM->aCpus[i];
723
724 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
725 }
726}
727
728
729/**
730 * Initialize VT-x or AMD-V.
731 *
732 * @returns VBox status code.
733 * @param pVM Pointer to the VM.
734 */
735static int hmR3InitFinalizeR0(PVM pVM)
736{
737 int rc;
738
739 /*
740 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
741 * is already using AMD-V.
742 */
743 if ( !pVM->hm.s.vmx.fSupported
744 && !pVM->hm.s.svm.fSupported
745 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
746 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
747 {
748 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
749 pVM->hm.s.svm.fSupported = true;
750 pVM->hm.s.svm.fIgnoreInUseError = true;
751 }
752 else
753 if ( !pVM->hm.s.vmx.fSupported
754 && !pVM->hm.s.svm.fSupported)
755 {
756 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
757 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
758
759 if (VMMIsHwVirtExtForced(pVM))
760 {
761 switch (pVM->hm.s.lLastError)
762 {
763 case VERR_VMX_NO_VMX:
764 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
765 case VERR_VMX_IN_VMX_ROOT_MODE:
766 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
767 case VERR_SVM_IN_USE:
768 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
769 case VERR_SVM_NO_SVM:
770 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
771 case VERR_SVM_DISABLED:
772 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
773 default:
774 return pVM->hm.s.lLastError;
775 }
776 }
777 return VINF_SUCCESS;
778 }
779
780 if (pVM->hm.s.vmx.fSupported)
781 {
782 rc = SUPR3QueryVTxSupported();
783 if (RT_FAILURE(rc))
784 {
785#ifdef RT_OS_LINUX
786 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
787#else
788 LogRel(("HM: The host kernel does not support VT-x!\n"));
789#endif
790 if ( pVM->cCpus > 1
791 || VMMIsHwVirtExtForced(pVM))
792 return rc;
793
794 /* silently fall back to raw mode */
795 return VINF_SUCCESS;
796 }
797 }
798
799 if (!pVM->hm.s.fAllowed)
800 return VINF_SUCCESS; /* nothing to do */
801
802 /* Enable VT-x or AMD-V on all host CPUs. */
803 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
804 if (RT_FAILURE(rc))
805 {
806 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
807 return rc;
808 }
809 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
810
811 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
812 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
813 if (!pVM->hm.s.fHasIoApic)
814 {
815 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
816 pVM->hm.s.fTRPPatchingAllowed = false;
817 }
818
819 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
820 if (pVM->hm.s.vmx.fSupported)
821 {
822 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
823
824 if ( pVM->hm.s.fInitialized == false
825 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
826 {
827 uint64_t val;
828 RTGCPHYS GCPhys = 0;
829
830 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
831 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
832 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
833 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
834 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
835 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
836 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
837 LogRel(("HM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
838
839 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
840 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
841 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
842 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
843 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
844 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
845 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
846 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
847 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
848 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
849 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
850 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
851 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
852 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
853 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
854 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
855 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
856 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
857 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
858
859 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
860 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT)
862 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
864 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
866 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
867 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
868 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
869 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
870 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
872 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
874 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
875 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
876 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
877 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
878 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
879 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
880 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
881 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
882 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
884 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
885 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
886 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
887 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
888 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
889 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
890 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
891 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
892 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
893 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
894 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
895 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
896 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
898 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
899 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
900 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
901 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
902 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
903
904 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
905 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT)
906 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT *must* be set\n"));
907 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
908 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
909 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
910 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
911 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
912 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
913 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
914 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
915 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
916 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
917 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
918 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
919 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
920 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
921 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
922 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
923 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
924 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
925 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
926 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
927 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
928 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
929 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
930 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
931 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
932 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
933 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
934 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
935 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
936 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
937 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
938 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
939 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
940 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
941 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
942 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
943 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
944 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
945 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
946 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
947
948 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
949 {
950 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
951 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
952 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
953 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
954 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
955 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
956 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
957 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT\n"));
958 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
959 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP\n"));
960 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
961 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
962 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
963 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
964 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
965 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
966 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
967 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
968 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
969 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
970
971 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
972 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
973 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
974 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
975 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT *must* be set\n"));
976 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
977 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP *must* be set\n"));
978 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
979 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
980 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
981 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
982 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
983 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
984 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
985 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
986 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
987 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
988 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
989 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
990 }
991
992 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
993 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
994 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
995 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
996 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST)
997 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST\n"));
998 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
999 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
1000 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
1001 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
1002 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
1003 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
1004 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
1005 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
1006 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1007 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
1008 val = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
1009 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
1010 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
1011 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST)
1012 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST *must* be set\n"));
1013 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
1014 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
1015 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
1016 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
1017 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
1018 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
1019 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
1020 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
1021 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1022 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
1023
1024 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
1025 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1026 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1027 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
1028 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE)
1029 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE\n"));
1030 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT)
1031 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT\n"));
1032 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1033 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
1034 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1035 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
1036 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1037 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
1038 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1039 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
1040 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1041 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
1042 val = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1043 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1044 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
1045 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE)
1046 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE *must* be set\n"));
1047 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT)
1048 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT *must* be set\n"));
1049 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1050 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
1051 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1052 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
1053 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1054 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
1055 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1056 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
1057 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1058 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
1059
1060 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
1061 {
1062 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", pVM->hm.s.vmx.msr.vmx_ept_vpid_caps));
1063
1064 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY)
1065 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY\n"));
1066 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY)
1067 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY\n"));
1068 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY)
1069 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY\n"));
1070 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS)
1071 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS\n"));
1072 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS)
1073 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS\n"));
1074 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS)
1075 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS\n"));
1076 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS)
1077 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS\n"));
1078 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS)
1079 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS\n"));
1080 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC)
1081 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC\n"));
1082 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC)
1083 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC\n"));
1084 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT)
1085 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT\n"));
1086 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP)
1087 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP\n"));
1088 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)
1089 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB\n"));
1090 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS)
1091 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS\n"));
1092 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS)
1093 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS\n"));
1094 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS)
1095 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS\n"));
1096 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS)
1097 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS\n"));
1098 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
1099 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT\n"));
1100 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
1101 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT\n"));
1102 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1103 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS\n"));
1104 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
1105 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID\n"));
1106 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1107 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR\n"));
1108 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
1109 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT\n"));
1110 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
1111 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS\n"));
1112 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1113 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1114 }
1115
1116 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1117 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1118 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1119 else
1120 {
1121 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n",
1122 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1123 }
1124 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1125 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1126 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1127 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1128
1129 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1130 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1131 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1132 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1133 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1134
1135 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1136
1137 /* Paranoia */
1138 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1139
1140 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1141 {
1142 LogRel(("HM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1143 LogRel(("HM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
1144 }
1145
1146 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1147 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1148
1149 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1150 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1151
1152 /*
1153 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1154 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1155 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1156 */
1157 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1158 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1159 {
1160 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1161 }
1162
1163 /* Unrestricted guest execution relies on EPT. */
1164 if ( pVM->hm.s.fNestedPaging
1165 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1166 {
1167 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1168 }
1169
1170 /* Only try once. */
1171 pVM->hm.s.fInitialized = true;
1172
1173 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1174 {
1175 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1176 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1177 if (RT_SUCCESS(rc))
1178 {
1179 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1180 /* Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode" esp. Figure 20-5.*/
1181 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1182 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1183 /* Bit set to 0 means software interrupts are redirected to the 8086 program interrupt handler rather than
1184 switching to protected-mode handler. */
1185 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1186 /* Allow all port IO, so that port IO instructions do not cause exceptions and would instead
1187 cause a VM-exit (based on VT-x's IO bitmap which we currently configure to always cause an exit). */
1188 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1189 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1190
1191 /*
1192 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1193 * real and protected mode without paging with EPT.
1194 */
1195 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1196 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1197 {
1198 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1199 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1200 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1201 | X86_PDE4M_G;
1202 }
1203
1204 /* We convert it here every time as pci regions could be reconfigured. */
1205 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1206 AssertRC(rc);
1207 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1208
1209 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1210 AssertRC(rc);
1211 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1212 }
1213 else
1214 {
1215 /** @todo This cannot possibly work, there are other places which assumes
1216 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1217 * a failure case. */
1218 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1219 pVM->hm.s.vmx.pRealModeTSS = NULL;
1220 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1221 }
1222 }
1223
1224 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1225 AssertRC(rc);
1226 if (rc == VINF_SUCCESS)
1227 {
1228 pVM->fHMEnabled = true;
1229 pVM->hm.s.vmx.fEnabled = true;
1230 hmR3DisableRawMode(pVM);
1231
1232 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1233#ifdef VBOX_ENABLE_64_BITS_GUESTS
1234 if (pVM->hm.s.fAllow64BitGuests)
1235 {
1236 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1237 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1238 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1239 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1240 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1241 }
1242 else
1243 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1244 /* Todo: this needs to be fixed properly!! */
1245 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1246 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1247 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1248
1249 LogRel((pVM->hm.s.fAllow64BitGuests
1250 ? "HM: 32-bit and 64-bit guests supported.\n"
1251 : "HM: 32-bit guests supported.\n"));
1252#else
1253 LogRel(("HM: 32-bit guests supported.\n"));
1254#endif
1255 LogRel(("HM: VMX enabled!\n"));
1256 if (pVM->hm.s.fNestedPaging)
1257 {
1258 LogRel(("HM: Enabled nested paging\n"));
1259 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1260 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1261 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1262 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1263 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1264 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1265 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1266 else
1267 LogRel(("HM: enmFlushEpt = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1268
1269 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1270 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1271
1272#if HC_ARCH_BITS == 64
1273 if (pVM->hm.s.fLargePages)
1274 {
1275 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1276 PGMSetLargePageUsage(pVM, true);
1277 LogRel(("HM: Large page support enabled!\n"));
1278 }
1279#endif
1280 }
1281 else
1282 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1283
1284 if (pVM->hm.s.vmx.fVpid)
1285 {
1286 LogRel(("HM: Enabled VPID\n"));
1287 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1288 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1289 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1290 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1291 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1292 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1293 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1294 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1295 else
1296 LogRel(("HM: enmFlushVpid = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1297 }
1298 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1299 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1300
1301 /* TPR patching status logging. */
1302 if (pVM->hm.s.fTRPPatchingAllowed)
1303 {
1304 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1305 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1306 {
1307 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1308 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1309 }
1310 else
1311 {
1312 uint32_t u32Eax, u32Dummy;
1313
1314 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1315 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1316 if ( u32Eax < 0x80000001
1317 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1318 {
1319 pVM->hm.s.fTRPPatchingAllowed = false;
1320 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1321 }
1322 }
1323 }
1324 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1325
1326 /*
1327 * Check for preemption timer config override and log the state of it.
1328 */
1329 if (pVM->hm.s.vmx.fUsePreemptTimer)
1330 {
1331 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1332 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1333 AssertLogRelRC(rc2);
1334 }
1335 if (pVM->hm.s.vmx.fUsePreemptTimer)
1336 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1337 }
1338 else
1339 {
1340 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1341 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1342 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1343 pVM->fHMEnabled = false;
1344 }
1345 }
1346 }
1347 else
1348 if (pVM->hm.s.svm.fSupported)
1349 {
1350 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1351
1352 if (pVM->hm.s.fInitialized == false)
1353 {
1354 /* Erratum 170 which requires a forced TLB flush for each world switch:
1355 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1356 *
1357 * All BH-G1/2 and DH-G1/2 models include a fix:
1358 * Athlon X2: 0x6b 1/2
1359 * 0x68 1/2
1360 * Athlon 64: 0x7f 1
1361 * 0x6f 2
1362 * Sempron: 0x7f 1/2
1363 * 0x6f 2
1364 * 0x6c 2
1365 * 0x7c 2
1366 * Turion 64: 0x68 2
1367 *
1368 */
1369 uint32_t u32Dummy;
1370 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1371 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1372 u32BaseFamily= (u32Version >> 8) & 0xf;
1373 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1374 u32Model = ((u32Version >> 4) & 0xf);
1375 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1376 u32Stepping = u32Version & 0xf;
1377 if ( u32Family == 0xf
1378 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1379 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1380 {
1381 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1382 }
1383
1384 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1385 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1386 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1387 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1388 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1389 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1390 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1391 {
1392#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1393 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1394 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1395 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1396 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1397 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1398 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1399 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1400 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1401 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1402 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1403 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1404#undef FLAG_NAME
1405 };
1406 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1407 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1408 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1409 {
1410 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1411 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1412 }
1413 if (fSvmFeatures)
1414 for (unsigned iBit = 0; iBit < 32; iBit++)
1415 if (RT_BIT_32(iBit) & fSvmFeatures)
1416 LogRel(("HM: Reserved bit %u\n", iBit));
1417
1418 /* Only try once. */
1419 pVM->hm.s.fInitialized = true;
1420
1421 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1422 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1423
1424 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1425 AssertRC(rc);
1426 if (rc == VINF_SUCCESS)
1427 {
1428 pVM->fHMEnabled = true;
1429 pVM->hm.s.svm.fEnabled = true;
1430
1431 if (pVM->hm.s.fNestedPaging)
1432 {
1433 LogRel(("HM: Enabled nested paging\n"));
1434#if HC_ARCH_BITS == 64
1435 if (pVM->hm.s.fLargePages)
1436 {
1437 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1438 PGMSetLargePageUsage(pVM, true);
1439 LogRel(("HM: Large page support enabled!\n"));
1440 }
1441#endif
1442 }
1443
1444 hmR3DisableRawMode(pVM);
1445 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1446 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1447#ifdef VBOX_ENABLE_64_BITS_GUESTS
1448 if (pVM->hm.s.fAllow64BitGuests)
1449 {
1450 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1451 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1452 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1453 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1454 }
1455 else
1456 /* Turn on NXE if PAE has been enabled. */
1457 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1458 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1459#endif
1460
1461 LogRel((pVM->hm.s.fAllow64BitGuests
1462 ? "HM: 32-bit and 64-bit guest supported.\n"
1463 : "HM: 32-bit guest supported.\n"));
1464
1465 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1466 }
1467 else
1468 {
1469 pVM->fHMEnabled = false;
1470 }
1471 }
1472 }
1473 if (pVM->fHMEnabled)
1474 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1475 RTLogRelSetBuffering(fOldBuffered);
1476 return VINF_SUCCESS;
1477}
1478
1479
1480/**
1481 * Applies relocations to data and code managed by this
1482 * component. This function will be called at init and
1483 * whenever the VMM need to relocate it self inside the GC.
1484 *
1485 * @param pVM The VM.
1486 */
1487VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1488{
1489 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1490
1491 /* Fetch the current paging mode during the relocate callback during state loading. */
1492 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1493 {
1494 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1495 {
1496 PVMCPU pVCpu = &pVM->aCpus[i];
1497
1498 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1499 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1500 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1501 }
1502 }
1503#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1504 if (pVM->fHMEnabled)
1505 {
1506 int rc;
1507 switch (PGMGetHostMode(pVM))
1508 {
1509 case PGMMODE_32_BIT:
1510 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1511 break;
1512
1513 case PGMMODE_PAE:
1514 case PGMMODE_PAE_NX:
1515 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1516 break;
1517
1518 default:
1519 AssertFailed();
1520 break;
1521 }
1522 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1523 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1524
1525 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1526 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1527
1528 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1529 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1530
1531 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1532 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1533
1534# ifdef DEBUG
1535 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1536 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1537# endif
1538 }
1539#endif
1540 return;
1541}
1542
1543
1544/**
1545 * Checks if hardware accelerated raw mode is allowed.
1546 *
1547 * @returns true if hardware acceleration is allowed, otherwise false.
1548 * @param pVM Pointer to the VM.
1549 */
1550VMMR3_INT_DECL(bool) HMR3IsAllowed(PVM pVM)
1551{
1552 return pVM->hm.s.fAllowed;
1553}
1554
1555
1556/**
1557 * Notification callback which is called whenever there is a chance that a CR3
1558 * value might have changed.
1559 *
1560 * This is called by PGM.
1561 *
1562 * @param pVM Pointer to the VM.
1563 * @param pVCpu Pointer to the VMCPU.
1564 * @param enmShadowMode New shadow paging mode.
1565 * @param enmGuestMode New guest paging mode.
1566 */
1567VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1568{
1569 /* Ignore page mode changes during state loading. */
1570 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1571 return;
1572
1573 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1574
1575 if ( pVM->hm.s.vmx.fEnabled
1576 && pVM->fHMEnabled)
1577 {
1578 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1579 && enmGuestMode >= PGMMODE_PROTECTED)
1580 {
1581 PCPUMCTX pCtx;
1582
1583 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1584
1585 /* After a real mode switch to protected mode we must force
1586 CPL to 0. Our real mode emulation had to set it to 3. */
1587 pCtx->ss.Attr.n.u2Dpl = 0;
1588 }
1589 }
1590
1591 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1592 {
1593 /* Keep track of paging mode changes. */
1594 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1595 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1596
1597 /* Did we miss a change, because all code was executed in the recompiler? */
1598 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1599 {
1600 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1601 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1602 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1603 }
1604 }
1605
1606 /* Reset the contents of the read cache. */
1607 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1608 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1609 pCache->Read.aFieldVal[j] = 0;
1610}
1611
1612
1613/**
1614 * Terminates the HM.
1615 *
1616 * Termination means cleaning up and freeing all resources,
1617 * the VM itself is, at this point, powered off or suspended.
1618 *
1619 * @returns VBox status code.
1620 * @param pVM Pointer to the VM.
1621 */
1622VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1623{
1624 if (pVM->hm.s.vmx.pRealModeTSS)
1625 {
1626 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1627 pVM->hm.s.vmx.pRealModeTSS = 0;
1628 }
1629 hmR3TermCPU(pVM);
1630 return 0;
1631}
1632
1633
1634/**
1635 * Terminates the per-VCPU HM.
1636 *
1637 * @returns VBox status code.
1638 * @param pVM Pointer to the VM.
1639 */
1640static int hmR3TermCPU(PVM pVM)
1641{
1642 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1643 {
1644 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1645
1646#ifdef VBOX_WITH_STATISTICS
1647 if (pVCpu->hm.s.paStatExitReason)
1648 {
1649 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1650 pVCpu->hm.s.paStatExitReason = NULL;
1651 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1652 }
1653 if (pVCpu->hm.s.paStatInjectedIrqs)
1654 {
1655 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1656 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1657 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1658 }
1659#endif
1660
1661#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1662 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1663 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1664 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1665#endif
1666 }
1667 return 0;
1668}
1669
1670
1671/**
1672 * Resets a virtual CPU.
1673 *
1674 * Used by HMR3Reset and CPU hot plugging.
1675 *
1676 * @param pVCpu The CPU to reset.
1677 */
1678VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1679{
1680 /* On first entry we'll sync everything. */
1681 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1682
1683 pVCpu->hm.s.vmx.cr0_mask = 0;
1684 pVCpu->hm.s.vmx.cr4_mask = 0;
1685
1686 pVCpu->hm.s.fActive = false;
1687 pVCpu->hm.s.Event.fPending = false;
1688
1689 /* Reset state information for real-mode emulation in VT-x. */
1690 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1691 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1692 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1693
1694 /* Reset the contents of the read cache. */
1695 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1696 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1697 pCache->Read.aFieldVal[j] = 0;
1698
1699#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1700 /* Magic marker for searching in crash dumps. */
1701 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1702 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1703#endif
1704}
1705
1706
1707/**
1708 * The VM is being reset.
1709 *
1710 * For the HM component this means that any GDT/LDT/TSS monitors
1711 * needs to be removed.
1712 *
1713 * @param pVM Pointer to the VM.
1714 */
1715VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1716{
1717 LogFlow(("HMR3Reset:\n"));
1718
1719 if (pVM->fHMEnabled)
1720 hmR3DisableRawMode(pVM);
1721
1722 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1723 {
1724 PVMCPU pVCpu = &pVM->aCpus[i];
1725
1726 HMR3ResetCpu(pVCpu);
1727 }
1728
1729 /* Clear all patch information. */
1730 pVM->hm.s.pGuestPatchMem = 0;
1731 pVM->hm.s.pFreeGuestPatchMem = 0;
1732 pVM->hm.s.cbGuestPatchMem = 0;
1733 pVM->hm.s.cPatches = 0;
1734 pVM->hm.s.PatchTree = 0;
1735 pVM->hm.s.fTPRPatchingActive = false;
1736 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1737}
1738
1739
1740/**
1741 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1742 *
1743 * @returns VBox strict status code.
1744 * @param pVM Pointer to the VM.
1745 * @param pVCpu The VMCPU for the EMT we're being called on.
1746 * @param pvUser Unused.
1747 */
1748DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1749{
1750 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1751
1752 /* Only execute the handler on the VCPU the original patch request was issued. */
1753 if (pVCpu->idCpu != idCpu)
1754 return VINF_SUCCESS;
1755
1756 Log(("hmR3RemovePatches\n"));
1757 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1758 {
1759 uint8_t abInstr[15];
1760 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1761 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1762 int rc;
1763
1764#ifdef LOG_ENABLED
1765 char szOutput[256];
1766
1767 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1768 szOutput, sizeof(szOutput), NULL);
1769 if (RT_SUCCESS(rc))
1770 Log(("Patched instr: %s\n", szOutput));
1771#endif
1772
1773 /* Check if the instruction is still the same. */
1774 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1775 if (rc != VINF_SUCCESS)
1776 {
1777 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1778 continue; /* swapped out or otherwise removed; skip it. */
1779 }
1780
1781 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1782 {
1783 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1784 continue; /* skip it. */
1785 }
1786
1787 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1788 AssertRC(rc);
1789
1790#ifdef LOG_ENABLED
1791 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1792 szOutput, sizeof(szOutput), NULL);
1793 if (RT_SUCCESS(rc))
1794 Log(("Original instr: %s\n", szOutput));
1795#endif
1796 }
1797 pVM->hm.s.cPatches = 0;
1798 pVM->hm.s.PatchTree = 0;
1799 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1800 pVM->hm.s.fTPRPatchingActive = false;
1801 return VINF_SUCCESS;
1802}
1803
1804
1805/**
1806 * Worker for enabling patching in a VT-x/AMD-V guest.
1807 *
1808 * @returns VBox status code.
1809 * @param pVM Pointer to the VM.
1810 * @param idCpu VCPU to execute hmR3RemovePatches on.
1811 * @param pPatchMem Patch memory range.
1812 * @param cbPatchMem Size of the memory range.
1813 */
1814static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1815{
1816 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1817 AssertRC(rc);
1818
1819 pVM->hm.s.pGuestPatchMem = pPatchMem;
1820 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1821 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1822 return VINF_SUCCESS;
1823}
1824
1825
1826/**
1827 * Enable patching in a VT-x/AMD-V guest
1828 *
1829 * @returns VBox status code.
1830 * @param pVM Pointer to the VM.
1831 * @param pPatchMem Patch memory range.
1832 * @param cbPatchMem Size of the memory range.
1833 */
1834VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1835{
1836 VM_ASSERT_EMT(pVM);
1837 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1838 if (pVM->cCpus > 1)
1839 {
1840 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1841 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1842 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1843 AssertRC(rc);
1844 return rc;
1845 }
1846 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1847}
1848
1849
1850/**
1851 * Disable patching in a VT-x/AMD-V guest.
1852 *
1853 * @returns VBox status code.
1854 * @param pVM Pointer to the VM.
1855 * @param pPatchMem Patch memory range.
1856 * @param cbPatchMem Size of the memory range.
1857 */
1858VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1859{
1860 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1861
1862 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1863 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1864
1865 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1866 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1867 (void *)(uintptr_t)VMMGetCpuId(pVM));
1868 AssertRC(rc);
1869
1870 pVM->hm.s.pGuestPatchMem = 0;
1871 pVM->hm.s.pFreeGuestPatchMem = 0;
1872 pVM->hm.s.cbGuestPatchMem = 0;
1873 pVM->hm.s.fTPRPatchingActive = false;
1874 return VINF_SUCCESS;
1875}
1876
1877
1878/**
1879 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1880 *
1881 * @returns VBox strict status code.
1882 * @param pVM Pointer to the VM.
1883 * @param pVCpu The VMCPU for the EMT we're being called on.
1884 * @param pvUser User specified CPU context.
1885 *
1886 */
1887DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1888{
1889 /*
1890 * Only execute the handler on the VCPU the original patch request was
1891 * issued. (The other CPU(s) might not yet have switched to protected
1892 * mode, nor have the correct memory context.)
1893 */
1894 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1895 if (pVCpu->idCpu != idCpu)
1896 return VINF_SUCCESS;
1897
1898 /*
1899 * We're racing other VCPUs here, so don't try patch the instruction twice
1900 * and make sure there is still room for our patch record.
1901 */
1902 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1903 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1904 if (pPatch)
1905 {
1906 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1907 return VINF_SUCCESS;
1908 }
1909 uint32_t const idx = pVM->hm.s.cPatches;
1910 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1911 {
1912 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1913 return VINF_SUCCESS;
1914 }
1915 pPatch = &pVM->hm.s.aPatches[idx];
1916
1917 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1918
1919 /*
1920 * Disassembler the instruction and get cracking.
1921 */
1922 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1923 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1924 uint32_t cbOp;
1925 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1926 AssertRC(rc);
1927 if ( rc == VINF_SUCCESS
1928 && pDis->pCurInstr->uOpcode == OP_MOV
1929 && cbOp >= 3)
1930 {
1931 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1932
1933 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1934 AssertRC(rc);
1935
1936 pPatch->cbOp = cbOp;
1937
1938 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1939 {
1940 /* write. */
1941 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1942 {
1943 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1944 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1945 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1946 }
1947 else
1948 {
1949 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1950 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1951 pPatch->uSrcOperand = pDis->Param2.uValue;
1952 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1953 }
1954 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1955 AssertRC(rc);
1956
1957 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1958 pPatch->cbNewOp = sizeof(s_abVMMCall);
1959 }
1960 else
1961 {
1962 /*
1963 * TPR Read.
1964 *
1965 * Found:
1966 * mov eax, dword [fffe0080] (5 bytes)
1967 * Check if next instruction is:
1968 * shr eax, 4
1969 */
1970 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1971
1972 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1973 uint8_t const cbOpMmio = cbOp;
1974 uint64_t const uSavedRip = pCtx->rip;
1975
1976 pCtx->rip += cbOp;
1977 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1978 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1979 pCtx->rip = uSavedRip;
1980
1981 if ( rc == VINF_SUCCESS
1982 && pDis->pCurInstr->uOpcode == OP_SHR
1983 && pDis->Param1.fUse == DISUSE_REG_GEN32
1984 && pDis->Param1.Base.idxGenReg == idxMmioReg
1985 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1986 && pDis->Param2.uValue == 4
1987 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1988 {
1989 uint8_t abInstr[15];
1990
1991 /* Replacing two instructions now. */
1992 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1993 AssertRC(rc);
1994
1995 pPatch->cbOp = cbOpMmio + cbOp;
1996
1997 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1998 abInstr[0] = 0xF0;
1999 abInstr[1] = 0x0F;
2000 abInstr[2] = 0x20;
2001 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2002 for (unsigned i = 4; i < pPatch->cbOp; i++)
2003 abInstr[i] = 0x90; /* nop */
2004
2005 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2006 AssertRC(rc);
2007
2008 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2009 pPatch->cbNewOp = pPatch->cbOp;
2010
2011 Log(("Acceptable read/shr candidate!\n"));
2012 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2013 }
2014 else
2015 {
2016 pPatch->enmType = HMTPRINSTR_READ;
2017 pPatch->uDstOperand = idxMmioReg;
2018
2019 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2020 AssertRC(rc);
2021
2022 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2023 pPatch->cbNewOp = sizeof(s_abVMMCall);
2024 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2025 }
2026 }
2027
2028 pPatch->Core.Key = pCtx->eip;
2029 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2030 AssertRC(rc);
2031
2032 pVM->hm.s.cPatches++;
2033 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
2034 return VINF_SUCCESS;
2035 }
2036
2037 /*
2038 * Save invalid patch, so we will not try again.
2039 */
2040 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2041 pPatch->Core.Key = pCtx->eip;
2042 pPatch->enmType = HMTPRINSTR_INVALID;
2043 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2044 AssertRC(rc);
2045 pVM->hm.s.cPatches++;
2046 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2047 return VINF_SUCCESS;
2048}
2049
2050
2051/**
2052 * Callback to patch a TPR instruction (jump to generated code).
2053 *
2054 * @returns VBox strict status code.
2055 * @param pVM Pointer to the VM.
2056 * @param pVCpu The VMCPU for the EMT we're being called on.
2057 * @param pvUser User specified CPU context.
2058 *
2059 */
2060DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2061{
2062 /*
2063 * Only execute the handler on the VCPU the original patch request was
2064 * issued. (The other CPU(s) might not yet have switched to protected
2065 * mode, nor have the correct memory context.)
2066 */
2067 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2068 if (pVCpu->idCpu != idCpu)
2069 return VINF_SUCCESS;
2070
2071 /*
2072 * We're racing other VCPUs here, so don't try patch the instruction twice
2073 * and make sure there is still room for our patch record.
2074 */
2075 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2076 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2077 if (pPatch)
2078 {
2079 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2080 return VINF_SUCCESS;
2081 }
2082 uint32_t const idx = pVM->hm.s.cPatches;
2083 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2084 {
2085 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2086 return VINF_SUCCESS;
2087 }
2088 pPatch = &pVM->hm.s.aPatches[idx];
2089
2090 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2091 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2092
2093 /*
2094 * Disassemble the instruction and get cracking.
2095 */
2096 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2097 uint32_t cbOp;
2098 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2099 AssertRC(rc);
2100 if ( rc == VINF_SUCCESS
2101 && pDis->pCurInstr->uOpcode == OP_MOV
2102 && cbOp >= 5)
2103 {
2104 uint8_t aPatch[64];
2105 uint32_t off = 0;
2106
2107 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2108 AssertRC(rc);
2109
2110 pPatch->cbOp = cbOp;
2111 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2112
2113 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2114 {
2115 /*
2116 * TPR write:
2117 *
2118 * push ECX [51]
2119 * push EDX [52]
2120 * push EAX [50]
2121 * xor EDX,EDX [31 D2]
2122 * mov EAX,EAX [89 C0]
2123 * or
2124 * mov EAX,0000000CCh [B8 CC 00 00 00]
2125 * mov ECX,0C0000082h [B9 82 00 00 C0]
2126 * wrmsr [0F 30]
2127 * pop EAX [58]
2128 * pop EDX [5A]
2129 * pop ECX [59]
2130 * jmp return_address [E9 return_address]
2131 *
2132 */
2133 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2134
2135 aPatch[off++] = 0x51; /* push ecx */
2136 aPatch[off++] = 0x52; /* push edx */
2137 if (!fUsesEax)
2138 aPatch[off++] = 0x50; /* push eax */
2139 aPatch[off++] = 0x31; /* xor edx, edx */
2140 aPatch[off++] = 0xD2;
2141 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2142 {
2143 if (!fUsesEax)
2144 {
2145 aPatch[off++] = 0x89; /* mov eax, src_reg */
2146 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2147 }
2148 }
2149 else
2150 {
2151 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2152 aPatch[off++] = 0xB8; /* mov eax, immediate */
2153 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2154 off += sizeof(uint32_t);
2155 }
2156 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2157 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2158 off += sizeof(uint32_t);
2159
2160 aPatch[off++] = 0x0F; /* wrmsr */
2161 aPatch[off++] = 0x30;
2162 if (!fUsesEax)
2163 aPatch[off++] = 0x58; /* pop eax */
2164 aPatch[off++] = 0x5A; /* pop edx */
2165 aPatch[off++] = 0x59; /* pop ecx */
2166 }
2167 else
2168 {
2169 /*
2170 * TPR read:
2171 *
2172 * push ECX [51]
2173 * push EDX [52]
2174 * push EAX [50]
2175 * mov ECX,0C0000082h [B9 82 00 00 C0]
2176 * rdmsr [0F 32]
2177 * mov EAX,EAX [89 C0]
2178 * pop EAX [58]
2179 * pop EDX [5A]
2180 * pop ECX [59]
2181 * jmp return_address [E9 return_address]
2182 *
2183 */
2184 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2185
2186 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2187 aPatch[off++] = 0x51; /* push ecx */
2188 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2189 aPatch[off++] = 0x52; /* push edx */
2190 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2191 aPatch[off++] = 0x50; /* push eax */
2192
2193 aPatch[off++] = 0x31; /* xor edx, edx */
2194 aPatch[off++] = 0xD2;
2195
2196 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2197 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2198 off += sizeof(uint32_t);
2199
2200 aPatch[off++] = 0x0F; /* rdmsr */
2201 aPatch[off++] = 0x32;
2202
2203 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2204 {
2205 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2206 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2207 }
2208
2209 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2210 aPatch[off++] = 0x58; /* pop eax */
2211 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2212 aPatch[off++] = 0x5A; /* pop edx */
2213 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2214 aPatch[off++] = 0x59; /* pop ecx */
2215 }
2216 aPatch[off++] = 0xE9; /* jmp return_address */
2217 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2218 off += sizeof(RTRCUINTPTR);
2219
2220 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2221 {
2222 /* Write new code to the patch buffer. */
2223 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2224 AssertRC(rc);
2225
2226#ifdef LOG_ENABLED
2227 uint32_t cbCurInstr;
2228 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2229 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2230 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2231 {
2232 char szOutput[256];
2233 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2234 szOutput, sizeof(szOutput), &cbCurInstr);
2235 if (RT_SUCCESS(rc))
2236 Log(("Patch instr %s\n", szOutput));
2237 else
2238 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2239 }
2240#endif
2241
2242 pPatch->aNewOpcode[0] = 0xE9;
2243 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2244
2245 /* Overwrite the TPR instruction with a jump. */
2246 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2247 AssertRC(rc);
2248
2249 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2250
2251 pVM->hm.s.pFreeGuestPatchMem += off;
2252 pPatch->cbNewOp = 5;
2253
2254 pPatch->Core.Key = pCtx->eip;
2255 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2256 AssertRC(rc);
2257
2258 pVM->hm.s.cPatches++;
2259 pVM->hm.s.fTPRPatchingActive = true;
2260 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2261 return VINF_SUCCESS;
2262 }
2263
2264 Log(("Ran out of space in our patch buffer!\n"));
2265 }
2266 else
2267 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2268
2269
2270 /*
2271 * Save invalid patch, so we will not try again.
2272 */
2273 pPatch = &pVM->hm.s.aPatches[idx];
2274 pPatch->Core.Key = pCtx->eip;
2275 pPatch->enmType = HMTPRINSTR_INVALID;
2276 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2277 AssertRC(rc);
2278 pVM->hm.s.cPatches++;
2279 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2280 return VINF_SUCCESS;
2281}
2282
2283
2284/**
2285 * Attempt to patch TPR mmio instructions.
2286 *
2287 * @returns VBox status code.
2288 * @param pVM Pointer to the VM.
2289 * @param pVCpu Pointer to the VMCPU.
2290 * @param pCtx Pointer to the guest CPU context.
2291 */
2292VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2293{
2294 NOREF(pCtx);
2295 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2296 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2297 (void *)(uintptr_t)pVCpu->idCpu);
2298 AssertRC(rc);
2299 return rc;
2300}
2301
2302
2303/**
2304 * Force execution of the current IO code in the recompiler.
2305 *
2306 * @returns VBox status code.
2307 * @param pVM Pointer to the VM.
2308 * @param pCtx Partial VM execution context.
2309 */
2310VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2311{
2312 PVMCPU pVCpu = VMMGetCpu(pVM);
2313
2314 Assert(pVM->fHMEnabled);
2315 Log(("HMR3EmulateIoBlock\n"));
2316
2317 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2318 if (HMCanEmulateIoBlockEx(pCtx))
2319 {
2320 Log(("HMR3EmulateIoBlock -> enabled\n"));
2321 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2322 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2323 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2324 return VINF_EM_RESCHEDULE_REM;
2325 }
2326 return VINF_SUCCESS;
2327}
2328
2329
2330/**
2331 * Checks if we can currently use hardware accelerated raw mode.
2332 *
2333 * @returns true if we can currently use hardware acceleration, otherwise false.
2334 * @param pVM Pointer to the VM.
2335 * @param pCtx Partial VM execution context.
2336 */
2337VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2338{
2339 PVMCPU pVCpu = VMMGetCpu(pVM);
2340
2341 Assert(pVM->fHMEnabled);
2342
2343 /* If we're still executing the IO code, then return false. */
2344 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2345 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2346 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2347 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2348 return false;
2349
2350 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2351
2352 /* AMD-V supports real & protected mode with or without paging. */
2353 if (pVM->hm.s.svm.fEnabled)
2354 {
2355 pVCpu->hm.s.fActive = true;
2356 return true;
2357 }
2358
2359 pVCpu->hm.s.fActive = false;
2360
2361 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2362 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2363 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2364
2365 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2366 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2367 {
2368 /*
2369 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2370 * guest execution feature i missing (VT-x only).
2371 */
2372 if (fSupportsRealMode)
2373 {
2374 if (CPUMIsGuestInRealModeEx(pCtx))
2375 {
2376 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2377 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2378 * If this is not true, we cannot execute real mode as V86 and have to fall
2379 * back to emulation.
2380 */
2381 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2382 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2383 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2384 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2385 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2386 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2387 || (pCtx->cs.u32Limit != 0xffff)
2388 || (pCtx->ds.u32Limit != 0xffff)
2389 || (pCtx->es.u32Limit != 0xffff)
2390 || (pCtx->ss.u32Limit != 0xffff)
2391 || (pCtx->fs.u32Limit != 0xffff)
2392 || (pCtx->gs.u32Limit != 0xffff))
2393 {
2394 return false;
2395 }
2396 }
2397 else
2398 {
2399 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2400 /* Verify the requirements for executing code in protected
2401 mode. VT-x can't handle the CPU state right after a switch
2402 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2403 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2404 && enmGuestMode >= PGMMODE_PROTECTED)
2405 {
2406 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2407 || (pCtx->ds.Sel & X86_SEL_RPL)
2408 || (pCtx->es.Sel & X86_SEL_RPL)
2409 || (pCtx->fs.Sel & X86_SEL_RPL)
2410 || (pCtx->gs.Sel & X86_SEL_RPL)
2411 || (pCtx->ss.Sel & X86_SEL_RPL))
2412 {
2413 return false;
2414 }
2415 }
2416 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2417 if ( pCtx->gdtr.cbGdt
2418 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2419 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2420 {
2421 return false;
2422 }
2423 }
2424 }
2425 else
2426 {
2427 if ( !CPUMIsGuestInLongModeEx(pCtx)
2428 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2429 {
2430 /** @todo This should (probably) be set on every excursion to the REM,
2431 * however it's too risky right now. So, only apply it when we go
2432 * back to REM for real mode execution. (The XP hack below doesn't
2433 * work reliably without this.)
2434 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2435 for (uint32_t i = 0; i < pVM->cCpus; i++)
2436 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2437
2438 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2439 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2440 return false;
2441
2442 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2443 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2444 return false;
2445
2446 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2447 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2448 * hidden registers (possible recompiler bug; see load_seg_vm) */
2449 if (pCtx->cs.Attr.n.u1Present == 0)
2450 return false;
2451 if (pCtx->ss.Attr.n.u1Present == 0)
2452 return false;
2453
2454 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2455 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2456 /** @todo This check is actually wrong, it doesn't take the direction of the
2457 * stack segment into account. But, it does the job for now. */
2458 if (pCtx->rsp >= pCtx->ss.u32Limit)
2459 return false;
2460#if 0
2461 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2462 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2463 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2464 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2465 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2466 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2467 return false;
2468#endif
2469 }
2470 }
2471 }
2472
2473 if (pVM->hm.s.vmx.fEnabled)
2474 {
2475 uint32_t mask;
2476
2477 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2478 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2479 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2480 mask &= ~X86_CR0_NE;
2481
2482 if (fSupportsRealMode)
2483 {
2484 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2485 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2486 }
2487 else
2488 {
2489 /* We support protected mode without paging using identity mapping. */
2490 mask &= ~X86_CR0_PG;
2491 }
2492 if ((pCtx->cr0 & mask) != mask)
2493 return false;
2494
2495 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2496 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2497 if ((pCtx->cr0 & mask) != 0)
2498 return false;
2499
2500 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2501 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2502 mask &= ~X86_CR4_VMXE;
2503 if ((pCtx->cr4 & mask) != mask)
2504 return false;
2505
2506 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2507 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2508 if ((pCtx->cr4 & mask) != 0)
2509 return false;
2510
2511 pVCpu->hm.s.fActive = true;
2512 return true;
2513 }
2514
2515 return false;
2516}
2517
2518
2519/**
2520 * Checks if we need to reschedule due to VMM device heap changes.
2521 *
2522 * @returns true if a reschedule is required, otherwise false.
2523 * @param pVM Pointer to the VM.
2524 * @param pCtx VM execution context.
2525 */
2526VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2527{
2528 /*
2529 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2530 * when the unrestricted guest execution feature is missing (VT-x only).
2531 */
2532 if ( pVM->hm.s.vmx.fEnabled
2533 && !pVM->hm.s.vmx.fUnrestrictedGuest
2534 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2535 && !PDMVmmDevHeapIsEnabled(pVM)
2536 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2537 return true;
2538
2539 return false;
2540}
2541
2542
2543/**
2544 * Notification from EM about a rescheduling into hardware assisted execution
2545 * mode.
2546 *
2547 * @param pVCpu Pointer to the current VMCPU.
2548 */
2549VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2550{
2551 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2552}
2553
2554
2555/**
2556 * Notification from EM about returning from instruction emulation (REM / EM).
2557 *
2558 * @param pVCpu Pointer to the VMCPU.
2559 */
2560VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2561{
2562 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2563}
2564
2565
2566/**
2567 * Checks if we are currently using hardware accelerated raw mode.
2568 *
2569 * @returns true if hardware acceleration is being used, otherwise false.
2570 * @param pVCpu Pointer to the VMCPU.
2571 */
2572VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2573{
2574 return pVCpu->hm.s.fActive;
2575}
2576
2577
2578/**
2579 * Checks if we are currently using nested paging.
2580 *
2581 * @returns true if nested paging is being used, otherwise false.
2582 * @param pUVM The user mode VM handle.
2583 */
2584VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2585{
2586 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2587 PVM pVM = pUVM->pVM;
2588 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2589 return HMIsEnabled(pVM);
2590}
2591
2592
2593/**
2594 * Checks if we are currently using nested paging.
2595 *
2596 * @returns true if nested paging is being used, otherwise false.
2597 * @param pUVM The user mode VM handle.
2598 */
2599VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2600{
2601 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2602 PVM pVM = pUVM->pVM;
2603 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2604 return pVM->hm.s.fNestedPaging;
2605}
2606
2607
2608/**
2609 * Checks if we are currently using VPID in VT-x mode.
2610 *
2611 * @returns true if VPID is being used, otherwise false.
2612 * @param pUVM The user mode VM handle.
2613 */
2614VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2615{
2616 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2617 PVM pVM = pUVM->pVM;
2618 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2619 return pVM->hm.s.vmx.fVpid;
2620}
2621
2622
2623/**
2624 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2625 *
2626 * @returns true if an internal event is pending, otherwise false.
2627 * @param pVM Pointer to the VM.
2628 */
2629VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2630{
2631 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2632}
2633
2634
2635/**
2636 * Checks if the VMX-preemption timer is being used.
2637 *
2638 * @returns true if the VMX-preemption timer is being used, otherwise false.
2639 * @param pVM Pointer to the VM.
2640 */
2641VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2642{
2643 return HMIsEnabled(pVM)
2644 && pVM->hm.s.vmx.fEnabled
2645 && pVM->hm.s.vmx.fUsePreemptTimer;
2646}
2647
2648
2649/**
2650 * Restart an I/O instruction that was refused in ring-0
2651 *
2652 * @returns Strict VBox status code. Informational status codes other than the one documented
2653 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2654 * @retval VINF_SUCCESS Success.
2655 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2656 * status code must be passed on to EM.
2657 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2658 *
2659 * @param pVM Pointer to the VM.
2660 * @param pVCpu Pointer to the VMCPU.
2661 * @param pCtx Pointer to the guest CPU context.
2662 */
2663VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2664{
2665 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2666
2667 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2668
2669 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2670 || enmType == HMPENDINGIO_INVALID)
2671 return VERR_NOT_FOUND;
2672
2673 VBOXSTRICTRC rcStrict;
2674 switch (enmType)
2675 {
2676 case HMPENDINGIO_PORT_READ:
2677 {
2678 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2679 uint32_t u32Val = 0;
2680
2681 rcStrict = IOMIOPortRead(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2682 &u32Val,
2683 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2684 if (IOM_SUCCESS(rcStrict))
2685 {
2686 /* Write back to the EAX register. */
2687 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2688 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2689 }
2690 break;
2691 }
2692
2693 case HMPENDINGIO_PORT_WRITE:
2694 rcStrict = IOMIOPortWrite(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2695 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2696 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2697 if (IOM_SUCCESS(rcStrict))
2698 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2699 break;
2700
2701 default:
2702 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2703 }
2704
2705 return rcStrict;
2706}
2707
2708
2709/**
2710 * Check fatal VT-x/AMD-V error and produce some meaningful
2711 * log release message.
2712 *
2713 * @param pVM Pointer to the VM.
2714 * @param iStatusCode VBox status code.
2715 */
2716VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2717{
2718 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2719 {
2720 switch (iStatusCode)
2721 {
2722 case VERR_VMX_INVALID_VMCS_FIELD:
2723 break;
2724
2725 case VERR_VMX_INVALID_VMCS_PTR:
2726 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
2727 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2728 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2729 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2730 break;
2731
2732 case VERR_VMX_UNABLE_TO_START_VM:
2733 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2734 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2735 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2736 {
2737 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2738#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2739 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2740 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2741 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d cGuestMSRs %x\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2742#endif
2743 }
2744 /** @todo Log VM-entry event injection control fields
2745 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2746 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2747 break;
2748
2749 case VERR_VMX_UNABLE_TO_RESUME_VM:
2750 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2751 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2752 break;
2753
2754 case VERR_VMX_INVALID_VMXON_PTR:
2755 break;
2756 }
2757 }
2758
2759 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2760 {
2761 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2762 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2763 }
2764}
2765
2766
2767/**
2768 * Execute state save operation.
2769 *
2770 * @returns VBox status code.
2771 * @param pVM Pointer to the VM.
2772 * @param pSSM SSM operation handle.
2773 */
2774static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2775{
2776 int rc;
2777
2778 Log(("hmR3Save:\n"));
2779
2780 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2781 {
2782 /*
2783 * Save the basic bits - fortunately all the other things can be resynced on load.
2784 */
2785 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2786 AssertRCReturn(rc, rc);
2787 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2788 AssertRCReturn(rc, rc);
2789 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2790 AssertRCReturn(rc, rc);
2791
2792 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2793 AssertRCReturn(rc, rc);
2794 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2795 AssertRCReturn(rc, rc);
2796 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2797 AssertRCReturn(rc, rc);
2798 }
2799#ifdef VBOX_HM_WITH_GUEST_PATCHING
2800 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2801 AssertRCReturn(rc, rc);
2802 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2803 AssertRCReturn(rc, rc);
2804 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2805 AssertRCReturn(rc, rc);
2806
2807 /* Store all the guest patch records too. */
2808 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2809 AssertRCReturn(rc, rc);
2810
2811 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2812 {
2813 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2814
2815 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2819 AssertRCReturn(rc, rc);
2820
2821 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2822 AssertRCReturn(rc, rc);
2823
2824 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2825 AssertRCReturn(rc, rc);
2826
2827 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2828 AssertRCReturn(rc, rc);
2829
2830 AssertCompileSize(HMTPRINSTR, 4);
2831 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2832 AssertRCReturn(rc, rc);
2833
2834 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2835 AssertRCReturn(rc, rc);
2836
2837 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2838 AssertRCReturn(rc, rc);
2839
2840 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2841 AssertRCReturn(rc, rc);
2842
2843 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2844 AssertRCReturn(rc, rc);
2845 }
2846#endif
2847 return VINF_SUCCESS;
2848}
2849
2850
2851/**
2852 * Execute state load operation.
2853 *
2854 * @returns VBox status code.
2855 * @param pVM Pointer to the VM.
2856 * @param pSSM SSM operation handle.
2857 * @param uVersion Data layout version.
2858 * @param uPass The data pass.
2859 */
2860static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2861{
2862 int rc;
2863
2864 Log(("hmR3Load:\n"));
2865 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2866
2867 /*
2868 * Validate version.
2869 */
2870 if ( uVersion != HM_SSM_VERSION
2871 && uVersion != HM_SSM_VERSION_NO_PATCHING
2872 && uVersion != HM_SSM_VERSION_2_0_X)
2873 {
2874 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2875 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2876 }
2877 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2878 {
2879 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2880 AssertRCReturn(rc, rc);
2881 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2882 AssertRCReturn(rc, rc);
2883 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2884 AssertRCReturn(rc, rc);
2885
2886 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2887 {
2888 uint32_t val;
2889
2890 rc = SSMR3GetU32(pSSM, &val);
2891 AssertRCReturn(rc, rc);
2892 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2893
2894 rc = SSMR3GetU32(pSSM, &val);
2895 AssertRCReturn(rc, rc);
2896 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2897
2898 rc = SSMR3GetU32(pSSM, &val);
2899 AssertRCReturn(rc, rc);
2900 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2901 }
2902 }
2903#ifdef VBOX_HM_WITH_GUEST_PATCHING
2904 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2905 {
2906 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2907 AssertRCReturn(rc, rc);
2908 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2909 AssertRCReturn(rc, rc);
2910 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2911 AssertRCReturn(rc, rc);
2912
2913 /* Fetch all TPR patch records. */
2914 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2915 AssertRCReturn(rc, rc);
2916
2917 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2918 {
2919 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2920
2921 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2922 AssertRCReturn(rc, rc);
2923
2924 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2925 AssertRCReturn(rc, rc);
2926
2927 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2928 AssertRCReturn(rc, rc);
2929
2930 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2931 AssertRCReturn(rc, rc);
2932
2933 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2934 AssertRCReturn(rc, rc);
2935
2936 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2937 AssertRCReturn(rc, rc);
2938
2939 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2940 pVM->hm.s.fTPRPatchingActive = true;
2941
2942 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2943
2944 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2945 AssertRCReturn(rc, rc);
2946
2947 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2948 AssertRCReturn(rc, rc);
2949
2950 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2951 AssertRCReturn(rc, rc);
2952
2953 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2954 AssertRCReturn(rc, rc);
2955
2956 Log(("hmR3Load: patch %d\n", i));
2957 Log(("Key = %x\n", pPatch->Core.Key));
2958 Log(("cbOp = %d\n", pPatch->cbOp));
2959 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2960 Log(("type = %d\n", pPatch->enmType));
2961 Log(("srcop = %d\n", pPatch->uSrcOperand));
2962 Log(("dstop = %d\n", pPatch->uDstOperand));
2963 Log(("cFaults = %d\n", pPatch->cFaults));
2964 Log(("target = %x\n", pPatch->pJumpTarget));
2965 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2966 AssertRC(rc);
2967 }
2968 }
2969#endif
2970
2971 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2972 if (HMIsEnabled(pVM))
2973 {
2974 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2975 {
2976 PVMCPU pVCpu = &pVM->aCpus[i];
2977
2978 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2979 }
2980 }
2981 return VINF_SUCCESS;
2982}
2983
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